1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <linux/clk.h>
40 #include <linux/component.h>
41 #include <linux/gpio/consumer.h>
42 #include <linux/i2c.h>
43 #include <linux/of_address.h>
44 #include <linux/of_gpio.h>
45 #include <linux/of_platform.h>
46 #include <linux/pm_runtime.h>
47 #include <linux/rational.h>
48 #include <linux/reset.h>
49 #include <sound/dmaengine_pcm.h>
50 #include <sound/hdmi-codec.h>
51 #include <sound/pcm_drm_eld.h>
52 #include <sound/pcm_params.h>
53 #include <sound/soc.h>
54 #include "media/cec.h"
55 #include "vc4_drv.h"
56 #include "vc4_hdmi.h"
57 #include "vc4_hdmi_regs.h"
58 #include "vc4_regs.h"
59
60 #define VC5_HDMI_HORZA_HFP_SHIFT 16
61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
62 #define VC5_HDMI_HORZA_VPOS BIT(15)
63 #define VC5_HDMI_HORZA_HPOS BIT(14)
64 #define VC5_HDMI_HORZA_HAP_SHIFT 0
65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
66
67 #define VC5_HDMI_HORZB_HBP_SHIFT 16
68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
69 #define VC5_HDMI_HORZB_HSP_SHIFT 0
70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
71
72 #define VC5_HDMI_VERTA_VSP_SHIFT 24
73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
74 #define VC5_HDMI_VERTA_VFP_SHIFT 16
75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
76 #define VC5_HDMI_VERTA_VAL_SHIFT 0
77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
78
79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
81
82 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
83 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
84
85 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
86
87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
88 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
89
90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
91 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
92
93 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
94
95 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
96 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
97
98 # define VC4_HD_M_SW_RST BIT(2)
99 # define VC4_HD_M_ENABLE BIT(0)
100
101 #define HSM_MIN_CLOCK_FREQ 120000000
102 #define CEC_CLOCK_FREQ 40000
103
104 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
105
vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode * mode)106 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
107 {
108 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
109 }
110
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)111 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
112 {
113 struct drm_info_node *node = (struct drm_info_node *)m->private;
114 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
115 struct drm_printer p = drm_seq_file_printer(m);
116
117 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
118 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
119
120 return 0;
121 }
122
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)123 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
124 {
125 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
126 udelay(1);
127 HDMI_WRITE(HDMI_M_CTL, 0);
128
129 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
130
131 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
132 VC4_HDMI_SW_RESET_HDMI |
133 VC4_HDMI_SW_RESET_FORMAT_DETECT);
134
135 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
136 }
137
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)138 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
139 {
140 reset_control_reset(vc4_hdmi->reset);
141
142 HDMI_WRITE(HDMI_DVP_CTL, 0);
143
144 HDMI_WRITE(HDMI_CLOCK_STOP,
145 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
146 }
147
148 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)149 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
150 {
151 u16 clk_cnt;
152 u32 value;
153
154 value = HDMI_READ(HDMI_CEC_CNTRL_1);
155 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
156
157 /*
158 * Set the clock divider: the hsm_clock rate and this divider
159 * setting will give a 40 kHz CEC clock.
160 */
161 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
162 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
163 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
164 }
165 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)166 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
167 #endif
168
169 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
170
171 static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector * connector,bool force)172 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
173 {
174 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
175 bool connected = false;
176
177 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
178
179 if (vc4_hdmi->hpd_gpio) {
180 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
181 connected = true;
182 } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
183 connected = true;
184 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
185 connected = true;
186 }
187
188 if (connected) {
189 if (connector->status != connector_status_connected) {
190 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
191
192 if (edid) {
193 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
194 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
195 kfree(edid);
196 }
197 }
198
199 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
200 pm_runtime_put(&vc4_hdmi->pdev->dev);
201 return connector_status_connected;
202 }
203
204 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
205 pm_runtime_put(&vc4_hdmi->pdev->dev);
206 return connector_status_disconnected;
207 }
208
vc4_hdmi_connector_destroy(struct drm_connector * connector)209 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
210 {
211 drm_connector_unregister(connector);
212 drm_connector_cleanup(connector);
213 }
214
vc4_hdmi_connector_get_modes(struct drm_connector * connector)215 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
216 {
217 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
218 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
219 int ret = 0;
220 struct edid *edid;
221
222 edid = drm_get_edid(connector, vc4_hdmi->ddc);
223 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
224 if (!edid)
225 return -ENODEV;
226
227 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
228
229 drm_connector_update_edid_property(connector, edid);
230 ret = drm_add_edid_modes(connector, edid);
231 kfree(edid);
232
233 if (vc4_hdmi->disable_4kp60) {
234 struct drm_device *drm = connector->dev;
235 struct drm_display_mode *mode;
236
237 list_for_each_entry(mode, &connector->probed_modes, head) {
238 if (vc4_hdmi_mode_needs_scrambling(mode)) {
239 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
240 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
241 }
242 }
243 }
244
245 return ret;
246 }
247
vc4_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)248 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
249 struct drm_atomic_state *state)
250 {
251 struct drm_connector_state *old_state =
252 drm_atomic_get_old_connector_state(state, connector);
253 struct drm_connector_state *new_state =
254 drm_atomic_get_new_connector_state(state, connector);
255 struct drm_crtc *crtc = new_state->crtc;
256
257 if (!crtc)
258 return 0;
259
260 if (old_state->colorspace != new_state->colorspace ||
261 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
262 struct drm_crtc_state *crtc_state;
263
264 crtc_state = drm_atomic_get_crtc_state(state, crtc);
265 if (IS_ERR(crtc_state))
266 return PTR_ERR(crtc_state);
267
268 crtc_state->mode_changed = true;
269 }
270
271 return 0;
272 }
273
vc4_hdmi_connector_reset(struct drm_connector * connector)274 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
275 {
276 struct vc4_hdmi_connector_state *old_state =
277 conn_state_to_vc4_hdmi_conn_state(connector->state);
278 struct vc4_hdmi_connector_state *new_state =
279 kzalloc(sizeof(*new_state), GFP_KERNEL);
280
281 if (connector->state)
282 __drm_atomic_helper_connector_destroy_state(connector->state);
283
284 kfree(old_state);
285 __drm_atomic_helper_connector_reset(connector, &new_state->base);
286
287 if (!new_state)
288 return;
289
290 new_state->base.max_bpc = 8;
291 new_state->base.max_requested_bpc = 8;
292 drm_atomic_helper_connector_tv_reset(connector);
293 }
294
295 static struct drm_connector_state *
vc4_hdmi_connector_duplicate_state(struct drm_connector * connector)296 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
297 {
298 struct drm_connector_state *conn_state = connector->state;
299 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
300 struct vc4_hdmi_connector_state *new_state;
301
302 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
303 if (!new_state)
304 return NULL;
305
306 new_state->pixel_rate = vc4_state->pixel_rate;
307 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
308
309 return &new_state->base;
310 }
311
312 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
313 .detect = vc4_hdmi_connector_detect,
314 .fill_modes = drm_helper_probe_single_connector_modes,
315 .destroy = vc4_hdmi_connector_destroy,
316 .reset = vc4_hdmi_connector_reset,
317 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
318 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
319 };
320
321 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
322 .get_modes = vc4_hdmi_connector_get_modes,
323 .atomic_check = vc4_hdmi_connector_atomic_check,
324 };
325
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)326 static int vc4_hdmi_connector_init(struct drm_device *dev,
327 struct vc4_hdmi *vc4_hdmi)
328 {
329 struct drm_connector *connector = &vc4_hdmi->connector;
330 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
331 int ret;
332
333 drm_connector_init_with_ddc(dev, connector,
334 &vc4_hdmi_connector_funcs,
335 DRM_MODE_CONNECTOR_HDMIA,
336 vc4_hdmi->ddc);
337 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
338
339 /*
340 * Some of the properties below require access to state, like bpc.
341 * Allocate some default initial connector state with our reset helper.
342 */
343 if (connector->funcs->reset)
344 connector->funcs->reset(connector);
345
346 /* Create and attach TV margin props to this connector. */
347 ret = drm_mode_create_tv_margin_properties(dev);
348 if (ret)
349 return ret;
350
351 ret = drm_mode_create_hdmi_colorspace_property(connector);
352 if (ret)
353 return ret;
354
355 drm_connector_attach_colorspace_property(connector);
356 drm_connector_attach_tv_margin_properties(connector);
357 drm_connector_attach_max_bpc_property(connector, 8, 12);
358
359 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
360 DRM_CONNECTOR_POLL_DISCONNECT);
361
362 connector->interlace_allowed = 1;
363 connector->doublescan_allowed = 0;
364
365 if (vc4_hdmi->variant->supports_hdr)
366 drm_connector_attach_hdr_output_metadata_property(connector);
367
368 drm_connector_attach_encoder(connector, encoder);
369
370 return 0;
371 }
372
vc4_hdmi_stop_packet(struct drm_encoder * encoder,enum hdmi_infoframe_type type,bool poll)373 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
374 enum hdmi_infoframe_type type,
375 bool poll)
376 {
377 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
378 u32 packet_id = type - 0x80;
379
380 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
381 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
382
383 if (!poll)
384 return 0;
385
386 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
387 BIT(packet_id)), 100);
388 }
389
vc4_hdmi_write_infoframe(struct drm_encoder * encoder,union hdmi_infoframe * frame)390 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
391 union hdmi_infoframe *frame)
392 {
393 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
394 u32 packet_id = frame->any.type - 0x80;
395 const struct vc4_hdmi_register *ram_packet_start =
396 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
397 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
398 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
399 ram_packet_start->reg);
400 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
401 ssize_t len, i;
402 int ret;
403
404 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
405 VC4_HDMI_RAM_PACKET_ENABLE),
406 "Packet RAM has to be on to store the packet.");
407
408 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
409 if (len < 0)
410 return;
411
412 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
413 if (ret) {
414 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
415 return;
416 }
417
418 for (i = 0; i < len; i += 7) {
419 writel(buffer[i + 0] << 0 |
420 buffer[i + 1] << 8 |
421 buffer[i + 2] << 16,
422 base + packet_reg);
423 packet_reg += 4;
424
425 writel(buffer[i + 3] << 0 |
426 buffer[i + 4] << 8 |
427 buffer[i + 5] << 16 |
428 buffer[i + 6] << 24,
429 base + packet_reg);
430 packet_reg += 4;
431 }
432
433 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
434 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
435 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
436 BIT(packet_id)), 100);
437 if (ret)
438 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
439 }
440
vc4_hdmi_set_avi_infoframe(struct drm_encoder * encoder)441 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
442 {
443 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
444 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
445 struct drm_connector *connector = &vc4_hdmi->connector;
446 struct drm_connector_state *cstate = connector->state;
447 struct drm_crtc *crtc = encoder->crtc;
448 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
449 union hdmi_infoframe frame;
450 int ret;
451
452 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
453 connector, mode);
454 if (ret < 0) {
455 DRM_ERROR("couldn't fill AVI infoframe\n");
456 return;
457 }
458
459 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
460 connector, mode,
461 vc4_encoder->limited_rgb_range ?
462 HDMI_QUANTIZATION_RANGE_LIMITED :
463 HDMI_QUANTIZATION_RANGE_FULL);
464 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
465 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
466
467 vc4_hdmi_write_infoframe(encoder, &frame);
468 }
469
vc4_hdmi_set_spd_infoframe(struct drm_encoder * encoder)470 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
471 {
472 union hdmi_infoframe frame;
473 int ret;
474
475 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
476 if (ret < 0) {
477 DRM_ERROR("couldn't fill SPD infoframe\n");
478 return;
479 }
480
481 frame.spd.sdi = HDMI_SPD_SDI_PC;
482
483 vc4_hdmi_write_infoframe(encoder, &frame);
484 }
485
vc4_hdmi_set_audio_infoframe(struct drm_encoder * encoder)486 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
487 {
488 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
489 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
490 union hdmi_infoframe frame;
491
492 memcpy(&frame.audio, audio, sizeof(*audio));
493 vc4_hdmi_write_infoframe(encoder, &frame);
494 }
495
vc4_hdmi_set_hdr_infoframe(struct drm_encoder * encoder)496 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
497 {
498 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
499 struct drm_connector *connector = &vc4_hdmi->connector;
500 struct drm_connector_state *conn_state = connector->state;
501 union hdmi_infoframe frame;
502
503 if (!vc4_hdmi->variant->supports_hdr)
504 return;
505
506 if (!conn_state->hdr_output_metadata)
507 return;
508
509 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
510 return;
511
512 vc4_hdmi_write_infoframe(encoder, &frame);
513 }
514
vc4_hdmi_set_infoframes(struct drm_encoder * encoder)515 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
516 {
517 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
518
519 vc4_hdmi_set_avi_infoframe(encoder);
520 vc4_hdmi_set_spd_infoframe(encoder);
521 /*
522 * If audio was streaming, then we need to reenabled the audio
523 * infoframe here during encoder_enable.
524 */
525 if (vc4_hdmi->audio.streaming)
526 vc4_hdmi_set_audio_infoframe(encoder);
527
528 vc4_hdmi_set_hdr_infoframe(encoder);
529 }
530
vc4_hdmi_supports_scrambling(struct drm_encoder * encoder,struct drm_display_mode * mode)531 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
532 struct drm_display_mode *mode)
533 {
534 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
535 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
536 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
537
538 if (!vc4_encoder->hdmi_monitor)
539 return false;
540
541 if (!display->hdmi.scdc.supported ||
542 !display->hdmi.scdc.scrambling.supported)
543 return false;
544
545 return true;
546 }
547
548 #define SCRAMBLING_POLLING_DELAY_MS 1000
549
vc4_hdmi_enable_scrambling(struct drm_encoder * encoder)550 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
551 {
552 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
553 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
554
555 if (!vc4_hdmi_supports_scrambling(encoder, mode))
556 return;
557
558 if (!vc4_hdmi_mode_needs_scrambling(mode))
559 return;
560
561 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
562 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
563
564 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
565 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
566
567 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
568 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
569 }
570
vc4_hdmi_disable_scrambling(struct drm_encoder * encoder)571 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
572 {
573 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
574 struct drm_crtc *crtc = encoder->crtc;
575
576 /*
577 * At boot, encoder->crtc will be NULL. Since we don't know the
578 * state of the scrambler and in order to avoid any
579 * inconsistency, let's disable it all the time.
580 */
581 if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
582 return;
583
584 if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
585 return;
586
587 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
588 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
589
590 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
591 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
592
593 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
594 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
595 }
596
vc4_hdmi_scrambling_wq(struct work_struct * work)597 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
598 {
599 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
600 struct vc4_hdmi,
601 scrambling_work);
602
603 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
604 return;
605
606 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
607 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
608
609 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
610 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
611 }
612
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)613 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
614 struct drm_atomic_state *state)
615 {
616 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
617
618 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
619
620 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
621
622 mdelay(1);
623
624 HDMI_WRITE(HDMI_VID_CTL,
625 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
626 vc4_hdmi_disable_scrambling(encoder);
627 }
628
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder,struct drm_atomic_state * state)629 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
630 struct drm_atomic_state *state)
631 {
632 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
633 int ret;
634
635 HDMI_WRITE(HDMI_VID_CTL,
636 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
637
638 if (vc4_hdmi->variant->phy_disable)
639 vc4_hdmi->variant->phy_disable(vc4_hdmi);
640
641 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
642 clk_disable_unprepare(vc4_hdmi->pixel_clock);
643
644 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
645 if (ret < 0)
646 DRM_ERROR("Failed to release power domain: %d\n", ret);
647 }
648
vc4_hdmi_encoder_disable(struct drm_encoder * encoder)649 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
650 {
651 }
652
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)653 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
654 {
655 u32 csc_ctl;
656
657 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
658 VC4_HD_CSC_CTL_ORDER);
659
660 if (enable) {
661 /* CEA VICs other than #1 requre limited range RGB
662 * output unless overridden by an AVI infoframe.
663 * Apply a colorspace conversion to squash 0-255 down
664 * to 16-235. The matrix here is:
665 *
666 * [ 0 0 0.8594 16]
667 * [ 0 0.8594 0 16]
668 * [ 0.8594 0 0 16]
669 * [ 0 0 0 1]
670 */
671 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
672 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
673 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
674 VC4_HD_CSC_CTL_MODE);
675
676 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
677 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
678 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
679 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
680 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
681 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
682 }
683
684 /* The RGB order applies even when CSC is disabled. */
685 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
686 }
687
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)688 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
689 {
690 u32 csc_ctl;
691
692 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
693
694 if (enable) {
695 /* CEA VICs other than #1 requre limited range RGB
696 * output unless overridden by an AVI infoframe.
697 * Apply a colorspace conversion to squash 0-255 down
698 * to 16-235. The matrix here is:
699 *
700 * [ 0.8594 0 0 16]
701 * [ 0 0.8594 0 16]
702 * [ 0 0 0.8594 16]
703 * [ 0 0 0 1]
704 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
705 */
706 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
707 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
708 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
709 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
710 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
711 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
712 } else {
713 /* Still use the matrix for full range, but make it unity.
714 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
715 */
716 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
717 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
718 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
719 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
720 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
721 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
722 }
723
724 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
725 }
726
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,struct drm_display_mode * mode)727 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
728 struct drm_connector_state *state,
729 struct drm_display_mode *mode)
730 {
731 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
732 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
733 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
734 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
735 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
736 VC4_HDMI_VERTA_VSP) |
737 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
738 VC4_HDMI_VERTA_VFP) |
739 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
740 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
741 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
742 interlaced,
743 VC4_HDMI_VERTB_VBP));
744 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
745 VC4_SET_FIELD(mode->crtc_vtotal -
746 mode->crtc_vsync_end,
747 VC4_HDMI_VERTB_VBP));
748
749 HDMI_WRITE(HDMI_HORZA,
750 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
751 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
752 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
753 VC4_HDMI_HORZA_HAP));
754
755 HDMI_WRITE(HDMI_HORZB,
756 VC4_SET_FIELD((mode->htotal -
757 mode->hsync_end) * pixel_rep,
758 VC4_HDMI_HORZB_HBP) |
759 VC4_SET_FIELD((mode->hsync_end -
760 mode->hsync_start) * pixel_rep,
761 VC4_HDMI_HORZB_HSP) |
762 VC4_SET_FIELD((mode->hsync_start -
763 mode->hdisplay) * pixel_rep,
764 VC4_HDMI_HORZB_HFP));
765
766 HDMI_WRITE(HDMI_VERTA0, verta);
767 HDMI_WRITE(HDMI_VERTA1, verta);
768
769 HDMI_WRITE(HDMI_VERTB0, vertb_even);
770 HDMI_WRITE(HDMI_VERTB1, vertb);
771 }
772
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,struct drm_display_mode * mode)773 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
774 struct drm_connector_state *state,
775 struct drm_display_mode *mode)
776 {
777 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
778 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
779 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
780 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
781 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
782 VC5_HDMI_VERTA_VSP) |
783 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
784 VC5_HDMI_VERTA_VFP) |
785 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
786 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
787 VC5_HDMI_VERTB_VSPO) |
788 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
789 interlaced,
790 VC4_HDMI_VERTB_VBP));
791 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
792 VC4_SET_FIELD(mode->crtc_vtotal -
793 mode->crtc_vsync_end,
794 VC4_HDMI_VERTB_VBP));
795 unsigned char gcp;
796 bool gcp_en;
797 u32 reg;
798
799 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
800 HDMI_WRITE(HDMI_HORZA,
801 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
802 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
803 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
804 VC5_HDMI_HORZA_HAP) |
805 VC4_SET_FIELD((mode->hsync_start -
806 mode->hdisplay) * pixel_rep,
807 VC5_HDMI_HORZA_HFP));
808
809 HDMI_WRITE(HDMI_HORZB,
810 VC4_SET_FIELD((mode->htotal -
811 mode->hsync_end) * pixel_rep,
812 VC5_HDMI_HORZB_HBP) |
813 VC4_SET_FIELD((mode->hsync_end -
814 mode->hsync_start) * pixel_rep,
815 VC5_HDMI_HORZB_HSP));
816
817 HDMI_WRITE(HDMI_VERTA0, verta);
818 HDMI_WRITE(HDMI_VERTA1, verta);
819
820 HDMI_WRITE(HDMI_VERTB0, vertb_even);
821 HDMI_WRITE(HDMI_VERTB1, vertb);
822
823 switch (state->max_bpc) {
824 case 12:
825 gcp = 6;
826 gcp_en = true;
827 break;
828 case 10:
829 gcp = 5;
830 gcp_en = true;
831 break;
832 case 8:
833 default:
834 gcp = 4;
835 gcp_en = false;
836 break;
837 }
838
839 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
840 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
841 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
842 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
843 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
844 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
845
846 reg = HDMI_READ(HDMI_GCP_WORD_1);
847 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
848 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
849 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
850
851 reg = HDMI_READ(HDMI_GCP_CONFIG);
852 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
853 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
854 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
855
856 reg = HDMI_READ(HDMI_MISC_CONTROL);
857 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
858 reg |= VC4_SET_FIELD(0, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
859 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
860
861 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
862 }
863
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)864 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
865 {
866 u32 drift;
867 int ret;
868
869 drift = HDMI_READ(HDMI_FIFO_CTL);
870 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
871
872 HDMI_WRITE(HDMI_FIFO_CTL,
873 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
874 HDMI_WRITE(HDMI_FIFO_CTL,
875 drift | VC4_HDMI_FIFO_CTL_RECENTER);
876 usleep_range(1000, 1100);
877 HDMI_WRITE(HDMI_FIFO_CTL,
878 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
879 HDMI_WRITE(HDMI_FIFO_CTL,
880 drift | VC4_HDMI_FIFO_CTL_RECENTER);
881
882 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
883 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
884 WARN_ONCE(ret, "Timeout waiting for "
885 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
886 }
887
888 static struct drm_connector_state *
vc4_hdmi_encoder_get_connector_state(struct drm_encoder * encoder,struct drm_atomic_state * state)889 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
890 struct drm_atomic_state *state)
891 {
892 struct drm_connector_state *conn_state;
893 struct drm_connector *connector;
894 unsigned int i;
895
896 for_each_new_connector_in_state(state, connector, conn_state, i) {
897 if (conn_state->best_encoder == encoder)
898 return conn_state;
899 }
900
901 return NULL;
902 }
903
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder,struct drm_atomic_state * state)904 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
905 struct drm_atomic_state *state)
906 {
907 struct drm_connector_state *conn_state =
908 vc4_hdmi_encoder_get_connector_state(encoder, state);
909 struct vc4_hdmi_connector_state *vc4_conn_state =
910 conn_state_to_vc4_hdmi_conn_state(conn_state);
911 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
912 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
913 unsigned long pixel_rate = vc4_conn_state->pixel_rate;
914 unsigned long bvb_rate, hsm_rate;
915 int ret;
916
917 /*
918 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
919 * be faster than pixel clock, infinitesimally faster, tested in
920 * simulation. Otherwise, exact value is unimportant for HDMI
921 * operation." This conflicts with bcm2835's vc4 documentation, which
922 * states HSM's clock has to be at least 108% of the pixel clock.
923 *
924 * Real life tests reveal that vc4's firmware statement holds up, and
925 * users are able to use pixel clocks closer to HSM's, namely for
926 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
927 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
928 * 162MHz.
929 *
930 * Additionally, the AXI clock needs to be at least 25% of
931 * pixel clock, but HSM ends up being the limiting factor.
932 */
933 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
934 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
935 if (ret) {
936 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
937 return;
938 }
939
940 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
941 if (ret < 0) {
942 DRM_ERROR("Failed to retain power domain: %d\n", ret);
943 return;
944 }
945
946 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
947 if (ret) {
948 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
949 goto err_put_runtime_pm;
950 }
951
952 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
953 if (ret) {
954 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
955 goto err_put_runtime_pm;
956 }
957
958
959 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
960
961 if (pixel_rate > 297000000)
962 bvb_rate = 300000000;
963 else if (pixel_rate > 148500000)
964 bvb_rate = 150000000;
965 else
966 bvb_rate = 75000000;
967
968 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
969 if (ret) {
970 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
971 goto err_disable_pixel_clock;
972 }
973
974 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
975 if (ret) {
976 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
977 goto err_disable_pixel_clock;
978 }
979
980 if (vc4_hdmi->variant->phy_init)
981 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
982
983 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
984 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
985 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
986 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
987
988 if (vc4_hdmi->variant->set_timings)
989 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
990
991 return;
992
993 err_disable_pixel_clock:
994 clk_disable_unprepare(vc4_hdmi->pixel_clock);
995 err_put_runtime_pm:
996 pm_runtime_put(&vc4_hdmi->pdev->dev);
997
998 return;
999 }
1000
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1001 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1002 struct drm_atomic_state *state)
1003 {
1004 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1005 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1006 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1007
1008 if (vc4_encoder->hdmi_monitor &&
1009 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
1010 if (vc4_hdmi->variant->csc_setup)
1011 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1012
1013 vc4_encoder->limited_rgb_range = true;
1014 } else {
1015 if (vc4_hdmi->variant->csc_setup)
1016 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1017
1018 vc4_encoder->limited_rgb_range = false;
1019 }
1020
1021 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1022 }
1023
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1024 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1025 struct drm_atomic_state *state)
1026 {
1027 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1028 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1029 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1030 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1031 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1032 int ret;
1033
1034 HDMI_WRITE(HDMI_VID_CTL,
1035 VC4_HD_VID_CTL_ENABLE |
1036 VC4_HD_VID_CTL_CLRRGB |
1037 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1038 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1039 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1040 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1041
1042 HDMI_WRITE(HDMI_VID_CTL,
1043 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1044
1045 if (vc4_encoder->hdmi_monitor) {
1046 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1047 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1048 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1049
1050 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1051 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1052 WARN_ONCE(ret, "Timeout waiting for "
1053 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1054 } else {
1055 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1056 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1057 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1058 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1059 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1060 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1061
1062 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1063 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1064 WARN_ONCE(ret, "Timeout waiting for "
1065 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1066 }
1067
1068 if (vc4_encoder->hdmi_monitor) {
1069 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1070 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1071 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1072 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1073 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1074
1075 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1076 VC4_HDMI_RAM_PACKET_ENABLE);
1077
1078 vc4_hdmi_set_infoframes(encoder);
1079 }
1080
1081 vc4_hdmi_recenter_fifo(vc4_hdmi);
1082 vc4_hdmi_enable_scrambling(encoder);
1083 }
1084
vc4_hdmi_encoder_enable(struct drm_encoder * encoder)1085 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1086 {
1087 }
1088
1089 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1090 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1091
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1092 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1093 struct drm_crtc_state *crtc_state,
1094 struct drm_connector_state *conn_state)
1095 {
1096 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1097 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1098 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1099 unsigned long long pixel_rate = mode->clock * 1000;
1100 unsigned long long tmds_rate;
1101
1102 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1103 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1104 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1105 (mode->hsync_end % 2) || (mode->htotal % 2)))
1106 return -EINVAL;
1107
1108 /*
1109 * The 1440p@60 pixel rate is in the same range than the first
1110 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1111 * bandwidth). Slightly lower the frequency to bring it out of
1112 * the WiFi range.
1113 */
1114 tmds_rate = pixel_rate * 10;
1115 if (vc4_hdmi->disable_wifi_frequencies &&
1116 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1117 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1118 mode->clock = 238560;
1119 pixel_rate = mode->clock * 1000;
1120 }
1121
1122 if (conn_state->max_bpc == 12) {
1123 pixel_rate = pixel_rate * 150;
1124 do_div(pixel_rate, 100);
1125 } else if (conn_state->max_bpc == 10) {
1126 pixel_rate = pixel_rate * 125;
1127 do_div(pixel_rate, 100);
1128 }
1129
1130 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1131 pixel_rate = pixel_rate * 2;
1132
1133 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1134 return -EINVAL;
1135
1136 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1137 return -EINVAL;
1138
1139 vc4_state->pixel_rate = pixel_rate;
1140
1141 return 0;
1142 }
1143
1144 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)1145 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1146 const struct drm_display_mode *mode)
1147 {
1148 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1149
1150 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1151 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1152 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1153 (mode->hsync_end % 2) || (mode->htotal % 2)))
1154 return MODE_H_ILLEGAL;
1155
1156 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1157 return MODE_CLOCK_HIGH;
1158
1159 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1160 return MODE_CLOCK_HIGH;
1161
1162 return MODE_OK;
1163 }
1164
1165 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1166 .atomic_check = vc4_hdmi_encoder_atomic_check,
1167 .mode_valid = vc4_hdmi_encoder_mode_valid,
1168 .disable = vc4_hdmi_encoder_disable,
1169 .enable = vc4_hdmi_encoder_enable,
1170 };
1171
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1172 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1173 {
1174 int i;
1175 u32 channel_map = 0;
1176
1177 for (i = 0; i < 8; i++) {
1178 if (channel_mask & BIT(i))
1179 channel_map |= i << (3 * i);
1180 }
1181 return channel_map;
1182 }
1183
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1184 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1185 {
1186 int i;
1187 u32 channel_map = 0;
1188
1189 for (i = 0; i < 8; i++) {
1190 if (channel_mask & BIT(i))
1191 channel_map |= i << (4 * i);
1192 }
1193 return channel_map;
1194 }
1195
1196 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1197 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1198 unsigned int samplerate)
1199 {
1200 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1201 unsigned long n, m;
1202
1203 rational_best_approximation(hsm_clock, samplerate,
1204 VC4_HD_MAI_SMP_N_MASK >>
1205 VC4_HD_MAI_SMP_N_SHIFT,
1206 (VC4_HD_MAI_SMP_M_MASK >>
1207 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1208 &n, &m);
1209
1210 HDMI_WRITE(HDMI_MAI_SMP,
1211 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1212 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1213 }
1214
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1215 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1216 {
1217 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1218 struct drm_crtc *crtc = encoder->crtc;
1219 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1220 u32 n, cts;
1221 u64 tmp;
1222
1223 n = 128 * samplerate / 1000;
1224 tmp = (u64)(mode->clock * 1000) * n;
1225 do_div(tmp, 128 * samplerate);
1226 cts = tmp;
1227
1228 HDMI_WRITE(HDMI_CRP_CFG,
1229 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1230 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1231
1232 /*
1233 * We could get slightly more accurate clocks in some cases by
1234 * providing a CTS_1 value. The two CTS values are alternated
1235 * between based on the period fields
1236 */
1237 HDMI_WRITE(HDMI_CTS_0, cts);
1238 HDMI_WRITE(HDMI_CTS_1, cts);
1239 }
1240
dai_to_hdmi(struct snd_soc_dai * dai)1241 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1242 {
1243 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1244
1245 return snd_soc_card_get_drvdata(card);
1246 }
1247
vc4_hdmi_audio_startup(struct device * dev,void * data)1248 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1249 {
1250 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1251 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1252
1253 /*
1254 * If the HDMI encoder hasn't probed, or the encoder is
1255 * currently in DVI mode, treat the codec dai as missing.
1256 */
1257 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1258 VC4_HDMI_RAM_PACKET_ENABLE))
1259 return -ENODEV;
1260
1261 vc4_hdmi->audio.streaming = true;
1262
1263 HDMI_WRITE(HDMI_MAI_CTL,
1264 VC4_HD_MAI_CTL_RESET |
1265 VC4_HD_MAI_CTL_FLUSH |
1266 VC4_HD_MAI_CTL_DLATE |
1267 VC4_HD_MAI_CTL_ERRORE |
1268 VC4_HD_MAI_CTL_ERRORF);
1269
1270 if (vc4_hdmi->variant->phy_rng_enable)
1271 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1272
1273 return 0;
1274 }
1275
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)1276 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1277 {
1278 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1279 struct device *dev = &vc4_hdmi->pdev->dev;
1280 int ret;
1281
1282 vc4_hdmi->audio.streaming = false;
1283 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1284 if (ret)
1285 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1286
1287 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1288 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1289 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1290 }
1291
vc4_hdmi_audio_shutdown(struct device * dev,void * data)1292 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1293 {
1294 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1295
1296 HDMI_WRITE(HDMI_MAI_CTL,
1297 VC4_HD_MAI_CTL_DLATE |
1298 VC4_HD_MAI_CTL_ERRORE |
1299 VC4_HD_MAI_CTL_ERRORF);
1300
1301 if (vc4_hdmi->variant->phy_rng_disable)
1302 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1303
1304 vc4_hdmi->audio.streaming = false;
1305 vc4_hdmi_audio_reset(vc4_hdmi);
1306 }
1307
sample_rate_to_mai_fmt(int samplerate)1308 static int sample_rate_to_mai_fmt(int samplerate)
1309 {
1310 switch (samplerate) {
1311 case 8000:
1312 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1313 case 11025:
1314 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1315 case 12000:
1316 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1317 case 16000:
1318 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1319 case 22050:
1320 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1321 case 24000:
1322 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1323 case 32000:
1324 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1325 case 44100:
1326 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1327 case 48000:
1328 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1329 case 64000:
1330 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1331 case 88200:
1332 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1333 case 96000:
1334 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1335 case 128000:
1336 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1337 case 176400:
1338 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1339 case 192000:
1340 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1341 default:
1342 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1343 }
1344 }
1345
1346 /* HDMI audio codec callbacks */
vc4_hdmi_audio_prepare(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)1347 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1348 struct hdmi_codec_daifmt *daifmt,
1349 struct hdmi_codec_params *params)
1350 {
1351 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1352 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1353 unsigned int sample_rate = params->sample_rate;
1354 unsigned int channels = params->channels;
1355 u32 audio_packet_config, channel_mask;
1356 u32 channel_map;
1357 u32 mai_audio_format;
1358 u32 mai_sample_rate;
1359
1360 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1361 sample_rate, params->sample_width, channels);
1362
1363 HDMI_WRITE(HDMI_MAI_CTL,
1364 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1365 VC4_HD_MAI_CTL_WHOLSMP |
1366 VC4_HD_MAI_CTL_CHALIGN |
1367 VC4_HD_MAI_CTL_ENABLE);
1368
1369 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1370
1371 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1372 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1373 params->channels == 8)
1374 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1375 else
1376 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1377 HDMI_WRITE(HDMI_MAI_FMT,
1378 VC4_SET_FIELD(mai_sample_rate,
1379 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1380 VC4_SET_FIELD(mai_audio_format,
1381 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1382
1383 /* The B frame identifier should match the value used by alsa-lib (8) */
1384 audio_packet_config =
1385 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1386 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1387 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1388
1389 channel_mask = GENMASK(channels - 1, 0);
1390 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1391 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1392
1393 /* Set the MAI threshold */
1394 HDMI_WRITE(HDMI_MAI_THR,
1395 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
1396 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
1397 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
1398 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
1399
1400 HDMI_WRITE(HDMI_MAI_CONFIG,
1401 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1402 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1403 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1404
1405 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1406 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1407 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1408 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1409
1410 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
1411 vc4_hdmi_set_audio_infoframe(encoder);
1412
1413 return 0;
1414 }
1415
1416 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1417 .name = "vc4-hdmi-cpu-dai-component",
1418 };
1419
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)1420 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1421 {
1422 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1423
1424 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1425
1426 return 0;
1427 }
1428
1429 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1430 .name = "vc4-hdmi-cpu-dai",
1431 .probe = vc4_hdmi_audio_cpu_dai_probe,
1432 .playback = {
1433 .stream_name = "Playback",
1434 .channels_min = 1,
1435 .channels_max = 8,
1436 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1437 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1438 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1439 SNDRV_PCM_RATE_192000,
1440 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1441 },
1442 };
1443
1444 static const struct snd_dmaengine_pcm_config pcm_conf = {
1445 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1446 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1447 };
1448
vc4_hdmi_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)1449 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1450 uint8_t *buf, size_t len)
1451 {
1452 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1453 struct drm_connector *connector = &vc4_hdmi->connector;
1454
1455 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1456
1457 return 0;
1458 }
1459
1460 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1461 .get_eld = vc4_hdmi_audio_get_eld,
1462 .prepare = vc4_hdmi_audio_prepare,
1463 .audio_shutdown = vc4_hdmi_audio_shutdown,
1464 .audio_startup = vc4_hdmi_audio_startup,
1465 };
1466
1467 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1468 .ops = &vc4_hdmi_codec_ops,
1469 .max_i2s_channels = 8,
1470 .i2s = 1,
1471 };
1472
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)1473 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1474 {
1475 const struct vc4_hdmi_register *mai_data =
1476 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1477 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1478 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1479 struct device *dev = &vc4_hdmi->pdev->dev;
1480 struct platform_device *codec_pdev;
1481 const __be32 *addr;
1482 int index, len;
1483 int ret;
1484
1485 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
1486 dev_warn(dev,
1487 "'dmas' DT property is missing or empty, no HDMI audio\n");
1488 return 0;
1489 }
1490
1491 if (mai_data->reg != VC4_HD) {
1492 WARN_ONCE(true, "MAI isn't in the HD block\n");
1493 return -EINVAL;
1494 }
1495
1496 /*
1497 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1498 * the bus address specified in the DT, because the physical address
1499 * (the one returned by platform_get_resource()) is not appropriate
1500 * for DMA transfers.
1501 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1502 */
1503 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1504 /* Before BCM2711, we don't have a named register range */
1505 if (index < 0)
1506 index = 1;
1507
1508 addr = of_get_address(dev->of_node, index, NULL, NULL);
1509
1510 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1511 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1512 vc4_hdmi->audio.dma_data.maxburst = 2;
1513
1514 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1515 if (ret) {
1516 dev_err(dev, "Could not register PCM component: %d\n", ret);
1517 return ret;
1518 }
1519
1520 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1521 &vc4_hdmi_audio_cpu_dai_drv, 1);
1522 if (ret) {
1523 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1524 return ret;
1525 }
1526
1527 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1528 PLATFORM_DEVID_AUTO,
1529 &vc4_hdmi_codec_pdata,
1530 sizeof(vc4_hdmi_codec_pdata));
1531 if (IS_ERR(codec_pdev)) {
1532 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1533 return PTR_ERR(codec_pdev);
1534 }
1535 vc4_hdmi->audio.codec_pdev = codec_pdev;
1536
1537 dai_link->cpus = &vc4_hdmi->audio.cpu;
1538 dai_link->codecs = &vc4_hdmi->audio.codec;
1539 dai_link->platforms = &vc4_hdmi->audio.platform;
1540
1541 dai_link->num_cpus = 1;
1542 dai_link->num_codecs = 1;
1543 dai_link->num_platforms = 1;
1544
1545 dai_link->name = "MAI";
1546 dai_link->stream_name = "MAI PCM";
1547 dai_link->codecs->dai_name = "i2s-hifi";
1548 dai_link->cpus->dai_name = dev_name(dev);
1549 dai_link->codecs->name = dev_name(&codec_pdev->dev);
1550 dai_link->platforms->name = dev_name(dev);
1551
1552 card->dai_link = dai_link;
1553 card->num_links = 1;
1554 card->name = vc4_hdmi->variant->card_name;
1555 card->driver_name = "vc4-hdmi";
1556 card->dev = dev;
1557 card->owner = THIS_MODULE;
1558
1559 /*
1560 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1561 * stores a pointer to the snd card object in dev->driver_data. This
1562 * means we cannot use it for something else. The hdmi back-pointer is
1563 * now stored in card->drvdata and should be retrieved with
1564 * snd_soc_card_get_drvdata() if needed.
1565 */
1566 snd_soc_card_set_drvdata(card, vc4_hdmi);
1567 ret = devm_snd_soc_register_card(dev, card);
1568 if (ret)
1569 dev_err_probe(dev, ret, "Could not register sound card\n");
1570
1571 return ret;
1572
1573 }
1574
vc4_hdmi_audio_exit(struct vc4_hdmi * vc4_hdmi)1575 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1576 {
1577 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1578 vc4_hdmi->audio.codec_pdev = NULL;
1579 }
1580
vc4_hdmi_hpd_irq_thread(int irq,void * priv)1581 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1582 {
1583 struct vc4_hdmi *vc4_hdmi = priv;
1584 struct drm_device *dev = vc4_hdmi->connector.dev;
1585
1586 if (dev && dev->registered)
1587 drm_kms_helper_hotplug_event(dev);
1588
1589 return IRQ_HANDLED;
1590 }
1591
vc4_hdmi_hotplug_init(struct vc4_hdmi * vc4_hdmi)1592 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1593 {
1594 struct drm_connector *connector = &vc4_hdmi->connector;
1595 struct platform_device *pdev = vc4_hdmi->pdev;
1596 int ret;
1597
1598 if (vc4_hdmi->variant->external_irq_controller) {
1599 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1600 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1601
1602 ret = request_threaded_irq(hpd_con,
1603 NULL,
1604 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1605 "vc4 hdmi hpd connected", vc4_hdmi);
1606 if (ret)
1607 return ret;
1608
1609 ret = request_threaded_irq(hpd_rm,
1610 NULL,
1611 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1612 "vc4 hdmi hpd disconnected", vc4_hdmi);
1613 if (ret) {
1614 free_irq(hpd_con, vc4_hdmi);
1615 return ret;
1616 }
1617
1618 connector->polled = DRM_CONNECTOR_POLL_HPD;
1619 }
1620
1621 return 0;
1622 }
1623
vc4_hdmi_hotplug_exit(struct vc4_hdmi * vc4_hdmi)1624 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1625 {
1626 struct platform_device *pdev = vc4_hdmi->pdev;
1627
1628 if (vc4_hdmi->variant->external_irq_controller) {
1629 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1630 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1631 }
1632 }
1633
1634 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_rx_thread(int irq,void * priv)1635 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1636 {
1637 struct vc4_hdmi *vc4_hdmi = priv;
1638
1639 if (vc4_hdmi->cec_rx_msg.len)
1640 cec_received_msg(vc4_hdmi->cec_adap,
1641 &vc4_hdmi->cec_rx_msg);
1642
1643 return IRQ_HANDLED;
1644 }
1645
vc4_cec_irq_handler_tx_thread(int irq,void * priv)1646 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1647 {
1648 struct vc4_hdmi *vc4_hdmi = priv;
1649
1650 if (vc4_hdmi->cec_tx_ok) {
1651 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1652 0, 0, 0, 0);
1653 } else {
1654 /*
1655 * This CEC implementation makes 1 retry, so if we
1656 * get a NACK, then that means it made 2 attempts.
1657 */
1658 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1659 0, 2, 0, 0);
1660 }
1661 return IRQ_HANDLED;
1662 }
1663
vc4_cec_irq_handler_thread(int irq,void * priv)1664 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1665 {
1666 struct vc4_hdmi *vc4_hdmi = priv;
1667 irqreturn_t ret;
1668
1669 if (vc4_hdmi->cec_irq_was_rx)
1670 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1671 else
1672 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1673
1674 return ret;
1675 }
1676
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)1677 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1678 {
1679 struct drm_device *dev = vc4_hdmi->connector.dev;
1680 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1681 unsigned int i;
1682
1683 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1684 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1685
1686 if (msg->len > 16) {
1687 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1688 return;
1689 }
1690
1691 for (i = 0; i < msg->len; i += 4) {
1692 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1693
1694 msg->msg[i] = val & 0xff;
1695 msg->msg[i + 1] = (val >> 8) & 0xff;
1696 msg->msg[i + 2] = (val >> 16) & 0xff;
1697 msg->msg[i + 3] = (val >> 24) & 0xff;
1698 }
1699 }
1700
vc4_cec_irq_handler_tx_bare(int irq,void * priv)1701 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1702 {
1703 struct vc4_hdmi *vc4_hdmi = priv;
1704 u32 cntrl1;
1705
1706 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1707 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1708 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1709 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1710
1711 return IRQ_WAKE_THREAD;
1712 }
1713
vc4_cec_irq_handler_rx_bare(int irq,void * priv)1714 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1715 {
1716 struct vc4_hdmi *vc4_hdmi = priv;
1717 u32 cntrl1;
1718
1719 vc4_hdmi->cec_rx_msg.len = 0;
1720 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1721 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1722 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1723 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1724 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1725
1726 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1727
1728 return IRQ_WAKE_THREAD;
1729 }
1730
vc4_cec_irq_handler(int irq,void * priv)1731 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1732 {
1733 struct vc4_hdmi *vc4_hdmi = priv;
1734 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1735 irqreturn_t ret;
1736 u32 cntrl5;
1737
1738 if (!(stat & VC4_HDMI_CPU_CEC))
1739 return IRQ_NONE;
1740
1741 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1742 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1743 if (vc4_hdmi->cec_irq_was_rx)
1744 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1745 else
1746 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1747
1748 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1749 return ret;
1750 }
1751
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)1752 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1753 {
1754 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1755 /* clock period in microseconds */
1756 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1757 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1758
1759 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1760 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1761 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1762 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1763 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1764
1765 if (enable) {
1766 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1767 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1768 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1769 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1770 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1771 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1772 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1773 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1774 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1775 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1776 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1777 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1778 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1779 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1780 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1781 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1782 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1783 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1784 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1785
1786 if (!vc4_hdmi->variant->external_irq_controller)
1787 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1788 } else {
1789 if (!vc4_hdmi->variant->external_irq_controller)
1790 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1791 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1792 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1793 }
1794 return 0;
1795 }
1796
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)1797 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1798 {
1799 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1800
1801 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1802 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1803 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1804 return 0;
1805 }
1806
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)1807 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1808 u32 signal_free_time, struct cec_msg *msg)
1809 {
1810 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1811 struct drm_device *dev = vc4_hdmi->connector.dev;
1812 u32 val;
1813 unsigned int i;
1814
1815 if (msg->len > 16) {
1816 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1817 return -ENOMEM;
1818 }
1819
1820 for (i = 0; i < msg->len; i += 4)
1821 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1822 (msg->msg[i]) |
1823 (msg->msg[i + 1] << 8) |
1824 (msg->msg[i + 2] << 16) |
1825 (msg->msg[i + 3] << 24));
1826
1827 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1828 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1829 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1830 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1831 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1832 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1833
1834 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1835 return 0;
1836 }
1837
1838 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1839 .adap_enable = vc4_hdmi_cec_adap_enable,
1840 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1841 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1842 };
1843
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1844 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1845 {
1846 struct cec_connector_info conn_info;
1847 struct platform_device *pdev = vc4_hdmi->pdev;
1848 struct device *dev = &pdev->dev;
1849 u32 value;
1850 int ret;
1851
1852 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1853 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1854 return 0;
1855 }
1856
1857 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1858 vc4_hdmi,
1859 vc4_hdmi->variant->card_name,
1860 CEC_CAP_DEFAULTS |
1861 CEC_CAP_CONNECTOR_INFO, 1);
1862 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1863 if (ret < 0)
1864 return ret;
1865
1866 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1867 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1868
1869 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1870 /* Set the logical address to Unregistered */
1871 value |= VC4_HDMI_CEC_ADDR_MASK;
1872 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1873
1874 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1875
1876 if (vc4_hdmi->variant->external_irq_controller) {
1877 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1878 vc4_cec_irq_handler_rx_bare,
1879 vc4_cec_irq_handler_rx_thread, 0,
1880 "vc4 hdmi cec rx", vc4_hdmi);
1881 if (ret)
1882 goto err_delete_cec_adap;
1883
1884 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1885 vc4_cec_irq_handler_tx_bare,
1886 vc4_cec_irq_handler_tx_thread, 0,
1887 "vc4 hdmi cec tx", vc4_hdmi);
1888 if (ret)
1889 goto err_remove_cec_rx_handler;
1890 } else {
1891 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1892
1893 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1894 vc4_cec_irq_handler,
1895 vc4_cec_irq_handler_thread, 0,
1896 "vc4 hdmi cec", vc4_hdmi);
1897 if (ret)
1898 goto err_delete_cec_adap;
1899 }
1900
1901 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1902 if (ret < 0)
1903 goto err_remove_handlers;
1904
1905 return 0;
1906
1907 err_remove_handlers:
1908 if (vc4_hdmi->variant->external_irq_controller)
1909 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1910 else
1911 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1912
1913 err_remove_cec_rx_handler:
1914 if (vc4_hdmi->variant->external_irq_controller)
1915 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1916
1917 err_delete_cec_adap:
1918 cec_delete_adapter(vc4_hdmi->cec_adap);
1919
1920 return ret;
1921 }
1922
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1923 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1924 {
1925 struct platform_device *pdev = vc4_hdmi->pdev;
1926
1927 if (vc4_hdmi->variant->external_irq_controller) {
1928 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1929 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1930 } else {
1931 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1932 }
1933
1934 cec_unregister_adapter(vc4_hdmi->cec_adap);
1935 }
1936 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1937 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1938 {
1939 return 0;
1940 }
1941
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1942 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1943
1944 #endif
1945
vc4_hdmi_build_regset(struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)1946 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1947 struct debugfs_regset32 *regset,
1948 enum vc4_hdmi_regs reg)
1949 {
1950 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1951 struct debugfs_reg32 *regs, *new_regs;
1952 unsigned int count = 0;
1953 unsigned int i;
1954
1955 regs = kcalloc(variant->num_registers, sizeof(*regs),
1956 GFP_KERNEL);
1957 if (!regs)
1958 return -ENOMEM;
1959
1960 for (i = 0; i < variant->num_registers; i++) {
1961 const struct vc4_hdmi_register *field = &variant->registers[i];
1962
1963 if (field->reg != reg)
1964 continue;
1965
1966 regs[count].name = field->name;
1967 regs[count].offset = field->offset;
1968 count++;
1969 }
1970
1971 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1972 if (!new_regs)
1973 return -ENOMEM;
1974
1975 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1976 regset->regs = new_regs;
1977 regset->nregs = count;
1978
1979 return 0;
1980 }
1981
vc4_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)1982 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1983 {
1984 struct platform_device *pdev = vc4_hdmi->pdev;
1985 struct device *dev = &pdev->dev;
1986 int ret;
1987
1988 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1989 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1990 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1991
1992 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1993 if (IS_ERR(vc4_hdmi->hd_regs))
1994 return PTR_ERR(vc4_hdmi->hd_regs);
1995
1996 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1997 if (ret)
1998 return ret;
1999
2000 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2001 if (ret)
2002 return ret;
2003
2004 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2005 if (IS_ERR(vc4_hdmi->pixel_clock)) {
2006 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2007 if (ret != -EPROBE_DEFER)
2008 DRM_ERROR("Failed to get pixel clock\n");
2009 return ret;
2010 }
2011
2012 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2013 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2014 DRM_ERROR("Failed to get HDMI state machine clock\n");
2015 return PTR_ERR(vc4_hdmi->hsm_clock);
2016 }
2017 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2018 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2019
2020 return 0;
2021 }
2022
vc5_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)2023 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2024 {
2025 struct platform_device *pdev = vc4_hdmi->pdev;
2026 struct device *dev = &pdev->dev;
2027 struct resource *res;
2028
2029 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2030 if (!res)
2031 return -ENODEV;
2032
2033 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2034 resource_size(res));
2035 if (!vc4_hdmi->hdmicore_regs)
2036 return -ENOMEM;
2037
2038 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2039 if (!res)
2040 return -ENODEV;
2041
2042 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2043 if (!vc4_hdmi->hd_regs)
2044 return -ENOMEM;
2045
2046 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2047 if (!res)
2048 return -ENODEV;
2049
2050 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2051 if (!vc4_hdmi->cec_regs)
2052 return -ENOMEM;
2053
2054 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2055 if (!res)
2056 return -ENODEV;
2057
2058 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2059 if (!vc4_hdmi->csc_regs)
2060 return -ENOMEM;
2061
2062 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2063 if (!res)
2064 return -ENODEV;
2065
2066 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2067 if (!vc4_hdmi->dvp_regs)
2068 return -ENOMEM;
2069
2070 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2071 if (!res)
2072 return -ENODEV;
2073
2074 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2075 if (!vc4_hdmi->phy_regs)
2076 return -ENOMEM;
2077
2078 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2079 if (!res)
2080 return -ENODEV;
2081
2082 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2083 if (!vc4_hdmi->ram_regs)
2084 return -ENOMEM;
2085
2086 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2087 if (!res)
2088 return -ENODEV;
2089
2090 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2091 if (!vc4_hdmi->rm_regs)
2092 return -ENOMEM;
2093
2094 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2095 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2096 DRM_ERROR("Failed to get HDMI state machine clock\n");
2097 return PTR_ERR(vc4_hdmi->hsm_clock);
2098 }
2099
2100 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2101 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2102 DRM_ERROR("Failed to get pixel bvb clock\n");
2103 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2104 }
2105
2106 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2107 if (IS_ERR(vc4_hdmi->audio_clock)) {
2108 DRM_ERROR("Failed to get audio clock\n");
2109 return PTR_ERR(vc4_hdmi->audio_clock);
2110 }
2111
2112 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2113 if (IS_ERR(vc4_hdmi->cec_clock)) {
2114 DRM_ERROR("Failed to get CEC clock\n");
2115 return PTR_ERR(vc4_hdmi->cec_clock);
2116 }
2117
2118 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2119 if (IS_ERR(vc4_hdmi->reset)) {
2120 DRM_ERROR("Failed to get HDMI reset line\n");
2121 return PTR_ERR(vc4_hdmi->reset);
2122 }
2123
2124 return 0;
2125 }
2126
vc4_hdmi_runtime_suspend(struct device * dev)2127 static int vc4_hdmi_runtime_suspend(struct device *dev)
2128 {
2129 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2130
2131 clk_disable_unprepare(vc4_hdmi->hsm_clock);
2132
2133 return 0;
2134 }
2135
vc4_hdmi_runtime_resume(struct device * dev)2136 static int vc4_hdmi_runtime_resume(struct device *dev)
2137 {
2138 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2139 int ret;
2140
2141 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2142 if (ret)
2143 return ret;
2144
2145 return 0;
2146 }
2147
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)2148 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2149 {
2150 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2151 struct platform_device *pdev = to_platform_device(dev);
2152 struct drm_device *drm = dev_get_drvdata(master);
2153 struct vc4_hdmi *vc4_hdmi;
2154 struct drm_encoder *encoder;
2155 struct device_node *ddc_node;
2156 int ret;
2157
2158 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2159 if (!vc4_hdmi)
2160 return -ENOMEM;
2161 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2162
2163 dev_set_drvdata(dev, vc4_hdmi);
2164 encoder = &vc4_hdmi->encoder.base.base;
2165 vc4_hdmi->encoder.base.type = variant->encoder_type;
2166 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2167 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2168 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2169 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2170 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2171 vc4_hdmi->pdev = pdev;
2172 vc4_hdmi->variant = variant;
2173
2174 ret = variant->init_resources(vc4_hdmi);
2175 if (ret)
2176 return ret;
2177
2178 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2179 if (!ddc_node) {
2180 DRM_ERROR("Failed to find ddc node in device tree\n");
2181 return -ENODEV;
2182 }
2183
2184 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2185 of_node_put(ddc_node);
2186 if (!vc4_hdmi->ddc) {
2187 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2188 return -EPROBE_DEFER;
2189 }
2190
2191 /* Only use the GPIO HPD pin if present in the DT, otherwise
2192 * we'll use the HDMI core's register.
2193 */
2194 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2195 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2196 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2197 goto err_put_ddc;
2198 }
2199
2200 vc4_hdmi->disable_wifi_frequencies =
2201 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2202
2203 if (variant->max_pixel_clock == 600000000) {
2204 struct vc4_dev *vc4 = to_vc4_dev(drm);
2205 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2206
2207 if (max_rate < 550000000)
2208 vc4_hdmi->disable_4kp60 = true;
2209 }
2210
2211 /*
2212 * If we boot without any cable connected to the HDMI connector,
2213 * the firmware will skip the HSM initialization and leave it
2214 * with a rate of 0, resulting in a bus lockup when we're
2215 * accessing the registers even if it's enabled.
2216 *
2217 * Let's put a sensible default at runtime_resume so that we
2218 * don't end up in this situation.
2219 */
2220 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2221 if (ret)
2222 goto err_put_ddc;
2223
2224 pm_runtime_enable(dev);
2225
2226 /*
2227 * We need to have the device powered up at this point to call
2228 * our reset hook and for the CEC init.
2229 */
2230 ret = pm_runtime_resume_and_get(dev);
2231 if (ret)
2232 goto err_disable_runtime_pm;
2233
2234 if (vc4_hdmi->variant->reset)
2235 vc4_hdmi->variant->reset(vc4_hdmi);
2236
2237 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2238 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2239 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2240 clk_prepare_enable(vc4_hdmi->pixel_clock);
2241 clk_prepare_enable(vc4_hdmi->hsm_clock);
2242 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2243 }
2244
2245 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2246 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2247
2248 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2249 if (ret)
2250 goto err_destroy_encoder;
2251
2252 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2253 if (ret)
2254 goto err_destroy_conn;
2255
2256 ret = vc4_hdmi_cec_init(vc4_hdmi);
2257 if (ret)
2258 goto err_free_hotplug;
2259
2260 ret = vc4_hdmi_audio_init(vc4_hdmi);
2261 if (ret)
2262 goto err_free_cec;
2263
2264 vc4_debugfs_add_file(drm, variant->debugfs_name,
2265 vc4_hdmi_debugfs_regs,
2266 vc4_hdmi);
2267
2268 pm_runtime_put_sync(dev);
2269
2270 return 0;
2271
2272 err_free_cec:
2273 vc4_hdmi_cec_exit(vc4_hdmi);
2274 err_free_hotplug:
2275 vc4_hdmi_hotplug_exit(vc4_hdmi);
2276 err_destroy_conn:
2277 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2278 err_destroy_encoder:
2279 drm_encoder_cleanup(encoder);
2280 pm_runtime_put_sync(dev);
2281 err_disable_runtime_pm:
2282 pm_runtime_disable(dev);
2283 err_put_ddc:
2284 put_device(&vc4_hdmi->ddc->dev);
2285
2286 return ret;
2287 }
2288
vc4_hdmi_unbind(struct device * dev,struct device * master,void * data)2289 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2290 void *data)
2291 {
2292 struct vc4_hdmi *vc4_hdmi;
2293
2294 /*
2295 * ASoC makes it a bit hard to retrieve a pointer to the
2296 * vc4_hdmi structure. Registering the card will overwrite our
2297 * device drvdata with a pointer to the snd_soc_card structure,
2298 * which can then be used to retrieve whatever drvdata we want
2299 * to associate.
2300 *
2301 * However, that doesn't fly in the case where we wouldn't
2302 * register an ASoC card (because of an old DT that is missing
2303 * the dmas properties for example), then the card isn't
2304 * registered and the device drvdata wouldn't be set.
2305 *
2306 * We can deal with both cases by making sure a snd_soc_card
2307 * pointer and a vc4_hdmi structure are pointing to the same
2308 * memory address, so we can treat them indistinctly without any
2309 * issue.
2310 */
2311 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2312 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2313 vc4_hdmi = dev_get_drvdata(dev);
2314
2315 kfree(vc4_hdmi->hdmi_regset.regs);
2316 kfree(vc4_hdmi->hd_regset.regs);
2317
2318 vc4_hdmi_audio_exit(vc4_hdmi);
2319 vc4_hdmi_cec_exit(vc4_hdmi);
2320 vc4_hdmi_hotplug_exit(vc4_hdmi);
2321 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2322 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2323
2324 pm_runtime_disable(dev);
2325
2326 put_device(&vc4_hdmi->ddc->dev);
2327 }
2328
2329 static const struct component_ops vc4_hdmi_ops = {
2330 .bind = vc4_hdmi_bind,
2331 .unbind = vc4_hdmi_unbind,
2332 };
2333
vc4_hdmi_dev_probe(struct platform_device * pdev)2334 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2335 {
2336 return component_add(&pdev->dev, &vc4_hdmi_ops);
2337 }
2338
vc4_hdmi_dev_remove(struct platform_device * pdev)2339 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2340 {
2341 component_del(&pdev->dev, &vc4_hdmi_ops);
2342 return 0;
2343 }
2344
2345 static const struct vc4_hdmi_variant bcm2835_variant = {
2346 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2347 .debugfs_name = "hdmi_regs",
2348 .card_name = "vc4-hdmi",
2349 .max_pixel_clock = 162000000,
2350 .registers = vc4_hdmi_fields,
2351 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
2352
2353 .init_resources = vc4_hdmi_init_resources,
2354 .csc_setup = vc4_hdmi_csc_setup,
2355 .reset = vc4_hdmi_reset,
2356 .set_timings = vc4_hdmi_set_timings,
2357 .phy_init = vc4_hdmi_phy_init,
2358 .phy_disable = vc4_hdmi_phy_disable,
2359 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
2360 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
2361 .channel_map = vc4_hdmi_channel_map,
2362 .supports_hdr = false,
2363 };
2364
2365 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2366 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2367 .debugfs_name = "hdmi0_regs",
2368 .card_name = "vc4-hdmi-0",
2369 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2370 .registers = vc5_hdmi_hdmi0_fields,
2371 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2372 .phy_lane_mapping = {
2373 PHY_LANE_0,
2374 PHY_LANE_1,
2375 PHY_LANE_2,
2376 PHY_LANE_CK,
2377 },
2378 .unsupported_odd_h_timings = true,
2379 .external_irq_controller = true,
2380
2381 .init_resources = vc5_hdmi_init_resources,
2382 .csc_setup = vc5_hdmi_csc_setup,
2383 .reset = vc5_hdmi_reset,
2384 .set_timings = vc5_hdmi_set_timings,
2385 .phy_init = vc5_hdmi_phy_init,
2386 .phy_disable = vc5_hdmi_phy_disable,
2387 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2388 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2389 .channel_map = vc5_hdmi_channel_map,
2390 .supports_hdr = true,
2391 };
2392
2393 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2394 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
2395 .debugfs_name = "hdmi1_regs",
2396 .card_name = "vc4-hdmi-1",
2397 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2398 .registers = vc5_hdmi_hdmi1_fields,
2399 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2400 .phy_lane_mapping = {
2401 PHY_LANE_1,
2402 PHY_LANE_0,
2403 PHY_LANE_CK,
2404 PHY_LANE_2,
2405 },
2406 .unsupported_odd_h_timings = true,
2407 .external_irq_controller = true,
2408
2409 .init_resources = vc5_hdmi_init_resources,
2410 .csc_setup = vc5_hdmi_csc_setup,
2411 .reset = vc5_hdmi_reset,
2412 .set_timings = vc5_hdmi_set_timings,
2413 .phy_init = vc5_hdmi_phy_init,
2414 .phy_disable = vc5_hdmi_phy_disable,
2415 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2416 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2417 .channel_map = vc5_hdmi_channel_map,
2418 .supports_hdr = true,
2419 };
2420
2421 static const struct of_device_id vc4_hdmi_dt_match[] = {
2422 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2423 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2424 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2425 {}
2426 };
2427
2428 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2429 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2430 vc4_hdmi_runtime_resume,
2431 NULL)
2432 };
2433
2434 struct platform_driver vc4_hdmi_driver = {
2435 .probe = vc4_hdmi_dev_probe,
2436 .remove = vc4_hdmi_dev_remove,
2437 .driver = {
2438 .name = "vc4_hdmi",
2439 .of_match_table = vc4_hdmi_dt_match,
2440 .pm = &vc4_hdmi_pm_ops,
2441 },
2442 };
2443