1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMD MP2 PCIe communication driver
4 * Copyright 2020 Advanced Micro Devices, Inc.
5 *
6 * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
7 * Sandeep Singh <Sandeep.singh@amd.com>
8 */
9
10 #include <linux/bitops.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmi.h>
14 #include <linux/interrupt.h>
15 #include <linux/io-64-nonatomic-lo-hi.h>
16 #include <linux/iopoll.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19
20 #include "amd_sfh_pcie.h"
21
22 #define DRIVER_NAME "pcie_mp2_amd"
23 #define DRIVER_DESC "AMD(R) PCIe MP2 Communication Driver"
24
25 #define ACEL_EN BIT(0)
26 #define GYRO_EN BIT(1)
27 #define MAGNO_EN BIT(2)
28 #define HPD_EN BIT(16)
29 #define ALS_EN BIT(19)
30
31 static int sensor_mask_override = -1;
32 module_param_named(sensor_mask, sensor_mask_override, int, 0444);
33 MODULE_PARM_DESC(sensor_mask, "override the detected sensors mask");
34
amd_sfh_wait_response_v2(struct amd_mp2_dev * mp2,u8 sid,u32 sensor_sts)35 static int amd_sfh_wait_response_v2(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts)
36 {
37 union cmd_response cmd_resp;
38
39 /* Get response with status within a max of 1600 ms timeout */
40 if (!readl_poll_timeout(mp2->mmio + AMD_P2C_MSG(0), cmd_resp.resp,
41 (cmd_resp.response_v2.response == sensor_sts &&
42 cmd_resp.response_v2.status == 0 && (sid == 0xff ||
43 cmd_resp.response_v2.sensor_id == sid)), 500, 1600000))
44 return cmd_resp.response_v2.response;
45
46 return SENSOR_DISABLED;
47 }
48
amd_start_sensor_v2(struct amd_mp2_dev * privdata,struct amd_mp2_sensor_info info)49 static void amd_start_sensor_v2(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info)
50 {
51 union sfh_cmd_base cmd_base;
52
53 cmd_base.ul = 0;
54 cmd_base.cmd_v2.cmd_id = ENABLE_SENSOR;
55 cmd_base.cmd_v2.period = info.period;
56 cmd_base.cmd_v2.sensor_id = info.sensor_idx;
57 cmd_base.cmd_v2.length = 16;
58
59 if (info.sensor_idx == als_idx)
60 cmd_base.cmd_v2.mem_type = USE_C2P_REG;
61
62 writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG1);
63 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
64 }
65
amd_stop_sensor_v2(struct amd_mp2_dev * privdata,u16 sensor_idx)66 static void amd_stop_sensor_v2(struct amd_mp2_dev *privdata, u16 sensor_idx)
67 {
68 union sfh_cmd_base cmd_base;
69
70 cmd_base.ul = 0;
71 cmd_base.cmd_v2.cmd_id = DISABLE_SENSOR;
72 cmd_base.cmd_v2.period = 0;
73 cmd_base.cmd_v2.sensor_id = sensor_idx;
74 cmd_base.cmd_v2.length = 16;
75
76 writeq(0x0, privdata->mmio + AMD_C2P_MSG1);
77 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
78 }
79
amd_stop_all_sensor_v2(struct amd_mp2_dev * privdata)80 static void amd_stop_all_sensor_v2(struct amd_mp2_dev *privdata)
81 {
82 union sfh_cmd_base cmd_base;
83
84 cmd_base.cmd_v2.cmd_id = STOP_ALL_SENSORS;
85 cmd_base.cmd_v2.period = 0;
86 cmd_base.cmd_v2.sensor_id = 0;
87
88 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
89 }
90
amd_sfh_clear_intr_v2(struct amd_mp2_dev * privdata)91 static void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata)
92 {
93 if (readl(privdata->mmio + AMD_P2C_MSG(4))) {
94 writel(0, privdata->mmio + AMD_P2C_MSG(4));
95 writel(0xf, privdata->mmio + AMD_P2C_MSG(5));
96 }
97 }
98
amd_sfh_clear_intr(struct amd_mp2_dev * privdata)99 static void amd_sfh_clear_intr(struct amd_mp2_dev *privdata)
100 {
101 if (privdata->mp2_ops->clear_intr)
102 privdata->mp2_ops->clear_intr(privdata);
103 }
104
amd_sfh_irq_handler(int irq,void * data)105 static irqreturn_t amd_sfh_irq_handler(int irq, void *data)
106 {
107 amd_sfh_clear_intr(data);
108
109 return IRQ_HANDLED;
110 }
111
amd_sfh_irq_init_v2(struct amd_mp2_dev * privdata)112 static int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata)
113 {
114 int rc;
115
116 pci_intx(privdata->pdev, true);
117
118 rc = devm_request_irq(&privdata->pdev->dev, privdata->pdev->irq,
119 amd_sfh_irq_handler, 0, DRIVER_NAME, privdata);
120 if (rc) {
121 dev_err(&privdata->pdev->dev, "failed to request irq %d err=%d\n",
122 privdata->pdev->irq, rc);
123 return rc;
124 }
125
126 return 0;
127 }
128
amd_sfh_dis_sts_v2(struct amd_mp2_dev * privdata)129 static int amd_sfh_dis_sts_v2(struct amd_mp2_dev *privdata)
130 {
131 return (readl(privdata->mmio + AMD_P2C_MSG(1)) &
132 SENSOR_DISCOVERY_STATUS_MASK) >> SENSOR_DISCOVERY_STATUS_SHIFT;
133 }
134
amd_start_sensor(struct amd_mp2_dev * privdata,struct amd_mp2_sensor_info info)135 void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info)
136 {
137 union sfh_cmd_param cmd_param;
138 union sfh_cmd_base cmd_base;
139
140 /* fill up command register */
141 memset(&cmd_base, 0, sizeof(cmd_base));
142 cmd_base.s.cmd_id = ENABLE_SENSOR;
143 cmd_base.s.period = info.period;
144 cmd_base.s.sensor_id = info.sensor_idx;
145
146 /* fill up command param register */
147 memset(&cmd_param, 0, sizeof(cmd_param));
148 cmd_param.s.buf_layout = 1;
149 cmd_param.s.buf_length = 16;
150
151 writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG2);
152 writel(cmd_param.ul, privdata->mmio + AMD_C2P_MSG1);
153 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
154 }
155
amd_stop_sensor(struct amd_mp2_dev * privdata,u16 sensor_idx)156 void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx)
157 {
158 union sfh_cmd_base cmd_base;
159
160 /* fill up command register */
161 memset(&cmd_base, 0, sizeof(cmd_base));
162 cmd_base.s.cmd_id = DISABLE_SENSOR;
163 cmd_base.s.period = 0;
164 cmd_base.s.sensor_id = sensor_idx;
165
166 writeq(0x0, privdata->mmio + AMD_C2P_MSG2);
167 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
168 }
169
amd_stop_all_sensors(struct amd_mp2_dev * privdata)170 void amd_stop_all_sensors(struct amd_mp2_dev *privdata)
171 {
172 union sfh_cmd_base cmd_base;
173
174 /* fill up command register */
175 memset(&cmd_base, 0, sizeof(cmd_base));
176 cmd_base.s.cmd_id = STOP_ALL_SENSORS;
177 cmd_base.s.period = 0;
178 cmd_base.s.sensor_id = 0;
179
180 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
181 }
182
183 static const struct dmi_system_id dmi_sensor_mask_overrides[] = {
184 {
185 .matches = {
186 DMI_MATCH(DMI_PRODUCT_NAME, "HP ENVY x360 Convertible 13-ag0xxx"),
187 },
188 .driver_data = (void *)(ACEL_EN | MAGNO_EN),
189 },
190 {
191 .matches = {
192 DMI_MATCH(DMI_PRODUCT_NAME, "HP ENVY x360 Convertible 15-cp0xxx"),
193 },
194 .driver_data = (void *)(ACEL_EN | MAGNO_EN),
195 },
196 { }
197 };
198
amd_mp2_get_sensor_num(struct amd_mp2_dev * privdata,u8 * sensor_id)199 int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id)
200 {
201 int activestatus, num_of_sensors = 0;
202 const struct dmi_system_id *dmi_id;
203
204 if (sensor_mask_override == -1) {
205 dmi_id = dmi_first_match(dmi_sensor_mask_overrides);
206 if (dmi_id)
207 sensor_mask_override = (long)dmi_id->driver_data;
208 }
209
210 if (sensor_mask_override >= 0) {
211 activestatus = sensor_mask_override;
212 } else {
213 activestatus = privdata->mp2_acs >> 4;
214 }
215
216 if (ACEL_EN & activestatus)
217 sensor_id[num_of_sensors++] = accel_idx;
218
219 if (GYRO_EN & activestatus)
220 sensor_id[num_of_sensors++] = gyro_idx;
221
222 if (MAGNO_EN & activestatus)
223 sensor_id[num_of_sensors++] = mag_idx;
224
225 if (ALS_EN & activestatus)
226 sensor_id[num_of_sensors++] = als_idx;
227
228 if (HPD_EN & activestatus)
229 sensor_id[num_of_sensors++] = HPD_IDX;
230
231 return num_of_sensors;
232 }
233
amd_mp2_pci_remove(void * privdata)234 static void amd_mp2_pci_remove(void *privdata)
235 {
236 struct amd_mp2_dev *mp2 = privdata;
237 amd_sfh_hid_client_deinit(privdata);
238 mp2->mp2_ops->stop_all(mp2);
239 pci_intx(mp2->pdev, false);
240 amd_sfh_clear_intr(mp2);
241 }
242
243 static const struct amd_mp2_ops amd_sfh_ops_v2 = {
244 .start = amd_start_sensor_v2,
245 .stop = amd_stop_sensor_v2,
246 .stop_all = amd_stop_all_sensor_v2,
247 .response = amd_sfh_wait_response_v2,
248 .clear_intr = amd_sfh_clear_intr_v2,
249 .init_intr = amd_sfh_irq_init_v2,
250 .discovery_status = amd_sfh_dis_sts_v2,
251 };
252
253 static const struct amd_mp2_ops amd_sfh_ops = {
254 .start = amd_start_sensor,
255 .stop = amd_stop_sensor,
256 .stop_all = amd_stop_all_sensors,
257 };
258
mp2_select_ops(struct amd_mp2_dev * privdata)259 static void mp2_select_ops(struct amd_mp2_dev *privdata)
260 {
261 u8 acs;
262
263 privdata->mp2_acs = readl(privdata->mmio + AMD_P2C_MSG3);
264 acs = privdata->mp2_acs & GENMASK(3, 0);
265
266 switch (acs) {
267 case V2_STATUS:
268 privdata->mp2_ops = &amd_sfh_ops_v2;
269 break;
270 default:
271 privdata->mp2_ops = &amd_sfh_ops;
272 break;
273 }
274 }
275
amd_sfh_irq_init(struct amd_mp2_dev * privdata)276 static int amd_sfh_irq_init(struct amd_mp2_dev *privdata)
277 {
278 if (privdata->mp2_ops->init_intr)
279 return privdata->mp2_ops->init_intr(privdata);
280
281 return 0;
282 }
283
284 static const struct dmi_system_id dmi_nodevs[] = {
285 {
286 /*
287 * Google Chromebooks use Chrome OS Embedded Controller Sensor
288 * Hub instead of Sensor Hub Fusion and leaves MP2
289 * uninitialized, which disables all functionalities, even
290 * including the registers necessary for feature detections.
291 */
292 .matches = {
293 DMI_MATCH(DMI_SYS_VENDOR, "Google"),
294 },
295 },
296 { }
297 };
298
amd_mp2_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)299 static int amd_mp2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
300 {
301 struct amd_mp2_dev *privdata;
302 int rc;
303
304 if (dmi_first_match(dmi_nodevs))
305 return -ENODEV;
306
307 privdata = devm_kzalloc(&pdev->dev, sizeof(*privdata), GFP_KERNEL);
308 if (!privdata)
309 return -ENOMEM;
310
311 privdata->pdev = pdev;
312 pci_set_drvdata(pdev, privdata);
313 rc = pcim_enable_device(pdev);
314 if (rc)
315 return rc;
316
317 rc = pcim_iomap_regions(pdev, BIT(2), DRIVER_NAME);
318 if (rc)
319 return rc;
320
321 privdata->mmio = pcim_iomap_table(pdev)[2];
322 pci_set_master(pdev);
323 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
324 if (rc) {
325 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
326 return rc;
327 }
328
329 privdata->cl_data = devm_kzalloc(&pdev->dev, sizeof(struct amdtp_cl_data), GFP_KERNEL);
330 if (!privdata->cl_data)
331 return -ENOMEM;
332
333 mp2_select_ops(privdata);
334
335 rc = amd_sfh_irq_init(privdata);
336 if (rc) {
337 dev_err(&pdev->dev, "amd_sfh_irq_init failed\n");
338 return rc;
339 }
340
341 rc = amd_sfh_hid_client_init(privdata);
342 if (rc) {
343 amd_sfh_clear_intr(privdata);
344 if (rc != -EOPNOTSUPP)
345 dev_err(&pdev->dev, "amd_sfh_hid_client_init failed\n");
346 return rc;
347 }
348
349 amd_sfh_clear_intr(privdata);
350
351 return devm_add_action_or_reset(&pdev->dev, amd_mp2_pci_remove, privdata);
352 }
353
amd_sfh_shutdown(struct pci_dev * pdev)354 static void amd_sfh_shutdown(struct pci_dev *pdev)
355 {
356 struct amd_mp2_dev *mp2 = pci_get_drvdata(pdev);
357
358 if (mp2 && mp2->mp2_ops)
359 mp2->mp2_ops->stop_all(mp2);
360 }
361
amd_mp2_pci_resume(struct device * dev)362 static int __maybe_unused amd_mp2_pci_resume(struct device *dev)
363 {
364 struct pci_dev *pdev = to_pci_dev(dev);
365 struct amd_mp2_dev *mp2 = pci_get_drvdata(pdev);
366 struct amdtp_cl_data *cl_data = mp2->cl_data;
367 struct amd_mp2_sensor_info info;
368 int i, status;
369
370 for (i = 0; i < cl_data->num_hid_devices; i++) {
371 if (cl_data->sensor_sts[i] == SENSOR_DISABLED) {
372 info.period = AMD_SFH_IDLE_LOOP;
373 info.sensor_idx = cl_data->sensor_idx[i];
374 info.dma_address = cl_data->sensor_dma_addr[i];
375 mp2->mp2_ops->start(mp2, info);
376 status = amd_sfh_wait_for_response
377 (mp2, cl_data->sensor_idx[i], SENSOR_ENABLED);
378 if (status == SENSOR_ENABLED)
379 cl_data->sensor_sts[i] = SENSOR_ENABLED;
380 dev_dbg(dev, "resume sid 0x%x status 0x%x\n",
381 cl_data->sensor_idx[i], cl_data->sensor_sts[i]);
382 }
383 }
384
385 schedule_delayed_work(&cl_data->work_buffer, msecs_to_jiffies(AMD_SFH_IDLE_LOOP));
386 amd_sfh_clear_intr(mp2);
387
388 return 0;
389 }
390
amd_mp2_pci_suspend(struct device * dev)391 static int __maybe_unused amd_mp2_pci_suspend(struct device *dev)
392 {
393 struct pci_dev *pdev = to_pci_dev(dev);
394 struct amd_mp2_dev *mp2 = pci_get_drvdata(pdev);
395 struct amdtp_cl_data *cl_data = mp2->cl_data;
396 int i, status;
397
398 for (i = 0; i < cl_data->num_hid_devices; i++) {
399 if (cl_data->sensor_idx[i] != HPD_IDX &&
400 cl_data->sensor_sts[i] == SENSOR_ENABLED) {
401 mp2->mp2_ops->stop(mp2, cl_data->sensor_idx[i]);
402 status = amd_sfh_wait_for_response
403 (mp2, cl_data->sensor_idx[i], SENSOR_DISABLED);
404 if (status != SENSOR_ENABLED)
405 cl_data->sensor_sts[i] = SENSOR_DISABLED;
406 dev_dbg(dev, "suspend sid 0x%x status 0x%x\n",
407 cl_data->sensor_idx[i], cl_data->sensor_sts[i]);
408 }
409 }
410
411 cancel_delayed_work_sync(&cl_data->work_buffer);
412 amd_sfh_clear_intr(mp2);
413
414 return 0;
415 }
416
417 static SIMPLE_DEV_PM_OPS(amd_mp2_pm_ops, amd_mp2_pci_suspend,
418 amd_mp2_pci_resume);
419
420 static const struct pci_device_id amd_mp2_pci_tbl[] = {
421 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MP2) },
422 { }
423 };
424 MODULE_DEVICE_TABLE(pci, amd_mp2_pci_tbl);
425
426 static struct pci_driver amd_mp2_pci_driver = {
427 .name = DRIVER_NAME,
428 .id_table = amd_mp2_pci_tbl,
429 .probe = amd_mp2_pci_probe,
430 .driver.pm = &amd_mp2_pm_ops,
431 .shutdown = amd_sfh_shutdown,
432 };
433 module_pci_driver(amd_mp2_pci_driver);
434
435 MODULE_DESCRIPTION(DRIVER_DESC);
436 MODULE_LICENSE("Dual BSD/GPL");
437 MODULE_AUTHOR("Shyam Sundar S K <Shyam-sundar.S-k@amd.com>");
438 MODULE_AUTHOR("Sandeep Singh <Sandeep.singh@amd.com>");
439