1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
4 * processor hardware monitoring
5 *
6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
8 *
9 * Implementation notes:
10 * - CCD register address information as well as the calculation to
11 * convert raw register values is from https://github.com/ocerman/zenpower.
12 * The information is not confirmed from chip datasheets, but experiments
13 * suggest that it provides reasonable temperature values.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/hwmon.h>
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pci_ids.h>
23 #include <asm/amd_nb.h>
24 #include <asm/processor.h>
25
26 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
27 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
28 MODULE_LICENSE("GPL");
29
30 static bool force;
31 module_param(force, bool, 0444);
32 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
33
34 /* Provide lock for writing to NB_SMU_IND_ADDR */
35 static DEFINE_MUTEX(nb_smu_ind_mutex);
36
37 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
39 #endif
40
41 /* CPUID function 0x80000001, ebx */
42 #define CPUID_PKGTYPE_MASK GENMASK(31, 28)
43 #define CPUID_PKGTYPE_F 0x00000000
44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
45
46 /* DRAM controller (PCI function 2) */
47 #define REG_DCT0_CONFIG_HIGH 0x094
48 #define DDR3_MODE BIT(8)
49
50 /* miscellaneous (PCI function 3) */
51 #define REG_HARDWARE_THERMAL_CONTROL 0x64
52 #define HTC_ENABLE BIT(0)
53
54 #define REG_REPORTED_TEMPERATURE 0xa4
55
56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
57 #define NB_CAP_HTC BIT(10)
58
59 /*
60 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
61 * and REG_REPORTED_TEMPERATURE have been moved to
62 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
63 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
64 */
65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
67
68 /* Common for Zen CPU families (Family 17h and 18h and 19h) */
69 #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800
70
71 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \
72 (offset) + ((x) * 4))
73 #define ZEN_CCD_TEMP_VALID BIT(11)
74 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
75
76 #define ZEN_CUR_TEMP_SHIFT 21
77 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
78 #define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16)
79
80 #define ZEN_SVI_BASE 0x0005A000
81
82 /* F17h thermal registers through SMN */
83 #define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc)
84 #define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
85 #define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
86 #define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
87
88 #define F17H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */
89 #define F17H_M01H_CFACTOR_ISOC 250000 /* 0.25A / LSB */
90 #define F17H_M31H_CFACTOR_ICORE 1000000 /* 1A / LSB */
91 #define F17H_M31H_CFACTOR_ISOC 310000 /* 0.31A / LSB */
92
93 /* F19h thermal registers through SMN */
94 #define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
95 #define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
96
97 #define F19H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */
98 #define F19H_M01H_CFACTOR_ISOC 310000 /* 0.31A / LSB */
99
100 /*
101 * AMD's Industrial processor 3255 supports temperature from -40 deg to 105 deg Celsius.
102 * Use the model name to identify 3255 CPUs and set a flag to display negative temperature.
103 * Do not round off to zero for negative Tctl or Tdie values if the flag is set
104 */
105 #define AMD_I3255_STR "3255"
106
107 struct k10temp_data {
108 struct pci_dev *pdev;
109 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
110 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
111 int temp_offset;
112 u32 temp_adjust_mask;
113 u32 show_temp;
114 bool is_zen;
115 u32 ccd_offset;
116 bool disp_negative;
117 };
118
119 #define TCTL_BIT 0
120 #define TDIE_BIT 1
121 #define TCCD_BIT(x) ((x) + 2)
122
123 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
124 #define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
125
126 struct tctl_offset {
127 u8 model;
128 char const *id;
129 int offset;
130 };
131
132 static const struct tctl_offset tctl_offset_table[] = {
133 { 0x17, "AMD Ryzen 5 1600X", 20000 },
134 { 0x17, "AMD Ryzen 7 1700X", 20000 },
135 { 0x17, "AMD Ryzen 7 1800X", 20000 },
136 { 0x17, "AMD Ryzen 7 2700X", 10000 },
137 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
138 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
139 };
140
read_htcreg_pci(struct pci_dev * pdev,u32 * regval)141 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
142 {
143 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
144 }
145
read_tempreg_pci(struct pci_dev * pdev,u32 * regval)146 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
147 {
148 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
149 }
150
amd_nb_index_read(struct pci_dev * pdev,unsigned int devfn,unsigned int base,int offset,u32 * val)151 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
152 unsigned int base, int offset, u32 *val)
153 {
154 mutex_lock(&nb_smu_ind_mutex);
155 pci_bus_write_config_dword(pdev->bus, devfn,
156 base, offset);
157 pci_bus_read_config_dword(pdev->bus, devfn,
158 base + 4, val);
159 mutex_unlock(&nb_smu_ind_mutex);
160 }
161
read_htcreg_nb_f15(struct pci_dev * pdev,u32 * regval)162 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
163 {
164 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
165 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
166 }
167
read_tempreg_nb_f15(struct pci_dev * pdev,u32 * regval)168 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
169 {
170 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
171 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
172 }
173
read_tempreg_nb_zen(struct pci_dev * pdev,u32 * regval)174 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
175 {
176 amd_smn_read(amd_pci_dev_to_node_id(pdev),
177 ZEN_REPORTED_TEMP_CTRL_BASE, regval);
178 }
179
get_raw_temp(struct k10temp_data * data)180 static long get_raw_temp(struct k10temp_data *data)
181 {
182 u32 regval;
183 long temp;
184
185 data->read_tempreg(data->pdev, ®val);
186 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
187 if ((regval & data->temp_adjust_mask) ||
188 (regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK)
189 temp -= 49000;
190 return temp;
191 }
192
193 static const char *k10temp_temp_label[] = {
194 "Tctl",
195 "Tdie",
196 "Tccd1",
197 "Tccd2",
198 "Tccd3",
199 "Tccd4",
200 "Tccd5",
201 "Tccd6",
202 "Tccd7",
203 "Tccd8",
204 };
205
k10temp_read_labels(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)206 static int k10temp_read_labels(struct device *dev,
207 enum hwmon_sensor_types type,
208 u32 attr, int channel, const char **str)
209 {
210 switch (type) {
211 case hwmon_temp:
212 *str = k10temp_temp_label[channel];
213 break;
214 default:
215 return -EOPNOTSUPP;
216 }
217 return 0;
218 }
219
k10temp_read_temp(struct device * dev,u32 attr,int channel,long * val)220 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
221 long *val)
222 {
223 struct k10temp_data *data = dev_get_drvdata(dev);
224 u32 regval;
225
226 switch (attr) {
227 case hwmon_temp_input:
228 switch (channel) {
229 case 0: /* Tctl */
230 *val = get_raw_temp(data);
231 if (*val < 0 && !data->disp_negative)
232 *val = 0;
233 break;
234 case 1: /* Tdie */
235 *val = get_raw_temp(data) - data->temp_offset;
236 if (*val < 0 && !data->disp_negative)
237 *val = 0;
238 break;
239 case 2 ... 9: /* Tccd{1-8} */
240 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
241 ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
242 ®val);
243 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
244 break;
245 default:
246 return -EOPNOTSUPP;
247 }
248 break;
249 case hwmon_temp_max:
250 *val = 70 * 1000;
251 break;
252 case hwmon_temp_crit:
253 data->read_htcreg(data->pdev, ®val);
254 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
255 break;
256 case hwmon_temp_crit_hyst:
257 data->read_htcreg(data->pdev, ®val);
258 *val = (((regval >> 16) & 0x7f)
259 - ((regval >> 24) & 0xf)) * 500 + 52000;
260 break;
261 default:
262 return -EOPNOTSUPP;
263 }
264 return 0;
265 }
266
k10temp_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)267 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
268 u32 attr, int channel, long *val)
269 {
270 switch (type) {
271 case hwmon_temp:
272 return k10temp_read_temp(dev, attr, channel, val);
273 default:
274 return -EOPNOTSUPP;
275 }
276 }
277
k10temp_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)278 static umode_t k10temp_is_visible(const void *_data,
279 enum hwmon_sensor_types type,
280 u32 attr, int channel)
281 {
282 const struct k10temp_data *data = _data;
283 struct pci_dev *pdev = data->pdev;
284 u32 reg;
285
286 switch (type) {
287 case hwmon_temp:
288 switch (attr) {
289 case hwmon_temp_input:
290 if (!HAVE_TEMP(data, channel))
291 return 0;
292 break;
293 case hwmon_temp_max:
294 if (channel || data->is_zen)
295 return 0;
296 break;
297 case hwmon_temp_crit:
298 case hwmon_temp_crit_hyst:
299 if (channel || !data->read_htcreg)
300 return 0;
301
302 pci_read_config_dword(pdev,
303 REG_NORTHBRIDGE_CAPABILITIES,
304 ®);
305 if (!(reg & NB_CAP_HTC))
306 return 0;
307
308 data->read_htcreg(data->pdev, ®);
309 if (!(reg & HTC_ENABLE))
310 return 0;
311 break;
312 case hwmon_temp_label:
313 /* Show temperature labels only on Zen CPUs */
314 if (!data->is_zen || !HAVE_TEMP(data, channel))
315 return 0;
316 break;
317 default:
318 return 0;
319 }
320 break;
321 default:
322 return 0;
323 }
324 return 0444;
325 }
326
has_erratum_319(struct pci_dev * pdev)327 static bool has_erratum_319(struct pci_dev *pdev)
328 {
329 u32 pkg_type, reg_dram_cfg;
330
331 if (boot_cpu_data.x86 != 0x10)
332 return false;
333
334 /*
335 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
336 * may be unreliable.
337 */
338 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
339 if (pkg_type == CPUID_PKGTYPE_F)
340 return true;
341 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
342 return false;
343
344 /* DDR3 memory implies socket AM3, which is good */
345 pci_bus_read_config_dword(pdev->bus,
346 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
347 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
348 if (reg_dram_cfg & DDR3_MODE)
349 return false;
350
351 /*
352 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
353 * memory. We blacklist all the cores which do exist in socket AM2+
354 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
355 * and AM3 formats, but that's the best we can do.
356 */
357 return boot_cpu_data.x86_model < 4 ||
358 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
359 }
360
361 static const struct hwmon_channel_info *k10temp_info[] = {
362 HWMON_CHANNEL_INFO(temp,
363 HWMON_T_INPUT | HWMON_T_MAX |
364 HWMON_T_CRIT | HWMON_T_CRIT_HYST |
365 HWMON_T_LABEL,
366 HWMON_T_INPUT | HWMON_T_LABEL,
367 HWMON_T_INPUT | HWMON_T_LABEL,
368 HWMON_T_INPUT | HWMON_T_LABEL,
369 HWMON_T_INPUT | HWMON_T_LABEL,
370 HWMON_T_INPUT | HWMON_T_LABEL,
371 HWMON_T_INPUT | HWMON_T_LABEL,
372 HWMON_T_INPUT | HWMON_T_LABEL,
373 HWMON_T_INPUT | HWMON_T_LABEL,
374 HWMON_T_INPUT | HWMON_T_LABEL),
375 NULL
376 };
377
378 static const struct hwmon_ops k10temp_hwmon_ops = {
379 .is_visible = k10temp_is_visible,
380 .read = k10temp_read,
381 .read_string = k10temp_read_labels,
382 };
383
384 static const struct hwmon_chip_info k10temp_chip_info = {
385 .ops = &k10temp_hwmon_ops,
386 .info = k10temp_info,
387 };
388
k10temp_get_ccd_support(struct pci_dev * pdev,struct k10temp_data * data,int limit)389 static void k10temp_get_ccd_support(struct pci_dev *pdev,
390 struct k10temp_data *data, int limit)
391 {
392 u32 regval;
393 int i;
394
395 for (i = 0; i < limit; i++) {
396 amd_smn_read(amd_pci_dev_to_node_id(pdev),
397 ZEN_CCD_TEMP(data->ccd_offset, i), ®val);
398 if (regval & ZEN_CCD_TEMP_VALID)
399 data->show_temp |= BIT(TCCD_BIT(i));
400 }
401 }
402
k10temp_probe(struct pci_dev * pdev,const struct pci_device_id * id)403 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
404 {
405 int unreliable = has_erratum_319(pdev);
406 struct device *dev = &pdev->dev;
407 struct k10temp_data *data;
408 struct device *hwmon_dev;
409 int i;
410
411 if (unreliable) {
412 if (!force) {
413 dev_err(dev,
414 "unreliable CPU thermal sensor; monitoring disabled\n");
415 return -ENODEV;
416 }
417 dev_warn(dev,
418 "unreliable CPU thermal sensor; check erratum 319\n");
419 }
420
421 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
422 if (!data)
423 return -ENOMEM;
424
425 data->pdev = pdev;
426 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */
427
428 if (boot_cpu_data.x86 == 0x17 &&
429 strstr(boot_cpu_data.x86_model_id, AMD_I3255_STR)) {
430 data->disp_negative = true;
431 }
432
433 if (boot_cpu_data.x86 == 0x15 &&
434 ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
435 (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
436 data->read_htcreg = read_htcreg_nb_f15;
437 data->read_tempreg = read_tempreg_nb_f15;
438 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
439 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
440 data->read_tempreg = read_tempreg_nb_zen;
441 data->is_zen = true;
442
443 switch (boot_cpu_data.x86_model) {
444 case 0x1: /* Zen */
445 case 0x8: /* Zen+ */
446 case 0x11: /* Zen APU */
447 case 0x18: /* Zen+ APU */
448 data->ccd_offset = 0x154;
449 k10temp_get_ccd_support(pdev, data, 4);
450 break;
451 case 0x31: /* Zen2 Threadripper */
452 case 0x60: /* Renoir */
453 case 0x68: /* Lucienne */
454 case 0x71: /* Zen2 */
455 data->ccd_offset = 0x154;
456 k10temp_get_ccd_support(pdev, data, 8);
457 break;
458 }
459 } else if (boot_cpu_data.x86 == 0x19) {
460 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
461 data->read_tempreg = read_tempreg_nb_zen;
462 data->is_zen = true;
463
464 switch (boot_cpu_data.x86_model) {
465 case 0x0 ... 0x1: /* Zen3 SP3/TR */
466 case 0x21: /* Zen3 Ryzen Desktop */
467 case 0x50 ... 0x5f: /* Green Sardine */
468 data->ccd_offset = 0x154;
469 k10temp_get_ccd_support(pdev, data, 8);
470 break;
471 case 0x40 ... 0x4f: /* Yellow Carp */
472 data->ccd_offset = 0x300;
473 k10temp_get_ccd_support(pdev, data, 8);
474 break;
475 }
476 } else {
477 data->read_htcreg = read_htcreg_pci;
478 data->read_tempreg = read_tempreg_pci;
479 }
480
481 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
482 const struct tctl_offset *entry = &tctl_offset_table[i];
483
484 if (boot_cpu_data.x86 == entry->model &&
485 strstr(boot_cpu_data.x86_model_id, entry->id)) {
486 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */
487 data->temp_offset = entry->offset;
488 break;
489 }
490 }
491
492 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
493 &k10temp_chip_info,
494 NULL);
495 return PTR_ERR_OR_ZERO(hwmon_dev);
496 }
497
498 static const struct pci_device_id k10temp_id_table[] = {
499 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
500 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
501 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
502 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
503 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
504 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
505 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
506 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
507 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
508 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
509 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
510 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
511 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
512 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
513 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
514 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
515 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
516 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
517 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
518 {}
519 };
520 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
521
522 static struct pci_driver k10temp_driver = {
523 .name = "k10temp",
524 .id_table = k10temp_id_table,
525 .probe = k10temp_probe,
526 };
527
528 module_pci_driver(k10temp_driver);
529