1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * LTC2992 - Dual Wide Range Power Monitor
4 *
5 * Copyright 2020 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/err.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/hwmon.h>
13 #include <linux/i2c.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
18
19 #define LTC2992_CTRLB 0x01
20 #define LTC2992_FAULT1 0x03
21 #define LTC2992_POWER1 0x05
22 #define LTC2992_POWER1_MAX 0x08
23 #define LTC2992_POWER1_MIN 0x0B
24 #define LTC2992_POWER1_MAX_THRESH 0x0E
25 #define LTC2992_POWER1_MIN_THRESH 0x11
26 #define LTC2992_DSENSE1 0x14
27 #define LTC2992_DSENSE1_MAX 0x16
28 #define LTC2992_DSENSE1_MIN 0x18
29 #define LTC2992_DSENSE1_MAX_THRESH 0x1A
30 #define LTC2992_DSENSE1_MIN_THRESH 0x1C
31 #define LTC2992_SENSE1 0x1E
32 #define LTC2992_SENSE1_MAX 0x20
33 #define LTC2992_SENSE1_MIN 0x22
34 #define LTC2992_SENSE1_MAX_THRESH 0x24
35 #define LTC2992_SENSE1_MIN_THRESH 0x26
36 #define LTC2992_G1 0x28
37 #define LTC2992_G1_MAX 0x2A
38 #define LTC2992_G1_MIN 0x2C
39 #define LTC2992_G1_MAX_THRESH 0x2E
40 #define LTC2992_G1_MIN_THRESH 0x30
41 #define LTC2992_FAULT2 0x35
42 #define LTC2992_G2 0x5A
43 #define LTC2992_G2_MAX 0x5C
44 #define LTC2992_G2_MIN 0x5E
45 #define LTC2992_G2_MAX_THRESH 0x60
46 #define LTC2992_G2_MIN_THRESH 0x62
47 #define LTC2992_G3 0x64
48 #define LTC2992_G3_MAX 0x66
49 #define LTC2992_G3_MIN 0x68
50 #define LTC2992_G3_MAX_THRESH 0x6A
51 #define LTC2992_G3_MIN_THRESH 0x6C
52 #define LTC2992_G4 0x6E
53 #define LTC2992_G4_MAX 0x70
54 #define LTC2992_G4_MIN 0x72
55 #define LTC2992_G4_MAX_THRESH 0x74
56 #define LTC2992_G4_MIN_THRESH 0x76
57 #define LTC2992_FAULT3 0x92
58 #define LTC2992_GPIO_STATUS 0x95
59 #define LTC2992_GPIO_IO_CTRL 0x96
60 #define LTC2992_GPIO_CTRL 0x97
61
62 #define LTC2992_POWER(x) (LTC2992_POWER1 + ((x) * 0x32))
63 #define LTC2992_POWER_MAX(x) (LTC2992_POWER1_MAX + ((x) * 0x32))
64 #define LTC2992_POWER_MIN(x) (LTC2992_POWER1_MIN + ((x) * 0x32))
65 #define LTC2992_POWER_MAX_THRESH(x) (LTC2992_POWER1_MAX_THRESH + ((x) * 0x32))
66 #define LTC2992_POWER_MIN_THRESH(x) (LTC2992_POWER1_MIN_THRESH + ((x) * 0x32))
67 #define LTC2992_DSENSE(x) (LTC2992_DSENSE1 + ((x) * 0x32))
68 #define LTC2992_DSENSE_MAX(x) (LTC2992_DSENSE1_MAX + ((x) * 0x32))
69 #define LTC2992_DSENSE_MIN(x) (LTC2992_DSENSE1_MIN + ((x) * 0x32))
70 #define LTC2992_DSENSE_MAX_THRESH(x) (LTC2992_DSENSE1_MAX_THRESH + ((x) * 0x32))
71 #define LTC2992_DSENSE_MIN_THRESH(x) (LTC2992_DSENSE1_MIN_THRESH + ((x) * 0x32))
72 #define LTC2992_SENSE(x) (LTC2992_SENSE1 + ((x) * 0x32))
73 #define LTC2992_SENSE_MAX(x) (LTC2992_SENSE1_MAX + ((x) * 0x32))
74 #define LTC2992_SENSE_MIN(x) (LTC2992_SENSE1_MIN + ((x) * 0x32))
75 #define LTC2992_SENSE_MAX_THRESH(x) (LTC2992_SENSE1_MAX_THRESH + ((x) * 0x32))
76 #define LTC2992_SENSE_MIN_THRESH(x) (LTC2992_SENSE1_MIN_THRESH + ((x) * 0x32))
77 #define LTC2992_POWER_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
78 #define LTC2992_SENSE_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
79 #define LTC2992_DSENSE_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
80
81 /* CTRLB register bitfields */
82 #define LTC2992_RESET_HISTORY BIT(3)
83
84 /* FAULT1 FAULT2 registers common bitfields */
85 #define LTC2992_POWER_FAULT_MSK(x) (BIT(6) << (x))
86 #define LTC2992_DSENSE_FAULT_MSK(x) (BIT(4) << (x))
87 #define LTC2992_SENSE_FAULT_MSK(x) (BIT(2) << (x))
88
89 /* FAULT1 bitfields */
90 #define LTC2992_GPIO1_FAULT_MSK(x) (BIT(0) << (x))
91
92 /* FAULT2 bitfields */
93 #define LTC2992_GPIO2_FAULT_MSK(x) (BIT(0) << (x))
94
95 /* FAULT3 bitfields */
96 #define LTC2992_GPIO3_FAULT_MSK(x) (BIT(6) << (x))
97 #define LTC2992_GPIO4_FAULT_MSK(x) (BIT(4) << (x))
98
99 #define LTC2992_IADC_NANOV_LSB 12500
100 #define LTC2992_VADC_UV_LSB 25000
101 #define LTC2992_VADC_GPIO_UV_LSB 500
102
103 #define LTC2992_GPIO_NR 4
104 #define LTC2992_GPIO1_BIT 7
105 #define LTC2992_GPIO2_BIT 6
106 #define LTC2992_GPIO3_BIT 0
107 #define LTC2992_GPIO4_BIT 6
108 #define LTC2992_GPIO_BIT(x) (LTC2992_GPIO_NR - (x) - 1)
109
110 struct ltc2992_state {
111 struct i2c_client *client;
112 struct gpio_chip gc;
113 struct mutex gpio_mutex; /* lock for gpio access */
114 const char *gpio_names[LTC2992_GPIO_NR];
115 struct regmap *regmap;
116 u32 r_sense_uohm[2];
117 };
118
119 struct ltc2992_gpio_regs {
120 u8 data;
121 u8 max;
122 u8 min;
123 u8 max_thresh;
124 u8 min_thresh;
125 u8 alarm;
126 u8 min_alarm_msk;
127 u8 max_alarm_msk;
128 u8 ctrl;
129 u8 ctrl_bit;
130 };
131
132 static const struct ltc2992_gpio_regs ltc2992_gpio_addr_map[] = {
133 {
134 .data = LTC2992_G1,
135 .max = LTC2992_G1_MAX,
136 .min = LTC2992_G1_MIN,
137 .max_thresh = LTC2992_G1_MAX_THRESH,
138 .min_thresh = LTC2992_G1_MIN_THRESH,
139 .alarm = LTC2992_FAULT1,
140 .min_alarm_msk = LTC2992_GPIO1_FAULT_MSK(0),
141 .max_alarm_msk = LTC2992_GPIO1_FAULT_MSK(1),
142 .ctrl = LTC2992_GPIO_IO_CTRL,
143 .ctrl_bit = LTC2992_GPIO1_BIT,
144 },
145 {
146 .data = LTC2992_G2,
147 .max = LTC2992_G2_MAX,
148 .min = LTC2992_G2_MIN,
149 .max_thresh = LTC2992_G2_MAX_THRESH,
150 .min_thresh = LTC2992_G2_MIN_THRESH,
151 .alarm = LTC2992_FAULT2,
152 .min_alarm_msk = LTC2992_GPIO2_FAULT_MSK(0),
153 .max_alarm_msk = LTC2992_GPIO2_FAULT_MSK(1),
154 .ctrl = LTC2992_GPIO_IO_CTRL,
155 .ctrl_bit = LTC2992_GPIO2_BIT,
156 },
157 {
158 .data = LTC2992_G3,
159 .max = LTC2992_G3_MAX,
160 .min = LTC2992_G3_MIN,
161 .max_thresh = LTC2992_G3_MAX_THRESH,
162 .min_thresh = LTC2992_G3_MIN_THRESH,
163 .alarm = LTC2992_FAULT3,
164 .min_alarm_msk = LTC2992_GPIO3_FAULT_MSK(0),
165 .max_alarm_msk = LTC2992_GPIO3_FAULT_MSK(1),
166 .ctrl = LTC2992_GPIO_IO_CTRL,
167 .ctrl_bit = LTC2992_GPIO3_BIT,
168 },
169 {
170 .data = LTC2992_G4,
171 .max = LTC2992_G4_MAX,
172 .min = LTC2992_G4_MIN,
173 .max_thresh = LTC2992_G4_MAX_THRESH,
174 .min_thresh = LTC2992_G4_MIN_THRESH,
175 .alarm = LTC2992_FAULT3,
176 .min_alarm_msk = LTC2992_GPIO4_FAULT_MSK(0),
177 .max_alarm_msk = LTC2992_GPIO4_FAULT_MSK(1),
178 .ctrl = LTC2992_GPIO_CTRL,
179 .ctrl_bit = LTC2992_GPIO4_BIT,
180 },
181 };
182
183 static const char *ltc2992_gpio_names[LTC2992_GPIO_NR] = {
184 "GPIO1", "GPIO2", "GPIO3", "GPIO4",
185 };
186
ltc2992_read_reg(struct ltc2992_state * st,u8 addr,const u8 reg_len)187 static int ltc2992_read_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len)
188 {
189 u8 regvals[4];
190 int val;
191 int ret;
192 int i;
193
194 ret = regmap_bulk_read(st->regmap, addr, regvals, reg_len);
195 if (ret < 0)
196 return ret;
197
198 val = 0;
199 for (i = 0; i < reg_len; i++)
200 val |= regvals[reg_len - i - 1] << (i * 8);
201
202 return val;
203 }
204
ltc2992_write_reg(struct ltc2992_state * st,u8 addr,const u8 reg_len,u32 val)205 static int ltc2992_write_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len, u32 val)
206 {
207 u8 regvals[4];
208 int i;
209
210 for (i = 0; i < reg_len; i++)
211 regvals[reg_len - i - 1] = (val >> (i * 8)) & 0xFF;
212
213 return regmap_bulk_write(st->regmap, addr, regvals, reg_len);
214 }
215
ltc2992_gpio_get(struct gpio_chip * chip,unsigned int offset)216 static int ltc2992_gpio_get(struct gpio_chip *chip, unsigned int offset)
217 {
218 struct ltc2992_state *st = gpiochip_get_data(chip);
219 unsigned long gpio_status;
220 int reg;
221
222 mutex_lock(&st->gpio_mutex);
223 reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
224 mutex_unlock(&st->gpio_mutex);
225
226 if (reg < 0)
227 return reg;
228
229 gpio_status = reg;
230
231 return !test_bit(LTC2992_GPIO_BIT(offset), &gpio_status);
232 }
233
ltc2992_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)234 static int ltc2992_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
235 unsigned long *bits)
236 {
237 struct ltc2992_state *st = gpiochip_get_data(chip);
238 unsigned long gpio_status;
239 unsigned int gpio_nr;
240 int reg;
241
242 mutex_lock(&st->gpio_mutex);
243 reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
244 mutex_unlock(&st->gpio_mutex);
245
246 if (reg < 0)
247 return reg;
248
249 gpio_status = reg;
250
251 gpio_nr = 0;
252 for_each_set_bit_from(gpio_nr, mask, LTC2992_GPIO_NR) {
253 if (test_bit(LTC2992_GPIO_BIT(gpio_nr), &gpio_status))
254 set_bit(gpio_nr, bits);
255 }
256
257 return 0;
258 }
259
ltc2992_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)260 static void ltc2992_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
261 {
262 struct ltc2992_state *st = gpiochip_get_data(chip);
263 unsigned long gpio_ctrl;
264 int reg;
265
266 mutex_lock(&st->gpio_mutex);
267 reg = ltc2992_read_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1);
268 if (reg < 0) {
269 mutex_unlock(&st->gpio_mutex);
270 return;
271 }
272
273 gpio_ctrl = reg;
274 assign_bit(ltc2992_gpio_addr_map[offset].ctrl_bit, &gpio_ctrl, value);
275
276 ltc2992_write_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1, gpio_ctrl);
277 mutex_unlock(&st->gpio_mutex);
278 }
279
ltc2992_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)280 static void ltc2992_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
281 unsigned long *bits)
282 {
283 struct ltc2992_state *st = gpiochip_get_data(chip);
284 unsigned long gpio_ctrl_io = 0;
285 unsigned long gpio_ctrl = 0;
286 unsigned int gpio_nr;
287
288 for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
289 if (gpio_nr < 3)
290 assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl_io, true);
291
292 if (gpio_nr == 3)
293 assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl, true);
294 }
295
296 mutex_lock(&st->gpio_mutex);
297 ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, gpio_ctrl_io);
298 ltc2992_write_reg(st, LTC2992_GPIO_CTRL, 1, gpio_ctrl);
299 mutex_unlock(&st->gpio_mutex);
300 }
301
ltc2992_config_gpio(struct ltc2992_state * st)302 static int ltc2992_config_gpio(struct ltc2992_state *st)
303 {
304 const char *name = dev_name(&st->client->dev);
305 char *gpio_name;
306 int ret;
307 int i;
308
309 ret = ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, 0);
310 if (ret < 0)
311 return ret;
312
313 mutex_init(&st->gpio_mutex);
314
315 for (i = 0; i < ARRAY_SIZE(st->gpio_names); i++) {
316 gpio_name = devm_kasprintf(&st->client->dev, GFP_KERNEL, "ltc2992-%x-%s",
317 st->client->addr, ltc2992_gpio_names[i]);
318 if (!gpio_name)
319 return -ENOMEM;
320
321 st->gpio_names[i] = gpio_name;
322 }
323
324 st->gc.label = name;
325 st->gc.parent = &st->client->dev;
326 st->gc.owner = THIS_MODULE;
327 st->gc.can_sleep = true;
328 st->gc.base = -1;
329 st->gc.names = st->gpio_names;
330 st->gc.ngpio = ARRAY_SIZE(st->gpio_names);
331 st->gc.get = ltc2992_gpio_get;
332 st->gc.get_multiple = ltc2992_gpio_get_multiple;
333 st->gc.set = ltc2992_gpio_set;
334 st->gc.set_multiple = ltc2992_gpio_set_multiple;
335
336 ret = devm_gpiochip_add_data(&st->client->dev, &st->gc, st);
337 if (ret)
338 dev_err(&st->client->dev, "GPIO registering failed (%d)\n", ret);
339
340 return ret;
341 }
342
ltc2992_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)343 static umode_t ltc2992_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
344 int channel)
345 {
346 const struct ltc2992_state *st = data;
347
348 switch (type) {
349 case hwmon_chip:
350 switch (attr) {
351 case hwmon_chip_in_reset_history:
352 return 0200;
353 }
354 break;
355 case hwmon_in:
356 switch (attr) {
357 case hwmon_in_input:
358 case hwmon_in_lowest:
359 case hwmon_in_highest:
360 case hwmon_in_min_alarm:
361 case hwmon_in_max_alarm:
362 return 0444;
363 case hwmon_in_min:
364 case hwmon_in_max:
365 return 0644;
366 }
367 break;
368 case hwmon_curr:
369 switch (attr) {
370 case hwmon_curr_input:
371 case hwmon_curr_lowest:
372 case hwmon_curr_highest:
373 case hwmon_curr_min_alarm:
374 case hwmon_curr_max_alarm:
375 if (st->r_sense_uohm[channel])
376 return 0444;
377 break;
378 case hwmon_curr_min:
379 case hwmon_curr_max:
380 if (st->r_sense_uohm[channel])
381 return 0644;
382 break;
383 }
384 break;
385 case hwmon_power:
386 switch (attr) {
387 case hwmon_power_input:
388 case hwmon_power_input_lowest:
389 case hwmon_power_input_highest:
390 case hwmon_power_min_alarm:
391 case hwmon_power_max_alarm:
392 if (st->r_sense_uohm[channel])
393 return 0444;
394 break;
395 case hwmon_power_min:
396 case hwmon_power_max:
397 if (st->r_sense_uohm[channel])
398 return 0644;
399 break;
400 }
401 break;
402 default:
403 break;
404 }
405
406 return 0;
407 }
408
ltc2992_get_voltage(struct ltc2992_state * st,u32 reg,u32 scale,long * val)409 static int ltc2992_get_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long *val)
410 {
411 int reg_val;
412
413 reg_val = ltc2992_read_reg(st, reg, 2);
414 if (reg_val < 0)
415 return reg_val;
416
417 reg_val = reg_val >> 4;
418 *val = DIV_ROUND_CLOSEST(reg_val * scale, 1000);
419
420 return 0;
421 }
422
ltc2992_set_voltage(struct ltc2992_state * st,u32 reg,u32 scale,long val)423 static int ltc2992_set_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long val)
424 {
425 val = DIV_ROUND_CLOSEST(val * 1000, scale);
426 val = val << 4;
427
428 return ltc2992_write_reg(st, reg, 2, val);
429 }
430
ltc2992_read_gpio_alarm(struct ltc2992_state * st,int nr_gpio,u32 attr,long * val)431 static int ltc2992_read_gpio_alarm(struct ltc2992_state *st, int nr_gpio, u32 attr, long *val)
432 {
433 int reg_val;
434 u32 mask;
435
436 if (attr == hwmon_in_max_alarm)
437 mask = ltc2992_gpio_addr_map[nr_gpio].max_alarm_msk;
438 else
439 mask = ltc2992_gpio_addr_map[nr_gpio].min_alarm_msk;
440
441 reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1);
442 if (reg_val < 0)
443 return reg_val;
444
445 *val = !!(reg_val & mask);
446 reg_val &= ~mask;
447
448 return ltc2992_write_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1, reg_val);
449 }
450
ltc2992_read_gpios_in(struct device * dev,u32 attr,int nr_gpio,long * val)451 static int ltc2992_read_gpios_in(struct device *dev, u32 attr, int nr_gpio, long *val)
452 {
453 struct ltc2992_state *st = dev_get_drvdata(dev);
454 u32 reg;
455
456 switch (attr) {
457 case hwmon_in_input:
458 reg = ltc2992_gpio_addr_map[nr_gpio].data;
459 break;
460 case hwmon_in_lowest:
461 reg = ltc2992_gpio_addr_map[nr_gpio].min;
462 break;
463 case hwmon_in_highest:
464 reg = ltc2992_gpio_addr_map[nr_gpio].max;
465 break;
466 case hwmon_in_min:
467 reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
468 break;
469 case hwmon_in_max:
470 reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
471 break;
472 case hwmon_in_min_alarm:
473 case hwmon_in_max_alarm:
474 return ltc2992_read_gpio_alarm(st, nr_gpio, attr, val);
475 default:
476 return -EOPNOTSUPP;
477 }
478
479 return ltc2992_get_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
480 }
481
ltc2992_read_in_alarm(struct ltc2992_state * st,int channel,long * val,u32 attr)482 static int ltc2992_read_in_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
483 {
484 int reg_val;
485 u32 mask;
486
487 if (attr == hwmon_in_max_alarm)
488 mask = LTC2992_SENSE_FAULT_MSK(1);
489 else
490 mask = LTC2992_SENSE_FAULT_MSK(0);
491
492 reg_val = ltc2992_read_reg(st, LTC2992_SENSE_FAULT(channel), 1);
493 if (reg_val < 0)
494 return reg_val;
495
496 *val = !!(reg_val & mask);
497 reg_val &= ~mask;
498
499 return ltc2992_write_reg(st, LTC2992_SENSE_FAULT(channel), 1, reg_val);
500 }
501
ltc2992_read_in(struct device * dev,u32 attr,int channel,long * val)502 static int ltc2992_read_in(struct device *dev, u32 attr, int channel, long *val)
503 {
504 struct ltc2992_state *st = dev_get_drvdata(dev);
505 u32 reg;
506
507 if (channel > 1)
508 return ltc2992_read_gpios_in(dev, attr, channel - 2, val);
509
510 switch (attr) {
511 case hwmon_in_input:
512 reg = LTC2992_SENSE(channel);
513 break;
514 case hwmon_in_lowest:
515 reg = LTC2992_SENSE_MIN(channel);
516 break;
517 case hwmon_in_highest:
518 reg = LTC2992_SENSE_MAX(channel);
519 break;
520 case hwmon_in_min:
521 reg = LTC2992_SENSE_MIN_THRESH(channel);
522 break;
523 case hwmon_in_max:
524 reg = LTC2992_SENSE_MAX_THRESH(channel);
525 break;
526 case hwmon_in_min_alarm:
527 case hwmon_in_max_alarm:
528 return ltc2992_read_in_alarm(st, channel, val, attr);
529 default:
530 return -EOPNOTSUPP;
531 }
532
533 return ltc2992_get_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
534 }
535
ltc2992_get_current(struct ltc2992_state * st,u32 reg,u32 channel,long * val)536 static int ltc2992_get_current(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
537 {
538 int reg_val;
539
540 reg_val = ltc2992_read_reg(st, reg, 2);
541 if (reg_val < 0)
542 return reg_val;
543
544 reg_val = reg_val >> 4;
545 *val = DIV_ROUND_CLOSEST(reg_val * LTC2992_IADC_NANOV_LSB, st->r_sense_uohm[channel]);
546
547 return 0;
548 }
549
ltc2992_set_current(struct ltc2992_state * st,u32 reg,u32 channel,long val)550 static int ltc2992_set_current(struct ltc2992_state *st, u32 reg, u32 channel, long val)
551 {
552 u32 reg_val;
553
554 reg_val = DIV_ROUND_CLOSEST(val * st->r_sense_uohm[channel], LTC2992_IADC_NANOV_LSB);
555 reg_val = reg_val << 4;
556
557 return ltc2992_write_reg(st, reg, 2, reg_val);
558 }
559
ltc2992_read_curr_alarm(struct ltc2992_state * st,int channel,long * val,u32 attr)560 static int ltc2992_read_curr_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
561 {
562 int reg_val;
563 u32 mask;
564
565 if (attr == hwmon_curr_max_alarm)
566 mask = LTC2992_DSENSE_FAULT_MSK(1);
567 else
568 mask = LTC2992_DSENSE_FAULT_MSK(0);
569
570 reg_val = ltc2992_read_reg(st, LTC2992_DSENSE_FAULT(channel), 1);
571 if (reg_val < 0)
572 return reg_val;
573
574 *val = !!(reg_val & mask);
575
576 reg_val &= ~mask;
577 return ltc2992_write_reg(st, LTC2992_DSENSE_FAULT(channel), 1, reg_val);
578 }
579
ltc2992_read_curr(struct device * dev,u32 attr,int channel,long * val)580 static int ltc2992_read_curr(struct device *dev, u32 attr, int channel, long *val)
581 {
582 struct ltc2992_state *st = dev_get_drvdata(dev);
583 u32 reg;
584
585 switch (attr) {
586 case hwmon_curr_input:
587 reg = LTC2992_DSENSE(channel);
588 break;
589 case hwmon_curr_lowest:
590 reg = LTC2992_DSENSE_MIN(channel);
591 break;
592 case hwmon_curr_highest:
593 reg = LTC2992_DSENSE_MAX(channel);
594 break;
595 case hwmon_curr_min:
596 reg = LTC2992_DSENSE_MIN_THRESH(channel);
597 break;
598 case hwmon_curr_max:
599 reg = LTC2992_DSENSE_MAX_THRESH(channel);
600 break;
601 case hwmon_curr_min_alarm:
602 case hwmon_curr_max_alarm:
603 return ltc2992_read_curr_alarm(st, channel, val, attr);
604 default:
605 return -EOPNOTSUPP;
606 }
607
608 return ltc2992_get_current(st, reg, channel, val);
609 }
610
ltc2992_get_power(struct ltc2992_state * st,u32 reg,u32 channel,long * val)611 static int ltc2992_get_power(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
612 {
613 int reg_val;
614
615 reg_val = ltc2992_read_reg(st, reg, 3);
616 if (reg_val < 0)
617 return reg_val;
618
619 *val = mul_u64_u32_div(reg_val, LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB,
620 st->r_sense_uohm[channel] * 1000);
621
622 return 0;
623 }
624
ltc2992_set_power(struct ltc2992_state * st,u32 reg,u32 channel,long val)625 static int ltc2992_set_power(struct ltc2992_state *st, u32 reg, u32 channel, long val)
626 {
627 u32 reg_val;
628
629 reg_val = mul_u64_u32_div(val, st->r_sense_uohm[channel] * 1000,
630 LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB);
631
632 return ltc2992_write_reg(st, reg, 3, reg_val);
633 }
634
ltc2992_read_power_alarm(struct ltc2992_state * st,int channel,long * val,u32 attr)635 static int ltc2992_read_power_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
636 {
637 int reg_val;
638 u32 mask;
639
640 if (attr == hwmon_power_max_alarm)
641 mask = LTC2992_POWER_FAULT_MSK(1);
642 else
643 mask = LTC2992_POWER_FAULT_MSK(0);
644
645 reg_val = ltc2992_read_reg(st, LTC2992_POWER_FAULT(channel), 1);
646 if (reg_val < 0)
647 return reg_val;
648
649 *val = !!(reg_val & mask);
650 reg_val &= ~mask;
651
652 return ltc2992_write_reg(st, LTC2992_POWER_FAULT(channel), 1, reg_val);
653 }
654
ltc2992_read_power(struct device * dev,u32 attr,int channel,long * val)655 static int ltc2992_read_power(struct device *dev, u32 attr, int channel, long *val)
656 {
657 struct ltc2992_state *st = dev_get_drvdata(dev);
658 u32 reg;
659
660 switch (attr) {
661 case hwmon_power_input:
662 reg = LTC2992_POWER(channel);
663 break;
664 case hwmon_power_input_lowest:
665 reg = LTC2992_POWER_MIN(channel);
666 break;
667 case hwmon_power_input_highest:
668 reg = LTC2992_POWER_MAX(channel);
669 break;
670 case hwmon_power_min:
671 reg = LTC2992_POWER_MIN_THRESH(channel);
672 break;
673 case hwmon_power_max:
674 reg = LTC2992_POWER_MAX_THRESH(channel);
675 break;
676 case hwmon_power_min_alarm:
677 case hwmon_power_max_alarm:
678 return ltc2992_read_power_alarm(st, channel, val, attr);
679 default:
680 return -EOPNOTSUPP;
681 }
682
683 return ltc2992_get_power(st, reg, channel, val);
684 }
685
ltc2992_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)686 static int ltc2992_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
687 long *val)
688 {
689 switch (type) {
690 case hwmon_in:
691 return ltc2992_read_in(dev, attr, channel, val);
692 case hwmon_curr:
693 return ltc2992_read_curr(dev, attr, channel, val);
694 case hwmon_power:
695 return ltc2992_read_power(dev, attr, channel, val);
696 default:
697 return -EOPNOTSUPP;
698 }
699 }
700
ltc2992_write_curr(struct device * dev,u32 attr,int channel,long val)701 static int ltc2992_write_curr(struct device *dev, u32 attr, int channel, long val)
702 {
703 struct ltc2992_state *st = dev_get_drvdata(dev);
704 u32 reg;
705
706 switch (attr) {
707 case hwmon_curr_min:
708 reg = LTC2992_DSENSE_MIN_THRESH(channel);
709 break;
710 case hwmon_curr_max:
711 reg = LTC2992_DSENSE_MAX_THRESH(channel);
712 break;
713 default:
714 return -EOPNOTSUPP;
715 }
716
717 return ltc2992_set_current(st, reg, channel, val);
718 }
719
ltc2992_write_gpios_in(struct device * dev,u32 attr,int nr_gpio,long val)720 static int ltc2992_write_gpios_in(struct device *dev, u32 attr, int nr_gpio, long val)
721 {
722 struct ltc2992_state *st = dev_get_drvdata(dev);
723 u32 reg;
724
725 switch (attr) {
726 case hwmon_in_min:
727 reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
728 break;
729 case hwmon_in_max:
730 reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
731 break;
732 default:
733 return -EOPNOTSUPP;
734 }
735
736 return ltc2992_set_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
737 }
738
ltc2992_write_in(struct device * dev,u32 attr,int channel,long val)739 static int ltc2992_write_in(struct device *dev, u32 attr, int channel, long val)
740 {
741 struct ltc2992_state *st = dev_get_drvdata(dev);
742 u32 reg;
743
744 if (channel > 1)
745 return ltc2992_write_gpios_in(dev, attr, channel - 2, val);
746
747 switch (attr) {
748 case hwmon_in_min:
749 reg = LTC2992_SENSE_MIN_THRESH(channel);
750 break;
751 case hwmon_in_max:
752 reg = LTC2992_SENSE_MAX_THRESH(channel);
753 break;
754 default:
755 return -EOPNOTSUPP;
756 }
757
758 return ltc2992_set_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
759 }
760
ltc2992_write_power(struct device * dev,u32 attr,int channel,long val)761 static int ltc2992_write_power(struct device *dev, u32 attr, int channel, long val)
762 {
763 struct ltc2992_state *st = dev_get_drvdata(dev);
764 u32 reg;
765
766 switch (attr) {
767 case hwmon_power_min:
768 reg = LTC2992_POWER_MIN_THRESH(channel);
769 break;
770 case hwmon_power_max:
771 reg = LTC2992_POWER_MAX_THRESH(channel);
772 break;
773 default:
774 return -EOPNOTSUPP;
775 }
776
777 return ltc2992_set_power(st, reg, channel, val);
778 }
779
ltc2992_write_chip(struct device * dev,u32 attr,int channel,long val)780 static int ltc2992_write_chip(struct device *dev, u32 attr, int channel, long val)
781 {
782 struct ltc2992_state *st = dev_get_drvdata(dev);
783
784 switch (attr) {
785 case hwmon_chip_in_reset_history:
786 return regmap_update_bits(st->regmap, LTC2992_CTRLB, LTC2992_RESET_HISTORY,
787 LTC2992_RESET_HISTORY);
788 default:
789 return -EOPNOTSUPP;
790 }
791 }
792
ltc2992_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)793 static int ltc2992_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
794 long val)
795 {
796 switch (type) {
797 case hwmon_chip:
798 return ltc2992_write_chip(dev, attr, channel, val);
799 case hwmon_in:
800 return ltc2992_write_in(dev, attr, channel, val);
801 case hwmon_curr:
802 return ltc2992_write_curr(dev, attr, channel, val);
803 case hwmon_power:
804 return ltc2992_write_power(dev, attr, channel, val);
805 default:
806 return -EOPNOTSUPP;
807 }
808 }
809
810 static const struct hwmon_ops ltc2992_hwmon_ops = {
811 .is_visible = ltc2992_is_visible,
812 .read = ltc2992_read,
813 .write = ltc2992_write,
814 };
815
816 static const u32 ltc2992_chip_config[] = {
817 HWMON_C_IN_RESET_HISTORY,
818 0
819 };
820
821 static const struct hwmon_channel_info ltc2992_chip = {
822 .type = hwmon_chip,
823 .config = ltc2992_chip_config,
824 };
825
826 static const u32 ltc2992_in_config[] = {
827 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
828 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
829 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
830 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
831 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
832 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
833 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
834 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
835 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
836 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
837 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
838 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
839 0
840 };
841
842 static const struct hwmon_channel_info ltc2992_in = {
843 .type = hwmon_in,
844 .config = ltc2992_in_config,
845 };
846
847 static const u32 ltc2992_curr_config[] = {
848 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN | HWMON_C_MAX |
849 HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM,
850 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN | HWMON_C_MAX |
851 HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM,
852 0
853 };
854
855 static const struct hwmon_channel_info ltc2992_curr = {
856 .type = hwmon_curr,
857 .config = ltc2992_curr_config,
858 };
859
860 static const u32 ltc2992_power_config[] = {
861 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST | HWMON_P_MIN | HWMON_P_MAX |
862 HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM,
863 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST | HWMON_P_MIN | HWMON_P_MAX |
864 HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM,
865 0
866 };
867
868 static const struct hwmon_channel_info ltc2992_power = {
869 .type = hwmon_power,
870 .config = ltc2992_power_config,
871 };
872
873 static const struct hwmon_channel_info *ltc2992_info[] = {
874 <c2992_chip,
875 <c2992_in,
876 <c2992_curr,
877 <c2992_power,
878 NULL
879 };
880
881 static const struct hwmon_chip_info ltc2992_chip_info = {
882 .ops = <c2992_hwmon_ops,
883 .info = ltc2992_info,
884 };
885
886 static const struct regmap_config ltc2992_regmap_config = {
887 .reg_bits = 8,
888 .val_bits = 8,
889 .max_register = 0xE8,
890 };
891
ltc2992_parse_dt(struct ltc2992_state * st)892 static int ltc2992_parse_dt(struct ltc2992_state *st)
893 {
894 struct fwnode_handle *fwnode;
895 struct fwnode_handle *child;
896 u32 addr;
897 u32 val;
898 int ret;
899
900 fwnode = dev_fwnode(&st->client->dev);
901
902 fwnode_for_each_available_child_node(fwnode, child) {
903 ret = fwnode_property_read_u32(child, "reg", &addr);
904 if (ret < 0) {
905 fwnode_handle_put(child);
906 return ret;
907 }
908
909 if (addr > 1) {
910 fwnode_handle_put(child);
911 return -EINVAL;
912 }
913
914 ret = fwnode_property_read_u32(child, "shunt-resistor-micro-ohms", &val);
915 if (!ret)
916 st->r_sense_uohm[addr] = val;
917 }
918
919 return 0;
920 }
921
ltc2992_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)922 static int ltc2992_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
923 {
924 struct device *hwmon_dev;
925 struct ltc2992_state *st;
926 int ret;
927
928 st = devm_kzalloc(&client->dev, sizeof(*st), GFP_KERNEL);
929 if (!st)
930 return -ENOMEM;
931
932 st->client = client;
933 st->regmap = devm_regmap_init_i2c(client, <c2992_regmap_config);
934 if (IS_ERR(st->regmap))
935 return PTR_ERR(st->regmap);
936
937 ret = ltc2992_parse_dt(st);
938 if (ret < 0)
939 return ret;
940
941 ret = ltc2992_config_gpio(st);
942 if (ret < 0)
943 return ret;
944
945 hwmon_dev = devm_hwmon_device_register_with_info(&client->dev, client->name, st,
946 <c2992_chip_info, NULL);
947
948 return PTR_ERR_OR_ZERO(hwmon_dev);
949 }
950
951 static const struct of_device_id ltc2992_of_match[] = {
952 { .compatible = "adi,ltc2992" },
953 { }
954 };
955 MODULE_DEVICE_TABLE(of, ltc2992_of_match);
956
957 static const struct i2c_device_id ltc2992_i2c_id[] = {
958 {"ltc2992", 0},
959 {}
960 };
961 MODULE_DEVICE_TABLE(i2c, ltc2992_i2c_id);
962
963 static struct i2c_driver ltc2992_i2c_driver = {
964 .driver = {
965 .name = "ltc2992",
966 .of_match_table = ltc2992_of_match,
967 },
968 .probe = ltc2992_i2c_probe,
969 .id_table = ltc2992_i2c_id,
970 };
971
972 module_i2c_driver(ltc2992_i2c_driver);
973
974 MODULE_AUTHOR("Alexandru Tachici <alexandru.tachici@analog.com>");
975 MODULE_DESCRIPTION("Hwmon driver for Linear Technology 2992");
976 MODULE_LICENSE("Dual BSD/GPL");
977