1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/kernel.h>
8 #include <linux/moduleparam.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/device.h>
12 #include <linux/io.h>
13 #include <linux/err.h>
14 #include <linux/fs.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/smp.h>
18 #include <linux/sysfs.h>
19 #include <linux/stat.h>
20 #include <linux/clk.h>
21 #include <linux/cpu.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/coresight.h>
24 #include <linux/coresight-pmu.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/amba/bus.h>
27 #include <linux/seq_file.h>
28 #include <linux/uaccess.h>
29 #include <linux/perf_event.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/property.h>
33
34 #include <asm/barrier.h>
35 #include <asm/sections.h>
36 #include <asm/sysreg.h>
37 #include <asm/local.h>
38 #include <asm/virt.h>
39
40 #include "coresight-etm4x.h"
41 #include "coresight-etm-perf.h"
42 #include "coresight-etm4x-cfg.h"
43 #include "coresight-self-hosted-trace.h"
44 #include "coresight-syscfg.h"
45
46 static int boot_enable;
47 module_param(boot_enable, int, 0444);
48 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
49
50 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
51 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */
52 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
53
54 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
55 module_param(pm_save_enable, int, 0444);
56 MODULE_PARM_DESC(pm_save_enable,
57 "Save/restore state on power down: 1 = never, 2 = self-hosted");
58
59 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
60 static void etm4_set_default_config(struct etmv4_config *config);
61 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
62 struct perf_event *event);
63 static u64 etm4_get_access_type(struct etmv4_config *config);
64
65 static enum cpuhp_state hp_online;
66
67 struct etm4_init_arg {
68 unsigned int pid;
69 struct etmv4_drvdata *drvdata;
70 struct csdev_access *csa;
71 };
72
73 /*
74 * Check if TRCSSPCICRn(i) is implemented for a given instance.
75 *
76 * TRCSSPCICRn is implemented only if :
77 * TRCSSPCICR<n> is present only if all of the following are true:
78 * TRCIDR4.NUMSSCC > n.
79 * TRCIDR4.NUMPC > 0b0000 .
80 * TRCSSCSR<n>.PC == 0b1
81 */
etm4x_sspcicrn_present(struct etmv4_drvdata * drvdata,int n)82 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
83 {
84 return (n < drvdata->nr_ss_cmp) &&
85 drvdata->nr_pe &&
86 (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
87 }
88
etm4x_sysreg_read(u32 offset,bool _relaxed,bool _64bit)89 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
90 {
91 u64 res = 0;
92
93 switch (offset) {
94 ETM4x_READ_SYSREG_CASES(res)
95 default :
96 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
97 offset);
98 }
99
100 if (!_relaxed)
101 __iormb(res); /* Imitate the !relaxed I/O helpers */
102
103 return res;
104 }
105
etm4x_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)106 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
107 {
108 if (!_relaxed)
109 __iowmb(); /* Imitate the !relaxed I/O helpers */
110 if (!_64bit)
111 val &= GENMASK(31, 0);
112
113 switch (offset) {
114 ETM4x_WRITE_SYSREG_CASES(val)
115 default :
116 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
117 offset);
118 }
119 }
120
ete_sysreg_read(u32 offset,bool _relaxed,bool _64bit)121 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
122 {
123 u64 res = 0;
124
125 switch (offset) {
126 ETE_READ_CASES(res)
127 default :
128 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
129 offset);
130 }
131
132 if (!_relaxed)
133 __iormb(res); /* Imitate the !relaxed I/O helpers */
134
135 return res;
136 }
137
ete_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)138 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
139 {
140 if (!_relaxed)
141 __iowmb(); /* Imitate the !relaxed I/O helpers */
142 if (!_64bit)
143 val &= GENMASK(31, 0);
144
145 switch (offset) {
146 ETE_WRITE_CASES(val)
147 default :
148 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
149 offset);
150 }
151 }
152
etm_detect_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)153 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
154 struct csdev_access *csa)
155 {
156 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
157
158 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
159 }
160
etm_write_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa,u32 val)161 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
162 struct csdev_access *csa, u32 val)
163 {
164 val = !!val;
165
166 switch (drvdata->os_lock_model) {
167 case ETM_OSLOCK_PRESENT:
168 etm4x_relaxed_write32(csa, val, TRCOSLAR);
169 break;
170 case ETM_OSLOCK_PE:
171 write_sysreg_s(val, SYS_OSLAR_EL1);
172 break;
173 default:
174 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
175 smp_processor_id(), drvdata->os_lock_model);
176 fallthrough;
177 case ETM_OSLOCK_NI:
178 return;
179 }
180 isb();
181 }
182
etm4_os_unlock_csa(struct etmv4_drvdata * drvdata,struct csdev_access * csa)183 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
184 struct csdev_access *csa)
185 {
186 WARN_ON(drvdata->cpu != smp_processor_id());
187
188 /* Writing 0 to OS Lock unlocks the trace unit registers */
189 etm_write_os_lock(drvdata, csa, 0x0);
190 drvdata->os_unlock = true;
191 }
192
etm4_os_unlock(struct etmv4_drvdata * drvdata)193 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
194 {
195 if (!WARN_ON(!drvdata->csdev))
196 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
197 }
198
etm4_os_lock(struct etmv4_drvdata * drvdata)199 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
200 {
201 if (WARN_ON(!drvdata->csdev))
202 return;
203 /* Writing 0x1 to OS Lock locks the trace registers */
204 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
205 drvdata->os_unlock = false;
206 }
207
etm4_cs_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)208 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
209 struct csdev_access *csa)
210 {
211 /* Software Lock is only accessible via memory mapped interface */
212 if (csa->io_mem)
213 CS_LOCK(csa->base);
214 }
215
etm4_cs_unlock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)216 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
217 struct csdev_access *csa)
218 {
219 if (csa->io_mem)
220 CS_UNLOCK(csa->base);
221 }
222
etm4_cpu_id(struct coresight_device * csdev)223 static int etm4_cpu_id(struct coresight_device *csdev)
224 {
225 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
226
227 return drvdata->cpu;
228 }
229
etm4_trace_id(struct coresight_device * csdev)230 static int etm4_trace_id(struct coresight_device *csdev)
231 {
232 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
233
234 return drvdata->trcid;
235 }
236
237 struct etm4_enable_arg {
238 struct etmv4_drvdata *drvdata;
239 int rc;
240 };
241
242 /*
243 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
244 * When the CPU supports FEAT_TRF, we could move the ETM to a trace
245 * prohibited state by filtering the Exception levels via TRFCR_EL1.
246 */
etm4x_prohibit_trace(struct etmv4_drvdata * drvdata)247 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
248 {
249 /* If the CPU doesn't support FEAT_TRF, nothing to do */
250 if (!drvdata->trfcr)
251 return;
252 cpu_prohibit_trace();
253 }
254
255 /*
256 * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
257 * as configured by the drvdata->config.mode for the current
258 * session. Even though we have TRCVICTLR bits to filter the
259 * trace in the ELs, it doesn't prevent the ETM from generating
260 * a packet (e.g, TraceInfo) that might contain the addresses from
261 * the excluded levels. Thus we use the additional controls provided
262 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
263 * is generated for the excluded ELs.
264 */
etm4x_allow_trace(struct etmv4_drvdata * drvdata)265 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
266 {
267 u64 trfcr = drvdata->trfcr;
268
269 /* If the CPU doesn't support FEAT_TRF, nothing to do */
270 if (!trfcr)
271 return;
272
273 if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
274 trfcr &= ~TRFCR_ELx_ExTRE;
275 if (drvdata->config.mode & ETM_MODE_EXCL_USER)
276 trfcr &= ~TRFCR_ELx_E0TRE;
277
278 write_trfcr(trfcr);
279 }
280
281 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
282
283 #define HISI_HIP08_AMBA_ID 0x000b6d01
284 #define ETM4_AMBA_MASK 0xfffff
285 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000
286 #define HISI_HIP08_CORE_COMMIT_SHIFT 12
287 #define HISI_HIP08_CORE_COMMIT_FULL 0b00
288 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01
289 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
290
291 struct etm4_arch_features {
292 void (*arch_callback)(bool enable);
293 };
294
etm4_hisi_match_pid(unsigned int id)295 static bool etm4_hisi_match_pid(unsigned int id)
296 {
297 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
298 }
299
etm4_hisi_config_core_commit(bool enable)300 static void etm4_hisi_config_core_commit(bool enable)
301 {
302 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
303 HISI_HIP08_CORE_COMMIT_FULL;
304 u64 val;
305
306 /*
307 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
308 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
309 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
310 * speed(minimun value). So bit 12 and 13 should be cleared together.
311 */
312 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
313 val &= ~HISI_HIP08_CORE_COMMIT_MASK;
314 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
315 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
316 }
317
318 static struct etm4_arch_features etm4_features[] = {
319 [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
320 .arch_callback = etm4_hisi_config_core_commit,
321 },
322 {},
323 };
324
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)325 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
326 {
327 struct etm4_arch_features *ftr;
328 int bit;
329
330 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
331 ftr = &etm4_features[bit];
332
333 if (ftr->arch_callback)
334 ftr->arch_callback(true);
335 }
336 }
337
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)338 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
339 {
340 struct etm4_arch_features *ftr;
341 int bit;
342
343 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
344 ftr = &etm4_features[bit];
345
346 if (ftr->arch_callback)
347 ftr->arch_callback(false);
348 }
349 }
350
etm4_check_arch_features(struct etmv4_drvdata * drvdata,unsigned int id)351 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
352 unsigned int id)
353 {
354 if (etm4_hisi_match_pid(id))
355 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
356 }
357 #else
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)358 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
359 {
360 }
361
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)362 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
363 {
364 }
365
etm4_check_arch_features(struct etmv4_drvdata * drvdata,unsigned int id)366 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
367 unsigned int id)
368 {
369 }
370 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
371
etm4_enable_hw(struct etmv4_drvdata * drvdata)372 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
373 {
374 int i, rc;
375 struct etmv4_config *config = &drvdata->config;
376 struct coresight_device *csdev = drvdata->csdev;
377 struct device *etm_dev = &csdev->dev;
378 struct csdev_access *csa = &csdev->access;
379
380
381 etm4_cs_unlock(drvdata, csa);
382 etm4_enable_arch_specific(drvdata);
383
384 etm4_os_unlock(drvdata);
385
386 rc = coresight_claim_device_unlocked(csdev);
387 if (rc)
388 goto done;
389
390 /* Disable the trace unit before programming trace registers */
391 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
392
393 /*
394 * If we use system instructions, we need to synchronize the
395 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
396 * See ARM IHI0064F, section
397 * "4.3.7 Synchronization of register updates"
398 */
399 if (!csa->io_mem)
400 isb();
401
402 /* wait for TRCSTATR.IDLE to go up */
403 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
404 dev_err(etm_dev,
405 "timeout while waiting for Idle Trace Status\n");
406 if (drvdata->nr_pe)
407 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
408 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
409 /* nothing specific implemented */
410 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
411 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
412 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
413 if (drvdata->stallctl)
414 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
415 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
416 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
417 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
418 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
419 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
420 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
421 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
422 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
423 if (drvdata->nr_pe_cmp)
424 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
425 for (i = 0; i < drvdata->nrseqstate - 1; i++)
426 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
427 if (drvdata->nrseqstate) {
428 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
429 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
430 }
431 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
432 for (i = 0; i < drvdata->nr_cntr; i++) {
433 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
434 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
435 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
436 }
437
438 /*
439 * Resource selector pair 0 is always implemented and reserved. As
440 * such start at 2.
441 */
442 for (i = 2; i < drvdata->nr_resource * 2; i++)
443 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
444
445 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
446 /* always clear status bit on restart if using single-shot */
447 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
448 config->ss_status[i] &= ~BIT(31);
449 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
450 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
451 if (etm4x_sspcicrn_present(drvdata, i))
452 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
453 }
454 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
455 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
456 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
457 }
458 for (i = 0; i < drvdata->numcidc; i++)
459 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
460 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
461 if (drvdata->numcidc > 4)
462 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
463
464 for (i = 0; i < drvdata->numvmidc; i++)
465 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
466 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
467 if (drvdata->numvmidc > 4)
468 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
469
470 if (!drvdata->skip_power_up) {
471 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
472
473 /*
474 * Request to keep the trace unit powered and also
475 * emulation of powerdown
476 */
477 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
478 }
479
480 /*
481 * ETE mandates that the TRCRSR is written to before
482 * enabling it.
483 */
484 if (etm4x_is_ete(drvdata))
485 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
486
487 etm4x_allow_trace(drvdata);
488 /* Enable the trace unit */
489 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
490
491 /* Synchronize the register updates for sysreg access */
492 if (!csa->io_mem)
493 isb();
494
495 /* wait for TRCSTATR.IDLE to go back down to '0' */
496 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
497 dev_err(etm_dev,
498 "timeout while waiting for Idle Trace Status\n");
499
500 /*
501 * As recommended by section 4.3.7 ("Synchronization when using the
502 * memory-mapped interface") of ARM IHI 0064D
503 */
504 dsb(sy);
505 isb();
506
507 done:
508 etm4_cs_lock(drvdata, csa);
509
510 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
511 drvdata->cpu, rc);
512 return rc;
513 }
514
etm4_enable_hw_smp_call(void * info)515 static void etm4_enable_hw_smp_call(void *info)
516 {
517 struct etm4_enable_arg *arg = info;
518
519 if (WARN_ON(!arg))
520 return;
521 arg->rc = etm4_enable_hw(arg->drvdata);
522 }
523
524 /*
525 * The goal of function etm4_config_timestamp_event() is to configure a
526 * counter that will tell the tracer to emit a timestamp packet when it
527 * reaches zero. This is done in order to get a more fine grained idea
528 * of when instructions are executed so that they can be correlated
529 * with execution on other CPUs.
530 *
531 * To do this the counter itself is configured to self reload and
532 * TRCRSCTLR1 (always true) used to get the counter to decrement. From
533 * there a resource selector is configured with the counter and the
534 * timestamp control register to use the resource selector to trigger the
535 * event that will insert a timestamp packet in the stream.
536 */
etm4_config_timestamp_event(struct etmv4_drvdata * drvdata)537 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
538 {
539 int ctridx, ret = -EINVAL;
540 int counter, rselector;
541 u32 val = 0;
542 struct etmv4_config *config = &drvdata->config;
543
544 /* No point in trying if we don't have at least one counter */
545 if (!drvdata->nr_cntr)
546 goto out;
547
548 /* Find a counter that hasn't been initialised */
549 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
550 if (config->cntr_val[ctridx] == 0)
551 break;
552
553 /* All the counters have been configured already, bail out */
554 if (ctridx == drvdata->nr_cntr) {
555 pr_debug("%s: no available counter found\n", __func__);
556 ret = -ENOSPC;
557 goto out;
558 }
559
560 /*
561 * Searching for an available resource selector to use, starting at
562 * '2' since every implementation has at least 2 resource selector.
563 * ETMIDR4 gives the number of resource selector _pairs_,
564 * hence multiply by 2.
565 */
566 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
567 if (!config->res_ctrl[rselector])
568 break;
569
570 if (rselector == drvdata->nr_resource * 2) {
571 pr_debug("%s: no available resource selector found\n",
572 __func__);
573 ret = -ENOSPC;
574 goto out;
575 }
576
577 /* Remember what counter we used */
578 counter = 1 << ctridx;
579
580 /*
581 * Initialise original and reload counter value to the smallest
582 * possible value in order to get as much precision as we can.
583 */
584 config->cntr_val[ctridx] = 1;
585 config->cntrldvr[ctridx] = 1;
586
587 /* Set the trace counter control register */
588 val = 0x1 << 16 | /* Bit 16, reload counter automatically */
589 0x0 << 7 | /* Select single resource selector */
590 0x1; /* Resource selector 1, i.e always true */
591
592 config->cntr_ctrl[ctridx] = val;
593
594 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
595 counter << 0; /* Counter to use */
596
597 config->res_ctrl[rselector] = val;
598
599 val = 0x0 << 7 | /* Select single resource selector */
600 rselector; /* Resource selector */
601
602 config->ts_ctrl = val;
603
604 ret = 0;
605 out:
606 return ret;
607 }
608
etm4_parse_event_config(struct coresight_device * csdev,struct perf_event * event)609 static int etm4_parse_event_config(struct coresight_device *csdev,
610 struct perf_event *event)
611 {
612 int ret = 0;
613 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
614 struct etmv4_config *config = &drvdata->config;
615 struct perf_event_attr *attr = &event->attr;
616 unsigned long cfg_hash;
617 int preset;
618
619 /* Clear configuration from previous run */
620 memset(config, 0, sizeof(struct etmv4_config));
621
622 if (attr->exclude_kernel)
623 config->mode = ETM_MODE_EXCL_KERN;
624
625 if (attr->exclude_user)
626 config->mode = ETM_MODE_EXCL_USER;
627
628 /* Always start from the default config */
629 etm4_set_default_config(config);
630
631 /* Configure filters specified on the perf cmd line, if any. */
632 ret = etm4_set_event_filters(drvdata, event);
633 if (ret)
634 goto out;
635
636 /* Go from generic option to ETMv4 specifics */
637 if (attr->config & BIT(ETM_OPT_CYCACC)) {
638 config->cfg |= BIT(4);
639 /* TRM: Must program this for cycacc to work */
640 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
641 }
642 if (attr->config & BIT(ETM_OPT_TS)) {
643 /*
644 * Configure timestamps to be emitted at regular intervals in
645 * order to correlate instructions executed on different CPUs
646 * (CPU-wide trace scenarios).
647 */
648 ret = etm4_config_timestamp_event(drvdata);
649
650 /*
651 * No need to go further if timestamp intervals can't
652 * be configured.
653 */
654 if (ret)
655 goto out;
656
657 /* bit[11], Global timestamp tracing bit */
658 config->cfg |= BIT(11);
659 }
660
661 if (attr->config & BIT(ETM_OPT_CTXTID))
662 /* bit[6], Context ID tracing bit */
663 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
664
665 /*
666 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
667 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
668 * kernel is not running in EL2.
669 */
670 if (attr->config & BIT(ETM_OPT_CTXTID2)) {
671 if (!is_kernel_in_hyp_mode()) {
672 ret = -EINVAL;
673 goto out;
674 }
675 config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT);
676 }
677
678 /* return stack - enable if selected and supported */
679 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
680 /* bit[12], Return stack enable bit */
681 config->cfg |= BIT(12);
682
683 /*
684 * Set any selected configuration and preset.
685 *
686 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
687 * in the perf attributes defined in coresight-etm-perf.c.
688 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
689 * A zero configid means no configuration active, preset = 0 means no preset selected.
690 */
691 if (attr->config2 & GENMASK_ULL(63, 32)) {
692 cfg_hash = (u32)(attr->config2 >> 32);
693 preset = attr->config & 0xF;
694 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
695 }
696
697 out:
698 return ret;
699 }
700
etm4_enable_perf(struct coresight_device * csdev,struct perf_event * event)701 static int etm4_enable_perf(struct coresight_device *csdev,
702 struct perf_event *event)
703 {
704 int ret = 0;
705 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
706
707 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
708 ret = -EINVAL;
709 goto out;
710 }
711
712 /* Configure the tracer based on the session's specifics */
713 ret = etm4_parse_event_config(csdev, event);
714 if (ret)
715 goto out;
716 /* And enable it */
717 ret = etm4_enable_hw(drvdata);
718
719 out:
720 return ret;
721 }
722
etm4_enable_sysfs(struct coresight_device * csdev)723 static int etm4_enable_sysfs(struct coresight_device *csdev)
724 {
725 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
726 struct etm4_enable_arg arg = { };
727 int ret;
728
729 spin_lock(&drvdata->spinlock);
730
731 /*
732 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
733 * ensures that register writes occur when cpu is powered.
734 */
735 arg.drvdata = drvdata;
736 ret = smp_call_function_single(drvdata->cpu,
737 etm4_enable_hw_smp_call, &arg, 1);
738 if (!ret)
739 ret = arg.rc;
740 if (!ret)
741 drvdata->sticky_enable = true;
742 spin_unlock(&drvdata->spinlock);
743
744 if (!ret)
745 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
746 return ret;
747 }
748
etm4_enable(struct coresight_device * csdev,struct perf_event * event,u32 mode)749 static int etm4_enable(struct coresight_device *csdev,
750 struct perf_event *event, u32 mode)
751 {
752 int ret;
753 u32 val;
754 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
755
756 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
757
758 /* Someone is already using the tracer */
759 if (val)
760 return -EBUSY;
761
762 switch (mode) {
763 case CS_MODE_SYSFS:
764 ret = etm4_enable_sysfs(csdev);
765 break;
766 case CS_MODE_PERF:
767 ret = etm4_enable_perf(csdev, event);
768 break;
769 default:
770 ret = -EINVAL;
771 }
772
773 /* The tracer didn't start */
774 if (ret)
775 local_set(&drvdata->mode, CS_MODE_DISABLED);
776
777 return ret;
778 }
779
etm4_disable_hw(void * info)780 static void etm4_disable_hw(void *info)
781 {
782 u32 control;
783 struct etmv4_drvdata *drvdata = info;
784 struct etmv4_config *config = &drvdata->config;
785 struct coresight_device *csdev = drvdata->csdev;
786 struct device *etm_dev = &csdev->dev;
787 struct csdev_access *csa = &csdev->access;
788 int i;
789
790 etm4_cs_unlock(drvdata, csa);
791 etm4_disable_arch_specific(drvdata);
792
793 if (!drvdata->skip_power_up) {
794 /* power can be removed from the trace unit now */
795 control = etm4x_relaxed_read32(csa, TRCPDCR);
796 control &= ~TRCPDCR_PU;
797 etm4x_relaxed_write32(csa, control, TRCPDCR);
798 }
799
800 control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
801
802 /* EN, bit[0] Trace unit enable bit */
803 control &= ~0x1;
804
805 /*
806 * If the CPU supports v8.4 Trace filter Control,
807 * set the ETM to trace prohibited region.
808 */
809 etm4x_prohibit_trace(drvdata);
810 /*
811 * Make sure everything completes before disabling, as recommended
812 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
813 * SSTATUS") of ARM IHI 0064D
814 */
815 dsb(sy);
816 isb();
817 /* Trace synchronization barrier, is a nop if not supported */
818 tsb_csync();
819 etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
820
821 /* wait for TRCSTATR.PMSTABLE to go to '1' */
822 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
823 dev_err(etm_dev,
824 "timeout while waiting for PM stable Trace Status\n");
825 /* read the status of the single shot comparators */
826 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
827 config->ss_status[i] =
828 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
829 }
830
831 /* read back the current counter values */
832 for (i = 0; i < drvdata->nr_cntr; i++) {
833 config->cntr_val[i] =
834 etm4x_relaxed_read32(csa, TRCCNTVRn(i));
835 }
836
837 coresight_disclaim_device_unlocked(csdev);
838 etm4_cs_lock(drvdata, csa);
839
840 dev_dbg(&drvdata->csdev->dev,
841 "cpu: %d disable smp call done\n", drvdata->cpu);
842 }
843
etm4_disable_perf(struct coresight_device * csdev,struct perf_event * event)844 static int etm4_disable_perf(struct coresight_device *csdev,
845 struct perf_event *event)
846 {
847 u32 control;
848 struct etm_filters *filters = event->hw.addr_filters;
849 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
850 struct perf_event_attr *attr = &event->attr;
851
852 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
853 return -EINVAL;
854
855 etm4_disable_hw(drvdata);
856 /*
857 * The config_id occupies bits 63:32 of the config2 perf event attr
858 * field. If this is non-zero then we will have enabled a config.
859 */
860 if (attr->config2 & GENMASK_ULL(63, 32))
861 cscfg_csdev_disable_active_config(csdev);
862
863 /*
864 * Check if the start/stop logic was active when the unit was stopped.
865 * That way we can re-enable the start/stop logic when the process is
866 * scheduled again. Configuration of the start/stop logic happens in
867 * function etm4_set_event_filters().
868 */
869 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
870 /* TRCVICTLR::SSSTATUS, bit[9] */
871 filters->ssstatus = (control & BIT(9));
872
873 return 0;
874 }
875
etm4_disable_sysfs(struct coresight_device * csdev)876 static void etm4_disable_sysfs(struct coresight_device *csdev)
877 {
878 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
879
880 /*
881 * Taking hotplug lock here protects from clocks getting disabled
882 * with tracing being left on (crash scenario) if user disable occurs
883 * after cpu online mask indicates the cpu is offline but before the
884 * DYING hotplug callback is serviced by the ETM driver.
885 */
886 cpus_read_lock();
887 spin_lock(&drvdata->spinlock);
888
889 /*
890 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
891 * ensures that register writes occur when cpu is powered.
892 */
893 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
894
895 spin_unlock(&drvdata->spinlock);
896 cpus_read_unlock();
897
898 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
899 }
900
etm4_disable(struct coresight_device * csdev,struct perf_event * event)901 static void etm4_disable(struct coresight_device *csdev,
902 struct perf_event *event)
903 {
904 u32 mode;
905 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
906
907 /*
908 * For as long as the tracer isn't disabled another entity can't
909 * change its status. As such we can read the status here without
910 * fearing it will change under us.
911 */
912 mode = local_read(&drvdata->mode);
913
914 switch (mode) {
915 case CS_MODE_DISABLED:
916 break;
917 case CS_MODE_SYSFS:
918 etm4_disable_sysfs(csdev);
919 break;
920 case CS_MODE_PERF:
921 etm4_disable_perf(csdev, event);
922 break;
923 }
924
925 if (mode)
926 local_set(&drvdata->mode, CS_MODE_DISABLED);
927 }
928
929 static const struct coresight_ops_source etm4_source_ops = {
930 .cpu_id = etm4_cpu_id,
931 .trace_id = etm4_trace_id,
932 .enable = etm4_enable,
933 .disable = etm4_disable,
934 };
935
936 static const struct coresight_ops etm4_cs_ops = {
937 .source_ops = &etm4_source_ops,
938 };
939
cpu_supports_sysreg_trace(void)940 static inline bool cpu_supports_sysreg_trace(void)
941 {
942 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
943
944 return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
945 }
946
etm4_init_sysreg_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)947 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
948 struct csdev_access *csa)
949 {
950 u32 devarch;
951
952 if (!cpu_supports_sysreg_trace())
953 return false;
954
955 /*
956 * ETMs implementing sysreg access must implement TRCDEVARCH.
957 */
958 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
959 switch (devarch & ETM_DEVARCH_ID_MASK) {
960 case ETM_DEVARCH_ETMv4x_ARCH:
961 *csa = (struct csdev_access) {
962 .io_mem = false,
963 .read = etm4x_sysreg_read,
964 .write = etm4x_sysreg_write,
965 };
966 break;
967 case ETM_DEVARCH_ETE_ARCH:
968 *csa = (struct csdev_access) {
969 .io_mem = false,
970 .read = ete_sysreg_read,
971 .write = ete_sysreg_write,
972 };
973 break;
974 default:
975 return false;
976 }
977
978 drvdata->arch = etm_devarch_to_arch(devarch);
979 return true;
980 }
981
etm4_init_iomem_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)982 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
983 struct csdev_access *csa)
984 {
985 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
986
987 /*
988 * All ETMs must implement TRCDEVARCH to indicate that
989 * the component is an ETMv4. Even though TRCIDR1 also
990 * contains the information, it is part of the "Trace"
991 * register and must be accessed with the OSLK cleared,
992 * with MMIO. But we cannot touch the OSLK until we are
993 * sure this is an ETM. So rely only on the TRCDEVARCH.
994 */
995 if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {
996 pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");
997 return false;
998 }
999
1000 drvdata->arch = etm_devarch_to_arch(devarch);
1001 *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1002 return true;
1003 }
1004
etm4_init_csdev_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1005 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1006 struct csdev_access *csa)
1007 {
1008 /*
1009 * Always choose the memory mapped io, if there is
1010 * a memory map to prevent sysreg access on broken
1011 * systems.
1012 */
1013 if (drvdata->base)
1014 return etm4_init_iomem_access(drvdata, csa);
1015
1016 if (etm4_init_sysreg_access(drvdata, csa))
1017 return true;
1018
1019 return false;
1020 }
1021
cpu_detect_trace_filtering(struct etmv4_drvdata * drvdata)1022 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1023 {
1024 u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1025 u64 trfcr;
1026
1027 drvdata->trfcr = 0;
1028 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT))
1029 return;
1030
1031 /*
1032 * If the CPU supports v8.4 SelfHosted Tracing, enable
1033 * tracing at the kernel EL and EL0, forcing to use the
1034 * virtual time as the timestamp.
1035 */
1036 trfcr = (TRFCR_ELx_TS_VIRTUAL |
1037 TRFCR_ELx_ExTRE |
1038 TRFCR_ELx_E0TRE);
1039
1040 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1041 if (is_kernel_in_hyp_mode())
1042 trfcr |= TRFCR_EL2_CX;
1043
1044 drvdata->trfcr = trfcr;
1045 }
1046
etm4_init_arch_data(void * info)1047 static void etm4_init_arch_data(void *info)
1048 {
1049 u32 etmidr0;
1050 u32 etmidr2;
1051 u32 etmidr3;
1052 u32 etmidr4;
1053 u32 etmidr5;
1054 struct etm4_init_arg *init_arg = info;
1055 struct etmv4_drvdata *drvdata;
1056 struct csdev_access *csa;
1057 int i;
1058
1059 drvdata = init_arg->drvdata;
1060 csa = init_arg->csa;
1061
1062 /*
1063 * If we are unable to detect the access mechanism,
1064 * or unable to detect the trace unit type, fail
1065 * early.
1066 */
1067 if (!etm4_init_csdev_access(drvdata, csa))
1068 return;
1069
1070 /* Detect the support for OS Lock before we actually use it */
1071 etm_detect_os_lock(drvdata, csa);
1072
1073 /* Make sure all registers are accessible */
1074 etm4_os_unlock_csa(drvdata, csa);
1075 etm4_cs_unlock(drvdata, csa);
1076
1077 etm4_check_arch_features(drvdata, init_arg->pid);
1078
1079 /* find all capabilities of the tracing unit */
1080 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1081
1082 /* INSTP0, bits[2:1] P0 tracing support field */
1083 if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
1084 drvdata->instrp0 = true;
1085 else
1086 drvdata->instrp0 = false;
1087
1088 /* TRCBB, bit[5] Branch broadcast tracing support bit */
1089 if (BMVAL(etmidr0, 5, 5))
1090 drvdata->trcbb = true;
1091 else
1092 drvdata->trcbb = false;
1093
1094 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1095 if (BMVAL(etmidr0, 6, 6))
1096 drvdata->trccond = true;
1097 else
1098 drvdata->trccond = false;
1099
1100 /* TRCCCI, bit[7] Cycle counting instruction bit */
1101 if (BMVAL(etmidr0, 7, 7))
1102 drvdata->trccci = true;
1103 else
1104 drvdata->trccci = false;
1105
1106 /* RETSTACK, bit[9] Return stack bit */
1107 if (BMVAL(etmidr0, 9, 9))
1108 drvdata->retstack = true;
1109 else
1110 drvdata->retstack = false;
1111
1112 /* NUMEVENT, bits[11:10] Number of events field */
1113 drvdata->nr_event = BMVAL(etmidr0, 10, 11);
1114 /* QSUPP, bits[16:15] Q element support field */
1115 drvdata->q_support = BMVAL(etmidr0, 15, 16);
1116 /* TSSIZE, bits[28:24] Global timestamp size field */
1117 drvdata->ts_size = BMVAL(etmidr0, 24, 28);
1118
1119 /* maximum size of resources */
1120 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1121 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1122 drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
1123 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1124 drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
1125 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1126 drvdata->ccsize = BMVAL(etmidr2, 25, 28);
1127
1128 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1129 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1130 drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
1131 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1132 drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
1133 drvdata->config.s_ex_level = drvdata->s_ex_level;
1134 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1135 drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
1136
1137 /*
1138 * TRCERR, bit[24] whether a trace unit can trace a
1139 * system error exception.
1140 */
1141 if (BMVAL(etmidr3, 24, 24))
1142 drvdata->trc_error = true;
1143 else
1144 drvdata->trc_error = false;
1145
1146 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1147 if (BMVAL(etmidr3, 25, 25))
1148 drvdata->syncpr = true;
1149 else
1150 drvdata->syncpr = false;
1151
1152 /* STALLCTL, bit[26] is stall control implemented? */
1153 if (BMVAL(etmidr3, 26, 26))
1154 drvdata->stallctl = true;
1155 else
1156 drvdata->stallctl = false;
1157
1158 /* SYSSTALL, bit[27] implementation can support stall control? */
1159 if (BMVAL(etmidr3, 27, 27))
1160 drvdata->sysstall = true;
1161 else
1162 drvdata->sysstall = false;
1163
1164 /*
1165 * NUMPROC - the number of PEs available for tracing, 5bits
1166 * = TRCIDR3.bits[13:12]bits[30:28]
1167 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1168 * bits[3:0] = TRCIDR3.bits[30:28]
1169 */
1170 drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
1171
1172 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1173 if (BMVAL(etmidr3, 31, 31))
1174 drvdata->nooverflow = true;
1175 else
1176 drvdata->nooverflow = false;
1177
1178 /* number of resources trace unit supports */
1179 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1180 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1181 drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
1182 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1183 drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
1184 /*
1185 * NUMRSPAIR, bits[19:16]
1186 * The number of resource pairs conveyed by the HW starts at 0, i.e a
1187 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1188 * As such add 1 to the value of NUMRSPAIR for a better representation.
1189 *
1190 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1191 * the default TRUE and FALSE resource selectors are omitted.
1192 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1193 */
1194 drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
1195 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1196 drvdata->nr_resource += 1;
1197 /*
1198 * NUMSSCC, bits[23:20] the number of single-shot
1199 * comparator control for tracing. Read any status regs as these
1200 * also contain RO capability data.
1201 */
1202 drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
1203 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1204 drvdata->config.ss_status[i] =
1205 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1206 }
1207 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1208 drvdata->numcidc = BMVAL(etmidr4, 24, 27);
1209 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1210 drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
1211
1212 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1213 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1214 drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
1215 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1216 drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
1217 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1218 if (BMVAL(etmidr5, 22, 22))
1219 drvdata->atbtrig = true;
1220 else
1221 drvdata->atbtrig = false;
1222 /*
1223 * LPOVERRIDE, bit[23] implementation supports
1224 * low-power state override
1225 */
1226 if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
1227 drvdata->lpoverride = true;
1228 else
1229 drvdata->lpoverride = false;
1230 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1231 drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
1232 /* NUMCNTR, bits[30:28] number of counters available for tracing */
1233 drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
1234 etm4_cs_lock(drvdata, csa);
1235 cpu_detect_trace_filtering(drvdata);
1236 }
1237
etm4_get_victlr_access_type(struct etmv4_config * config)1238 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1239 {
1240 return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT;
1241 }
1242
1243 /* Set ELx trace filter access in the TRCVICTLR register */
etm4_set_victlr_access(struct etmv4_config * config)1244 static void etm4_set_victlr_access(struct etmv4_config *config)
1245 {
1246 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1247 config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1248 }
1249
etm4_set_default_config(struct etmv4_config * config)1250 static void etm4_set_default_config(struct etmv4_config *config)
1251 {
1252 /* disable all events tracing */
1253 config->eventctrl0 = 0x0;
1254 config->eventctrl1 = 0x0;
1255
1256 /* disable stalling */
1257 config->stall_ctrl = 0x0;
1258
1259 /* enable trace synchronization every 4096 bytes, if available */
1260 config->syncfreq = 0xC;
1261
1262 /* disable timestamp event */
1263 config->ts_ctrl = 0x0;
1264
1265 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1266 config->vinst_ctrl = BIT(0);
1267
1268 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1269 etm4_set_victlr_access(config);
1270 }
1271
etm4_get_ns_access_type(struct etmv4_config * config)1272 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1273 {
1274 u64 access_type = 0;
1275
1276 /*
1277 * EXLEVEL_NS, for NonSecure Exception levels.
1278 * The mask here is a generic value and must be
1279 * shifted to the corresponding field for the registers
1280 */
1281 if (!is_kernel_in_hyp_mode()) {
1282 /* Stay away from hypervisor mode for non-VHE */
1283 access_type = ETM_EXLEVEL_NS_HYP;
1284 if (config->mode & ETM_MODE_EXCL_KERN)
1285 access_type |= ETM_EXLEVEL_NS_OS;
1286 } else if (config->mode & ETM_MODE_EXCL_KERN) {
1287 access_type = ETM_EXLEVEL_NS_HYP;
1288 }
1289
1290 if (config->mode & ETM_MODE_EXCL_USER)
1291 access_type |= ETM_EXLEVEL_NS_APP;
1292
1293 return access_type;
1294 }
1295
1296 /*
1297 * Construct the exception level masks for a given config.
1298 * This must be shifted to the corresponding register field
1299 * for usage.
1300 */
etm4_get_access_type(struct etmv4_config * config)1301 static u64 etm4_get_access_type(struct etmv4_config *config)
1302 {
1303 /* All Secure exception levels are excluded from the trace */
1304 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1305 }
1306
etm4_get_comparator_access_type(struct etmv4_config * config)1307 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1308 {
1309 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1310 }
1311
etm4_set_comparator_filter(struct etmv4_config * config,u64 start,u64 stop,int comparator)1312 static void etm4_set_comparator_filter(struct etmv4_config *config,
1313 u64 start, u64 stop, int comparator)
1314 {
1315 u64 access_type = etm4_get_comparator_access_type(config);
1316
1317 /* First half of default address comparator */
1318 config->addr_val[comparator] = start;
1319 config->addr_acc[comparator] = access_type;
1320 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1321
1322 /* Second half of default address comparator */
1323 config->addr_val[comparator + 1] = stop;
1324 config->addr_acc[comparator + 1] = access_type;
1325 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1326
1327 /*
1328 * Configure the ViewInst function to include this address range
1329 * comparator.
1330 *
1331 * @comparator is divided by two since it is the index in the
1332 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1333 * address range comparator _pairs_.
1334 *
1335 * Therefore:
1336 * index 0 -> compatator pair 0
1337 * index 2 -> comparator pair 1
1338 * index 4 -> comparator pair 2
1339 * ...
1340 * index 14 -> comparator pair 7
1341 */
1342 config->viiectlr |= BIT(comparator / 2);
1343 }
1344
etm4_set_start_stop_filter(struct etmv4_config * config,u64 address,int comparator,enum etm_addr_type type)1345 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1346 u64 address, int comparator,
1347 enum etm_addr_type type)
1348 {
1349 int shift;
1350 u64 access_type = etm4_get_comparator_access_type(config);
1351
1352 /* Configure the comparator */
1353 config->addr_val[comparator] = address;
1354 config->addr_acc[comparator] = access_type;
1355 config->addr_type[comparator] = type;
1356
1357 /*
1358 * Configure ViewInst Start-Stop control register.
1359 * Addresses configured to start tracing go from bit 0 to n-1,
1360 * while those configured to stop tracing from 16 to 16 + n-1.
1361 */
1362 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1363 config->vissctlr |= BIT(shift + comparator);
1364 }
1365
etm4_set_default_filter(struct etmv4_config * config)1366 static void etm4_set_default_filter(struct etmv4_config *config)
1367 {
1368 /* Trace everything 'default' filter achieved by no filtering */
1369 config->viiectlr = 0x0;
1370
1371 /*
1372 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1373 * in the started state
1374 */
1375 config->vinst_ctrl |= BIT(9);
1376 config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1377
1378 /* No start-stop filtering for ViewInst */
1379 config->vissctlr = 0x0;
1380 }
1381
etm4_set_default(struct etmv4_config * config)1382 static void etm4_set_default(struct etmv4_config *config)
1383 {
1384 if (WARN_ON_ONCE(!config))
1385 return;
1386
1387 /*
1388 * Make default initialisation trace everything
1389 *
1390 * This is done by a minimum default config sufficient to enable
1391 * full instruction trace - with a default filter for trace all
1392 * achieved by having no filtering.
1393 */
1394 etm4_set_default_config(config);
1395 etm4_set_default_filter(config);
1396 }
1397
etm4_get_next_comparator(struct etmv4_drvdata * drvdata,u32 type)1398 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1399 {
1400 int nr_comparator, index = 0;
1401 struct etmv4_config *config = &drvdata->config;
1402
1403 /*
1404 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1405 * for the total number of comparators.
1406 */
1407 nr_comparator = drvdata->nr_addr_cmp * 2;
1408
1409 /* Go through the tally of comparators looking for a free one. */
1410 while (index < nr_comparator) {
1411 switch (type) {
1412 case ETM_ADDR_TYPE_RANGE:
1413 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1414 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1415 return index;
1416
1417 /* Address range comparators go in pairs */
1418 index += 2;
1419 break;
1420 case ETM_ADDR_TYPE_START:
1421 case ETM_ADDR_TYPE_STOP:
1422 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1423 return index;
1424
1425 /* Start/stop address can have odd indexes */
1426 index += 1;
1427 break;
1428 default:
1429 return -EINVAL;
1430 }
1431 }
1432
1433 /* If we are here all the comparators have been used. */
1434 return -ENOSPC;
1435 }
1436
etm4_set_event_filters(struct etmv4_drvdata * drvdata,struct perf_event * event)1437 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1438 struct perf_event *event)
1439 {
1440 int i, comparator, ret = 0;
1441 u64 address;
1442 struct etmv4_config *config = &drvdata->config;
1443 struct etm_filters *filters = event->hw.addr_filters;
1444
1445 if (!filters)
1446 goto default_filter;
1447
1448 /* Sync events with what Perf got */
1449 perf_event_addr_filters_sync(event);
1450
1451 /*
1452 * If there are no filters to deal with simply go ahead with
1453 * the default filter, i.e the entire address range.
1454 */
1455 if (!filters->nr_filters)
1456 goto default_filter;
1457
1458 for (i = 0; i < filters->nr_filters; i++) {
1459 struct etm_filter *filter = &filters->etm_filter[i];
1460 enum etm_addr_type type = filter->type;
1461
1462 /* See if a comparator is free. */
1463 comparator = etm4_get_next_comparator(drvdata, type);
1464 if (comparator < 0) {
1465 ret = comparator;
1466 goto out;
1467 }
1468
1469 switch (type) {
1470 case ETM_ADDR_TYPE_RANGE:
1471 etm4_set_comparator_filter(config,
1472 filter->start_addr,
1473 filter->stop_addr,
1474 comparator);
1475 /*
1476 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1477 * in the started state
1478 */
1479 config->vinst_ctrl |= BIT(9);
1480
1481 /* No start-stop filtering for ViewInst */
1482 config->vissctlr = 0x0;
1483 break;
1484 case ETM_ADDR_TYPE_START:
1485 case ETM_ADDR_TYPE_STOP:
1486 /* Get the right start or stop address */
1487 address = (type == ETM_ADDR_TYPE_START ?
1488 filter->start_addr :
1489 filter->stop_addr);
1490
1491 /* Configure comparator */
1492 etm4_set_start_stop_filter(config, address,
1493 comparator, type);
1494
1495 /*
1496 * If filters::ssstatus == 1, trace acquisition was
1497 * started but the process was yanked away before the
1498 * the stop address was hit. As such the start/stop
1499 * logic needs to be re-started so that tracing can
1500 * resume where it left.
1501 *
1502 * The start/stop logic status when a process is
1503 * scheduled out is checked in function
1504 * etm4_disable_perf().
1505 */
1506 if (filters->ssstatus)
1507 config->vinst_ctrl |= BIT(9);
1508
1509 /* No include/exclude filtering for ViewInst */
1510 config->viiectlr = 0x0;
1511 break;
1512 default:
1513 ret = -EINVAL;
1514 goto out;
1515 }
1516 }
1517
1518 goto out;
1519
1520
1521 default_filter:
1522 etm4_set_default_filter(config);
1523
1524 out:
1525 return ret;
1526 }
1527
etm4_config_trace_mode(struct etmv4_config * config)1528 void etm4_config_trace_mode(struct etmv4_config *config)
1529 {
1530 u32 mode;
1531
1532 mode = config->mode;
1533 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1534
1535 /* excluding kernel AND user space doesn't make sense */
1536 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1537
1538 /* nothing to do if neither flags are set */
1539 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1540 return;
1541
1542 etm4_set_victlr_access(config);
1543 }
1544
etm4_online_cpu(unsigned int cpu)1545 static int etm4_online_cpu(unsigned int cpu)
1546 {
1547 if (!etmdrvdata[cpu])
1548 return 0;
1549
1550 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1551 coresight_enable(etmdrvdata[cpu]->csdev);
1552 return 0;
1553 }
1554
etm4_starting_cpu(unsigned int cpu)1555 static int etm4_starting_cpu(unsigned int cpu)
1556 {
1557 if (!etmdrvdata[cpu])
1558 return 0;
1559
1560 spin_lock(&etmdrvdata[cpu]->spinlock);
1561 if (!etmdrvdata[cpu]->os_unlock)
1562 etm4_os_unlock(etmdrvdata[cpu]);
1563
1564 if (local_read(&etmdrvdata[cpu]->mode))
1565 etm4_enable_hw(etmdrvdata[cpu]);
1566 spin_unlock(&etmdrvdata[cpu]->spinlock);
1567 return 0;
1568 }
1569
etm4_dying_cpu(unsigned int cpu)1570 static int etm4_dying_cpu(unsigned int cpu)
1571 {
1572 if (!etmdrvdata[cpu])
1573 return 0;
1574
1575 spin_lock(&etmdrvdata[cpu]->spinlock);
1576 if (local_read(&etmdrvdata[cpu]->mode))
1577 etm4_disable_hw(etmdrvdata[cpu]);
1578 spin_unlock(&etmdrvdata[cpu]->spinlock);
1579 return 0;
1580 }
1581
etm4_init_trace_id(struct etmv4_drvdata * drvdata)1582 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1583 {
1584 drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1585 }
1586
__etm4_cpu_save(struct etmv4_drvdata * drvdata)1587 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1588 {
1589 int i, ret = 0;
1590 struct etmv4_save_state *state;
1591 struct coresight_device *csdev = drvdata->csdev;
1592 struct csdev_access *csa;
1593 struct device *etm_dev;
1594
1595 if (WARN_ON(!csdev))
1596 return -ENODEV;
1597
1598 etm_dev = &csdev->dev;
1599 csa = &csdev->access;
1600
1601 /*
1602 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1603 * of ARM IHI 0064D
1604 */
1605 dsb(sy);
1606 isb();
1607
1608 etm4_cs_unlock(drvdata, csa);
1609 /* Lock the OS lock to disable trace and external debugger access */
1610 etm4_os_lock(drvdata);
1611
1612 /* wait for TRCSTATR.PMSTABLE to go up */
1613 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1614 dev_err(etm_dev,
1615 "timeout while waiting for PM Stable Status\n");
1616 etm4_os_unlock(drvdata);
1617 ret = -EBUSY;
1618 goto out;
1619 }
1620
1621 state = drvdata->save_state;
1622
1623 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1624 if (drvdata->nr_pe)
1625 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1626 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1627 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1628 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1629 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1630 if (drvdata->stallctl)
1631 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1632 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1633 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1634 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1635 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1636 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1637 state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1638
1639 state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1640 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1641 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1642 if (drvdata->nr_pe_cmp)
1643 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1644 state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1645 state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1646 state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1647
1648 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1649 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1650
1651 if (drvdata->nrseqstate) {
1652 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1653 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1654 }
1655 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1656
1657 for (i = 0; i < drvdata->nr_cntr; i++) {
1658 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1659 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1660 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1661 }
1662
1663 for (i = 0; i < drvdata->nr_resource * 2; i++)
1664 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1665
1666 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1667 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1668 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1669 if (etm4x_sspcicrn_present(drvdata, i))
1670 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1671 }
1672
1673 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1674 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1675 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1676 }
1677
1678 /*
1679 * Data trace stream is architecturally prohibited for A profile cores
1680 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1681 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1682 * unit") of ARM IHI 0064D.
1683 */
1684
1685 for (i = 0; i < drvdata->numcidc; i++)
1686 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1687
1688 for (i = 0; i < drvdata->numvmidc; i++)
1689 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1690
1691 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1692 if (drvdata->numcidc > 4)
1693 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1694
1695 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1696 if (drvdata->numvmidc > 4)
1697 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1698
1699 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1700
1701 if (!drvdata->skip_power_up)
1702 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1703
1704 /* wait for TRCSTATR.IDLE to go up */
1705 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1706 dev_err(etm_dev,
1707 "timeout while waiting for Idle Trace Status\n");
1708 etm4_os_unlock(drvdata);
1709 ret = -EBUSY;
1710 goto out;
1711 }
1712
1713 drvdata->state_needs_restore = true;
1714
1715 /*
1716 * Power can be removed from the trace unit now. We do this to
1717 * potentially save power on systems that respect the TRCPDCR_PU
1718 * despite requesting software to save/restore state.
1719 */
1720 if (!drvdata->skip_power_up)
1721 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1722 TRCPDCR);
1723 out:
1724 etm4_cs_lock(drvdata, csa);
1725 return ret;
1726 }
1727
etm4_cpu_save(struct etmv4_drvdata * drvdata)1728 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1729 {
1730 int ret = 0;
1731
1732 /* Save the TRFCR irrespective of whether the ETM is ON */
1733 if (drvdata->trfcr)
1734 drvdata->save_trfcr = read_trfcr();
1735 /*
1736 * Save and restore the ETM Trace registers only if
1737 * the ETM is active.
1738 */
1739 if (local_read(&drvdata->mode) && drvdata->save_state)
1740 ret = __etm4_cpu_save(drvdata);
1741 return ret;
1742 }
1743
__etm4_cpu_restore(struct etmv4_drvdata * drvdata)1744 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1745 {
1746 int i;
1747 struct etmv4_save_state *state = drvdata->save_state;
1748 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1749 struct csdev_access *csa = &tmp_csa;
1750
1751 etm4_cs_unlock(drvdata, csa);
1752 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1753
1754 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1755 if (drvdata->nr_pe)
1756 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1757 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1758 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1759 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1760 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1761 if (drvdata->stallctl)
1762 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1763 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1764 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1765 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1766 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1767 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1768 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1769
1770 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1771 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1772 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1773 if (drvdata->nr_pe_cmp)
1774 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1775 etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1776 etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1777 etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1778
1779 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1780 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1781
1782 if (drvdata->nrseqstate) {
1783 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1784 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1785 }
1786 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1787
1788 for (i = 0; i < drvdata->nr_cntr; i++) {
1789 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1790 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1791 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1792 }
1793
1794 for (i = 0; i < drvdata->nr_resource * 2; i++)
1795 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1796
1797 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1798 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1799 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1800 if (etm4x_sspcicrn_present(drvdata, i))
1801 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1802 }
1803
1804 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1805 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1806 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1807 }
1808
1809 for (i = 0; i < drvdata->numcidc; i++)
1810 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1811
1812 for (i = 0; i < drvdata->numvmidc; i++)
1813 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1814
1815 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1816 if (drvdata->numcidc > 4)
1817 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1818
1819 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1820 if (drvdata->numvmidc > 4)
1821 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1822
1823 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1824
1825 if (!drvdata->skip_power_up)
1826 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1827
1828 drvdata->state_needs_restore = false;
1829
1830 /*
1831 * As recommended by section 4.3.7 ("Synchronization when using the
1832 * memory-mapped interface") of ARM IHI 0064D
1833 */
1834 dsb(sy);
1835 isb();
1836
1837 /* Unlock the OS lock to re-enable trace and external debug access */
1838 etm4_os_unlock(drvdata);
1839 etm4_cs_lock(drvdata, csa);
1840 }
1841
etm4_cpu_restore(struct etmv4_drvdata * drvdata)1842 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1843 {
1844 if (drvdata->trfcr)
1845 write_trfcr(drvdata->save_trfcr);
1846 if (drvdata->state_needs_restore)
1847 __etm4_cpu_restore(drvdata);
1848 }
1849
etm4_cpu_pm_notify(struct notifier_block * nb,unsigned long cmd,void * v)1850 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1851 void *v)
1852 {
1853 struct etmv4_drvdata *drvdata;
1854 unsigned int cpu = smp_processor_id();
1855
1856 if (!etmdrvdata[cpu])
1857 return NOTIFY_OK;
1858
1859 drvdata = etmdrvdata[cpu];
1860
1861 if (WARN_ON_ONCE(drvdata->cpu != cpu))
1862 return NOTIFY_BAD;
1863
1864 switch (cmd) {
1865 case CPU_PM_ENTER:
1866 if (etm4_cpu_save(drvdata))
1867 return NOTIFY_BAD;
1868 break;
1869 case CPU_PM_EXIT:
1870 case CPU_PM_ENTER_FAILED:
1871 etm4_cpu_restore(drvdata);
1872 break;
1873 default:
1874 return NOTIFY_DONE;
1875 }
1876
1877 return NOTIFY_OK;
1878 }
1879
1880 static struct notifier_block etm4_cpu_pm_nb = {
1881 .notifier_call = etm4_cpu_pm_notify,
1882 };
1883
1884 /* Setup PM. Deals with error conditions and counts */
etm4_pm_setup(void)1885 static int __init etm4_pm_setup(void)
1886 {
1887 int ret;
1888
1889 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1890 if (ret)
1891 return ret;
1892
1893 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1894 "arm/coresight4:starting",
1895 etm4_starting_cpu, etm4_dying_cpu);
1896
1897 if (ret)
1898 goto unregister_notifier;
1899
1900 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1901 "arm/coresight4:online",
1902 etm4_online_cpu, NULL);
1903
1904 /* HP dyn state ID returned in ret on success */
1905 if (ret > 0) {
1906 hp_online = ret;
1907 return 0;
1908 }
1909
1910 /* failed dyn state - remove others */
1911 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1912
1913 unregister_notifier:
1914 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1915 return ret;
1916 }
1917
etm4_pm_clear(void)1918 static void etm4_pm_clear(void)
1919 {
1920 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1921 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1922 if (hp_online) {
1923 cpuhp_remove_state_nocalls(hp_online);
1924 hp_online = 0;
1925 }
1926 }
1927
etm4_probe(struct device * dev,void __iomem * base,u32 etm_pid)1928 static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
1929 {
1930 int ret;
1931 struct coresight_platform_data *pdata = NULL;
1932 struct etmv4_drvdata *drvdata;
1933 struct coresight_desc desc = { 0 };
1934 struct etm4_init_arg init_arg = { 0 };
1935 u8 major, minor;
1936 char *type_name;
1937
1938 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1939 if (!drvdata)
1940 return -ENOMEM;
1941
1942 dev_set_drvdata(dev, drvdata);
1943
1944 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1945 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1946 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1947
1948 if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1949 drvdata->save_state = devm_kmalloc(dev,
1950 sizeof(struct etmv4_save_state), GFP_KERNEL);
1951 if (!drvdata->save_state)
1952 return -ENOMEM;
1953 }
1954
1955 drvdata->base = base;
1956
1957 spin_lock_init(&drvdata->spinlock);
1958
1959 drvdata->cpu = coresight_get_cpu(dev);
1960 if (drvdata->cpu < 0)
1961 return drvdata->cpu;
1962
1963 init_arg.drvdata = drvdata;
1964 init_arg.csa = &desc.access;
1965 init_arg.pid = etm_pid;
1966
1967 if (smp_call_function_single(drvdata->cpu,
1968 etm4_init_arch_data, &init_arg, 1))
1969 dev_err(dev, "ETM arch init failed\n");
1970
1971 if (!drvdata->arch)
1972 return -EINVAL;
1973
1974 /* TRCPDCR is not accessible with system instructions. */
1975 if (!desc.access.io_mem ||
1976 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1977 drvdata->skip_power_up = true;
1978
1979 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
1980 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
1981
1982 if (etm4x_is_ete(drvdata)) {
1983 type_name = "ete";
1984 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
1985 major -= 4;
1986 } else {
1987 type_name = "etm";
1988 }
1989
1990 desc.name = devm_kasprintf(dev, GFP_KERNEL,
1991 "%s%d", type_name, drvdata->cpu);
1992 if (!desc.name)
1993 return -ENOMEM;
1994
1995 etm4_init_trace_id(drvdata);
1996 etm4_set_default(&drvdata->config);
1997
1998 pdata = coresight_get_platform_data(dev);
1999 if (IS_ERR(pdata))
2000 return PTR_ERR(pdata);
2001
2002 dev->platform_data = pdata;
2003
2004 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
2005 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
2006 desc.ops = &etm4_cs_ops;
2007 desc.pdata = pdata;
2008 desc.dev = dev;
2009 desc.groups = coresight_etmv4_groups;
2010 drvdata->csdev = coresight_register(&desc);
2011 if (IS_ERR(drvdata->csdev))
2012 return PTR_ERR(drvdata->csdev);
2013
2014 ret = etm_perf_symlink(drvdata->csdev, true);
2015 if (ret) {
2016 coresight_unregister(drvdata->csdev);
2017 return ret;
2018 }
2019
2020 /* register with config infrastructure & load any current features */
2021 ret = etm4_cscfg_register(drvdata->csdev);
2022 if (ret) {
2023 coresight_unregister(drvdata->csdev);
2024 return ret;
2025 }
2026
2027 etmdrvdata[drvdata->cpu] = drvdata;
2028
2029 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2030 drvdata->cpu, type_name, major, minor);
2031
2032 if (boot_enable) {
2033 coresight_enable(drvdata->csdev);
2034 drvdata->boot_enable = true;
2035 }
2036
2037 return 0;
2038 }
2039
etm4_probe_amba(struct amba_device * adev,const struct amba_id * id)2040 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2041 {
2042 void __iomem *base;
2043 struct device *dev = &adev->dev;
2044 struct resource *res = &adev->res;
2045 int ret;
2046
2047 /* Validity for the resource is already checked by the AMBA core */
2048 base = devm_ioremap_resource(dev, res);
2049 if (IS_ERR(base))
2050 return PTR_ERR(base);
2051
2052 ret = etm4_probe(dev, base, id->id);
2053 if (!ret)
2054 pm_runtime_put(&adev->dev);
2055
2056 return ret;
2057 }
2058
etm4_probe_platform_dev(struct platform_device * pdev)2059 static int etm4_probe_platform_dev(struct platform_device *pdev)
2060 {
2061 int ret;
2062
2063 pm_runtime_get_noresume(&pdev->dev);
2064 pm_runtime_set_active(&pdev->dev);
2065 pm_runtime_enable(&pdev->dev);
2066
2067 /*
2068 * System register based devices could match the
2069 * HW by reading appropriate registers on the HW
2070 * and thus we could skip the PID.
2071 */
2072 ret = etm4_probe(&pdev->dev, NULL, 0);
2073
2074 pm_runtime_put(&pdev->dev);
2075 return ret;
2076 }
2077
2078 static struct amba_cs_uci_id uci_id_etm4[] = {
2079 {
2080 /* ETMv4 UCI data */
2081 .devarch = ETM_DEVARCH_ETMv4x_ARCH,
2082 .devarch_mask = ETM_DEVARCH_ID_MASK,
2083 .devtype = 0x00000013,
2084 }
2085 };
2086
clear_etmdrvdata(void * info)2087 static void clear_etmdrvdata(void *info)
2088 {
2089 int cpu = *(int *)info;
2090
2091 etmdrvdata[cpu] = NULL;
2092 }
2093
etm4_remove_dev(struct etmv4_drvdata * drvdata)2094 static void etm4_remove_dev(struct etmv4_drvdata *drvdata)
2095 {
2096 etm_perf_symlink(drvdata->csdev, false);
2097 /*
2098 * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2099 * and CPU hotplug call backs.
2100 */
2101 cpus_read_lock();
2102 /*
2103 * The readers for etmdrvdata[] are CPU hotplug call backs
2104 * and PM notification call backs. Change etmdrvdata[i] on
2105 * CPU i ensures these call backs has consistent view
2106 * inside one call back function.
2107 */
2108 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2109 etmdrvdata[drvdata->cpu] = NULL;
2110
2111 cpus_read_unlock();
2112
2113 cscfg_unregister_csdev(drvdata->csdev);
2114 coresight_unregister(drvdata->csdev);
2115 }
2116
etm4_remove_amba(struct amba_device * adev)2117 static void etm4_remove_amba(struct amba_device *adev)
2118 {
2119 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2120
2121 if (drvdata)
2122 etm4_remove_dev(drvdata);
2123 }
2124
etm4_remove_platform_dev(struct platform_device * pdev)2125 static int etm4_remove_platform_dev(struct platform_device *pdev)
2126 {
2127 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2128
2129 if (drvdata)
2130 etm4_remove_dev(drvdata);
2131 pm_runtime_disable(&pdev->dev);
2132 return 0;
2133 }
2134
2135 static const struct amba_id etm4_ids[] = {
2136 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
2137 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
2138 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
2139 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
2140 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2141 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2142 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2143 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2144 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2145 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2146 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2147 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2148 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2149 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2150 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2151 CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2152 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2153 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2154 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2155 {},
2156 };
2157
2158 MODULE_DEVICE_TABLE(amba, etm4_ids);
2159
2160 static struct amba_driver etm4x_amba_driver = {
2161 .drv = {
2162 .name = "coresight-etm4x",
2163 .owner = THIS_MODULE,
2164 .suppress_bind_attrs = true,
2165 },
2166 .probe = etm4_probe_amba,
2167 .remove = etm4_remove_amba,
2168 .id_table = etm4_ids,
2169 };
2170
2171 static const struct of_device_id etm4_sysreg_match[] = {
2172 { .compatible = "arm,coresight-etm4x-sysreg" },
2173 { .compatible = "arm,embedded-trace-extension" },
2174 {}
2175 };
2176
2177 static struct platform_driver etm4_platform_driver = {
2178 .probe = etm4_probe_platform_dev,
2179 .remove = etm4_remove_platform_dev,
2180 .driver = {
2181 .name = "coresight-etm4x",
2182 .of_match_table = etm4_sysreg_match,
2183 .suppress_bind_attrs = true,
2184 },
2185 };
2186
etm4x_init(void)2187 static int __init etm4x_init(void)
2188 {
2189 int ret;
2190
2191 ret = etm4_pm_setup();
2192
2193 /* etm4_pm_setup() does its own cleanup - exit on error */
2194 if (ret)
2195 return ret;
2196
2197 ret = amba_driver_register(&etm4x_amba_driver);
2198 if (ret) {
2199 pr_err("Error registering etm4x AMBA driver\n");
2200 goto clear_pm;
2201 }
2202
2203 ret = platform_driver_register(&etm4_platform_driver);
2204 if (!ret)
2205 return 0;
2206
2207 pr_err("Error registering etm4x platform driver\n");
2208 amba_driver_unregister(&etm4x_amba_driver);
2209
2210 clear_pm:
2211 etm4_pm_clear();
2212 return ret;
2213 }
2214
etm4x_exit(void)2215 static void __exit etm4x_exit(void)
2216 {
2217 amba_driver_unregister(&etm4x_amba_driver);
2218 platform_driver_unregister(&etm4_platform_driver);
2219 etm4_pm_clear();
2220 }
2221
2222 module_init(etm4x_init);
2223 module_exit(etm4x_exit);
2224
2225 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2226 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2227 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2228 MODULE_LICENSE("GPL v2");
2229