1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _CORESIGHT_CORESIGHT_ETM_H
7 #define _CORESIGHT_CORESIGHT_ETM_H
8
9 #include <asm/local.h>
10 #include <linux/const.h>
11 #include <linux/spinlock.h>
12 #include <linux/types.h>
13 #include "coresight-priv.h"
14
15 /*
16 * Device registers:
17 * 0x000 - 0x2FC: Trace registers
18 * 0x300 - 0x314: Management registers
19 * 0x318 - 0xEFC: Trace registers
20 * 0xF00: Management registers
21 * 0xFA0 - 0xFA4: Trace registers
22 * 0xFA8 - 0xFFC: Management registers
23 */
24 /* Trace registers (0x000-0x2FC) */
25 /* Main control and configuration registers */
26 #define TRCPRGCTLR 0x004
27 #define TRCPROCSELR 0x008
28 #define TRCSTATR 0x00C
29 #define TRCCONFIGR 0x010
30 #define TRCAUXCTLR 0x018
31 #define TRCEVENTCTL0R 0x020
32 #define TRCEVENTCTL1R 0x024
33 #define TRCRSR 0x028
34 #define TRCSTALLCTLR 0x02C
35 #define TRCTSCTLR 0x030
36 #define TRCSYNCPR 0x034
37 #define TRCCCCTLR 0x038
38 #define TRCBBCTLR 0x03C
39 #define TRCTRACEIDR 0x040
40 #define TRCQCTLR 0x044
41 /* Filtering control registers */
42 #define TRCVICTLR 0x080
43 #define TRCVIIECTLR 0x084
44 #define TRCVISSCTLR 0x088
45 #define TRCVIPCSSCTLR 0x08C
46 #define TRCVDCTLR 0x0A0
47 #define TRCVDSACCTLR 0x0A4
48 #define TRCVDARCCTLR 0x0A8
49 /* Derived resources registers */
50 #define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */
51 #define TRCSEQRSTEVR 0x118
52 #define TRCSEQSTR 0x11C
53 #define TRCEXTINSELR 0x120
54 #define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */
55 #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */
56 #define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */
57 #define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */
58 /* ID registers */
59 #define TRCIDR8 0x180
60 #define TRCIDR9 0x184
61 #define TRCIDR10 0x188
62 #define TRCIDR11 0x18C
63 #define TRCIDR12 0x190
64 #define TRCIDR13 0x194
65 #define TRCIMSPEC0 0x1C0
66 #define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */
67 #define TRCIDR0 0x1E0
68 #define TRCIDR1 0x1E4
69 #define TRCIDR2 0x1E8
70 #define TRCIDR3 0x1EC
71 #define TRCIDR4 0x1F0
72 #define TRCIDR5 0x1F4
73 #define TRCIDR6 0x1F8
74 #define TRCIDR7 0x1FC
75 /*
76 * Resource selection registers, n = 2-31.
77 * First pair (regs 0, 1) is always present and is reserved.
78 */
79 #define TRCRSCTLRn(n) (0x200 + (n * 4))
80 /* Single-shot comparator registers, n = 0-7 */
81 #define TRCSSCCRn(n) (0x280 + (n * 4))
82 #define TRCSSCSRn(n) (0x2A0 + (n * 4))
83 #define TRCSSPCICRn(n) (0x2C0 + (n * 4))
84 /* Management registers (0x300-0x314) */
85 #define TRCOSLAR 0x300
86 #define TRCOSLSR 0x304
87 #define TRCPDCR 0x310
88 #define TRCPDSR 0x314
89 /* Trace registers (0x318-0xEFC) */
90 /* Address Comparator registers n = 0-15 */
91 #define TRCACVRn(n) (0x400 + (n * 8))
92 #define TRCACATRn(n) (0x480 + (n * 8))
93 /* Data Value Comparator Value registers, n = 0-7 */
94 #define TRCDVCVRn(n) (0x500 + (n * 16))
95 #define TRCDVCMRn(n) (0x580 + (n * 16))
96 /* ContextID/Virtual ContextID comparators, n = 0-7 */
97 #define TRCCIDCVRn(n) (0x600 + (n * 8))
98 #define TRCVMIDCVRn(n) (0x640 + (n * 8))
99 #define TRCCIDCCTLR0 0x680
100 #define TRCCIDCCTLR1 0x684
101 #define TRCVMIDCCTLR0 0x688
102 #define TRCVMIDCCTLR1 0x68C
103 /* Management register (0xF00) */
104 /* Integration control registers */
105 #define TRCITCTRL 0xF00
106 /* Trace registers (0xFA0-0xFA4) */
107 /* Claim tag registers */
108 #define TRCCLAIMSET 0xFA0
109 #define TRCCLAIMCLR 0xFA4
110 /* Management registers (0xFA8-0xFFC) */
111 #define TRCDEVAFF0 0xFA8
112 #define TRCDEVAFF1 0xFAC
113 #define TRCLAR 0xFB0
114 #define TRCLSR 0xFB4
115 #define TRCAUTHSTATUS 0xFB8
116 #define TRCDEVARCH 0xFBC
117 #define TRCDEVID 0xFC8
118 #define TRCDEVTYPE 0xFCC
119 #define TRCPIDR4 0xFD0
120 #define TRCPIDR5 0xFD4
121 #define TRCPIDR6 0xFD8
122 #define TRCPIDR7 0xFDC
123 #define TRCPIDR0 0xFE0
124 #define TRCPIDR1 0xFE4
125 #define TRCPIDR2 0xFE8
126 #define TRCPIDR3 0xFEC
127 #define TRCCIDR0 0xFF0
128 #define TRCCIDR1 0xFF4
129 #define TRCCIDR2 0xFF8
130 #define TRCCIDR3 0xFFC
131
132 #define TRCRSR_TA BIT(12)
133
134 /*
135 * System instructions to access ETM registers.
136 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
137 */
138 #define ETM4x_OFFSET_TO_REG(x) ((x) >> 2)
139
140 #define ETM4x_CRn(n) (((n) >> 7) & 0x7)
141 #define ETM4x_Op2(n) (((n) >> 4) & 0x7)
142 #define ETM4x_CRm(n) ((n) & 0xf)
143
144 #include <asm/sysreg.h>
145 #define ETM4x_REG_NUM_TO_SYSREG(n) \
146 sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n))
147
148 #define READ_ETM4x_REG(reg) \
149 read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg)))
150 #define WRITE_ETM4x_REG(val, reg) \
151 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))
152
153 #define read_etm4x_sysreg_const_offset(offset) \
154 READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset))
155
156 #define write_etm4x_sysreg_const_offset(val, offset) \
157 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))
158
159 #define CASE_READ(res, x) \
160 case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; }
161
162 #define CASE_WRITE(val, x) \
163 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }
164
165 #define CASE_NOP(__unused, x) \
166 case (x): /* fall through */
167
168 #define ETE_ONLY_SYSREG_LIST(op, val) \
169 CASE_##op((val), TRCRSR) \
170 CASE_##op((val), TRCEXTINSELRn(1)) \
171 CASE_##op((val), TRCEXTINSELRn(2)) \
172 CASE_##op((val), TRCEXTINSELRn(3))
173
174 /* List of registers accessible via System instructions */
175 #define ETM4x_ONLY_SYSREG_LIST(op, val) \
176 CASE_##op((val), TRCPROCSELR) \
177 CASE_##op((val), TRCVDCTLR) \
178 CASE_##op((val), TRCVDSACCTLR) \
179 CASE_##op((val), TRCVDARCCTLR) \
180 CASE_##op((val), TRCOSLAR)
181
182 #define ETM_COMMON_SYSREG_LIST(op, val) \
183 CASE_##op((val), TRCPRGCTLR) \
184 CASE_##op((val), TRCSTATR) \
185 CASE_##op((val), TRCCONFIGR) \
186 CASE_##op((val), TRCAUXCTLR) \
187 CASE_##op((val), TRCEVENTCTL0R) \
188 CASE_##op((val), TRCEVENTCTL1R) \
189 CASE_##op((val), TRCSTALLCTLR) \
190 CASE_##op((val), TRCTSCTLR) \
191 CASE_##op((val), TRCSYNCPR) \
192 CASE_##op((val), TRCCCCTLR) \
193 CASE_##op((val), TRCBBCTLR) \
194 CASE_##op((val), TRCTRACEIDR) \
195 CASE_##op((val), TRCQCTLR) \
196 CASE_##op((val), TRCVICTLR) \
197 CASE_##op((val), TRCVIIECTLR) \
198 CASE_##op((val), TRCVISSCTLR) \
199 CASE_##op((val), TRCVIPCSSCTLR) \
200 CASE_##op((val), TRCSEQEVRn(0)) \
201 CASE_##op((val), TRCSEQEVRn(1)) \
202 CASE_##op((val), TRCSEQEVRn(2)) \
203 CASE_##op((val), TRCSEQRSTEVR) \
204 CASE_##op((val), TRCSEQSTR) \
205 CASE_##op((val), TRCEXTINSELR) \
206 CASE_##op((val), TRCCNTRLDVRn(0)) \
207 CASE_##op((val), TRCCNTRLDVRn(1)) \
208 CASE_##op((val), TRCCNTRLDVRn(2)) \
209 CASE_##op((val), TRCCNTRLDVRn(3)) \
210 CASE_##op((val), TRCCNTCTLRn(0)) \
211 CASE_##op((val), TRCCNTCTLRn(1)) \
212 CASE_##op((val), TRCCNTCTLRn(2)) \
213 CASE_##op((val), TRCCNTCTLRn(3)) \
214 CASE_##op((val), TRCCNTVRn(0)) \
215 CASE_##op((val), TRCCNTVRn(1)) \
216 CASE_##op((val), TRCCNTVRn(2)) \
217 CASE_##op((val), TRCCNTVRn(3)) \
218 CASE_##op((val), TRCIDR8) \
219 CASE_##op((val), TRCIDR9) \
220 CASE_##op((val), TRCIDR10) \
221 CASE_##op((val), TRCIDR11) \
222 CASE_##op((val), TRCIDR12) \
223 CASE_##op((val), TRCIDR13) \
224 CASE_##op((val), TRCIMSPECn(0)) \
225 CASE_##op((val), TRCIMSPECn(1)) \
226 CASE_##op((val), TRCIMSPECn(2)) \
227 CASE_##op((val), TRCIMSPECn(3)) \
228 CASE_##op((val), TRCIMSPECn(4)) \
229 CASE_##op((val), TRCIMSPECn(5)) \
230 CASE_##op((val), TRCIMSPECn(6)) \
231 CASE_##op((val), TRCIMSPECn(7)) \
232 CASE_##op((val), TRCIDR0) \
233 CASE_##op((val), TRCIDR1) \
234 CASE_##op((val), TRCIDR2) \
235 CASE_##op((val), TRCIDR3) \
236 CASE_##op((val), TRCIDR4) \
237 CASE_##op((val), TRCIDR5) \
238 CASE_##op((val), TRCIDR6) \
239 CASE_##op((val), TRCIDR7) \
240 CASE_##op((val), TRCRSCTLRn(2)) \
241 CASE_##op((val), TRCRSCTLRn(3)) \
242 CASE_##op((val), TRCRSCTLRn(4)) \
243 CASE_##op((val), TRCRSCTLRn(5)) \
244 CASE_##op((val), TRCRSCTLRn(6)) \
245 CASE_##op((val), TRCRSCTLRn(7)) \
246 CASE_##op((val), TRCRSCTLRn(8)) \
247 CASE_##op((val), TRCRSCTLRn(9)) \
248 CASE_##op((val), TRCRSCTLRn(10)) \
249 CASE_##op((val), TRCRSCTLRn(11)) \
250 CASE_##op((val), TRCRSCTLRn(12)) \
251 CASE_##op((val), TRCRSCTLRn(13)) \
252 CASE_##op((val), TRCRSCTLRn(14)) \
253 CASE_##op((val), TRCRSCTLRn(15)) \
254 CASE_##op((val), TRCRSCTLRn(16)) \
255 CASE_##op((val), TRCRSCTLRn(17)) \
256 CASE_##op((val), TRCRSCTLRn(18)) \
257 CASE_##op((val), TRCRSCTLRn(19)) \
258 CASE_##op((val), TRCRSCTLRn(20)) \
259 CASE_##op((val), TRCRSCTLRn(21)) \
260 CASE_##op((val), TRCRSCTLRn(22)) \
261 CASE_##op((val), TRCRSCTLRn(23)) \
262 CASE_##op((val), TRCRSCTLRn(24)) \
263 CASE_##op((val), TRCRSCTLRn(25)) \
264 CASE_##op((val), TRCRSCTLRn(26)) \
265 CASE_##op((val), TRCRSCTLRn(27)) \
266 CASE_##op((val), TRCRSCTLRn(28)) \
267 CASE_##op((val), TRCRSCTLRn(29)) \
268 CASE_##op((val), TRCRSCTLRn(30)) \
269 CASE_##op((val), TRCRSCTLRn(31)) \
270 CASE_##op((val), TRCSSCCRn(0)) \
271 CASE_##op((val), TRCSSCCRn(1)) \
272 CASE_##op((val), TRCSSCCRn(2)) \
273 CASE_##op((val), TRCSSCCRn(3)) \
274 CASE_##op((val), TRCSSCCRn(4)) \
275 CASE_##op((val), TRCSSCCRn(5)) \
276 CASE_##op((val), TRCSSCCRn(6)) \
277 CASE_##op((val), TRCSSCCRn(7)) \
278 CASE_##op((val), TRCSSCSRn(0)) \
279 CASE_##op((val), TRCSSCSRn(1)) \
280 CASE_##op((val), TRCSSCSRn(2)) \
281 CASE_##op((val), TRCSSCSRn(3)) \
282 CASE_##op((val), TRCSSCSRn(4)) \
283 CASE_##op((val), TRCSSCSRn(5)) \
284 CASE_##op((val), TRCSSCSRn(6)) \
285 CASE_##op((val), TRCSSCSRn(7)) \
286 CASE_##op((val), TRCSSPCICRn(0)) \
287 CASE_##op((val), TRCSSPCICRn(1)) \
288 CASE_##op((val), TRCSSPCICRn(2)) \
289 CASE_##op((val), TRCSSPCICRn(3)) \
290 CASE_##op((val), TRCSSPCICRn(4)) \
291 CASE_##op((val), TRCSSPCICRn(5)) \
292 CASE_##op((val), TRCSSPCICRn(6)) \
293 CASE_##op((val), TRCSSPCICRn(7)) \
294 CASE_##op((val), TRCOSLSR) \
295 CASE_##op((val), TRCACVRn(0)) \
296 CASE_##op((val), TRCACVRn(1)) \
297 CASE_##op((val), TRCACVRn(2)) \
298 CASE_##op((val), TRCACVRn(3)) \
299 CASE_##op((val), TRCACVRn(4)) \
300 CASE_##op((val), TRCACVRn(5)) \
301 CASE_##op((val), TRCACVRn(6)) \
302 CASE_##op((val), TRCACVRn(7)) \
303 CASE_##op((val), TRCACVRn(8)) \
304 CASE_##op((val), TRCACVRn(9)) \
305 CASE_##op((val), TRCACVRn(10)) \
306 CASE_##op((val), TRCACVRn(11)) \
307 CASE_##op((val), TRCACVRn(12)) \
308 CASE_##op((val), TRCACVRn(13)) \
309 CASE_##op((val), TRCACVRn(14)) \
310 CASE_##op((val), TRCACVRn(15)) \
311 CASE_##op((val), TRCACATRn(0)) \
312 CASE_##op((val), TRCACATRn(1)) \
313 CASE_##op((val), TRCACATRn(2)) \
314 CASE_##op((val), TRCACATRn(3)) \
315 CASE_##op((val), TRCACATRn(4)) \
316 CASE_##op((val), TRCACATRn(5)) \
317 CASE_##op((val), TRCACATRn(6)) \
318 CASE_##op((val), TRCACATRn(7)) \
319 CASE_##op((val), TRCACATRn(8)) \
320 CASE_##op((val), TRCACATRn(9)) \
321 CASE_##op((val), TRCACATRn(10)) \
322 CASE_##op((val), TRCACATRn(11)) \
323 CASE_##op((val), TRCACATRn(12)) \
324 CASE_##op((val), TRCACATRn(13)) \
325 CASE_##op((val), TRCACATRn(14)) \
326 CASE_##op((val), TRCACATRn(15)) \
327 CASE_##op((val), TRCDVCVRn(0)) \
328 CASE_##op((val), TRCDVCVRn(1)) \
329 CASE_##op((val), TRCDVCVRn(2)) \
330 CASE_##op((val), TRCDVCVRn(3)) \
331 CASE_##op((val), TRCDVCVRn(4)) \
332 CASE_##op((val), TRCDVCVRn(5)) \
333 CASE_##op((val), TRCDVCVRn(6)) \
334 CASE_##op((val), TRCDVCVRn(7)) \
335 CASE_##op((val), TRCDVCMRn(0)) \
336 CASE_##op((val), TRCDVCMRn(1)) \
337 CASE_##op((val), TRCDVCMRn(2)) \
338 CASE_##op((val), TRCDVCMRn(3)) \
339 CASE_##op((val), TRCDVCMRn(4)) \
340 CASE_##op((val), TRCDVCMRn(5)) \
341 CASE_##op((val), TRCDVCMRn(6)) \
342 CASE_##op((val), TRCDVCMRn(7)) \
343 CASE_##op((val), TRCCIDCVRn(0)) \
344 CASE_##op((val), TRCCIDCVRn(1)) \
345 CASE_##op((val), TRCCIDCVRn(2)) \
346 CASE_##op((val), TRCCIDCVRn(3)) \
347 CASE_##op((val), TRCCIDCVRn(4)) \
348 CASE_##op((val), TRCCIDCVRn(5)) \
349 CASE_##op((val), TRCCIDCVRn(6)) \
350 CASE_##op((val), TRCCIDCVRn(7)) \
351 CASE_##op((val), TRCVMIDCVRn(0)) \
352 CASE_##op((val), TRCVMIDCVRn(1)) \
353 CASE_##op((val), TRCVMIDCVRn(2)) \
354 CASE_##op((val), TRCVMIDCVRn(3)) \
355 CASE_##op((val), TRCVMIDCVRn(4)) \
356 CASE_##op((val), TRCVMIDCVRn(5)) \
357 CASE_##op((val), TRCVMIDCVRn(6)) \
358 CASE_##op((val), TRCVMIDCVRn(7)) \
359 CASE_##op((val), TRCCIDCCTLR0) \
360 CASE_##op((val), TRCCIDCCTLR1) \
361 CASE_##op((val), TRCVMIDCCTLR0) \
362 CASE_##op((val), TRCVMIDCCTLR1) \
363 CASE_##op((val), TRCCLAIMSET) \
364 CASE_##op((val), TRCCLAIMCLR) \
365 CASE_##op((val), TRCAUTHSTATUS) \
366 CASE_##op((val), TRCDEVARCH) \
367 CASE_##op((val), TRCDEVID)
368
369 /* List of registers only accessible via memory-mapped interface */
370 #define ETM_MMAP_LIST(op, val) \
371 CASE_##op((val), TRCDEVTYPE) \
372 CASE_##op((val), TRCPDCR) \
373 CASE_##op((val), TRCPDSR) \
374 CASE_##op((val), TRCDEVAFF0) \
375 CASE_##op((val), TRCDEVAFF1) \
376 CASE_##op((val), TRCLAR) \
377 CASE_##op((val), TRCLSR) \
378 CASE_##op((val), TRCITCTRL) \
379 CASE_##op((val), TRCPIDR4) \
380 CASE_##op((val), TRCPIDR0) \
381 CASE_##op((val), TRCPIDR1) \
382 CASE_##op((val), TRCPIDR2) \
383 CASE_##op((val), TRCPIDR3)
384
385 #define ETM4x_READ_SYSREG_CASES(res) \
386 ETM_COMMON_SYSREG_LIST(READ, (res)) \
387 ETM4x_ONLY_SYSREG_LIST(READ, (res))
388
389 #define ETM4x_WRITE_SYSREG_CASES(val) \
390 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
391 ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
392
393 #define ETM_COMMON_SYSREG_LIST_CASES \
394 ETM_COMMON_SYSREG_LIST(NOP, __unused)
395
396 #define ETM4x_ONLY_SYSREG_LIST_CASES \
397 ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
398
399 #define ETM4x_SYSREG_LIST_CASES \
400 ETM_COMMON_SYSREG_LIST_CASES \
401 ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
402
403 #define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused)
404
405 /* ETE only supports system register access */
406 #define ETE_READ_CASES(res) \
407 ETM_COMMON_SYSREG_LIST(READ, (res)) \
408 ETE_ONLY_SYSREG_LIST(READ, (res))
409
410 #define ETE_WRITE_CASES(val) \
411 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
412 ETE_ONLY_SYSREG_LIST(WRITE, (val))
413
414 #define ETE_ONLY_SYSREG_LIST_CASES \
415 ETE_ONLY_SYSREG_LIST(NOP, __unused)
416
417 #define read_etm4x_sysreg_offset(offset, _64bit) \
418 ({ \
419 u64 __val; \
420 \
421 if (__is_constexpr((offset))) \
422 __val = read_etm4x_sysreg_const_offset((offset)); \
423 else \
424 __val = etm4x_sysreg_read((offset), true, (_64bit)); \
425 __val; \
426 })
427
428 #define write_etm4x_sysreg_offset(val, offset, _64bit) \
429 do { \
430 if (__builtin_constant_p((offset))) \
431 write_etm4x_sysreg_const_offset((val), \
432 (offset)); \
433 else \
434 etm4x_sysreg_write((val), (offset), true, \
435 (_64bit)); \
436 } while (0)
437
438
439 #define etm4x_relaxed_read32(csa, offset) \
440 ((u32)((csa)->io_mem ? \
441 readl_relaxed((csa)->base + (offset)) : \
442 read_etm4x_sysreg_offset((offset), false)))
443
444 #define etm4x_relaxed_read64(csa, offset) \
445 ((u64)((csa)->io_mem ? \
446 readq_relaxed((csa)->base + (offset)) : \
447 read_etm4x_sysreg_offset((offset), true)))
448
449 #define etm4x_read32(csa, offset) \
450 ({ \
451 u32 __val = etm4x_relaxed_read32((csa), (offset)); \
452 __iormb(__val); \
453 __val; \
454 })
455
456 #define etm4x_read64(csa, offset) \
457 ({ \
458 u64 __val = etm4x_relaxed_read64((csa), (offset)); \
459 __iormb(__val); \
460 __val; \
461 })
462
463 #define etm4x_relaxed_write32(csa, val, offset) \
464 do { \
465 if ((csa)->io_mem) \
466 writel_relaxed((val), (csa)->base + (offset)); \
467 else \
468 write_etm4x_sysreg_offset((val), (offset), \
469 false); \
470 } while (0)
471
472 #define etm4x_relaxed_write64(csa, val, offset) \
473 do { \
474 if ((csa)->io_mem) \
475 writeq_relaxed((val), (csa)->base + (offset)); \
476 else \
477 write_etm4x_sysreg_offset((val), (offset), \
478 true); \
479 } while (0)
480
481 #define etm4x_write32(csa, val, offset) \
482 do { \
483 __iowmb(); \
484 etm4x_relaxed_write32((csa), (val), (offset)); \
485 } while (0)
486
487 #define etm4x_write64(csa, val, offset) \
488 do { \
489 __iowmb(); \
490 etm4x_relaxed_write64((csa), (val), (offset)); \
491 } while (0)
492
493
494 /* ETMv4 resources */
495 #define ETM_MAX_NR_PE 8
496 #define ETMv4_MAX_CNTR 4
497 #define ETM_MAX_SEQ_STATES 4
498 #define ETM_MAX_EXT_INP_SEL 4
499 #define ETM_MAX_EXT_INP 256
500 #define ETM_MAX_EXT_OUT 4
501 #define ETM_MAX_SINGLE_ADDR_CMP 16
502 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
503 #define ETM_MAX_DATA_VAL_CMP 8
504 #define ETMv4_MAX_CTXID_CMP 8
505 #define ETM_MAX_VMID_CMP 8
506 #define ETM_MAX_PE_CMP 8
507 #define ETM_MAX_RES_SEL 32
508 #define ETM_MAX_SS_CMP 8
509
510 #define ETMv4_SYNC_MASK 0x1F
511 #define ETM_CYC_THRESHOLD_MASK 0xFFF
512 #define ETM_CYC_THRESHOLD_DEFAULT 0x100
513 #define ETMv4_EVENT_MASK 0xFF
514 #define ETM_CNTR_MAX_VAL 0xFFFF
515 #define ETM_TRACEID_MASK 0x3f
516
517 /* ETMv4 programming modes */
518 #define ETM_MODE_EXCLUDE BIT(0)
519 #define ETM_MODE_LOAD BIT(1)
520 #define ETM_MODE_STORE BIT(2)
521 #define ETM_MODE_LOAD_STORE BIT(3)
522 #define ETM_MODE_BB BIT(4)
523 #define ETMv4_MODE_CYCACC BIT(5)
524 #define ETMv4_MODE_CTXID BIT(6)
525 #define ETM_MODE_VMID BIT(7)
526 #define ETM_MODE_COND(val) BMVAL(val, 8, 10)
527 #define ETMv4_MODE_TIMESTAMP BIT(11)
528 #define ETM_MODE_RETURNSTACK BIT(12)
529 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
530 #define ETM_MODE_DATA_TRACE_ADDR BIT(15)
531 #define ETM_MODE_DATA_TRACE_VAL BIT(16)
532 #define ETM_MODE_ISTALL BIT(17)
533 #define ETM_MODE_DSTALL BIT(18)
534 #define ETM_MODE_ATB_TRIGGER BIT(19)
535 #define ETM_MODE_LPOVERRIDE BIT(20)
536 #define ETM_MODE_ISTALL_EN BIT(21)
537 #define ETM_MODE_DSTALL_EN BIT(22)
538 #define ETM_MODE_INSTPRIO BIT(23)
539 #define ETM_MODE_NOOVERFLOW BIT(24)
540 #define ETM_MODE_TRACE_RESET BIT(25)
541 #define ETM_MODE_TRACE_ERR BIT(26)
542 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
543 #define ETMv4_MODE_ALL (GENMASK(27, 0) | \
544 ETM_MODE_EXCL_KERN | \
545 ETM_MODE_EXCL_USER)
546
547 /*
548 * TRCOSLSR.OSLM advertises the OS Lock model.
549 * OSLM[2:0] = TRCOSLSR[4:3,0]
550 *
551 * 0b000 - Trace OS Lock is not implemented.
552 * 0b010 - Trace OS Lock is implemented.
553 * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
554 */
555 #define ETM_OSLOCK_NI 0b000
556 #define ETM_OSLOCK_PRESENT 0b010
557 #define ETM_OSLOCK_PE 0b100
558
559 #define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
560
561 /*
562 * TRCDEVARCH Bit field definitions
563 * Bits[31:21] - ARCHITECT = Always Arm Ltd.
564 * * Bits[31:28] = 0x4
565 * * Bits[27:21] = 0b0111011
566 * Bit[20] - PRESENT, Indicates the presence of this register.
567 *
568 * Bit[19:16] - REVISION, Revision of the architecture.
569 *
570 * Bit[15:0] - ARCHID, Identifies this component as an ETM
571 * * Bits[15:12] - architecture version of ETM
572 * * = 4 for ETMv4
573 * * Bits[11:0] = 0xA13, architecture part number for ETM.
574 */
575 #define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21)
576 #define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21))
577 #define ETM_DEVARCH_PRESENT BIT(20)
578 #define ETM_DEVARCH_REVISION_SHIFT 16
579 #define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16)
580 #define ETM_DEVARCH_REVISION(x) \
581 (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT)
582 #define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0)
583 #define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12
584 #define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12)
585 #define ETM_DEVARCH_ARCHID_ARCH_VER(x) \
586 (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)
587
588 #define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \
589 (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK)
590
591 #define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL)
592
593 #define ETM_DEVARCH_MAKE_ARCHID(major) \
594 ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
595
596 #define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4)
597 #define ETM_DEVARCH_ARCHID_ETE ETM_DEVARCH_MAKE_ARCHID(0x5)
598
599 #define ETM_DEVARCH_ID_MASK \
600 (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
601 #define ETM_DEVARCH_ETMv4x_ARCH \
602 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
603 #define ETM_DEVARCH_ETE_ARCH \
604 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
605
606 #define TRCSTATR_IDLE_BIT 0
607 #define TRCSTATR_PMSTABLE_BIT 1
608 #define ETM_DEFAULT_ADDR_COMP 0
609
610 #define TRCSSCSRn_PC BIT(3)
611
612 /* PowerDown Control Register bits */
613 #define TRCPDCR_PU BIT(3)
614
615 #define TRCACATR_EXLEVEL_SHIFT 8
616
617 /*
618 * Exception level mask for Secure and Non-Secure ELs.
619 * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn).
620 * The Secure and Non-Secure ELs are always to gether.
621 * Non-secure EL3 is never implemented.
622 * We use the following generic mask as they appear in different
623 * registers and this can be shifted for the appropriate
624 * fields.
625 */
626 #define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */
627 #define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */
628 #define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */
629 #define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Monitor */
630 #define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */
631 #define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */
632 #define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */
633
634 #define ETM_EXLEVEL_MASK (GENMASK(6, 0))
635 #define ETM_EXLEVEL_S_MASK (GENMASK(3, 0))
636 #define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4))
637
638 /* access level controls in TRCACATRn */
639 #define TRCACATR_EXLEVEL_SHIFT 8
640
641 /* access level control in TRCVICTLR */
642 #define TRCVICTLR_EXLEVEL_SHIFT 16
643 #define TRCVICTLR_EXLEVEL_S_SHIFT 16
644 #define TRCVICTLR_EXLEVEL_NS_SHIFT 20
645
646 /* secure / non secure masks - TRCVICTLR, IDR3 */
647 #define TRCVICTLR_EXLEVEL_MASK (ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHIFT)
648 #define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT)
649 #define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT)
650
651 #define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8
652 #define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
653 #define ETM_TRCIDR1_ARCH_MAJOR(x) \
654 (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
655 #define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4
656 #define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT)
657 #define ETM_TRCIDR1_ARCH_MINOR(x) \
658 (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT)
659 #define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT
660 #define ETM_TRCIDR1_ARCH_MASK \
661 (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK)
662
663 #define ETM_TRCIDR1_ARCH_ETMv4 0x4
664
665 /*
666 * Driver representation of the ETM architecture.
667 * The version of an ETM component can be detected from
668 *
669 * TRCDEVARCH - CoreSight architected register
670 * - Bits[15:12] - Major version
671 * - Bits[19:16] - Minor version
672 *
673 * We must rely only on TRCDEVARCH for the version information. Even though,
674 * TRCIDR1 also provides the architecture version, it is a "Trace" register
675 * and as such must be accessed only with Trace power domain ON. This may
676 * not be available at probe time.
677 *
678 * Now to make certain decisions easier based on the version
679 * we use an internal representation of the version in the
680 * driver, as follows :
681 *
682 * ETM_ARCH_VERSION[7:0], where :
683 * Bits[7:4] - Major version
684 * Bits[3:0] - Minro version
685 */
686 #define ETM_ARCH_VERSION(major, minor) \
687 ((((major) & 0xfU) << 4) | (((minor) & 0xfU)))
688 #define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU)
689 #define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU)
690
691 #define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0)
692 #define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0)
693
694 /* Interpretation of resource numbers change at ETM v4.3 architecture */
695 #define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3)
696
etm_devarch_to_arch(u32 devarch)697 static inline u8 etm_devarch_to_arch(u32 devarch)
698 {
699 return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch),
700 ETM_DEVARCH_REVISION(devarch));
701 }
702
703 enum etm_impdef_type {
704 ETM4_IMPDEF_HISI_CORE_COMMIT,
705 ETM4_IMPDEF_FEATURE_MAX,
706 };
707
708 /**
709 * struct etmv4_config - configuration information related to an ETMv4
710 * @mode: Controls various modes supported by this ETM.
711 * @pe_sel: Controls which PE to trace.
712 * @cfg: Controls the tracing options.
713 * @eventctrl0: Controls the tracing of arbitrary events.
714 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
715 * @stallctl: If functionality that prevents trace unit buffer overflows
716 * is available.
717 * @ts_ctrl: Controls the insertion of global timestamps in the
718 * trace streams.
719 * @syncfreq: Controls how often trace synchronization requests occur.
720 * the TRCCCCTLR register.
721 * @ccctlr: Sets the threshold value for cycle counting.
722 * @vinst_ctrl: Controls instruction trace filtering.
723 * @viiectlr: Set or read, the address range comparators.
724 * @vissctlr: Set, or read, the single address comparators that control the
725 * ViewInst start-stop logic.
726 * @vipcssctlr: Set, or read, which PE comparator inputs can control the
727 * ViewInst start-stop logic.
728 * @seq_idx: Sequencor index selector.
729 * @seq_ctrl: Control for the sequencer state transition control register.
730 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
731 * @seq_state: Set, or read the sequencer state.
732 * @cntr_idx: Counter index seletor.
733 * @cntrldvr: Sets or returns the reload count value for a counter.
734 * @cntr_ctrl: Controls the operation of a counter.
735 * @cntr_val: Sets or returns the value for a counter.
736 * @res_idx: Resource index selector.
737 * @res_ctrl: Controls the selection of the resources in the trace unit.
738 * @ss_idx: Single-shot index selector.
739 * @ss_ctrl: Controls the corresponding single-shot comparator resource.
740 * @ss_status: The status of the corresponding single-shot comparator.
741 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
742 * @addr_idx: Address comparator index selector.
743 * @addr_val: Value for address comparator.
744 * @addr_acc: Address comparator access type.
745 * @addr_type: Current status of the comparator register.
746 * @ctxid_idx: Context ID index selector.
747 * @ctxid_pid: Value of the context ID comparator.
748 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
749 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
750 * @vmid_idx: VM ID index selector.
751 * @vmid_val: Value of the VM ID comparator.
752 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
753 * @vmid_mask1: VM ID comparator mask for comparator 4-7.
754 * @ext_inp: External input selection.
755 * @s_ex_level: Secure ELs where tracing is supported.
756 */
757 struct etmv4_config {
758 u32 mode;
759 u32 pe_sel;
760 u32 cfg;
761 u32 eventctrl0;
762 u32 eventctrl1;
763 u32 stall_ctrl;
764 u32 ts_ctrl;
765 u32 syncfreq;
766 u32 ccctlr;
767 u32 bb_ctrl;
768 u32 vinst_ctrl;
769 u32 viiectlr;
770 u32 vissctlr;
771 u32 vipcssctlr;
772 u8 seq_idx;
773 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
774 u32 seq_rst;
775 u32 seq_state;
776 u8 cntr_idx;
777 u32 cntrldvr[ETMv4_MAX_CNTR];
778 u32 cntr_ctrl[ETMv4_MAX_CNTR];
779 u32 cntr_val[ETMv4_MAX_CNTR];
780 u8 res_idx;
781 u32 res_ctrl[ETM_MAX_RES_SEL];
782 u8 ss_idx;
783 u32 ss_ctrl[ETM_MAX_SS_CMP];
784 u32 ss_status[ETM_MAX_SS_CMP];
785 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
786 u8 addr_idx;
787 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
788 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
789 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
790 u8 ctxid_idx;
791 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
792 u32 ctxid_mask0;
793 u32 ctxid_mask1;
794 u8 vmid_idx;
795 u64 vmid_val[ETM_MAX_VMID_CMP];
796 u32 vmid_mask0;
797 u32 vmid_mask1;
798 u32 ext_inp;
799 u8 s_ex_level;
800 };
801
802 /**
803 * struct etm4_save_state - state to be preserved when ETM is without power
804 */
805 struct etmv4_save_state {
806 u32 trcprgctlr;
807 u32 trcprocselr;
808 u32 trcconfigr;
809 u32 trcauxctlr;
810 u32 trceventctl0r;
811 u32 trceventctl1r;
812 u32 trcstallctlr;
813 u32 trctsctlr;
814 u32 trcsyncpr;
815 u32 trcccctlr;
816 u32 trcbbctlr;
817 u32 trctraceidr;
818 u32 trcqctlr;
819
820 u32 trcvictlr;
821 u32 trcviiectlr;
822 u32 trcvissctlr;
823 u32 trcvipcssctlr;
824 u32 trcvdctlr;
825 u32 trcvdsacctlr;
826 u32 trcvdarcctlr;
827
828 u32 trcseqevr[ETM_MAX_SEQ_STATES];
829 u32 trcseqrstevr;
830 u32 trcseqstr;
831 u32 trcextinselr;
832 u32 trccntrldvr[ETMv4_MAX_CNTR];
833 u32 trccntctlr[ETMv4_MAX_CNTR];
834 u32 trccntvr[ETMv4_MAX_CNTR];
835
836 u32 trcrsctlr[ETM_MAX_RES_SEL];
837
838 u32 trcssccr[ETM_MAX_SS_CMP];
839 u32 trcsscsr[ETM_MAX_SS_CMP];
840 u32 trcsspcicr[ETM_MAX_SS_CMP];
841
842 u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
843 u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
844 u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
845 u64 trcvmidcvr[ETM_MAX_VMID_CMP];
846 u32 trccidcctlr0;
847 u32 trccidcctlr1;
848 u32 trcvmidcctlr0;
849 u32 trcvmidcctlr1;
850
851 u32 trcclaimset;
852
853 u32 cntr_val[ETMv4_MAX_CNTR];
854 u32 seq_state;
855 u32 vinst_ctrl;
856 u32 ss_status[ETM_MAX_SS_CMP];
857
858 u32 trcpdcr;
859 };
860
861 /**
862 * struct etm4_drvdata - specifics associated to an ETM component
863 * @base: Memory mapped base address for this component.
864 * @csdev: Component vitals needed by the framework.
865 * @spinlock: Only one at a time pls.
866 * @mode: This tracer's mode, i.e sysFS, Perf or disabled.
867 * @cpu: The cpu this component is affined to.
868 * @arch: ETM architecture version.
869 * @nr_pe: The number of processing entity available for tracing.
870 * @nr_pe_cmp: The number of processing entity comparator inputs that are
871 * available for tracing.
872 * @nr_addr_cmp:Number of pairs of address comparators available
873 * as found in ETMIDR4 0-3.
874 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
875 * @nr_ext_inp: Number of external input.
876 * @numcidc: Number of contextID comparators.
877 * @numvmidc: Number of VMID comparators.
878 * @nrseqstate: The number of sequencer states that are implemented.
879 * @nr_event: Indicates how many events the trace unit support.
880 * @nr_resource:The number of resource selection pairs available for tracing.
881 * @nr_ss_cmp: Number of single-shot comparator controls that are available.
882 * @trcid: value of the current ID for this component.
883 * @trcid_size: Indicates the trace ID width.
884 * @ts_size: Global timestamp size field.
885 * @ctxid_size: Size of the context ID field to consider.
886 * @vmid_size: Size of the VM ID comparator to consider.
887 * @ccsize: Indicates the size of the cycle counter in bits.
888 * @ccitmin: minimum value that can be programmed in
889 * @s_ex_level: In secure state, indicates whether instruction tracing is
890 * supported for the corresponding Exception level.
891 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
892 * supported for the corresponding Exception level.
893 * @sticky_enable: true if ETM base configuration has been done.
894 * @boot_enable:True if we should start tracing at boot time.
895 * @os_unlock: True if access to management registers is allowed.
896 * @instrp0: Tracing of load and store instructions
897 * as P0 elements is supported.
898 * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
899 * @trccond: If the trace unit supports conditional
900 * instruction tracing.
901 * @retstack: Indicates if the implementation supports a return stack.
902 * @trccci: Indicates if the trace unit supports cycle counting
903 * for instruction.
904 * @q_support: Q element support characteristics.
905 * @trc_error: Whether a trace unit can trace a system
906 * error exception.
907 * @syncpr: Indicates if an implementation has a fixed
908 * synchronization period.
909 * @stall_ctrl: Enables trace unit functionality that prevents trace
910 * unit buffer overflows.
911 * @sysstall: Does the system support stall control of the PE?
912 * @nooverflow: Indicate if overflow prevention is supported.
913 * @atbtrig: If the implementation can support ATB triggers
914 * @lpoverride: If the implementation can support low-power state over.
915 * @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that
916 * allows tracing at all ELs. We don't want to compute this
917 * at runtime, due to the additional setting of TRFCR_CX when
918 * in EL2. Otherwise, 0.
919 * @config: structure holding configuration parameters.
920 * @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event.
921 * @save_state: State to be preserved across power loss
922 * @state_needs_restore: True when there is context to restore after PM exit
923 * @skip_power_up: Indicates if an implementation can skip powering up
924 * the trace unit.
925 * @arch_features: Bitmap of arch features of etmv4 devices.
926 */
927 struct etmv4_drvdata {
928 void __iomem *base;
929 struct coresight_device *csdev;
930 spinlock_t spinlock;
931 local_t mode;
932 int cpu;
933 u8 arch;
934 u8 nr_pe;
935 u8 nr_pe_cmp;
936 u8 nr_addr_cmp;
937 u8 nr_cntr;
938 u8 nr_ext_inp;
939 u8 numcidc;
940 u8 numvmidc;
941 u8 nrseqstate;
942 u8 nr_event;
943 u8 nr_resource;
944 u8 nr_ss_cmp;
945 u8 trcid;
946 u8 trcid_size;
947 u8 ts_size;
948 u8 ctxid_size;
949 u8 vmid_size;
950 u8 ccsize;
951 u16 ccitmin;
952 u8 s_ex_level;
953 u8 ns_ex_level;
954 u8 q_support;
955 u8 os_lock_model;
956 bool sticky_enable;
957 bool boot_enable;
958 bool os_unlock;
959 bool instrp0;
960 bool trcbb;
961 bool trccond;
962 bool retstack;
963 bool trccci;
964 bool trc_error;
965 bool syncpr;
966 bool stallctl;
967 bool sysstall;
968 bool nooverflow;
969 bool atbtrig;
970 bool lpoverride;
971 u64 trfcr;
972 struct etmv4_config config;
973 u64 save_trfcr;
974 struct etmv4_save_state *save_state;
975 bool state_needs_restore;
976 bool skip_power_up;
977 DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
978 };
979
980 /* Address comparator access types */
981 enum etm_addr_acctype {
982 ETM_INSTR_ADDR,
983 ETM_DATA_LOAD_ADDR,
984 ETM_DATA_STORE_ADDR,
985 ETM_DATA_LOAD_STORE_ADDR,
986 };
987
988 /* Address comparator context types */
989 enum etm_addr_ctxtype {
990 ETM_CTX_NONE,
991 ETM_CTX_CTXID,
992 ETM_CTX_VMID,
993 ETM_CTX_CTXID_VMID,
994 };
995
996 extern const struct attribute_group *coresight_etmv4_groups[];
997 void etm4_config_trace_mode(struct etmv4_config *config);
998
999 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
1000 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
1001
etm4x_is_ete(struct etmv4_drvdata * drvdata)1002 static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
1003 {
1004 return drvdata->arch >= ETM_ARCH_ETE;
1005 }
1006 #endif
1007