1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Mellanox BlueField I2C bus driver
4 *
5 * Copyright (C) 2020 Mellanox Technologies, Ltd.
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/bitfield.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
13 #include <linux/i2c.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/string.h>
21
22 /* Defines what functionality is present. */
23 #define MLXBF_I2C_FUNC_SMBUS_BLOCK \
24 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL)
25
26 #define MLXBF_I2C_FUNC_SMBUS_DEFAULT \
27 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \
28 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \
29 I2C_FUNC_SMBUS_PROC_CALL)
30
31 #define MLXBF_I2C_FUNC_ALL \
32 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \
33 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE)
34
35 #define MLXBF_I2C_SMBUS_MAX 3
36
37 /* Shared resources info in BlueField platforms. */
38
39 #define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300
40 #define MLXBF_I2C_COALESCE_TYU_SIZE 0x010
41
42 #define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000
43 #define MLXBF_I2C_GPIO_TYU_SIZE 0x100
44
45 #define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358
46 #define MLXBF_I2C_COREPLL_TYU_SIZE 0x008
47
48 #define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30
49 #define MLXBF_I2C_COREPLL_YU_SIZE 0x00c
50
51 #define MLXBF_I2C_SHARED_RES_MAX 3
52
53 /*
54 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
55 * refer to their respective offsets relative to the corresponding
56 * memory-mapped region whose addresses are specified in either the DT or
57 * the ACPI tables or above.
58 */
59
60 /*
61 * SMBus Master core clock frequency. Timing configurations are
62 * strongly dependent on the core clock frequency of the SMBus
63 * Master. Default value is set to 400MHz.
64 */
65 #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000)
66 /* Reference clock for Bluefield - 156 MHz. */
67 #define MLXBF_I2C_PLL_IN_FREQ 156250000ULL
68
69 /* Constant used to determine the PLL frequency. */
70 #define MLNXBF_I2C_COREPLL_CONST 16384ULL
71
72 #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000ULL
73
74 /* PLL registers. */
75 #define MLXBF_I2C_CORE_PLL_REG1 0x4
76 #define MLXBF_I2C_CORE_PLL_REG2 0x8
77
78 /* OR cause register. */
79 #define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14
80 #define MLXBF_I2C_CAUSE_OR_CLEAR 0x18
81
82 /* Arbiter Cause Register. */
83 #define MLXBF_I2C_CAUSE_ARBITER 0x1c
84
85 /*
86 * Cause Status flags. Note that those bits might be considered
87 * as interrupt enabled bits.
88 */
89
90 /* Transaction ended with STOP. */
91 #define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0)
92 /* Master arbitration lost. */
93 #define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1)
94 /* Unexpected start detected. */
95 #define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2)
96 /* Unexpected stop detected. */
97 #define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3)
98 /* Wait for transfer continuation. */
99 #define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4)
100 /* Failed to generate STOP. */
101 #define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5)
102 /* Failed to generate START. */
103 #define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6)
104 /* Clock toggle completed. */
105 #define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7)
106 /* Transfer timeout occurred. */
107 #define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8)
108 /* Master busy bit reset. */
109 #define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9)
110
111 #define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0)
112
113 #define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \
114 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \
115 MLXBF_I2C_CAUSE_UNEXPECTED_START | \
116 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \
117 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \
118 MLXBF_I2C_CAUSE_PUT_START_FAILED | \
119 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \
120 MLXBF_I2C_CAUSE_M_FW_TIMEOUT)
121
122 /*
123 * Slave cause status flags. Note that those bits might be considered
124 * as interrupt enabled bits.
125 */
126
127 /* Write transaction received successfully. */
128 #define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0)
129 /* Read transaction received, waiting for response. */
130 #define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13)
131 /* Slave busy bit reset. */
132 #define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18)
133
134 #define MLXBF_I2C_CAUSE_SLAVE_ARBITER_BITS_MASK GENMASK(20, 0)
135
136 /* Cause coalesce registers. */
137 #define MLXBF_I2C_CAUSE_COALESCE_0 0x00
138 #define MLXBF_I2C_CAUSE_COALESCE_1 0x04
139 #define MLXBF_I2C_CAUSE_COALESCE_2 0x08
140
141 #define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT MLXBF_I2C_SMBUS_MAX
142 #define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1
143
144 /* Functional enable register. */
145 #define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28
146 /* Force OE enable register. */
147 #define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30
148 /*
149 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control
150 * SDA/SCL lines:
151 *
152 * SMBUS GW0 -> bits[26:25]
153 * SMBUS GW1 -> bits[28:27]
154 * SMBUS GW2 -> bits[30:29]
155 */
156 #define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1))
157
158 /* Note that gw_id can be 0,1 or 2. */
159 #define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \
160 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))))
161
162 #define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \
163 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num))
164
165 #define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \
166 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))
167
168 /* SMBus timing parameters. */
169 #define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00
170 #define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04
171 #define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08
172 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c
173 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10
174 #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14
175 #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18
176
177 /*
178 * Defines SMBus operating frequency and core clock frequency.
179 * According to ADB files, default values are compliant to 100KHz SMBus
180 * @ 400MHz core clock. The driver should be able to calculate core
181 * frequency based on PLL parameters.
182 */
183 #define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ
184
185 /* Core PLL TYU configuration. */
186 #define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(15, 3)
187 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(19, 16)
188 #define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(25, 20)
189
190 /* Core PLL YU configuration. */
191 #define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0)
192 #define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0)
193 #define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(31, 26)
194
195
196 /* Core PLL frequency. */
197 static u64 mlxbf_i2c_corepll_frequency;
198
199 /* SMBus Master GW. */
200 #define MLXBF_I2C_SMBUS_MASTER_GW 0x200
201 /* Number of bytes received and sent. */
202 #define MLXBF_I2C_SMBUS_RS_BYTES 0x300
203 /* Packet error check (PEC) value. */
204 #define MLXBF_I2C_SMBUS_MASTER_PEC 0x304
205 /* Status bits (ACK/NACK/FW Timeout). */
206 #define MLXBF_I2C_SMBUS_MASTER_STATUS 0x308
207 /* SMbus Master Finite State Machine. */
208 #define MLXBF_I2C_SMBUS_MASTER_FSM 0x310
209
210 /*
211 * When enabled, the master will issue a stop condition in case of
212 * timeout while waiting for FW response.
213 */
214 #define MLXBF_I2C_SMBUS_EN_FW_TIMEOUT 0x31c
215
216 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */
217 #define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */
218 #define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */
219 #define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */
220 #define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */
221 #define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */
222 #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */
223
224 #define MLXBF_I2C_MASTER_ENABLE \
225 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \
226 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT)
227
228 #define MLXBF_I2C_MASTER_ENABLE_WRITE \
229 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT)
230
231 #define MLXBF_I2C_MASTER_ENABLE_READ \
232 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT)
233
234 #define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address shift. */
235 #define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes shift. */
236 #define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte shift. */
237 #define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Parse expected bytes shift. */
238 #define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes shift. */
239
240 /* SMBus master GW Data descriptor. */
241 #define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x280
242 #define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */
243
244 /* Maximum bytes to read/write per SMBus transaction. */
245 #define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE
246 #define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1)
247
248 /* All bytes were transmitted. */
249 #define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0)
250 /* NACK received. */
251 #define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1)
252 /* Slave's byte count >128 bytes. */
253 #define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2)
254 /* Timeout occurred. */
255 #define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3)
256
257 #define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0)
258
259 #define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \
260 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \
261 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \
262 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT)
263
264 #define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31)
265 #define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15)
266
267 /* SMBus slave GW. */
268 #define MLXBF_I2C_SMBUS_SLAVE_GW 0x400
269 /* Number of bytes received and sent from/to master. */
270 #define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x500
271 /* Packet error check (PEC) value. */
272 #define MLXBF_I2C_SMBUS_SLAVE_PEC 0x504
273 /* SMBus slave Finite State Machine (FSM). */
274 #define MLXBF_I2C_SMBUS_SLAVE_FSM 0x510
275 /*
276 * Should be set when all raised causes handled, and cleared by HW on
277 * every new cause.
278 */
279 #define MLXBF_I2C_SMBUS_SLAVE_READY 0x52c
280
281 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */
282 #define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */
283 #define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */
284
285 #define MLXBF_I2C_SLAVE_ENABLE \
286 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT)
287
288 #define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */
289 #define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */
290
291 /* SMBus slave GW Data descriptor. */
292 #define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x480
293 #define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */
294
295 /* SMbus slave configuration registers. */
296 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x514
297 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16
298 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7
299 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0)
300
301 #define MLXBF_I2C_SLAVE_ADDR_ENABLED(addr) \
302 ((addr) & (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT))
303
304 /*
305 * Timeout is given in microsends. Note also that timeout handling is not
306 * exact.
307 */
308 #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */
309 #define MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT (300 * 1000) /* 300ms */
310
311 /* Encapsulates timing parameters. */
312 struct mlxbf_i2c_timings {
313 u16 scl_high; /* Clock high period. */
314 u16 scl_low; /* Clock low period. */
315 u8 sda_rise; /* Data rise time. */
316 u8 sda_fall; /* Data fall time. */
317 u8 scl_rise; /* Clock rise time. */
318 u8 scl_fall; /* Clock fall time. */
319 u16 hold_start; /* Hold time after (REPEATED) START. */
320 u16 hold_data; /* Data hold time. */
321 u16 setup_start; /* REPEATED START condition setup time. */
322 u16 setup_stop; /* STOP condition setup time. */
323 u16 setup_data; /* Data setup time. */
324 u16 pad; /* Padding. */
325 u16 buf; /* Bus free time between STOP and START. */
326 u16 thigh_max; /* Thigh max. */
327 u32 timeout; /* Detect clock low timeout. */
328 };
329
330 enum {
331 MLXBF_I2C_F_READ = BIT(0),
332 MLXBF_I2C_F_WRITE = BIT(1),
333 MLXBF_I2C_F_NORESTART = BIT(3),
334 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4),
335 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5),
336 MLXBF_I2C_F_SMBUS_PEC = BIT(6),
337 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7),
338 };
339
340 struct mlxbf_i2c_smbus_operation {
341 u32 flags;
342 u32 length; /* Buffer length in bytes. */
343 u8 *buffer;
344 };
345
346 #define MLXBF_I2C_SMBUS_OP_CNT_1 1
347 #define MLXBF_I2C_SMBUS_OP_CNT_2 2
348 #define MLXBF_I2C_SMBUS_OP_CNT_3 3
349 #define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3
350
351 struct mlxbf_i2c_smbus_request {
352 u8 slave;
353 u8 operation_cnt;
354 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT];
355 };
356
357 struct mlxbf_i2c_resource {
358 void __iomem *io;
359 struct resource *params;
360 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */
361 u8 type;
362 };
363
364 /* List of chip resources that are being accessed by the driver. */
365 enum {
366 MLXBF_I2C_SMBUS_RES,
367 MLXBF_I2C_MST_CAUSE_RES,
368 MLXBF_I2C_SLV_CAUSE_RES,
369 MLXBF_I2C_COALESCE_RES,
370 MLXBF_I2C_COREPLL_RES,
371 MLXBF_I2C_GPIO_RES,
372 MLXBF_I2C_END_RES,
373 };
374
375 /* Helper macro to define an I2C resource parameters. */
376 #define MLXBF_I2C_RES_PARAMS(addr, size, str) \
377 { \
378 .start = (addr), \
379 .end = (addr) + (size) - 1, \
380 .name = (str) \
381 }
382
383 static struct resource mlxbf_i2c_coalesce_tyu_params =
384 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR,
385 MLXBF_I2C_COALESCE_TYU_SIZE,
386 "COALESCE_MEM");
387 static struct resource mlxbf_i2c_corepll_tyu_params =
388 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR,
389 MLXBF_I2C_COREPLL_TYU_SIZE,
390 "COREPLL_MEM");
391 static struct resource mlxbf_i2c_corepll_yu_params =
392 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR,
393 MLXBF_I2C_COREPLL_YU_SIZE,
394 "COREPLL_MEM");
395 static struct resource mlxbf_i2c_gpio_tyu_params =
396 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR,
397 MLXBF_I2C_GPIO_TYU_SIZE,
398 "GPIO_MEM");
399
400 static struct mutex mlxbf_i2c_coalesce_lock;
401 static struct mutex mlxbf_i2c_corepll_lock;
402 static struct mutex mlxbf_i2c_gpio_lock;
403
404 /* Mellanox BlueField chip type. */
405 enum mlxbf_i2c_chip_type {
406 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */
407 MLXBF_I2C_CHIP_TYPE_2, /* Mallanox BlueField-2 chip. */
408 };
409
410 struct mlxbf_i2c_chip_info {
411 enum mlxbf_i2c_chip_type type;
412 /* Chip shared resources that are being used by the I2C controller. */
413 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX];
414
415 /* Callback to calculate the core PLL frequency. */
416 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res);
417 };
418
419 struct mlxbf_i2c_priv {
420 const struct mlxbf_i2c_chip_info *chip;
421 struct i2c_adapter adap;
422 struct mlxbf_i2c_resource *smbus;
423 struct mlxbf_i2c_resource *mst_cause;
424 struct mlxbf_i2c_resource *slv_cause;
425 struct mlxbf_i2c_resource *coalesce;
426 u64 frequency; /* Core frequency in Hz. */
427 int bus; /* Physical bus identifier. */
428 int irq;
429 struct i2c_client *slave;
430 };
431
432 static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = {
433 [MLXBF_I2C_CHIP_TYPE_1] = {
434 .params = &mlxbf_i2c_coalesce_tyu_params,
435 .lock = &mlxbf_i2c_coalesce_lock,
436 .type = MLXBF_I2C_COALESCE_RES
437 },
438 {}
439 };
440
441 static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = {
442 [MLXBF_I2C_CHIP_TYPE_1] = {
443 .params = &mlxbf_i2c_corepll_tyu_params,
444 .lock = &mlxbf_i2c_corepll_lock,
445 .type = MLXBF_I2C_COREPLL_RES
446 },
447 [MLXBF_I2C_CHIP_TYPE_2] = {
448 .params = &mlxbf_i2c_corepll_yu_params,
449 .lock = &mlxbf_i2c_corepll_lock,
450 .type = MLXBF_I2C_COREPLL_RES,
451 }
452 };
453
454 static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = {
455 [MLXBF_I2C_CHIP_TYPE_1] = {
456 .params = &mlxbf_i2c_gpio_tyu_params,
457 .lock = &mlxbf_i2c_gpio_lock,
458 .type = MLXBF_I2C_GPIO_RES
459 },
460 {}
461 };
462
463 static u8 mlxbf_i2c_bus_count;
464
465 static struct mutex mlxbf_i2c_bus_lock;
466
467 /* Polling frequency in microseconds. */
468 #define MLXBF_I2C_POLL_FREQ_IN_USEC 200
469
470 #define MLXBF_I2C_SHIFT_0 0
471 #define MLXBF_I2C_SHIFT_8 8
472 #define MLXBF_I2C_SHIFT_16 16
473 #define MLXBF_I2C_SHIFT_24 24
474
475 #define MLXBF_I2C_MASK_8 GENMASK(7, 0)
476 #define MLXBF_I2C_MASK_16 GENMASK(15, 0)
477
478 /*
479 * Function to poll a set of bits at a specific address; it checks whether
480 * the bits are equal to zero when eq_zero is set to 'true', and not equal
481 * to zero when eq_zero is set to 'false'.
482 * Note that the timeout is given in microseconds.
483 */
mlxbf_smbus_poll(void __iomem * io,u32 addr,u32 mask,bool eq_zero,u32 timeout)484 static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask,
485 bool eq_zero, u32 timeout)
486 {
487 u32 bits;
488
489 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1;
490
491 do {
492 bits = readl(io + addr) & mask;
493 if (eq_zero ? bits == 0 : bits != 0)
494 return eq_zero ? 1 : bits;
495 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC);
496 } while (timeout-- != 0);
497
498 return 0;
499 }
500
501 /*
502 * SW must make sure that the SMBus Master GW is idle before starting
503 * a transaction. Accordingly, this function polls the Master FSM stop
504 * bit; it returns false when the bit is asserted, true if not.
505 */
mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv * priv)506 static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv)
507 {
508 u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK;
509 u32 addr = MLXBF_I2C_SMBUS_MASTER_FSM;
510 u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT;
511
512 if (mlxbf_smbus_poll(priv->smbus->io, addr, mask, true, timeout))
513 return true;
514
515 return false;
516 }
517
518 /*
519 * wait for the lock to be released before acquiring it.
520 */
mlxbf_i2c_smbus_master_lock(struct mlxbf_i2c_priv * priv)521 static bool mlxbf_i2c_smbus_master_lock(struct mlxbf_i2c_priv *priv)
522 {
523 if (mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW,
524 MLXBF_I2C_MASTER_LOCK_BIT, true,
525 MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT))
526 return true;
527
528 return false;
529 }
530
mlxbf_i2c_smbus_master_unlock(struct mlxbf_i2c_priv * priv)531 static void mlxbf_i2c_smbus_master_unlock(struct mlxbf_i2c_priv *priv)
532 {
533 /* Clear the gw to clear the lock */
534 writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW);
535 }
536
mlxbf_i2c_smbus_transaction_success(u32 master_status,u32 cause_status)537 static bool mlxbf_i2c_smbus_transaction_success(u32 master_status,
538 u32 cause_status)
539 {
540 /*
541 * When transaction ended with STOP, all bytes were transmitted,
542 * and no NACK received, then the transaction ended successfully.
543 * On the other hand, when the GW is configured with the stop bit
544 * de-asserted then the SMBus expects the following GW configuration
545 * for transfer continuation.
546 */
547 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) ||
548 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) &&
549 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) &&
550 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV)))
551 return true;
552
553 return false;
554 }
555
556 /*
557 * Poll SMBus master status and return transaction status,
558 * i.e. whether succeeded or failed. I2C and SMBus fault codes
559 * are returned as negative numbers from most calls, with zero
560 * or some positive number indicating a non-fault return.
561 */
mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv * priv)562 static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv)
563 {
564 u32 master_status_bits;
565 u32 cause_status_bits;
566
567 /*
568 * GW busy bit is raised by the driver and cleared by the HW
569 * when the transaction is completed. The busy bit is a good
570 * indicator of transaction status. So poll the busy bit, and
571 * then read the cause and master status bits to determine if
572 * errors occurred during the transaction.
573 */
574 mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW,
575 MLXBF_I2C_MASTER_BUSY_BIT, true,
576 MLXBF_I2C_SMBUS_TIMEOUT);
577
578 /* Read cause status bits. */
579 cause_status_bits = readl(priv->mst_cause->io +
580 MLXBF_I2C_CAUSE_ARBITER);
581 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK;
582
583 /*
584 * Parse both Cause and Master GW bits, then return transaction status.
585 */
586
587 master_status_bits = readl(priv->smbus->io +
588 MLXBF_I2C_SMBUS_MASTER_STATUS);
589 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK;
590
591 if (mlxbf_i2c_smbus_transaction_success(master_status_bits,
592 cause_status_bits))
593 return 0;
594
595 /*
596 * In case of timeout on GW busy, the ISR will clear busy bit but
597 * transaction ended bits cause will not be set so the transaction
598 * fails. Then, we must check Master GW status bits.
599 */
600 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) &&
601 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED |
602 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL)))
603 return -EIO;
604
605 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR)
606 return -EAGAIN;
607
608 return -ETIMEDOUT;
609 }
610
mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv * priv,const u8 * data,u8 length,u32 addr)611 static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv,
612 const u8 *data, u8 length, u32 addr)
613 {
614 u8 offset, aligned_length;
615 u32 data32;
616
617 aligned_length = round_up(length, 4);
618
619 /*
620 * Copy data bytes from 4-byte aligned source buffer.
621 * Data copied to the Master GW Data Descriptor MUST be shifted
622 * left so the data starts at the MSB of the descriptor registers
623 * as required by the underlying hardware. Enable byte swapping
624 * when writing data bytes to the 32 * 32-bit HW Data registers
625 * a.k.a Master GW Data Descriptor.
626 */
627 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) {
628 data32 = *((u32 *)(data + offset));
629 iowrite32be(data32, priv->smbus->io + addr + offset);
630 }
631 }
632
mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv * priv,u8 * data,u8 length,u32 addr)633 static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv,
634 u8 *data, u8 length, u32 addr)
635 {
636 u32 data32, mask;
637 u8 byte, offset;
638
639 mask = sizeof(u32) - 1;
640
641 /*
642 * Data bytes in the Master GW Data Descriptor are shifted left
643 * so the data starts at the MSB of the descriptor registers as
644 * set by the underlying hardware. Enable byte swapping while
645 * reading data bytes from the 32 * 32-bit HW Data registers
646 * a.k.a Master GW Data Descriptor.
647 */
648
649 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) {
650 data32 = ioread32be(priv->smbus->io + addr + offset);
651 *((u32 *)(data + offset)) = data32;
652 }
653
654 if (!(length & mask))
655 return;
656
657 data32 = ioread32be(priv->smbus->io + addr + offset);
658
659 for (byte = 0; byte < (length & mask); byte++) {
660 data[offset + byte] = data32 & GENMASK(7, 0);
661 data32 = ror32(data32, MLXBF_I2C_SHIFT_8);
662 }
663 }
664
mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv * priv,u8 slave,u8 len,u8 block_en,u8 pec_en,bool read)665 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,
666 u8 len, u8 block_en, u8 pec_en, bool read)
667 {
668 u32 command;
669
670 /* Set Master GW control word. */
671 if (read) {
672 command = MLXBF_I2C_MASTER_ENABLE_READ;
673 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT);
674 } else {
675 command = MLXBF_I2C_MASTER_ENABLE_WRITE;
676 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT);
677 }
678 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT);
679 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT);
680 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT);
681
682 /* Clear status bits. */
683 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS);
684 /* Set the cause data. */
685 writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
686 /* Zero PEC byte. */
687 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC);
688 /* Zero byte count. */
689 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES);
690
691 /* GW activation. */
692 writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW);
693
694 /*
695 * Poll master status and check status bits. An ACK is sent when
696 * completing writing data to the bus (Master 'byte_count_done' bit
697 * is set to 1).
698 */
699 return mlxbf_i2c_smbus_check_status(priv);
700 }
701
702 static int
mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv * priv,struct mlxbf_i2c_smbus_request * request)703 mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
704 struct mlxbf_i2c_smbus_request *request)
705 {
706 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 };
707 u8 op_idx, data_idx, data_len, write_len, read_len;
708 struct mlxbf_i2c_smbus_operation *operation;
709 u8 read_en, write_en, block_en, pec_en;
710 u8 slave, flags, addr;
711 u8 *read_buf;
712 int ret = 0;
713
714 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT)
715 return -EINVAL;
716
717 read_buf = NULL;
718 data_idx = 0;
719 read_en = 0;
720 write_en = 0;
721 write_len = 0;
722 read_len = 0;
723 block_en = 0;
724 pec_en = 0;
725 slave = request->slave & GENMASK(6, 0);
726 addr = slave << 1;
727
728 /*
729 * Try to acquire the smbus gw lock before any reads of the GW register since
730 * a read sets the lock.
731 */
732 if (WARN_ON(!mlxbf_i2c_smbus_master_lock(priv)))
733 return -EBUSY;
734
735 /* Check whether the HW is idle */
736 if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv))) {
737 ret = -EBUSY;
738 goto out_unlock;
739 }
740
741 /* Set first byte. */
742 data_desc[data_idx++] = addr;
743
744 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) {
745 operation = &request->operation[op_idx];
746 flags = operation->flags;
747
748 /*
749 * Note that read and write operations might be handled by a
750 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set
751 * then write command byte and set the optional SMBus specific
752 * bits such as block_en and pec_en. These bits MUST be
753 * submitted by the first operation only.
754 */
755 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) {
756 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK;
757 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC;
758 }
759
760 if (flags & MLXBF_I2C_F_WRITE) {
761 write_en = 1;
762 write_len += operation->length;
763 if (data_idx + operation->length >
764 MLXBF_I2C_MASTER_DATA_DESC_SIZE) {
765 ret = -ENOBUFS;
766 goto out_unlock;
767 }
768 memcpy(data_desc + data_idx,
769 operation->buffer, operation->length);
770 data_idx += operation->length;
771 }
772 /*
773 * We assume that read operations are performed only once per
774 * SMBus transaction. *TBD* protect this statement so it won't
775 * be executed twice? or return an error if we try to read more
776 * than once?
777 */
778 if (flags & MLXBF_I2C_F_READ) {
779 read_en = 1;
780 /* Subtract 1 as required by HW. */
781 read_len = operation->length - 1;
782 read_buf = operation->buffer;
783 }
784 }
785
786 /* Set Master GW data descriptor. */
787 data_len = write_len + 1; /* Add one byte of the slave address. */
788 /*
789 * Note that data_len cannot be 0. Indeed, the slave address byte
790 * must be written to the data registers.
791 */
792 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len,
793 MLXBF_I2C_MASTER_DATA_DESC_ADDR);
794
795 if (write_en) {
796 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en,
797 pec_en, 0);
798 if (ret)
799 goto out_unlock;
800 }
801
802 if (read_en) {
803 /* Write slave address to Master GW data descriptor. */
804 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1,
805 MLXBF_I2C_MASTER_DATA_DESC_ADDR);
806 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en,
807 pec_en, 1);
808 if (!ret) {
809 /* Get Master GW data descriptor. */
810 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1,
811 MLXBF_I2C_MASTER_DATA_DESC_ADDR);
812
813 /* Get data from Master GW data descriptor. */
814 memcpy(read_buf, data_desc, read_len + 1);
815 }
816
817 /*
818 * After a read operation the SMBus FSM ps (present state)
819 * needs to be 'manually' reset. This should be removed in
820 * next tag integration.
821 */
822 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK,
823 priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM);
824 }
825
826 out_unlock:
827 mlxbf_i2c_smbus_master_unlock(priv);
828
829 return ret;
830 }
831
832 /* I2C SMBus protocols. */
833
834 static void
mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request * request,u8 read)835 mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request,
836 u8 read)
837 {
838 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;
839
840 request->operation[0].length = 0;
841 request->operation[0].flags = MLXBF_I2C_F_WRITE;
842 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0;
843 }
844
mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request * request,u8 * data,bool read,bool pec_check)845 static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request,
846 u8 *data, bool read, bool pec_check)
847 {
848 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;
849
850 request->operation[0].length = 1;
851 request->operation[0].length += pec_check;
852
853 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION;
854 request->operation[0].flags |= read ?
855 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
856 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
857
858 request->operation[0].buffer = data;
859 }
860
861 static void
mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request * request,u8 * command,u8 * data,bool read,bool pec_check)862 mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request,
863 u8 *command, u8 *data, bool read, bool pec_check)
864 {
865 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
866
867 request->operation[0].length = 1;
868 request->operation[0].flags =
869 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
870 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
871 request->operation[0].buffer = command;
872
873 request->operation[1].length = 1;
874 request->operation[1].length += pec_check;
875 request->operation[1].flags = read ?
876 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
877 request->operation[1].buffer = data;
878 }
879
880 static void
mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request * request,u8 * command,u8 * data,bool read,bool pec_check)881 mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request,
882 u8 *command, u8 *data, bool read, bool pec_check)
883 {
884 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
885
886 request->operation[0].length = 1;
887 request->operation[0].flags =
888 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
889 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
890 request->operation[0].buffer = command;
891
892 request->operation[1].length = 2;
893 request->operation[1].length += pec_check;
894 request->operation[1].flags = read ?
895 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
896 request->operation[1].buffer = data;
897 }
898
899 static void
mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request * request,u8 * command,u8 * data,u8 * data_len,bool read,bool pec_check)900 mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request,
901 u8 *command, u8 *data, u8 *data_len, bool read,
902 bool pec_check)
903 {
904 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
905
906 request->operation[0].length = 1;
907 request->operation[0].flags =
908 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
909 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
910 request->operation[0].buffer = command;
911
912 /*
913 * As specified in the standard, the max number of bytes to read/write
914 * per block operation is 32 bytes. In Golan code, the controller can
915 * read up to 128 bytes and write up to 127 bytes.
916 */
917 request->operation[1].length =
918 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
919 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
920 request->operation[1].flags = read ?
921 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
922 /*
923 * Skip the first data byte, which corresponds to the number of bytes
924 * to read/write.
925 */
926 request->operation[1].buffer = data + 1;
927
928 *data_len = request->operation[1].length;
929
930 /* Set the number of byte to read. This will be used by userspace. */
931 if (read)
932 data[0] = *data_len;
933 }
934
mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request * request,u8 * command,u8 * data,u8 * data_len,bool read,bool pec_check)935 static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request,
936 u8 *command, u8 *data, u8 *data_len,
937 bool read, bool pec_check)
938 {
939 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
940
941 request->operation[0].length = 1;
942 request->operation[0].flags =
943 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
944 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
945 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
946 request->operation[0].buffer = command;
947
948 request->operation[1].length =
949 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
950 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
951 request->operation[1].flags = read ?
952 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
953 request->operation[1].buffer = data + 1;
954
955 *data_len = request->operation[1].length;
956
957 /* Set the number of bytes to read. This will be used by userspace. */
958 if (read)
959 data[0] = *data_len;
960 }
961
962 static void
mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request * request,u8 * command,u8 * data,bool pec_check)963 mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request,
964 u8 *command, u8 *data, bool pec_check)
965 {
966 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;
967
968 request->operation[0].length = 1;
969 request->operation[0].flags =
970 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
971 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
972 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
973 request->operation[0].buffer = command;
974
975 request->operation[1].length = 2;
976 request->operation[1].flags = MLXBF_I2C_F_WRITE;
977 request->operation[1].buffer = data;
978
979 request->operation[2].length = 3;
980 request->operation[2].flags = MLXBF_I2C_F_READ;
981 request->operation[2].buffer = data;
982 }
983
984 static void
mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request * request,u8 * command,u8 * data,u8 * data_len,bool pec_check)985 mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request,
986 u8 *command, u8 *data, u8 *data_len,
987 bool pec_check)
988 {
989 u32 length;
990
991 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;
992
993 request->operation[0].length = 1;
994 request->operation[0].flags =
995 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
996 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
997 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0;
998 request->operation[0].buffer = command;
999
1000 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
1001 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
1002
1003 request->operation[1].length = length - pec_check;
1004 request->operation[1].flags = MLXBF_I2C_F_WRITE;
1005 request->operation[1].buffer = data;
1006
1007 request->operation[2].length = length;
1008 request->operation[2].flags = MLXBF_I2C_F_READ;
1009 request->operation[2].buffer = data;
1010
1011 *data_len = length; /* including PEC byte. */
1012 }
1013
1014 /* Initialization functions. */
1015
mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv * priv,u8 type)1016 static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type)
1017 {
1018 return priv->chip->type == type;
1019 }
1020
1021 static struct mlxbf_i2c_resource *
mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv * priv,u8 type)1022 mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type)
1023 {
1024 const struct mlxbf_i2c_chip_info *chip = priv->chip;
1025 struct mlxbf_i2c_resource *res;
1026 u8 res_idx = 0;
1027
1028 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) {
1029 res = chip->shared_res[res_idx];
1030 if (res && res->type == type)
1031 return res;
1032 }
1033
1034 return NULL;
1035 }
1036
mlxbf_i2c_init_resource(struct platform_device * pdev,struct mlxbf_i2c_resource ** res,u8 type)1037 static int mlxbf_i2c_init_resource(struct platform_device *pdev,
1038 struct mlxbf_i2c_resource **res,
1039 u8 type)
1040 {
1041 struct mlxbf_i2c_resource *tmp_res;
1042 struct device *dev = &pdev->dev;
1043
1044 if (!res || *res || type >= MLXBF_I2C_END_RES)
1045 return -EINVAL;
1046
1047 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource),
1048 GFP_KERNEL);
1049 if (!tmp_res)
1050 return -ENOMEM;
1051
1052 tmp_res->params = platform_get_resource(pdev, IORESOURCE_MEM, type);
1053 if (!tmp_res->params) {
1054 devm_kfree(dev, tmp_res);
1055 return -EIO;
1056 }
1057
1058 tmp_res->io = devm_ioremap_resource(dev, tmp_res->params);
1059 if (IS_ERR(tmp_res->io)) {
1060 devm_kfree(dev, tmp_res);
1061 return PTR_ERR(tmp_res->io);
1062 }
1063
1064 tmp_res->type = type;
1065
1066 *res = tmp_res;
1067
1068 return 0;
1069 }
1070
mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv * priv,u64 nanoseconds,bool minimum)1071 static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds,
1072 bool minimum)
1073 {
1074 u64 frequency;
1075 u32 ticks;
1076
1077 /*
1078 * Compute ticks as follow:
1079 *
1080 * Ticks
1081 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9
1082 * Frequency
1083 */
1084 frequency = priv->frequency;
1085 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ;
1086 /*
1087 * The number of ticks is rounded down and if minimum is equal to 1
1088 * then add one tick.
1089 */
1090 if (minimum)
1091 ticks++;
1092
1093 return ticks;
1094 }
1095
mlxbf_i2c_set_timer(struct mlxbf_i2c_priv * priv,u64 nsec,bool opt,u32 mask,u8 shift)1096 static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt,
1097 u32 mask, u8 shift)
1098 {
1099 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift;
1100
1101 return val;
1102 }
1103
mlxbf_i2c_set_timings(struct mlxbf_i2c_priv * priv,const struct mlxbf_i2c_timings * timings)1104 static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
1105 const struct mlxbf_i2c_timings *timings)
1106 {
1107 u32 timer;
1108
1109 timer = mlxbf_i2c_set_timer(priv, timings->scl_high,
1110 false, MLXBF_I2C_MASK_16,
1111 MLXBF_I2C_SHIFT_0);
1112 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low,
1113 false, MLXBF_I2C_MASK_16,
1114 MLXBF_I2C_SHIFT_16);
1115 writel(timer, priv->smbus->io +
1116 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH);
1117
1118 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false,
1119 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0);
1120 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false,
1121 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8);
1122 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false,
1123 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16);
1124 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false,
1125 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24);
1126 writel(timer, priv->smbus->io +
1127 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE);
1128
1129 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true,
1130 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1131 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true,
1132 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
1133 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD);
1134
1135 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true,
1136 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1137 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true,
1138 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
1139 writel(timer, priv->smbus->io +
1140 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP);
1141
1142 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true,
1143 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1144 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA);
1145
1146 timer = mlxbf_i2c_set_timer(priv, timings->buf, false,
1147 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1148 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false,
1149 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
1150 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF);
1151
1152 timer = timings->timeout;
1153 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT);
1154 }
1155
1156 enum mlxbf_i2c_timings_config {
1157 MLXBF_I2C_TIMING_CONFIG_100KHZ,
1158 MLXBF_I2C_TIMING_CONFIG_400KHZ,
1159 MLXBF_I2C_TIMING_CONFIG_1000KHZ,
1160 };
1161
1162 /*
1163 * Note that the mlxbf_i2c_timings->timeout value is not related to the
1164 * bus frequency, it is impacted by the time it takes the driver to
1165 * complete data transmission before transaction abort.
1166 */
1167 static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = {
1168 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = {
1169 .scl_high = 4810,
1170 .scl_low = 5000,
1171 .hold_start = 4000,
1172 .setup_start = 4800,
1173 .setup_stop = 4000,
1174 .setup_data = 250,
1175 .sda_rise = 50,
1176 .sda_fall = 50,
1177 .scl_rise = 50,
1178 .scl_fall = 50,
1179 .hold_data = 300,
1180 .buf = 20000,
1181 .thigh_max = 5000,
1182 .timeout = 106500
1183 },
1184 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = {
1185 .scl_high = 1011,
1186 .scl_low = 1300,
1187 .hold_start = 600,
1188 .setup_start = 700,
1189 .setup_stop = 600,
1190 .setup_data = 100,
1191 .sda_rise = 50,
1192 .sda_fall = 50,
1193 .scl_rise = 50,
1194 .scl_fall = 50,
1195 .hold_data = 300,
1196 .buf = 20000,
1197 .thigh_max = 5000,
1198 .timeout = 106500
1199 },
1200 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = {
1201 .scl_high = 600,
1202 .scl_low = 1300,
1203 .hold_start = 600,
1204 .setup_start = 600,
1205 .setup_stop = 600,
1206 .setup_data = 100,
1207 .sda_rise = 50,
1208 .sda_fall = 50,
1209 .scl_rise = 50,
1210 .scl_fall = 50,
1211 .hold_data = 300,
1212 .buf = 20000,
1213 .thigh_max = 5000,
1214 .timeout = 106500
1215 }
1216 };
1217
mlxbf_i2c_init_timings(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1218 static int mlxbf_i2c_init_timings(struct platform_device *pdev,
1219 struct mlxbf_i2c_priv *priv)
1220 {
1221 enum mlxbf_i2c_timings_config config_idx;
1222 struct device *dev = &pdev->dev;
1223 u32 config_khz;
1224
1225 int ret;
1226
1227 ret = device_property_read_u32(dev, "clock-frequency", &config_khz);
1228 if (ret < 0)
1229 config_khz = I2C_MAX_STANDARD_MODE_FREQ;
1230
1231 switch (config_khz) {
1232 default:
1233 /* Default settings is 100 KHz. */
1234 pr_warn("Illegal value %d: defaulting to 100 KHz\n",
1235 config_khz);
1236 fallthrough;
1237 case I2C_MAX_STANDARD_MODE_FREQ:
1238 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ;
1239 break;
1240
1241 case I2C_MAX_FAST_MODE_FREQ:
1242 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ;
1243 break;
1244
1245 case I2C_MAX_FAST_MODE_PLUS_FREQ:
1246 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ;
1247 break;
1248 }
1249
1250 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]);
1251
1252 return 0;
1253 }
1254
mlxbf_i2c_get_gpio(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1255 static int mlxbf_i2c_get_gpio(struct platform_device *pdev,
1256 struct mlxbf_i2c_priv *priv)
1257 {
1258 struct mlxbf_i2c_resource *gpio_res;
1259 struct device *dev = &pdev->dev;
1260 struct resource *params;
1261 resource_size_t size;
1262
1263 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
1264 if (!gpio_res)
1265 return -EPERM;
1266
1267 /*
1268 * The GPIO region in TYU space is shared among I2C busses.
1269 * This function MUST be serialized to avoid racing when
1270 * claiming the memory region and/or setting up the GPIO.
1271 */
1272 lockdep_assert_held(gpio_res->lock);
1273
1274 /* Check whether the memory map exist. */
1275 if (gpio_res->io)
1276 return 0;
1277
1278 params = gpio_res->params;
1279 size = resource_size(params);
1280
1281 if (!devm_request_mem_region(dev, params->start, size, params->name))
1282 return -EFAULT;
1283
1284 gpio_res->io = devm_ioremap(dev, params->start, size);
1285 if (!gpio_res->io) {
1286 devm_release_mem_region(dev, params->start, size);
1287 return -ENOMEM;
1288 }
1289
1290 return 0;
1291 }
1292
mlxbf_i2c_release_gpio(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1293 static int mlxbf_i2c_release_gpio(struct platform_device *pdev,
1294 struct mlxbf_i2c_priv *priv)
1295 {
1296 struct mlxbf_i2c_resource *gpio_res;
1297 struct device *dev = &pdev->dev;
1298 struct resource *params;
1299
1300 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
1301 if (!gpio_res)
1302 return 0;
1303
1304 mutex_lock(gpio_res->lock);
1305
1306 if (gpio_res->io) {
1307 /* Release the GPIO resource. */
1308 params = gpio_res->params;
1309 devm_iounmap(dev, gpio_res->io);
1310 devm_release_mem_region(dev, params->start,
1311 resource_size(params));
1312 }
1313
1314 mutex_unlock(gpio_res->lock);
1315
1316 return 0;
1317 }
1318
mlxbf_i2c_get_corepll(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1319 static int mlxbf_i2c_get_corepll(struct platform_device *pdev,
1320 struct mlxbf_i2c_priv *priv)
1321 {
1322 struct mlxbf_i2c_resource *corepll_res;
1323 struct device *dev = &pdev->dev;
1324 struct resource *params;
1325 resource_size_t size;
1326
1327 corepll_res = mlxbf_i2c_get_shared_resource(priv,
1328 MLXBF_I2C_COREPLL_RES);
1329 if (!corepll_res)
1330 return -EPERM;
1331
1332 /*
1333 * The COREPLL region in TYU space is shared among I2C busses.
1334 * This function MUST be serialized to avoid racing when
1335 * claiming the memory region.
1336 */
1337 lockdep_assert_held(corepll_res->lock);
1338
1339 /* Check whether the memory map exist. */
1340 if (corepll_res->io)
1341 return 0;
1342
1343 params = corepll_res->params;
1344 size = resource_size(params);
1345
1346 if (!devm_request_mem_region(dev, params->start, size, params->name))
1347 return -EFAULT;
1348
1349 corepll_res->io = devm_ioremap(dev, params->start, size);
1350 if (!corepll_res->io) {
1351 devm_release_mem_region(dev, params->start, size);
1352 return -ENOMEM;
1353 }
1354
1355 return 0;
1356 }
1357
mlxbf_i2c_release_corepll(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1358 static int mlxbf_i2c_release_corepll(struct platform_device *pdev,
1359 struct mlxbf_i2c_priv *priv)
1360 {
1361 struct mlxbf_i2c_resource *corepll_res;
1362 struct device *dev = &pdev->dev;
1363 struct resource *params;
1364
1365 corepll_res = mlxbf_i2c_get_shared_resource(priv,
1366 MLXBF_I2C_COREPLL_RES);
1367
1368 mutex_lock(corepll_res->lock);
1369
1370 if (corepll_res->io) {
1371 /* Release the CorePLL resource. */
1372 params = corepll_res->params;
1373 devm_iounmap(dev, corepll_res->io);
1374 devm_release_mem_region(dev, params->start,
1375 resource_size(params));
1376 }
1377
1378 mutex_unlock(corepll_res->lock);
1379
1380 return 0;
1381 }
1382
mlxbf_i2c_init_master(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1383 static int mlxbf_i2c_init_master(struct platform_device *pdev,
1384 struct mlxbf_i2c_priv *priv)
1385 {
1386 struct mlxbf_i2c_resource *gpio_res;
1387 struct device *dev = &pdev->dev;
1388 u32 config_reg;
1389 int ret;
1390
1391 /* This configuration is only needed for BlueField 1. */
1392 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1))
1393 return 0;
1394
1395 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
1396 if (!gpio_res)
1397 return -EPERM;
1398
1399 /*
1400 * The GPIO region in TYU space is shared among I2C busses.
1401 * This function MUST be serialized to avoid racing when
1402 * claiming the memory region and/or setting up the GPIO.
1403 */
1404
1405 mutex_lock(gpio_res->lock);
1406
1407 ret = mlxbf_i2c_get_gpio(pdev, priv);
1408 if (ret < 0) {
1409 dev_err(dev, "Failed to get gpio resource");
1410 mutex_unlock(gpio_res->lock);
1411 return ret;
1412 }
1413
1414 /*
1415 * TYU - Configuration for GPIO pins. Those pins must be asserted in
1416 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must
1417 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven
1418 * instead of HW_OE.
1419 * For now, we do not reset the GPIO state when the driver is removed.
1420 * First, it is not necessary to disable the bus since we are using
1421 * the same busses. Then, some busses might be shared among Linux and
1422 * platform firmware; disabling the bus might compromise the system
1423 * functionality.
1424 */
1425 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
1426 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus,
1427 config_reg);
1428 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
1429
1430 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
1431 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus,
1432 config_reg);
1433 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
1434
1435 mutex_unlock(gpio_res->lock);
1436
1437 return 0;
1438 }
1439
mlxbf_i2c_calculate_freq_from_tyu(struct mlxbf_i2c_resource * corepll_res)1440 static u64 mlxbf_i2c_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
1441 {
1442 u64 core_frequency;
1443 u8 core_od, core_r;
1444 u32 corepll_val;
1445 u16 core_f;
1446
1447 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
1448
1449 /* Get Core PLL configuration bits. */
1450 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_TYU_MASK, corepll_val);
1451 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK, corepll_val);
1452 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_TYU_MASK, corepll_val);
1453
1454 /*
1455 * Compute PLL output frequency as follow:
1456 *
1457 * CORE_F + 1
1458 * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------
1459 * (CORE_R + 1) * (CORE_OD + 1)
1460 *
1461 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency
1462 * and PadFrequency, respectively.
1463 */
1464 core_frequency = MLXBF_I2C_PLL_IN_FREQ * (++core_f);
1465 core_frequency /= (++core_r) * (++core_od);
1466
1467 return core_frequency;
1468 }
1469
mlxbf_i2c_calculate_freq_from_yu(struct mlxbf_i2c_resource * corepll_res)1470 static u64 mlxbf_i2c_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
1471 {
1472 u32 corepll_reg1_val, corepll_reg2_val;
1473 u64 corepll_frequency;
1474 u8 core_od, core_r;
1475 u32 core_f;
1476
1477 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
1478 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
1479
1480 /* Get Core PLL configuration bits */
1481 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_YU_MASK, corepll_reg1_val);
1482 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_YU_MASK, corepll_reg1_val);
1483 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_YU_MASK, corepll_reg2_val);
1484
1485 /*
1486 * Compute PLL output frequency as follow:
1487 *
1488 * CORE_F / 16384
1489 * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------
1490 * (CORE_R + 1) * (CORE_OD + 1)
1491 *
1492 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency
1493 * and PadFrequency, respectively.
1494 */
1495 corepll_frequency = (MLXBF_I2C_PLL_IN_FREQ * core_f) / MLNXBF_I2C_COREPLL_CONST;
1496 corepll_frequency /= (++core_r) * (++core_od);
1497
1498 return corepll_frequency;
1499 }
1500
mlxbf_i2c_calculate_corepll_freq(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1501 static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev,
1502 struct mlxbf_i2c_priv *priv)
1503 {
1504 const struct mlxbf_i2c_chip_info *chip = priv->chip;
1505 struct mlxbf_i2c_resource *corepll_res;
1506 struct device *dev = &pdev->dev;
1507 u64 *freq = &priv->frequency;
1508 int ret;
1509
1510 corepll_res = mlxbf_i2c_get_shared_resource(priv,
1511 MLXBF_I2C_COREPLL_RES);
1512 if (!corepll_res)
1513 return -EPERM;
1514
1515 /*
1516 * First, check whether the TYU core Clock frequency is set.
1517 * The TYU core frequency is the same for all I2C busses; when
1518 * the first device gets probed the frequency is determined and
1519 * stored into a globally visible variable. So, first of all,
1520 * check whether the frequency is already set. Here, we assume
1521 * that the frequency is expected to be greater than 0.
1522 */
1523 mutex_lock(corepll_res->lock);
1524 if (!mlxbf_i2c_corepll_frequency) {
1525 if (!chip->calculate_freq) {
1526 mutex_unlock(corepll_res->lock);
1527 return -EPERM;
1528 }
1529
1530 ret = mlxbf_i2c_get_corepll(pdev, priv);
1531 if (ret < 0) {
1532 dev_err(dev, "Failed to get corePLL resource");
1533 mutex_unlock(corepll_res->lock);
1534 return ret;
1535 }
1536
1537 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res);
1538 }
1539 mutex_unlock(corepll_res->lock);
1540
1541 *freq = mlxbf_i2c_corepll_frequency;
1542
1543 return 0;
1544 }
1545
mlxbf_slave_enable(struct mlxbf_i2c_priv * priv,u8 addr)1546 static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
1547 {
1548 u32 slave_reg, slave_reg_tmp, slave_reg_avail, slave_addr_mask;
1549 u8 reg, reg_cnt, byte, addr_tmp, reg_avail, byte_avail;
1550 bool avail, disabled;
1551
1552 disabled = false;
1553 avail = false;
1554
1555 if (!priv)
1556 return -EPERM;
1557
1558 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
1559 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
1560
1561 /*
1562 * Read the slave registers. There are 4 * 32-bit slave registers.
1563 * Each slave register can hold up to 4 * 8-bit slave configuration
1564 * (7-bit address, 1 status bit (1 if enabled, 0 if not)).
1565 */
1566 for (reg = 0; reg < reg_cnt; reg++) {
1567 slave_reg = readl(priv->smbus->io +
1568 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
1569 /*
1570 * Each register holds 4 slave addresses. So, we have to keep
1571 * the byte order consistent with the value read in order to
1572 * update the register correctly, if needed.
1573 */
1574 slave_reg_tmp = slave_reg;
1575 for (byte = 0; byte < 4; byte++) {
1576 addr_tmp = slave_reg_tmp & GENMASK(7, 0);
1577
1578 /*
1579 * Mark the first available slave address slot, i.e. its
1580 * enabled bit should be unset. This slot might be used
1581 * later on to register our slave.
1582 */
1583 if (!avail && !MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) {
1584 avail = true;
1585 reg_avail = reg;
1586 byte_avail = byte;
1587 slave_reg_avail = slave_reg;
1588 }
1589
1590 /*
1591 * Parse slave address bytes and check whether the
1592 * slave address already exists and it's enabled,
1593 * i.e. most significant bit is set.
1594 */
1595 if ((addr_tmp & slave_addr_mask) == addr) {
1596 if (MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp))
1597 return 0;
1598 disabled = true;
1599 break;
1600 }
1601
1602 /* Parse next byte. */
1603 slave_reg_tmp >>= 8;
1604 }
1605
1606 /* Exit the loop if the slave address is found. */
1607 if (disabled)
1608 break;
1609 }
1610
1611 if (!avail && !disabled)
1612 return -EINVAL; /* No room for a new slave address. */
1613
1614 if (avail && !disabled) {
1615 reg = reg_avail;
1616 byte = byte_avail;
1617 /* Set the slave address. */
1618 slave_reg_avail &= ~(slave_addr_mask << (byte * 8));
1619 slave_reg_avail |= addr << (byte * 8);
1620 slave_reg = slave_reg_avail;
1621 }
1622
1623 /* Enable the slave address and update the register. */
1624 slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8);
1625 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
1626 reg * 0x4);
1627
1628 return 0;
1629 }
1630
mlxbf_slave_disable(struct mlxbf_i2c_priv * priv)1631 static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv)
1632 {
1633 u32 slave_reg, slave_reg_tmp, slave_addr_mask;
1634 u8 addr, addr_tmp, reg, reg_cnt, slave_byte;
1635 struct i2c_client *client = priv->slave;
1636 bool exist;
1637
1638 exist = false;
1639
1640 addr = client->addr;
1641 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
1642 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
1643
1644 /*
1645 * Read the slave registers. There are 4 * 32-bit slave registers.
1646 * Each slave register can hold up to 4 * 8-bit slave configuration
1647 * (7-bit address, 1 status bit (1 if enabled, 0 if not)).
1648 */
1649 for (reg = 0; reg < reg_cnt; reg++) {
1650 slave_reg = readl(priv->smbus->io +
1651 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
1652
1653 /* Check whether the address slots are empty. */
1654 if (slave_reg == 0)
1655 continue;
1656
1657 /*
1658 * Each register holds 4 slave addresses. So, we have to keep
1659 * the byte order consistent with the value read in order to
1660 * update the register correctly, if needed.
1661 */
1662 slave_reg_tmp = slave_reg;
1663 slave_byte = 0;
1664 while (slave_reg_tmp != 0) {
1665 addr_tmp = slave_reg_tmp & slave_addr_mask;
1666 /*
1667 * Parse slave address bytes and check whether the
1668 * slave address already exists.
1669 */
1670 if (addr_tmp == addr) {
1671 exist = true;
1672 break;
1673 }
1674
1675 /* Parse next byte. */
1676 slave_reg_tmp >>= 8;
1677 slave_byte += 1;
1678 }
1679
1680 /* Exit the loop if the slave address is found. */
1681 if (exist)
1682 break;
1683 }
1684
1685 if (!exist)
1686 return 0; /* Slave is not registered, nothing to do. */
1687
1688 /* Cleanup the slave address slot. */
1689 slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8));
1690 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
1691 reg * 0x4);
1692
1693 return 0;
1694 }
1695
mlxbf_i2c_init_coalesce(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1696 static int mlxbf_i2c_init_coalesce(struct platform_device *pdev,
1697 struct mlxbf_i2c_priv *priv)
1698 {
1699 struct mlxbf_i2c_resource *coalesce_res;
1700 struct resource *params;
1701 resource_size_t size;
1702 int ret = 0;
1703
1704 /*
1705 * Unlike BlueField-1 platform, the coalesce registers is a dedicated
1706 * resource in the next generations of BlueField.
1707 */
1708 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {
1709 coalesce_res = mlxbf_i2c_get_shared_resource(priv,
1710 MLXBF_I2C_COALESCE_RES);
1711 if (!coalesce_res)
1712 return -EPERM;
1713
1714 /*
1715 * The Cause Coalesce group in TYU space is shared among
1716 * I2C busses. This function MUST be serialized to avoid
1717 * racing when claiming the memory region.
1718 */
1719 lockdep_assert_held(mlxbf_i2c_gpio_res->lock);
1720
1721 /* Check whether the memory map exist. */
1722 if (coalesce_res->io) {
1723 priv->coalesce = coalesce_res;
1724 return 0;
1725 }
1726
1727 params = coalesce_res->params;
1728 size = resource_size(params);
1729
1730 if (!request_mem_region(params->start, size, params->name))
1731 return -EFAULT;
1732
1733 coalesce_res->io = ioremap(params->start, size);
1734 if (!coalesce_res->io) {
1735 release_mem_region(params->start, size);
1736 return -ENOMEM;
1737 }
1738
1739 priv->coalesce = coalesce_res;
1740
1741 } else {
1742 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce,
1743 MLXBF_I2C_COALESCE_RES);
1744 }
1745
1746 return ret;
1747 }
1748
mlxbf_i2c_release_coalesce(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1749 static int mlxbf_i2c_release_coalesce(struct platform_device *pdev,
1750 struct mlxbf_i2c_priv *priv)
1751 {
1752 struct mlxbf_i2c_resource *coalesce_res;
1753 struct device *dev = &pdev->dev;
1754 struct resource *params;
1755 resource_size_t size;
1756
1757 coalesce_res = priv->coalesce;
1758
1759 if (coalesce_res->io) {
1760 params = coalesce_res->params;
1761 size = resource_size(params);
1762 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {
1763 mutex_lock(coalesce_res->lock);
1764 iounmap(coalesce_res->io);
1765 release_mem_region(params->start, size);
1766 mutex_unlock(coalesce_res->lock);
1767 } else {
1768 devm_release_mem_region(dev, params->start, size);
1769 }
1770 }
1771
1772 return 0;
1773 }
1774
mlxbf_i2c_init_slave(struct platform_device * pdev,struct mlxbf_i2c_priv * priv)1775 static int mlxbf_i2c_init_slave(struct platform_device *pdev,
1776 struct mlxbf_i2c_priv *priv)
1777 {
1778 struct device *dev = &pdev->dev;
1779 u32 int_reg;
1780 int ret;
1781
1782 /* Reset FSM. */
1783 writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM);
1784
1785 /*
1786 * Enable slave cause interrupt bits. Drive
1787 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and
1788 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external
1789 * masters issue a Read and Write, respectively. But, clear all
1790 * interrupts first.
1791 */
1792 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
1793 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE;
1794 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS;
1795 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0);
1796
1797 /* Finally, set the 'ready' bit to start handling transactions. */
1798 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
1799
1800 /* Initialize the cause coalesce resource. */
1801 ret = mlxbf_i2c_init_coalesce(pdev, priv);
1802 if (ret < 0) {
1803 dev_err(dev, "failed to initialize cause coalesce\n");
1804 return ret;
1805 }
1806
1807 return 0;
1808 }
1809
mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv * priv,bool * read,bool * write)1810 static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read,
1811 bool *write)
1812 {
1813 const struct mlxbf_i2c_chip_info *chip = priv->chip;
1814 u32 coalesce0_reg, cause_reg;
1815 u8 slave_shift, is_set;
1816
1817 *write = false;
1818 *read = false;
1819
1820 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ?
1821 MLXBF_I2C_CAUSE_YU_SLAVE_BIT :
1822 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT;
1823
1824 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0);
1825 is_set = coalesce0_reg & (1 << slave_shift);
1826
1827 if (!is_set)
1828 return false;
1829
1830 /* Check the source of the interrupt, i.e. whether a Read or Write. */
1831 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER);
1832 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE)
1833 *read = true;
1834 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS)
1835 *write = true;
1836
1837 /* Clear cause bits. */
1838 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
1839
1840 return true;
1841 }
1842
mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv * priv,u32 timeout)1843 static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv,
1844 u32 timeout)
1845 {
1846 u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL;
1847 u32 addr = MLXBF_I2C_CAUSE_ARBITER;
1848
1849 if (mlxbf_smbus_poll(priv->slv_cause->io, addr, mask, false, timeout))
1850 return true;
1851
1852 return false;
1853 }
1854
1855 /* Send byte to 'external' smbus master. */
mlxbf_smbus_irq_send(struct mlxbf_i2c_priv * priv,u8 recv_bytes)1856 static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
1857 {
1858 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
1859 u8 write_size, pec_en, addr, byte, value, byte_cnt, desc_size;
1860 struct i2c_client *slave = priv->slave;
1861 u32 control32, data32;
1862 int ret;
1863
1864 if (!slave)
1865 return -EINVAL;
1866
1867 addr = 0;
1868 byte = 0;
1869 desc_size = MLXBF_I2C_SLAVE_DATA_DESC_SIZE;
1870
1871 /*
1872 * Read bytes received from the external master. These bytes should
1873 * be located in the first data descriptor register of the slave GW.
1874 * These bytes are the slave address byte and the internal register
1875 * address, if supplied.
1876 */
1877 if (recv_bytes > 0) {
1878 data32 = ioread32be(priv->smbus->io +
1879 MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
1880
1881 /* Parse the received bytes. */
1882 switch (recv_bytes) {
1883 case 2:
1884 byte = (data32 >> 8) & GENMASK(7, 0);
1885 fallthrough;
1886 case 1:
1887 addr = (data32 & GENMASK(7, 0)) >> 1;
1888 }
1889
1890 /* Check whether it's our slave address. */
1891 if (slave->addr != addr)
1892 return -EINVAL;
1893 }
1894
1895 /*
1896 * I2C read transactions may start by a WRITE followed by a READ.
1897 * Indeed, most slave devices would expect the internal address
1898 * following the slave address byte. So, write that byte first,
1899 * and then, send the requested data bytes to the master.
1900 */
1901 if (recv_bytes > 1) {
1902 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1903 value = byte;
1904 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
1905 &value);
1906 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1907
1908 if (ret < 0)
1909 return ret;
1910 }
1911
1912 /*
1913 * Now, send data to the master; currently, the driver supports
1914 * READ_BYTE, READ_WORD and BLOCK READ protocols. Note that the
1915 * hardware can send up to 128 bytes per transfer. That is the
1916 * size of its data registers.
1917 */
1918 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1919
1920 for (byte_cnt = 0; byte_cnt < desc_size; byte_cnt++) {
1921 data_desc[byte_cnt] = value;
1922 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
1923 }
1924
1925 /* Send a stop condition to the backend. */
1926 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1927
1928 /* Handle the actual transfer. */
1929
1930 /* Set the number of bytes to write to master. */
1931 write_size = (byte_cnt - 1) & 0x7f;
1932
1933 /* Write data to Slave GW data descriptor. */
1934 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt,
1935 MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
1936
1937 pec_en = 0; /* Disable PEC since it is not supported. */
1938
1939 /* Prepare control word. */
1940 control32 = MLXBF_I2C_SLAVE_ENABLE;
1941 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT);
1942 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT);
1943
1944 writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW);
1945
1946 /*
1947 * Wait until the transfer is completed; the driver will wait
1948 * until the GW is idle, a cause will rise on fall of GW busy.
1949 */
1950 mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT);
1951
1952 /* Release the Slave GW. */
1953 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
1954 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
1955 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
1956
1957 return 0;
1958 }
1959
1960 /* Receive bytes from 'external' smbus master. */
mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv * priv,u8 recv_bytes)1961 static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
1962 {
1963 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
1964 struct i2c_client *slave = priv->slave;
1965 u8 value, byte, addr;
1966 int ret = 0;
1967
1968 if (!slave)
1969 return -EINVAL;
1970
1971 /* Read data from Slave GW data descriptor. */
1972 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes,
1973 MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
1974
1975 /* Check whether its our slave address. */
1976 addr = data_desc[0] >> 1;
1977 if (slave->addr != addr)
1978 return -EINVAL;
1979
1980 /*
1981 * Notify the slave backend; another I2C master wants to write data
1982 * to us. This event is sent once the slave address and the write bit
1983 * is detected.
1984 */
1985 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1986
1987 /* Send the received data to the slave backend. */
1988 for (byte = 1; byte < recv_bytes; byte++) {
1989 value = data_desc[byte];
1990 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
1991 &value);
1992 if (ret < 0)
1993 break;
1994 }
1995
1996 /* Send a stop condition to the backend. */
1997 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1998
1999 /* Release the Slave GW. */
2000 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
2001 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
2002 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
2003
2004 return ret;
2005 }
2006
mlxbf_smbus_irq(int irq,void * ptr)2007 static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr)
2008 {
2009 struct mlxbf_i2c_priv *priv = ptr;
2010 bool read, write, irq_is_set;
2011 u32 rw_bytes_reg;
2012 u8 recv_bytes;
2013
2014 /*
2015 * Read TYU interrupt register and determine the source of the
2016 * interrupt. Based on the source of the interrupt one of the
2017 * following actions are performed:
2018 * - Receive data and send response to master.
2019 * - Send data and release slave GW.
2020 *
2021 * Handle read/write transaction only. CRmaster and Iarp requests
2022 * are ignored for now.
2023 */
2024 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write);
2025 if (!irq_is_set || (!read && !write)) {
2026 /* Nothing to do here, interrupt was not from this device. */
2027 return IRQ_NONE;
2028 }
2029
2030 /*
2031 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of
2032 * bytes from/to master. These are defined by 8-bits each. If the lower
2033 * 8 bits are set, then the master expect to read N bytes from the
2034 * slave, if the higher 8 bits are sent then the slave expect N bytes
2035 * from the master.
2036 */
2037 rw_bytes_reg = readl(priv->smbus->io +
2038 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
2039 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0);
2040
2041 /*
2042 * For now, the slave supports 128 bytes transfer. Discard remaining
2043 * data bytes if the master wrote more than
2044 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave
2045 * data descriptor.
2046 *
2047 * Note that we will never expect to transfer more than 128 bytes; as
2048 * specified in the SMBus standard, block transactions cannot exceed
2049 * 32 bytes.
2050 */
2051 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ?
2052 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes;
2053
2054 if (read)
2055 mlxbf_smbus_irq_send(priv, recv_bytes);
2056 else
2057 mlxbf_smbus_irq_recv(priv, recv_bytes);
2058
2059 return IRQ_HANDLED;
2060 }
2061
2062 /* Return negative errno on error. */
mlxbf_i2c_smbus_xfer(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)2063 static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
2064 unsigned short flags, char read_write,
2065 u8 command, int size,
2066 union i2c_smbus_data *data)
2067 {
2068 struct mlxbf_i2c_smbus_request request = { 0 };
2069 struct mlxbf_i2c_priv *priv;
2070 bool read, pec;
2071 u8 byte_cnt;
2072
2073 request.slave = addr;
2074
2075 read = (read_write == I2C_SMBUS_READ);
2076 pec = flags & I2C_FUNC_SMBUS_PEC;
2077
2078 switch (size) {
2079 case I2C_SMBUS_QUICK:
2080 mlxbf_i2c_smbus_quick_command(&request, read);
2081 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr);
2082 break;
2083
2084 case I2C_SMBUS_BYTE:
2085 mlxbf_i2c_smbus_byte_func(&request,
2086 read ? &data->byte : &command, read,
2087 pec);
2088 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n",
2089 read ? "read" : "write", addr);
2090 break;
2091
2092 case I2C_SMBUS_BYTE_DATA:
2093 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte,
2094 read, pec);
2095 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n",
2096 read ? "read" : "write", command, addr);
2097 break;
2098
2099 case I2C_SMBUS_WORD_DATA:
2100 mlxbf_i2c_smbus_data_word_func(&request, &command,
2101 (u8 *)&data->word, read, pec);
2102 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n",
2103 read ? "read" : "write", command, addr);
2104 break;
2105
2106 case I2C_SMBUS_I2C_BLOCK_DATA:
2107 byte_cnt = data->block[0];
2108 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block,
2109 &byte_cnt, read, pec);
2110 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
2111 read ? "read" : "write", byte_cnt, command, addr);
2112 break;
2113
2114 case I2C_SMBUS_BLOCK_DATA:
2115 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0];
2116 mlxbf_i2c_smbus_block_func(&request, &command, data->block,
2117 &byte_cnt, read, pec);
2118 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
2119 read ? "read" : "write", byte_cnt, command, addr);
2120 break;
2121
2122 case I2C_FUNC_SMBUS_PROC_CALL:
2123 mlxbf_i2c_smbus_process_call_func(&request, &command,
2124 (u8 *)&data->word, pec);
2125 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n",
2126 command, addr);
2127 break;
2128
2129 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL:
2130 byte_cnt = data->block[0];
2131 mlxbf_i2c_smbus_blk_process_call_func(&request, &command,
2132 data->block, &byte_cnt,
2133 pec);
2134 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n",
2135 byte_cnt, addr);
2136 break;
2137
2138 default:
2139 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n",
2140 size);
2141 return -EOPNOTSUPP;
2142 }
2143
2144 priv = i2c_get_adapdata(adap);
2145
2146 return mlxbf_i2c_smbus_start_transaction(priv, &request);
2147 }
2148
mlxbf_i2c_reg_slave(struct i2c_client * slave)2149 static int mlxbf_i2c_reg_slave(struct i2c_client *slave)
2150 {
2151 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
2152 int ret;
2153
2154 if (priv->slave)
2155 return -EBUSY;
2156
2157 /*
2158 * Do not support ten bit chip address and do not use Packet Error
2159 * Checking (PEC).
2160 */
2161 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC))
2162 return -EAFNOSUPPORT;
2163
2164 ret = mlxbf_slave_enable(priv, slave->addr);
2165 if (ret < 0)
2166 return ret;
2167
2168 priv->slave = slave;
2169
2170 return 0;
2171 }
2172
mlxbf_i2c_unreg_slave(struct i2c_client * slave)2173 static int mlxbf_i2c_unreg_slave(struct i2c_client *slave)
2174 {
2175 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
2176 int ret;
2177
2178 WARN_ON(!priv->slave);
2179
2180 /* Unregister slave, i.e. disable the slave address in hardware. */
2181 ret = mlxbf_slave_disable(priv);
2182 if (ret < 0)
2183 return ret;
2184
2185 priv->slave = NULL;
2186
2187 return 0;
2188 }
2189
mlxbf_i2c_functionality(struct i2c_adapter * adap)2190 static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap)
2191 {
2192 return MLXBF_I2C_FUNC_ALL;
2193 }
2194
2195 static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = {
2196 [MLXBF_I2C_CHIP_TYPE_1] = {
2197 .type = MLXBF_I2C_CHIP_TYPE_1,
2198 .shared_res = {
2199 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1],
2200 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1],
2201 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1]
2202 },
2203 .calculate_freq = mlxbf_i2c_calculate_freq_from_tyu
2204 },
2205 [MLXBF_I2C_CHIP_TYPE_2] = {
2206 .type = MLXBF_I2C_CHIP_TYPE_2,
2207 .shared_res = {
2208 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2]
2209 },
2210 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu
2211 }
2212 };
2213
2214 static const struct i2c_algorithm mlxbf_i2c_algo = {
2215 .smbus_xfer = mlxbf_i2c_smbus_xfer,
2216 .functionality = mlxbf_i2c_functionality,
2217 .reg_slave = mlxbf_i2c_reg_slave,
2218 .unreg_slave = mlxbf_i2c_unreg_slave,
2219 };
2220
2221 static struct i2c_adapter_quirks mlxbf_i2c_quirks = {
2222 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH,
2223 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH,
2224 };
2225
2226 static const struct of_device_id mlxbf_i2c_dt_ids[] = {
2227 {
2228 .compatible = "mellanox,i2c-mlxbf1",
2229 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1]
2230 },
2231 {
2232 .compatible = "mellanox,i2c-mlxbf2",
2233 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2]
2234 },
2235 {},
2236 };
2237
2238 MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids);
2239
2240 #ifdef CONFIG_ACPI
2241 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = {
2242 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] },
2243 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] },
2244 {},
2245 };
2246
2247 MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids);
2248
mlxbf_i2c_acpi_probe(struct device * dev,struct mlxbf_i2c_priv * priv)2249 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
2250 {
2251 const struct acpi_device_id *aid;
2252 struct acpi_device *adev;
2253 unsigned long bus_id = 0;
2254 const char *uid;
2255 int ret;
2256
2257 if (acpi_disabled)
2258 return -ENOENT;
2259
2260 adev = ACPI_COMPANION(dev);
2261 if (!adev)
2262 return -ENXIO;
2263
2264 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev);
2265 if (!aid)
2266 return -ENODEV;
2267
2268 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data;
2269
2270 uid = acpi_device_uid(adev);
2271 if (!uid || !(*uid)) {
2272 dev_err(dev, "Cannot retrieve UID\n");
2273 return -ENODEV;
2274 }
2275
2276 ret = kstrtoul(uid, 0, &bus_id);
2277 if (!ret)
2278 priv->bus = bus_id;
2279
2280 return ret;
2281 }
2282 #else
mlxbf_i2c_acpi_probe(struct device * dev,struct mlxbf_i2c_priv * priv)2283 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
2284 {
2285 return -ENOENT;
2286 }
2287 #endif /* CONFIG_ACPI */
2288
mlxbf_i2c_of_probe(struct device * dev,struct mlxbf_i2c_priv * priv)2289 static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
2290 {
2291 const struct of_device_id *oid;
2292 int bus_id = -1;
2293
2294 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
2295 oid = of_match_node(mlxbf_i2c_dt_ids, dev->of_node);
2296 if (!oid)
2297 return -ENODEV;
2298
2299 priv->chip = oid->data;
2300
2301 bus_id = of_alias_get_id(dev->of_node, "i2c");
2302 if (bus_id >= 0)
2303 priv->bus = bus_id;
2304 }
2305
2306 if (bus_id < 0) {
2307 dev_err(dev, "Cannot get bus id");
2308 return bus_id;
2309 }
2310
2311 return 0;
2312 }
2313
mlxbf_i2c_probe(struct platform_device * pdev)2314 static int mlxbf_i2c_probe(struct platform_device *pdev)
2315 {
2316 struct device *dev = &pdev->dev;
2317 struct mlxbf_i2c_priv *priv;
2318 struct i2c_adapter *adap;
2319 int irq, ret;
2320
2321 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL);
2322 if (!priv)
2323 return -ENOMEM;
2324
2325 ret = mlxbf_i2c_acpi_probe(dev, priv);
2326 if (ret < 0 && ret != -ENOENT && ret != -ENXIO)
2327 ret = mlxbf_i2c_of_probe(dev, priv);
2328
2329 if (ret < 0)
2330 return ret;
2331
2332 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus,
2333 MLXBF_I2C_SMBUS_RES);
2334 if (ret < 0) {
2335 dev_err(dev, "Cannot fetch smbus resource info");
2336 return ret;
2337 }
2338
2339 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause,
2340 MLXBF_I2C_MST_CAUSE_RES);
2341 if (ret < 0) {
2342 dev_err(dev, "Cannot fetch cause master resource info");
2343 return ret;
2344 }
2345
2346 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause,
2347 MLXBF_I2C_SLV_CAUSE_RES);
2348 if (ret < 0) {
2349 dev_err(dev, "Cannot fetch cause slave resource info");
2350 return ret;
2351 }
2352
2353 adap = &priv->adap;
2354 adap->owner = THIS_MODULE;
2355 adap->class = I2C_CLASS_HWMON;
2356 adap->algo = &mlxbf_i2c_algo;
2357 adap->quirks = &mlxbf_i2c_quirks;
2358 adap->dev.parent = dev;
2359 adap->dev.of_node = dev->of_node;
2360 adap->nr = priv->bus;
2361
2362 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr);
2363 i2c_set_adapdata(adap, priv);
2364
2365 /* Read Core PLL frequency. */
2366 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv);
2367 if (ret < 0) {
2368 dev_err(dev, "cannot get core clock frequency\n");
2369 /* Set to default value. */
2370 priv->frequency = MLXBF_I2C_COREPLL_FREQ;
2371 }
2372
2373 /*
2374 * Initialize master.
2375 * Note that a physical bus might be shared among Linux and firmware
2376 * (e.g., ATF). Thus, the bus should be initialized and ready and
2377 * bus initialization would be unnecessary. This requires additional
2378 * knowledge about physical busses. But, since an extra initialization
2379 * does not really hurt, then keep the code as is.
2380 */
2381 ret = mlxbf_i2c_init_master(pdev, priv);
2382 if (ret < 0) {
2383 dev_err(dev, "failed to initialize smbus master %d",
2384 priv->bus);
2385 return ret;
2386 }
2387
2388 mlxbf_i2c_init_timings(pdev, priv);
2389
2390 mlxbf_i2c_init_slave(pdev, priv);
2391
2392 irq = platform_get_irq(pdev, 0);
2393 if (irq < 0)
2394 return irq;
2395 ret = devm_request_irq(dev, irq, mlxbf_smbus_irq,
2396 IRQF_ONESHOT | IRQF_SHARED | IRQF_PROBE_SHARED,
2397 dev_name(dev), priv);
2398 if (ret < 0) {
2399 dev_err(dev, "Cannot get irq %d\n", irq);
2400 return ret;
2401 }
2402
2403 priv->irq = irq;
2404
2405 platform_set_drvdata(pdev, priv);
2406
2407 ret = i2c_add_numbered_adapter(adap);
2408 if (ret < 0)
2409 return ret;
2410
2411 mutex_lock(&mlxbf_i2c_bus_lock);
2412 mlxbf_i2c_bus_count++;
2413 mutex_unlock(&mlxbf_i2c_bus_lock);
2414
2415 return 0;
2416 }
2417
mlxbf_i2c_remove(struct platform_device * pdev)2418 static int mlxbf_i2c_remove(struct platform_device *pdev)
2419 {
2420 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev);
2421 struct device *dev = &pdev->dev;
2422 struct resource *params;
2423
2424 params = priv->smbus->params;
2425 devm_release_mem_region(dev, params->start, resource_size(params));
2426
2427 params = priv->mst_cause->params;
2428 devm_release_mem_region(dev, params->start, resource_size(params));
2429
2430 params = priv->slv_cause->params;
2431 devm_release_mem_region(dev, params->start, resource_size(params));
2432
2433 /*
2434 * Release shared resources. This should be done when releasing
2435 * the I2C controller.
2436 */
2437 mutex_lock(&mlxbf_i2c_bus_lock);
2438 if (--mlxbf_i2c_bus_count == 0) {
2439 mlxbf_i2c_release_coalesce(pdev, priv);
2440 mlxbf_i2c_release_corepll(pdev, priv);
2441 mlxbf_i2c_release_gpio(pdev, priv);
2442 }
2443 mutex_unlock(&mlxbf_i2c_bus_lock);
2444
2445 devm_free_irq(dev, priv->irq, priv);
2446
2447 i2c_del_adapter(&priv->adap);
2448
2449 return 0;
2450 }
2451
2452 static struct platform_driver mlxbf_i2c_driver = {
2453 .probe = mlxbf_i2c_probe,
2454 .remove = mlxbf_i2c_remove,
2455 .driver = {
2456 .name = "i2c-mlxbf",
2457 .of_match_table = mlxbf_i2c_dt_ids,
2458 #ifdef CONFIG_ACPI
2459 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids),
2460 #endif /* CONFIG_ACPI */
2461 },
2462 };
2463
mlxbf_i2c_init(void)2464 static int __init mlxbf_i2c_init(void)
2465 {
2466 mutex_init(&mlxbf_i2c_coalesce_lock);
2467 mutex_init(&mlxbf_i2c_corepll_lock);
2468 mutex_init(&mlxbf_i2c_gpio_lock);
2469
2470 mutex_init(&mlxbf_i2c_bus_lock);
2471
2472 return platform_driver_register(&mlxbf_i2c_driver);
2473 }
2474 module_init(mlxbf_i2c_init);
2475
mlxbf_i2c_exit(void)2476 static void __exit mlxbf_i2c_exit(void)
2477 {
2478 platform_driver_unregister(&mlxbf_i2c_driver);
2479
2480 mutex_destroy(&mlxbf_i2c_bus_lock);
2481
2482 mutex_destroy(&mlxbf_i2c_gpio_lock);
2483 mutex_destroy(&mlxbf_i2c_corepll_lock);
2484 mutex_destroy(&mlxbf_i2c_coalesce_lock);
2485 }
2486 module_exit(mlxbf_i2c_exit);
2487
2488 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver");
2489 MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>");
2490 MODULE_LICENSE("GPL v2");
2491