1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /*
3 * Mellanox i2c driver
4 *
5 * Copyright (C) 2016-2020 Mellanox Technologies
6 */
7
8 #include <linux/delay.h>
9 #include <linux/i2c.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/mlxreg.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17
18 /* General defines */
19 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADDR 0x2000
20 #define MLXCPLD_I2C_DEVICE_NAME "i2c_mlxcpld"
21 #define MLXCPLD_I2C_VALID_FLAG (I2C_M_RECV_LEN | I2C_M_RD)
22 #define MLXCPLD_I2C_BUS_NUM 1
23 #define MLXCPLD_I2C_DATA_REG_SZ 36
24 #define MLXCPLD_I2C_DATA_SZ_BIT BIT(5)
25 #define MLXCPLD_I2C_DATA_SZ_MASK GENMASK(6, 5)
26 #define MLXCPLD_I2C_SMBUS_BLK_BIT BIT(7)
27 #define MLXCPLD_I2C_MAX_ADDR_LEN 4
28 #define MLXCPLD_I2C_RETR_NUM 2
29 #define MLXCPLD_I2C_XFER_TO 500000 /* usec */
30 #define MLXCPLD_I2C_POLL_TIME 400 /* usec */
31
32 /* LPC I2C registers */
33 #define MLXCPLD_LPCI2C_CPBLTY_REG 0x0
34 #define MLXCPLD_LPCI2C_CTRL_REG 0x1
35 #define MLXCPLD_LPCI2C_HALF_CYC_REG 0x4
36 #define MLXCPLD_LPCI2C_I2C_HOLD_REG 0x5
37 #define MLXCPLD_LPCI2C_CMD_REG 0x6
38 #define MLXCPLD_LPCI2C_NUM_DAT_REG 0x7
39 #define MLXCPLD_LPCI2C_NUM_ADDR_REG 0x8
40 #define MLXCPLD_LPCI2C_STATUS_REG 0x9
41 #define MLXCPLD_LPCI2C_DATA_REG 0xa
42
43 /* LPC I2C masks and parametres */
44 #define MLXCPLD_LPCI2C_RST_SEL_MASK 0x1
45 #define MLXCPLD_LPCI2C_TRANS_END 0x1
46 #define MLXCPLD_LPCI2C_STATUS_NACK 0x10
47 #define MLXCPLD_LPCI2C_NO_IND 0
48 #define MLXCPLD_LPCI2C_ACK_IND 1
49 #define MLXCPLD_LPCI2C_NACK_IND 2
50
51 #define MLXCPLD_I2C_FREQ_1000KHZ_SET 0x04
52 #define MLXCPLD_I2C_FREQ_400KHZ_SET 0x0e
53 #define MLXCPLD_I2C_FREQ_100KHZ_SET 0x42
54
55 enum mlxcpld_i2c_frequency {
56 MLXCPLD_I2C_FREQ_1000KHZ = 1,
57 MLXCPLD_I2C_FREQ_400KHZ = 2,
58 MLXCPLD_I2C_FREQ_100KHZ = 3,
59 };
60
61 struct mlxcpld_i2c_curr_xfer {
62 u8 cmd;
63 u8 addr_width;
64 u8 data_len;
65 u8 msg_num;
66 struct i2c_msg *msg;
67 };
68
69 struct mlxcpld_i2c_priv {
70 struct i2c_adapter adap;
71 u32 base_addr;
72 struct mutex lock;
73 struct mlxcpld_i2c_curr_xfer xfer;
74 struct device *dev;
75 bool smbus_block;
76 };
77
mlxcpld_i2c_lpc_write_buf(u8 * data,u8 len,u32 addr)78 static void mlxcpld_i2c_lpc_write_buf(u8 *data, u8 len, u32 addr)
79 {
80 int i;
81
82 for (i = 0; i < len - len % 4; i += 4)
83 outl(*(u32 *)(data + i), addr + i);
84 for (; i < len; ++i)
85 outb(*(data + i), addr + i);
86 }
87
mlxcpld_i2c_lpc_read_buf(u8 * data,u8 len,u32 addr)88 static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr)
89 {
90 int i;
91
92 for (i = 0; i < len - len % 4; i += 4)
93 *(u32 *)(data + i) = inl(addr + i);
94 for (; i < len; ++i)
95 *(data + i) = inb(addr + i);
96 }
97
mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv * priv,u8 offs,u8 * data,u8 datalen)98 static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
99 u8 *data, u8 datalen)
100 {
101 u32 addr = priv->base_addr + offs;
102
103 switch (datalen) {
104 case 1:
105 *(data) = inb(addr);
106 break;
107 case 2:
108 *((u16 *)data) = inw(addr);
109 break;
110 case 3:
111 *((u16 *)data) = inw(addr);
112 *(data + 2) = inb(addr + 2);
113 break;
114 case 4:
115 *((u32 *)data) = inl(addr);
116 break;
117 default:
118 mlxcpld_i2c_lpc_read_buf(data, datalen, addr);
119 break;
120 }
121 }
122
mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv * priv,u8 offs,u8 * data,u8 datalen)123 static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
124 u8 *data, u8 datalen)
125 {
126 u32 addr = priv->base_addr + offs;
127
128 switch (datalen) {
129 case 1:
130 outb(*(data), addr);
131 break;
132 case 2:
133 outw(*((u16 *)data), addr);
134 break;
135 case 3:
136 outw(*((u16 *)data), addr);
137 outb(*(data + 2), addr + 2);
138 break;
139 case 4:
140 outl(*((u32 *)data), addr);
141 break;
142 default:
143 mlxcpld_i2c_lpc_write_buf(data, datalen, addr);
144 break;
145 }
146 }
147
148 /*
149 * Check validity of received i2c messages parameters.
150 * Returns 0 if OK, other - in case of invalid parameters.
151 */
mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv * priv,struct i2c_msg * msgs,int num)152 static int mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv *priv,
153 struct i2c_msg *msgs, int num)
154 {
155 int i;
156
157 if (!num) {
158 dev_err(priv->dev, "Incorrect 0 num of messages\n");
159 return -EINVAL;
160 }
161
162 if (unlikely(msgs[0].addr > 0x7f)) {
163 dev_err(priv->dev, "Invalid address 0x%03x\n",
164 msgs[0].addr);
165 return -EINVAL;
166 }
167
168 for (i = 0; i < num; ++i) {
169 if (unlikely(!msgs[i].buf)) {
170 dev_err(priv->dev, "Invalid buf in msg[%d]\n",
171 i);
172 return -EINVAL;
173 }
174 if (unlikely(msgs[0].addr != msgs[i].addr)) {
175 dev_err(priv->dev, "Invalid addr in msg[%d]\n",
176 i);
177 return -EINVAL;
178 }
179 }
180
181 return 0;
182 }
183
184 /*
185 * Check if transfer is completed and status of operation.
186 * Returns 0 - transfer completed (both ACK or NACK),
187 * negative - transfer isn't finished.
188 */
mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv * priv,int * status)189 static int mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv *priv, int *status)
190 {
191 u8 val;
192
193 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
194
195 if (val & MLXCPLD_LPCI2C_TRANS_END) {
196 if (val & MLXCPLD_LPCI2C_STATUS_NACK)
197 /*
198 * The slave is unable to accept the data. No such
199 * slave, command not understood, or unable to accept
200 * any more data.
201 */
202 *status = MLXCPLD_LPCI2C_NACK_IND;
203 else
204 *status = MLXCPLD_LPCI2C_ACK_IND;
205 return 0;
206 }
207 *status = MLXCPLD_LPCI2C_NO_IND;
208
209 return -EIO;
210 }
211
mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv * priv,struct i2c_msg * msgs,int num,u8 comm_len)212 static void mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv *priv,
213 struct i2c_msg *msgs, int num,
214 u8 comm_len)
215 {
216 priv->xfer.msg = msgs;
217 priv->xfer.msg_num = num;
218
219 /*
220 * All upper layers currently are never use transfer with more than
221 * 2 messages. Actually, it's also not so relevant in Mellanox systems
222 * because of HW limitation. Max size of transfer is not more than 32
223 * or 68 bytes in the current x86 LPCI2C bridge.
224 */
225 priv->xfer.cmd = msgs[num - 1].flags & I2C_M_RD;
226
227 if (priv->xfer.cmd == I2C_M_RD && comm_len != msgs[0].len) {
228 priv->xfer.addr_width = msgs[0].len;
229 priv->xfer.data_len = comm_len - priv->xfer.addr_width;
230 } else {
231 priv->xfer.addr_width = 0;
232 priv->xfer.data_len = comm_len;
233 }
234 }
235
236 /* Reset CPLD LPCI2C block */
mlxcpld_i2c_reset(struct mlxcpld_i2c_priv * priv)237 static void mlxcpld_i2c_reset(struct mlxcpld_i2c_priv *priv)
238 {
239 u8 val;
240
241 mutex_lock(&priv->lock);
242
243 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
244 val &= ~MLXCPLD_LPCI2C_RST_SEL_MASK;
245 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
246
247 mutex_unlock(&priv->lock);
248 }
249
250 /* Make sure the CPLD is ready to start transmitting. */
mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv * priv)251 static int mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv *priv)
252 {
253 u8 val;
254
255 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
256
257 if (val & MLXCPLD_LPCI2C_TRANS_END)
258 return 0;
259
260 return -EIO;
261 }
262
mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv * priv)263 static int mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv *priv)
264 {
265 int timeout = 0;
266
267 do {
268 if (!mlxcpld_i2c_check_busy(priv))
269 break;
270 usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME);
271 timeout += MLXCPLD_I2C_POLL_TIME;
272 } while (timeout <= MLXCPLD_I2C_XFER_TO);
273
274 if (timeout > MLXCPLD_I2C_XFER_TO)
275 return -ETIMEDOUT;
276
277 return 0;
278 }
279
280 /*
281 * Wait for master transfer to complete.
282 * It puts current process to sleep until we get interrupt or timeout expires.
283 * Returns the number of transferred or read bytes or error (<0).
284 */
mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv * priv)285 static int mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv *priv)
286 {
287 int status, i, timeout = 0;
288 u8 datalen, val;
289
290 do {
291 usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME);
292 if (!mlxcpld_i2c_check_status(priv, &status))
293 break;
294 timeout += MLXCPLD_I2C_POLL_TIME;
295 } while (status == 0 && timeout < MLXCPLD_I2C_XFER_TO);
296
297 switch (status) {
298 case MLXCPLD_LPCI2C_NO_IND:
299 return -ETIMEDOUT;
300
301 case MLXCPLD_LPCI2C_ACK_IND:
302 if (priv->xfer.cmd != I2C_M_RD)
303 return (priv->xfer.addr_width + priv->xfer.data_len);
304
305 if (priv->xfer.msg_num == 1)
306 i = 0;
307 else
308 i = 1;
309
310 if (!priv->xfer.msg[i].buf)
311 return -EINVAL;
312
313 /*
314 * Actual read data len will be always the same as
315 * requested len. 0xff (line pull-up) will be returned
316 * if slave has no data to return. Thus don't read
317 * MLXCPLD_LPCI2C_NUM_DAT_REG reg from CPLD. Only in case of
318 * SMBus block read transaction data len can be different,
319 * check this case.
320 */
321 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val,
322 1);
323 if (priv->smbus_block && (val & MLXCPLD_I2C_SMBUS_BLK_BIT)) {
324 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
325 &datalen, 1);
326 if (unlikely(datalen > I2C_SMBUS_BLOCK_MAX)) {
327 dev_err(priv->dev, "Incorrect smbus block read message len\n");
328 return -EPROTO;
329 }
330 } else {
331 datalen = priv->xfer.data_len;
332 }
333
334 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_DATA_REG,
335 priv->xfer.msg[i].buf, datalen);
336
337 return datalen;
338
339 case MLXCPLD_LPCI2C_NACK_IND:
340 return -ENXIO;
341
342 default:
343 return -EINVAL;
344 }
345 }
346
mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv * priv)347 static void mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv *priv)
348 {
349 int i, len = 0;
350 u8 cmd, val;
351
352 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
353 &priv->xfer.data_len, 1);
354
355 val = priv->xfer.addr_width;
356 /* Notify HW about SMBus block read transaction */
357 if (priv->smbus_block && priv->xfer.msg_num >= 2 &&
358 priv->xfer.msg[1].len == 1 &&
359 (priv->xfer.msg[1].flags & I2C_M_RECV_LEN) &&
360 (priv->xfer.msg[1].flags & I2C_M_RD))
361 val |= MLXCPLD_I2C_SMBUS_BLK_BIT;
362
363 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, 1);
364
365 for (i = 0; i < priv->xfer.msg_num; i++) {
366 if ((priv->xfer.msg[i].flags & I2C_M_RD) != I2C_M_RD) {
367 /* Don't write to CPLD buffer in read transaction */
368 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_DATA_REG +
369 len, priv->xfer.msg[i].buf,
370 priv->xfer.msg[i].len);
371 len += priv->xfer.msg[i].len;
372 }
373 }
374
375 /*
376 * Set target slave address with command for master transfer.
377 * It should be latest executed function before CPLD transaction.
378 */
379 cmd = (priv->xfer.msg[0].addr << 1) | priv->xfer.cmd;
380 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CMD_REG, &cmd, 1);
381 }
382
383 /*
384 * Generic lpc-i2c transfer.
385 * Returns the number of processed messages or error (<0).
386 */
mlxcpld_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)387 static int mlxcpld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
388 int num)
389 {
390 struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
391 u8 comm_len = 0;
392 int i, err;
393
394 err = mlxcpld_i2c_check_msg_params(priv, msgs, num);
395 if (err) {
396 dev_err(priv->dev, "Incorrect message\n");
397 return err;
398 }
399
400 for (i = 0; i < num; ++i)
401 comm_len += msgs[i].len;
402
403 /* Check bus state */
404 if (mlxcpld_i2c_wait_for_free(priv)) {
405 dev_err(priv->dev, "LPCI2C bridge is busy\n");
406
407 /*
408 * Usually it means something serious has happened.
409 * We can not have unfinished previous transfer
410 * so it doesn't make any sense to try to stop it.
411 * Probably we were not able to recover from the
412 * previous error.
413 * The only reasonable thing - is soft reset.
414 */
415 mlxcpld_i2c_reset(priv);
416 if (mlxcpld_i2c_check_busy(priv)) {
417 dev_err(priv->dev, "LPCI2C bridge is busy after reset\n");
418 return -EIO;
419 }
420 }
421
422 mlxcpld_i2c_set_transf_data(priv, msgs, num, comm_len);
423
424 mutex_lock(&priv->lock);
425
426 /* Do real transfer. Can't fail */
427 mlxcpld_i2c_xfer_msg(priv);
428
429 /* Wait for transaction complete */
430 err = mlxcpld_i2c_wait_for_tc(priv);
431
432 mutex_unlock(&priv->lock);
433
434 return err < 0 ? err : num;
435 }
436
mlxcpld_i2c_func(struct i2c_adapter * adap)437 static u32 mlxcpld_i2c_func(struct i2c_adapter *adap)
438 {
439 struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
440
441 if (priv->smbus_block)
442 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
443 I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_BLOCK_DATA;
444 else
445 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
446 I2C_FUNC_SMBUS_I2C_BLOCK;
447 }
448
449 static const struct i2c_algorithm mlxcpld_i2c_algo = {
450 .master_xfer = mlxcpld_i2c_xfer,
451 .functionality = mlxcpld_i2c_func
452 };
453
454 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks = {
455 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
456 .max_read_len = MLXCPLD_I2C_DATA_REG_SZ - MLXCPLD_I2C_MAX_ADDR_LEN,
457 .max_write_len = MLXCPLD_I2C_DATA_REG_SZ,
458 .max_comb_1st_msg_len = 4,
459 };
460
461 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = {
462 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
463 .max_read_len = MLXCPLD_I2C_DATA_REG_SZ * 2 - MLXCPLD_I2C_MAX_ADDR_LEN,
464 .max_write_len = MLXCPLD_I2C_DATA_REG_SZ * 2,
465 .max_comb_1st_msg_len = 4,
466 };
467
468 static struct i2c_adapter mlxcpld_i2c_adapter = {
469 .owner = THIS_MODULE,
470 .name = "i2c-mlxcpld",
471 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
472 .algo = &mlxcpld_i2c_algo,
473 .quirks = &mlxcpld_i2c_quirks,
474 .retries = MLXCPLD_I2C_RETR_NUM,
475 .nr = MLXCPLD_I2C_BUS_NUM,
476 };
477
478 static int
mlxcpld_i2c_set_frequency(struct mlxcpld_i2c_priv * priv,struct mlxreg_core_hotplug_platform_data * pdata)479 mlxcpld_i2c_set_frequency(struct mlxcpld_i2c_priv *priv,
480 struct mlxreg_core_hotplug_platform_data *pdata)
481 {
482 struct mlxreg_core_item *item = pdata->items;
483 struct mlxreg_core_data *data;
484 u32 regval;
485 u8 freq;
486 int err;
487
488 if (!item)
489 return 0;
490
491 /* Read frequency setting. */
492 data = item->data;
493 err = regmap_read(pdata->regmap, data->reg, ®val);
494 if (err)
495 return err;
496
497 /* Set frequency only if it is not 100KHz, which is default. */
498 switch ((regval & data->mask) >> data->bit) {
499 case MLXCPLD_I2C_FREQ_1000KHZ:
500 freq = MLXCPLD_I2C_FREQ_1000KHZ_SET;
501 break;
502 case MLXCPLD_I2C_FREQ_400KHZ:
503 freq = MLXCPLD_I2C_FREQ_400KHZ_SET;
504 break;
505 default:
506 return 0;
507 }
508
509 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_HALF_CYC_REG, &freq, 1);
510
511 return 0;
512 }
513
mlxcpld_i2c_probe(struct platform_device * pdev)514 static int mlxcpld_i2c_probe(struct platform_device *pdev)
515 {
516 struct mlxreg_core_hotplug_platform_data *pdata;
517 struct mlxcpld_i2c_priv *priv;
518 int err;
519 u8 val;
520
521 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
522 if (!priv)
523 return -ENOMEM;
524
525 mutex_init(&priv->lock);
526 platform_set_drvdata(pdev, priv);
527
528 priv->dev = &pdev->dev;
529 priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR;
530
531 /* Set I2C bus frequency if platform data provides this info. */
532 pdata = dev_get_platdata(&pdev->dev);
533 if (pdata) {
534 err = mlxcpld_i2c_set_frequency(priv, pdata);
535 if (err)
536 goto mlxcpld_i2_probe_failed;
537 }
538
539 /* Register with i2c layer */
540 mlxcpld_i2c_adapter.timeout = usecs_to_jiffies(MLXCPLD_I2C_XFER_TO);
541 /* Read capability register */
542 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CPBLTY_REG, &val, 1);
543 /* Check support for extended transaction length */
544 if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT)
545 mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext;
546 /* Check support for smbus block transaction */
547 if (val & MLXCPLD_I2C_SMBUS_BLK_BIT)
548 priv->smbus_block = true;
549 if (pdev->id >= -1)
550 mlxcpld_i2c_adapter.nr = pdev->id;
551 priv->adap = mlxcpld_i2c_adapter;
552 priv->adap.dev.parent = &pdev->dev;
553 i2c_set_adapdata(&priv->adap, priv);
554
555 err = i2c_add_numbered_adapter(&priv->adap);
556 if (err)
557 goto mlxcpld_i2_probe_failed;
558
559 return 0;
560
561 mlxcpld_i2_probe_failed:
562 mutex_destroy(&priv->lock);
563 return err;
564 }
565
mlxcpld_i2c_remove(struct platform_device * pdev)566 static int mlxcpld_i2c_remove(struct platform_device *pdev)
567 {
568 struct mlxcpld_i2c_priv *priv = platform_get_drvdata(pdev);
569
570 i2c_del_adapter(&priv->adap);
571 mutex_destroy(&priv->lock);
572
573 return 0;
574 }
575
576 static struct platform_driver mlxcpld_i2c_driver = {
577 .probe = mlxcpld_i2c_probe,
578 .remove = mlxcpld_i2c_remove,
579 .driver = {
580 .name = MLXCPLD_I2C_DEVICE_NAME,
581 },
582 };
583
584 module_platform_driver(mlxcpld_i2c_driver);
585
586 MODULE_AUTHOR("Michael Shych <michaels@mellanox.com>");
587 MODULE_DESCRIPTION("Mellanox I2C-CPLD controller driver");
588 MODULE_LICENSE("Dual BSD/GPL");
589 MODULE_ALIAS("platform:i2c-mlxcpld");
590