1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
16 */
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/iopoll.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/regmap.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
37
38 #include "i2c-stm32.h"
39
40 /* STM32F7 I2C registers */
41 #define STM32F7_I2C_CR1 0x00
42 #define STM32F7_I2C_CR2 0x04
43 #define STM32F7_I2C_OAR1 0x08
44 #define STM32F7_I2C_OAR2 0x0C
45 #define STM32F7_I2C_PECR 0x20
46 #define STM32F7_I2C_TIMINGR 0x10
47 #define STM32F7_I2C_ISR 0x18
48 #define STM32F7_I2C_ICR 0x1C
49 #define STM32F7_I2C_RXDR 0x24
50 #define STM32F7_I2C_TXDR 0x28
51
52 /* STM32F7 I2C control 1 */
53 #define STM32F7_I2C_CR1_PECEN BIT(23)
54 #define STM32F7_I2C_CR1_ALERTEN BIT(22)
55 #define STM32F7_I2C_CR1_SMBHEN BIT(20)
56 #define STM32F7_I2C_CR1_WUPEN BIT(18)
57 #define STM32F7_I2C_CR1_SBC BIT(16)
58 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
59 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
60 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
61 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
62 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
63 #define STM32F7_I2C_CR1_ERRIE BIT(7)
64 #define STM32F7_I2C_CR1_TCIE BIT(6)
65 #define STM32F7_I2C_CR1_STOPIE BIT(5)
66 #define STM32F7_I2C_CR1_NACKIE BIT(4)
67 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
68 #define STM32F7_I2C_CR1_RXIE BIT(2)
69 #define STM32F7_I2C_CR1_TXIE BIT(1)
70 #define STM32F7_I2C_CR1_PE BIT(0)
71 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
72 | STM32F7_I2C_CR1_TCIE \
73 | STM32F7_I2C_CR1_STOPIE \
74 | STM32F7_I2C_CR1_NACKIE \
75 | STM32F7_I2C_CR1_RXIE \
76 | STM32F7_I2C_CR1_TXIE)
77 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
78 | STM32F7_I2C_CR1_STOPIE \
79 | STM32F7_I2C_CR1_NACKIE \
80 | STM32F7_I2C_CR1_RXIE \
81 | STM32F7_I2C_CR1_TXIE)
82
83 /* STM32F7 I2C control 2 */
84 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
85 #define STM32F7_I2C_CR2_RELOAD BIT(24)
86 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
87 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
88 #define STM32F7_I2C_CR2_NACK BIT(15)
89 #define STM32F7_I2C_CR2_STOP BIT(14)
90 #define STM32F7_I2C_CR2_START BIT(13)
91 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
92 #define STM32F7_I2C_CR2_ADD10 BIT(11)
93 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
94 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
95 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
96 STM32F7_I2C_CR2_SADD10_MASK))
97 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
98 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
99
100 /* STM32F7 I2C Own Address 1 */
101 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
102 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
103 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
104 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
105 STM32F7_I2C_OAR1_OA1_10_MASK))
106 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
107 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
108 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
109 | STM32F7_I2C_OAR1_OA1_10_MASK \
110 | STM32F7_I2C_OAR1_OA1EN \
111 | STM32F7_I2C_OAR1_OA1MODE)
112
113 /* STM32F7 I2C Own Address 2 */
114 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
115 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
116 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
117 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
118 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
119 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
120 | STM32F7_I2C_OAR2_OA2_7_MASK \
121 | STM32F7_I2C_OAR2_OA2EN)
122
123 /* STM32F7 I2C Interrupt Status */
124 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
125 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
126 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
127 #define STM32F7_I2C_ISR_DIR BIT(16)
128 #define STM32F7_I2C_ISR_BUSY BIT(15)
129 #define STM32F7_I2C_ISR_ALERT BIT(13)
130 #define STM32F7_I2C_ISR_PECERR BIT(11)
131 #define STM32F7_I2C_ISR_ARLO BIT(9)
132 #define STM32F7_I2C_ISR_BERR BIT(8)
133 #define STM32F7_I2C_ISR_TCR BIT(7)
134 #define STM32F7_I2C_ISR_TC BIT(6)
135 #define STM32F7_I2C_ISR_STOPF BIT(5)
136 #define STM32F7_I2C_ISR_NACKF BIT(4)
137 #define STM32F7_I2C_ISR_ADDR BIT(3)
138 #define STM32F7_I2C_ISR_RXNE BIT(2)
139 #define STM32F7_I2C_ISR_TXIS BIT(1)
140 #define STM32F7_I2C_ISR_TXE BIT(0)
141
142 /* STM32F7 I2C Interrupt Clear */
143 #define STM32F7_I2C_ICR_ALERTCF BIT(13)
144 #define STM32F7_I2C_ICR_PECCF BIT(11)
145 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
146 #define STM32F7_I2C_ICR_BERRCF BIT(8)
147 #define STM32F7_I2C_ICR_STOPCF BIT(5)
148 #define STM32F7_I2C_ICR_NACKCF BIT(4)
149 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
150
151 /* STM32F7 I2C Timing */
152 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
153 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
154 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
155 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
156 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
157
158 #define STM32F7_I2C_MAX_LEN 0xff
159 #define STM32F7_I2C_DMA_LEN_MIN 0x16
160 enum {
161 STM32F7_SLAVE_HOSTNOTIFY,
162 STM32F7_SLAVE_7_10_BITS_ADDR,
163 STM32F7_SLAVE_7_BITS_ADDR,
164 STM32F7_I2C_MAX_SLAVE
165 };
166
167 #define STM32F7_I2C_DNF_DEFAULT 0
168 #define STM32F7_I2C_DNF_MAX 15
169
170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
172
173 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
174 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
175
176 #define STM32F7_PRESC_MAX BIT(4)
177 #define STM32F7_SCLDEL_MAX BIT(4)
178 #define STM32F7_SDADEL_MAX BIT(4)
179 #define STM32F7_SCLH_MAX BIT(8)
180 #define STM32F7_SCLL_MAX BIT(8)
181
182 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
183
184 /**
185 * struct stm32f7_i2c_regs - i2c f7 registers backup
186 * @cr1: Control register 1
187 * @cr2: Control register 2
188 * @oar1: Own address 1 register
189 * @oar2: Own address 2 register
190 * @tmgr: Timing register
191 */
192 struct stm32f7_i2c_regs {
193 u32 cr1;
194 u32 cr2;
195 u32 oar1;
196 u32 oar2;
197 u32 tmgr;
198 };
199
200 /**
201 * struct stm32f7_i2c_spec - private i2c specification timing
202 * @rate: I2C bus speed (Hz)
203 * @fall_max: Max fall time of both SDA and SCL signals (ns)
204 * @rise_max: Max rise time of both SDA and SCL signals (ns)
205 * @hddat_min: Min data hold time (ns)
206 * @vddat_max: Max data valid time (ns)
207 * @sudat_min: Min data setup time (ns)
208 * @l_min: Min low period of the SCL clock (ns)
209 * @h_min: Min high period of the SCL clock (ns)
210 */
211 struct stm32f7_i2c_spec {
212 u32 rate;
213 u32 fall_max;
214 u32 rise_max;
215 u32 hddat_min;
216 u32 vddat_max;
217 u32 sudat_min;
218 u32 l_min;
219 u32 h_min;
220 };
221
222 /**
223 * struct stm32f7_i2c_setup - private I2C timing setup parameters
224 * @speed_freq: I2C speed frequency (Hz)
225 * @clock_src: I2C clock source frequency (Hz)
226 * @rise_time: Rise time (ns)
227 * @fall_time: Fall time (ns)
228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
229 */
230 struct stm32f7_i2c_setup {
231 u32 speed_freq;
232 u32 clock_src;
233 u32 rise_time;
234 u32 fall_time;
235 u32 fmp_clr_offset;
236 };
237
238 /**
239 * struct stm32f7_i2c_timings - private I2C output parameters
240 * @node: List entry
241 * @presc: Prescaler value
242 * @scldel: Data setup time
243 * @sdadel: Data hold time
244 * @sclh: SCL high period (master mode)
245 * @scll: SCL low period (master mode)
246 */
247 struct stm32f7_i2c_timings {
248 struct list_head node;
249 u8 presc;
250 u8 scldel;
251 u8 sdadel;
252 u8 sclh;
253 u8 scll;
254 };
255
256 /**
257 * struct stm32f7_i2c_msg - client specific data
258 * @addr: 8-bit or 10-bit slave addr, including r/w bit
259 * @count: number of bytes to be transferred
260 * @buf: data buffer
261 * @result: result of the transfer
262 * @stop: last I2C msg to be sent, i.e. STOP to be generated
263 * @smbus: boolean to know if the I2C IP is used in SMBus mode
264 * @size: type of SMBus protocol
265 * @read_write: direction of SMBus protocol
266 * SMBus block read and SMBus block write - block read process call protocols
267 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
268 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
269 * This buffer has to be 32-bit aligned to be compliant with memory address
270 * register in DMA mode.
271 */
272 struct stm32f7_i2c_msg {
273 u16 addr;
274 u32 count;
275 u8 *buf;
276 int result;
277 bool stop;
278 bool smbus;
279 int size;
280 char read_write;
281 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
282 };
283
284 /**
285 * struct stm32f7_i2c_alert - SMBus alert specific data
286 * @setup: platform data for the smbus_alert i2c client
287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
288 * Response Address
289 */
290 struct stm32f7_i2c_alert {
291 struct i2c_smbus_alert_setup setup;
292 struct i2c_client *ara;
293 };
294
295 /**
296 * struct stm32f7_i2c_dev - private data of the controller
297 * @adap: I2C adapter for this controller
298 * @dev: device for this controller
299 * @base: virtual memory area
300 * @complete: completion of I2C message
301 * @clk: hw i2c clock
302 * @bus_rate: I2C clock frequency of the controller
303 * @msg: Pointer to data to be written
304 * @msg_num: number of I2C messages to be executed
305 * @msg_id: message identifiant
306 * @f7_msg: customized i2c msg for driver usage
307 * @setup: I2C timing input setup
308 * @timing: I2C computed timings
309 * @slave: list of slave devices registered on the I2C bus
310 * @slave_running: slave device currently used
311 * @backup_regs: backup of i2c controller registers (for suspend/resume)
312 * @slave_dir: transfer direction for the current slave device
313 * @master_mode: boolean to know in which mode the I2C is running (master or
314 * slave)
315 * @dma: dma data
316 * @use_dma: boolean to know if dma is used in the current transfer
317 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
318 * @fmp_sreg: register address for setting Fast Mode Plus bits
319 * @fmp_creg: register address for clearing Fast Mode Plus bits
320 * @fmp_mask: mask for Fast Mode Plus bits in set register
321 * @wakeup_src: boolean to know if the device is a wakeup source
322 * @smbus_mode: states that the controller is configured in SMBus mode
323 * @host_notify_client: SMBus host-notify client
324 * @analog_filter: boolean to indicate enabling of the analog filter
325 * @dnf_dt: value of digital filter requested via dt
326 * @dnf: value of digital filter to apply
327 * @alert: SMBus alert specific data
328 */
329 struct stm32f7_i2c_dev {
330 struct i2c_adapter adap;
331 struct device *dev;
332 void __iomem *base;
333 struct completion complete;
334 struct clk *clk;
335 unsigned int bus_rate;
336 struct i2c_msg *msg;
337 unsigned int msg_num;
338 unsigned int msg_id;
339 struct stm32f7_i2c_msg f7_msg;
340 struct stm32f7_i2c_setup setup;
341 struct stm32f7_i2c_timings timing;
342 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
343 struct i2c_client *slave_running;
344 struct stm32f7_i2c_regs backup_regs;
345 u32 slave_dir;
346 bool master_mode;
347 struct stm32_i2c_dma *dma;
348 bool use_dma;
349 struct regmap *regmap;
350 u32 fmp_sreg;
351 u32 fmp_creg;
352 u32 fmp_mask;
353 bool wakeup_src;
354 bool smbus_mode;
355 struct i2c_client *host_notify_client;
356 bool analog_filter;
357 u32 dnf_dt;
358 u32 dnf;
359 struct stm32f7_i2c_alert *alert;
360 };
361
362 /*
363 * All these values are coming from I2C Specification, Version 6.0, 4th of
364 * April 2014.
365 *
366 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
367 * and Fast-mode Plus I2C-bus devices
368 */
369 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
370 {
371 .rate = I2C_MAX_STANDARD_MODE_FREQ,
372 .fall_max = 300,
373 .rise_max = 1000,
374 .hddat_min = 0,
375 .vddat_max = 3450,
376 .sudat_min = 250,
377 .l_min = 4700,
378 .h_min = 4000,
379 },
380 {
381 .rate = I2C_MAX_FAST_MODE_FREQ,
382 .fall_max = 300,
383 .rise_max = 300,
384 .hddat_min = 0,
385 .vddat_max = 900,
386 .sudat_min = 100,
387 .l_min = 1300,
388 .h_min = 600,
389 },
390 {
391 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
392 .fall_max = 100,
393 .rise_max = 120,
394 .hddat_min = 0,
395 .vddat_max = 450,
396 .sudat_min = 50,
397 .l_min = 500,
398 .h_min = 260,
399 },
400 };
401
402 static const struct stm32f7_i2c_setup stm32f7_setup = {
403 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
404 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
405 };
406
407 static const struct stm32f7_i2c_setup stm32mp15_setup = {
408 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
409 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
410 .fmp_clr_offset = 0x40,
411 };
412
stm32f7_i2c_set_bits(void __iomem * reg,u32 mask)413 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
414 {
415 writel_relaxed(readl_relaxed(reg) | mask, reg);
416 }
417
stm32f7_i2c_clr_bits(void __iomem * reg,u32 mask)418 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
419 {
420 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
421 }
422
stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev * i2c_dev,u32 mask)423 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
424 {
425 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
426 }
427
stm32f7_get_specs(u32 rate)428 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
429 {
430 int i;
431
432 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
433 if (rate <= stm32f7_i2c_specs[i].rate)
434 return &stm32f7_i2c_specs[i];
435
436 return ERR_PTR(-EINVAL);
437 }
438
439 #define RATE_MIN(rate) ((rate) * 8 / 10)
stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup,struct stm32f7_i2c_timings * output)440 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
441 struct stm32f7_i2c_setup *setup,
442 struct stm32f7_i2c_timings *output)
443 {
444 struct stm32f7_i2c_spec *specs;
445 u32 p_prev = STM32F7_PRESC_MAX;
446 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
447 setup->clock_src);
448 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
449 setup->speed_freq);
450 u32 clk_error_prev = i2cbus;
451 u32 tsync;
452 u32 af_delay_min, af_delay_max;
453 u32 dnf_delay;
454 u32 clk_min, clk_max;
455 int sdadel_min, sdadel_max;
456 int scldel_min;
457 struct stm32f7_i2c_timings *v, *_v, *s;
458 struct list_head solutions;
459 u16 p, l, a, h;
460 int ret = 0;
461
462 specs = stm32f7_get_specs(setup->speed_freq);
463 if (specs == ERR_PTR(-EINVAL)) {
464 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
465 setup->speed_freq);
466 return -EINVAL;
467 }
468
469 if ((setup->rise_time > specs->rise_max) ||
470 (setup->fall_time > specs->fall_max)) {
471 dev_err(i2c_dev->dev,
472 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
473 setup->rise_time, specs->rise_max,
474 setup->fall_time, specs->fall_max);
475 return -EINVAL;
476 }
477
478 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
479 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
480 dev_err(i2c_dev->dev,
481 "DNF out of bound %d/%d\n",
482 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
483 return -EINVAL;
484 }
485
486 /* Analog and Digital Filters */
487 af_delay_min =
488 (i2c_dev->analog_filter ?
489 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
490 af_delay_max =
491 (i2c_dev->analog_filter ?
492 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
493 dnf_delay = i2c_dev->dnf * i2cclk;
494
495 sdadel_min = specs->hddat_min + setup->fall_time -
496 af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
497
498 sdadel_max = specs->vddat_max - setup->rise_time -
499 af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
500
501 scldel_min = setup->rise_time + specs->sudat_min;
502
503 if (sdadel_min < 0)
504 sdadel_min = 0;
505 if (sdadel_max < 0)
506 sdadel_max = 0;
507
508 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
509 sdadel_min, sdadel_max, scldel_min);
510
511 INIT_LIST_HEAD(&solutions);
512 /* Compute possible values for PRESC, SCLDEL and SDADEL */
513 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
514 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
515 u32 scldel = (l + 1) * (p + 1) * i2cclk;
516
517 if (scldel < scldel_min)
518 continue;
519
520 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
521 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
522
523 if (((sdadel >= sdadel_min) &&
524 (sdadel <= sdadel_max)) &&
525 (p != p_prev)) {
526 v = kmalloc(sizeof(*v), GFP_KERNEL);
527 if (!v) {
528 ret = -ENOMEM;
529 goto exit;
530 }
531
532 v->presc = p;
533 v->scldel = l;
534 v->sdadel = a;
535 p_prev = p;
536
537 list_add_tail(&v->node,
538 &solutions);
539 break;
540 }
541 }
542
543 if (p_prev == p)
544 break;
545 }
546 }
547
548 if (list_empty(&solutions)) {
549 dev_err(i2c_dev->dev, "no Prescaler solution\n");
550 ret = -EPERM;
551 goto exit;
552 }
553
554 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
555 s = NULL;
556 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
557 clk_min = NSEC_PER_SEC / setup->speed_freq;
558
559 /*
560 * Among Prescaler possibilities discovered above figures out SCL Low
561 * and High Period. Provided:
562 * - SCL Low Period has to be higher than SCL Clock Low Period
563 * defined by I2C Specification. I2C Clock has to be lower than
564 * (SCL Low Period - Analog/Digital filters) / 4.
565 * - SCL High Period has to be lower than SCL Clock High Period
566 * defined by I2C Specification
567 * - I2C Clock has to be lower than SCL High Period
568 */
569 list_for_each_entry(v, &solutions, node) {
570 u32 prescaler = (v->presc + 1) * i2cclk;
571
572 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
573 u32 tscl_l = (l + 1) * prescaler + tsync;
574
575 if ((tscl_l < specs->l_min) ||
576 (i2cclk >=
577 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
578 continue;
579 }
580
581 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
582 u32 tscl_h = (h + 1) * prescaler + tsync;
583 u32 tscl = tscl_l + tscl_h +
584 setup->rise_time + setup->fall_time;
585
586 if ((tscl >= clk_min) && (tscl <= clk_max) &&
587 (tscl_h >= specs->h_min) &&
588 (i2cclk < tscl_h)) {
589 int clk_error = tscl - i2cbus;
590
591 if (clk_error < 0)
592 clk_error = -clk_error;
593
594 if (clk_error < clk_error_prev) {
595 clk_error_prev = clk_error;
596 v->scll = l;
597 v->sclh = h;
598 s = v;
599 }
600 }
601 }
602 }
603 }
604
605 if (!s) {
606 dev_err(i2c_dev->dev, "no solution at all\n");
607 ret = -EPERM;
608 goto exit;
609 }
610
611 output->presc = s->presc;
612 output->scldel = s->scldel;
613 output->sdadel = s->sdadel;
614 output->scll = s->scll;
615 output->sclh = s->sclh;
616
617 dev_dbg(i2c_dev->dev,
618 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
619 output->presc,
620 output->scldel, output->sdadel,
621 output->scll, output->sclh);
622
623 exit:
624 /* Release list and memory */
625 list_for_each_entry_safe(v, _v, &solutions, node) {
626 list_del(&v->node);
627 kfree(v);
628 }
629
630 return ret;
631 }
632
stm32f7_get_lower_rate(u32 rate)633 static u32 stm32f7_get_lower_rate(u32 rate)
634 {
635 int i = ARRAY_SIZE(stm32f7_i2c_specs);
636
637 while (--i)
638 if (stm32f7_i2c_specs[i].rate < rate)
639 break;
640
641 return stm32f7_i2c_specs[i].rate;
642 }
643
stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup)644 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
645 struct stm32f7_i2c_setup *setup)
646 {
647 struct i2c_timings timings, *t = &timings;
648 int ret = 0;
649
650 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
651 t->scl_rise_ns = i2c_dev->setup.rise_time;
652 t->scl_fall_ns = i2c_dev->setup.fall_time;
653
654 i2c_parse_fw_timings(i2c_dev->dev, t, false);
655
656 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
657 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
658 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
659 return -EINVAL;
660 }
661
662 setup->speed_freq = t->bus_freq_hz;
663 i2c_dev->setup.rise_time = t->scl_rise_ns;
664 i2c_dev->setup.fall_time = t->scl_fall_ns;
665 i2c_dev->dnf_dt = t->digital_filter_width_ns;
666 setup->clock_src = clk_get_rate(i2c_dev->clk);
667
668 if (!setup->clock_src) {
669 dev_err(i2c_dev->dev, "clock rate is 0\n");
670 return -EINVAL;
671 }
672
673 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
674 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
675
676 do {
677 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
678 &i2c_dev->timing);
679 if (ret) {
680 dev_err(i2c_dev->dev,
681 "failed to compute I2C timings.\n");
682 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
683 break;
684 setup->speed_freq =
685 stm32f7_get_lower_rate(setup->speed_freq);
686 dev_warn(i2c_dev->dev,
687 "downgrade I2C Speed Freq to (%i)\n",
688 setup->speed_freq);
689 }
690 } while (ret);
691
692 if (ret) {
693 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
694 return ret;
695 }
696
697 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
698 "i2c-analog-filter");
699
700 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
701 setup->speed_freq, setup->clock_src);
702 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
703 setup->rise_time, setup->fall_time);
704 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
705 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf);
706
707 i2c_dev->bus_rate = setup->speed_freq;
708
709 return 0;
710 }
711
stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev * i2c_dev)712 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
713 {
714 void __iomem *base = i2c_dev->base;
715 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
716
717 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
718 }
719
stm32f7_i2c_dma_callback(void * arg)720 static void stm32f7_i2c_dma_callback(void *arg)
721 {
722 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
723 struct stm32_i2c_dma *dma = i2c_dev->dma;
724 struct device *dev = dma->chan_using->device->dev;
725
726 stm32f7_i2c_disable_dma_req(i2c_dev);
727 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
728 complete(&dma->dma_complete);
729 }
730
stm32f7_i2c_hw_config(struct stm32f7_i2c_dev * i2c_dev)731 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
732 {
733 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
734 u32 timing = 0;
735
736 /* Timing settings */
737 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
738 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
739 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
740 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
741 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
742 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
743
744 /* Configure the Analog Filter */
745 if (i2c_dev->analog_filter)
746 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
747 STM32F7_I2C_CR1_ANFOFF);
748 else
749 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
750 STM32F7_I2C_CR1_ANFOFF);
751
752 /* Program the Digital Filter */
753 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
754 STM32F7_I2C_CR1_DNF_MASK);
755 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
756 STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
757
758 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
759 STM32F7_I2C_CR1_PE);
760 }
761
stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev * i2c_dev)762 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
763 {
764 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
765 void __iomem *base = i2c_dev->base;
766
767 if (f7_msg->count) {
768 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
769 f7_msg->count--;
770 }
771 }
772
stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev * i2c_dev)773 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
774 {
775 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
776 void __iomem *base = i2c_dev->base;
777
778 if (f7_msg->count) {
779 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
780 f7_msg->count--;
781 } else {
782 /* Flush RX buffer has no data is expected */
783 readb_relaxed(base + STM32F7_I2C_RXDR);
784 }
785 }
786
stm32f7_i2c_reload(struct stm32f7_i2c_dev * i2c_dev)787 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
788 {
789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
790 u32 cr2;
791
792 if (i2c_dev->use_dma)
793 f7_msg->count -= STM32F7_I2C_MAX_LEN;
794
795 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
796
797 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
798 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
799 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
800 } else {
801 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
802 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
803 }
804
805 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
806 }
807
stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev * i2c_dev)808 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
809 {
810 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
811 u32 cr2;
812 u8 *val;
813
814 /*
815 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
816 * data received inform us how many data will follow.
817 */
818 stm32f7_i2c_read_rx_data(i2c_dev);
819
820 /*
821 * Update NBYTES with the value read to continue the transfer
822 */
823 val = f7_msg->buf - sizeof(u8);
824 f7_msg->count = *val;
825 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
826 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
827 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
828 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
829 }
830
stm32f7_i2c_release_bus(struct i2c_adapter * i2c_adap)831 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
832 {
833 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
834
835 dev_info(i2c_dev->dev, "Trying to recover bus\n");
836
837 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
838 STM32F7_I2C_CR1_PE);
839
840 stm32f7_i2c_hw_config(i2c_dev);
841
842 return 0;
843 }
844
stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev * i2c_dev)845 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
846 {
847 u32 status;
848 int ret;
849
850 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
851 status,
852 !(status & STM32F7_I2C_ISR_BUSY),
853 10, 1000);
854 if (!ret)
855 return 0;
856
857 dev_info(i2c_dev->dev, "bus busy\n");
858
859 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
860 if (ret) {
861 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
862 return ret;
863 }
864
865 return -EBUSY;
866 }
867
stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,struct i2c_msg * msg)868 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
869 struct i2c_msg *msg)
870 {
871 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
872 void __iomem *base = i2c_dev->base;
873 u32 cr1, cr2;
874 int ret;
875
876 f7_msg->addr = msg->addr;
877 f7_msg->buf = msg->buf;
878 f7_msg->count = msg->len;
879 f7_msg->result = 0;
880 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
881
882 reinit_completion(&i2c_dev->complete);
883
884 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
885 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
886
887 /* Set transfer direction */
888 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
889 if (msg->flags & I2C_M_RD)
890 cr2 |= STM32F7_I2C_CR2_RD_WRN;
891
892 /* Set slave address */
893 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
894 if (msg->flags & I2C_M_TEN) {
895 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
896 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
897 cr2 |= STM32F7_I2C_CR2_ADD10;
898 } else {
899 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
900 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
901 }
902
903 /* Set nb bytes to transfer and reload if needed */
904 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
905 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
906 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
907 cr2 |= STM32F7_I2C_CR2_RELOAD;
908 } else {
909 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
910 }
911
912 /* Enable NACK, STOP, error and transfer complete interrupts */
913 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
914 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
915
916 /* Clear DMA req and TX/RX interrupt */
917 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
918 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
919
920 /* Configure DMA or enable RX/TX interrupt */
921 i2c_dev->use_dma = false;
922 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
923 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
924 msg->flags & I2C_M_RD,
925 f7_msg->count, f7_msg->buf,
926 stm32f7_i2c_dma_callback,
927 i2c_dev);
928 if (!ret)
929 i2c_dev->use_dma = true;
930 else
931 dev_warn(i2c_dev->dev, "can't use DMA\n");
932 }
933
934 if (!i2c_dev->use_dma) {
935 if (msg->flags & I2C_M_RD)
936 cr1 |= STM32F7_I2C_CR1_RXIE;
937 else
938 cr1 |= STM32F7_I2C_CR1_TXIE;
939 } else {
940 if (msg->flags & I2C_M_RD)
941 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
942 else
943 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
944 }
945
946 /* Configure Start/Repeated Start */
947 cr2 |= STM32F7_I2C_CR2_START;
948
949 i2c_dev->master_mode = true;
950
951 /* Write configurations registers */
952 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
953 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
954 }
955
stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,unsigned short flags,u8 command,union i2c_smbus_data * data)956 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
957 unsigned short flags, u8 command,
958 union i2c_smbus_data *data)
959 {
960 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
961 struct device *dev = i2c_dev->dev;
962 void __iomem *base = i2c_dev->base;
963 u32 cr1, cr2;
964 int i, ret;
965
966 f7_msg->result = 0;
967 reinit_completion(&i2c_dev->complete);
968
969 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
970 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
971
972 /* Set transfer direction */
973 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
974 if (f7_msg->read_write)
975 cr2 |= STM32F7_I2C_CR2_RD_WRN;
976
977 /* Set slave address */
978 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
979 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
980
981 f7_msg->smbus_buf[0] = command;
982 switch (f7_msg->size) {
983 case I2C_SMBUS_QUICK:
984 f7_msg->stop = true;
985 f7_msg->count = 0;
986 break;
987 case I2C_SMBUS_BYTE:
988 f7_msg->stop = true;
989 f7_msg->count = 1;
990 break;
991 case I2C_SMBUS_BYTE_DATA:
992 if (f7_msg->read_write) {
993 f7_msg->stop = false;
994 f7_msg->count = 1;
995 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
996 } else {
997 f7_msg->stop = true;
998 f7_msg->count = 2;
999 f7_msg->smbus_buf[1] = data->byte;
1000 }
1001 break;
1002 case I2C_SMBUS_WORD_DATA:
1003 if (f7_msg->read_write) {
1004 f7_msg->stop = false;
1005 f7_msg->count = 1;
1006 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1007 } else {
1008 f7_msg->stop = true;
1009 f7_msg->count = 3;
1010 f7_msg->smbus_buf[1] = data->word & 0xff;
1011 f7_msg->smbus_buf[2] = data->word >> 8;
1012 }
1013 break;
1014 case I2C_SMBUS_BLOCK_DATA:
1015 if (f7_msg->read_write) {
1016 f7_msg->stop = false;
1017 f7_msg->count = 1;
1018 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1019 } else {
1020 f7_msg->stop = true;
1021 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1022 !data->block[0]) {
1023 dev_err(dev, "Invalid block write size %d\n",
1024 data->block[0]);
1025 return -EINVAL;
1026 }
1027 f7_msg->count = data->block[0] + 2;
1028 for (i = 1; i < f7_msg->count; i++)
1029 f7_msg->smbus_buf[i] = data->block[i - 1];
1030 }
1031 break;
1032 case I2C_SMBUS_PROC_CALL:
1033 f7_msg->stop = false;
1034 f7_msg->count = 3;
1035 f7_msg->smbus_buf[1] = data->word & 0xff;
1036 f7_msg->smbus_buf[2] = data->word >> 8;
1037 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1038 f7_msg->read_write = I2C_SMBUS_READ;
1039 break;
1040 case I2C_SMBUS_BLOCK_PROC_CALL:
1041 f7_msg->stop = false;
1042 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1043 dev_err(dev, "Invalid block write size %d\n",
1044 data->block[0]);
1045 return -EINVAL;
1046 }
1047 f7_msg->count = data->block[0] + 2;
1048 for (i = 1; i < f7_msg->count; i++)
1049 f7_msg->smbus_buf[i] = data->block[i - 1];
1050 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1051 f7_msg->read_write = I2C_SMBUS_READ;
1052 break;
1053 case I2C_SMBUS_I2C_BLOCK_DATA:
1054 /* Rely on emulated i2c transfer (through master_xfer) */
1055 return -EOPNOTSUPP;
1056 default:
1057 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1058 return -EOPNOTSUPP;
1059 }
1060
1061 f7_msg->buf = f7_msg->smbus_buf;
1062
1063 /* Configure PEC */
1064 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1065 cr1 |= STM32F7_I2C_CR1_PECEN;
1066 if (!f7_msg->read_write) {
1067 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1068 f7_msg->count++;
1069 }
1070 } else {
1071 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1072 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1073 }
1074
1075 /* Set number of bytes to be transferred */
1076 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1077 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1078
1079 /* Enable NACK, STOP, error and transfer complete interrupts */
1080 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1081 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1082
1083 /* Clear DMA req and TX/RX interrupt */
1084 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1085 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1086
1087 /* Configure DMA or enable RX/TX interrupt */
1088 i2c_dev->use_dma = false;
1089 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1090 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1091 cr2 & STM32F7_I2C_CR2_RD_WRN,
1092 f7_msg->count, f7_msg->buf,
1093 stm32f7_i2c_dma_callback,
1094 i2c_dev);
1095 if (!ret)
1096 i2c_dev->use_dma = true;
1097 else
1098 dev_warn(i2c_dev->dev, "can't use DMA\n");
1099 }
1100
1101 if (!i2c_dev->use_dma) {
1102 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1103 cr1 |= STM32F7_I2C_CR1_RXIE;
1104 else
1105 cr1 |= STM32F7_I2C_CR1_TXIE;
1106 } else {
1107 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1108 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1109 else
1110 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1111 }
1112
1113 /* Set Start bit */
1114 cr2 |= STM32F7_I2C_CR2_START;
1115
1116 i2c_dev->master_mode = true;
1117
1118 /* Write configurations registers */
1119 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1120 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1121
1122 return 0;
1123 }
1124
stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev * i2c_dev)1125 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1126 {
1127 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1128 void __iomem *base = i2c_dev->base;
1129 u32 cr1, cr2;
1130 int ret;
1131
1132 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1133 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1134
1135 /* Set transfer direction */
1136 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1137
1138 switch (f7_msg->size) {
1139 case I2C_SMBUS_BYTE_DATA:
1140 f7_msg->count = 1;
1141 break;
1142 case I2C_SMBUS_WORD_DATA:
1143 case I2C_SMBUS_PROC_CALL:
1144 f7_msg->count = 2;
1145 break;
1146 case I2C_SMBUS_BLOCK_DATA:
1147 case I2C_SMBUS_BLOCK_PROC_CALL:
1148 f7_msg->count = 1;
1149 cr2 |= STM32F7_I2C_CR2_RELOAD;
1150 break;
1151 }
1152
1153 f7_msg->buf = f7_msg->smbus_buf;
1154 f7_msg->stop = true;
1155
1156 /* Add one byte for PEC if needed */
1157 if (cr1 & STM32F7_I2C_CR1_PECEN) {
1158 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1159 f7_msg->count++;
1160 }
1161
1162 /* Set number of bytes to be transferred */
1163 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1164 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1165
1166 /*
1167 * Configure RX/TX interrupt:
1168 */
1169 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1170 cr1 |= STM32F7_I2C_CR1_RXIE;
1171
1172 /*
1173 * Configure DMA or enable RX/TX interrupt:
1174 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1175 * dma as we don't know in advance how many data will be received
1176 */
1177 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1178 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1179
1180 i2c_dev->use_dma = false;
1181 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1182 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1183 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1184 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1185 cr2 & STM32F7_I2C_CR2_RD_WRN,
1186 f7_msg->count, f7_msg->buf,
1187 stm32f7_i2c_dma_callback,
1188 i2c_dev);
1189
1190 if (!ret)
1191 i2c_dev->use_dma = true;
1192 else
1193 dev_warn(i2c_dev->dev, "can't use DMA\n");
1194 }
1195
1196 if (!i2c_dev->use_dma)
1197 cr1 |= STM32F7_I2C_CR1_RXIE;
1198 else
1199 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1200
1201 /* Configure Repeated Start */
1202 cr2 |= STM32F7_I2C_CR2_START;
1203
1204 /* Write configurations registers */
1205 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1206 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1207 }
1208
stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev * i2c_dev)1209 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1210 {
1211 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1212 u8 count, internal_pec, received_pec;
1213
1214 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1215
1216 switch (f7_msg->size) {
1217 case I2C_SMBUS_BYTE:
1218 case I2C_SMBUS_BYTE_DATA:
1219 received_pec = f7_msg->smbus_buf[1];
1220 break;
1221 case I2C_SMBUS_WORD_DATA:
1222 case I2C_SMBUS_PROC_CALL:
1223 received_pec = f7_msg->smbus_buf[2];
1224 break;
1225 case I2C_SMBUS_BLOCK_DATA:
1226 case I2C_SMBUS_BLOCK_PROC_CALL:
1227 count = f7_msg->smbus_buf[0];
1228 received_pec = f7_msg->smbus_buf[count];
1229 break;
1230 default:
1231 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1232 return -EINVAL;
1233 }
1234
1235 if (internal_pec != received_pec) {
1236 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1237 internal_pec, received_pec);
1238 return -EBADMSG;
1239 }
1240
1241 return 0;
1242 }
1243
stm32f7_i2c_is_addr_match(struct i2c_client * slave,u32 addcode)1244 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1245 {
1246 u32 addr;
1247
1248 if (!slave)
1249 return false;
1250
1251 if (slave->flags & I2C_CLIENT_TEN) {
1252 /*
1253 * For 10-bit addr, addcode = 11110XY with
1254 * X = Bit 9 of slave address
1255 * Y = Bit 8 of slave address
1256 */
1257 addr = slave->addr >> 8;
1258 addr |= 0x78;
1259 if (addr == addcode)
1260 return true;
1261 } else {
1262 addr = slave->addr & 0x7f;
1263 if (addr == addcode)
1264 return true;
1265 }
1266
1267 return false;
1268 }
1269
stm32f7_i2c_slave_start(struct stm32f7_i2c_dev * i2c_dev)1270 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1271 {
1272 struct i2c_client *slave = i2c_dev->slave_running;
1273 void __iomem *base = i2c_dev->base;
1274 u32 mask;
1275 u8 value = 0;
1276
1277 if (i2c_dev->slave_dir) {
1278 /* Notify i2c slave that new read transfer is starting */
1279 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1280
1281 /*
1282 * Disable slave TX config in case of I2C combined message
1283 * (I2C Write followed by I2C Read)
1284 */
1285 mask = STM32F7_I2C_CR2_RELOAD;
1286 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1287 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1288 STM32F7_I2C_CR1_TCIE;
1289 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1290
1291 /* Enable TX empty, STOP, NACK interrupts */
1292 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1293 STM32F7_I2C_CR1_TXIE;
1294 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1295
1296 /* Write 1st data byte */
1297 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1298 } else {
1299 /* Notify i2c slave that new write transfer is starting */
1300 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1301
1302 /* Set reload mode to be able to ACK/NACK each received byte */
1303 mask = STM32F7_I2C_CR2_RELOAD;
1304 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1305
1306 /*
1307 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1308 * Set Slave Byte Control to be able to ACK/NACK each data
1309 * byte received
1310 */
1311 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1312 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1313 STM32F7_I2C_CR1_TCIE;
1314 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1315 }
1316 }
1317
stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev * i2c_dev)1318 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1319 {
1320 void __iomem *base = i2c_dev->base;
1321 u32 isr, addcode, dir, mask;
1322 int i;
1323
1324 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1325 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1326 dir = isr & STM32F7_I2C_ISR_DIR;
1327
1328 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1329 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1330 i2c_dev->slave_running = i2c_dev->slave[i];
1331 i2c_dev->slave_dir = dir;
1332
1333 /* Start I2C slave processing */
1334 stm32f7_i2c_slave_start(i2c_dev);
1335
1336 /* Clear ADDR flag */
1337 mask = STM32F7_I2C_ICR_ADDRCF;
1338 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1339 break;
1340 }
1341 }
1342 }
1343
stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1344 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1345 struct i2c_client *slave, int *id)
1346 {
1347 int i;
1348
1349 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1350 if (i2c_dev->slave[i] == slave) {
1351 *id = i;
1352 return 0;
1353 }
1354 }
1355
1356 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1357
1358 return -ENODEV;
1359 }
1360
stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1361 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1362 struct i2c_client *slave, int *id)
1363 {
1364 struct device *dev = i2c_dev->dev;
1365 int i;
1366
1367 /*
1368 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1369 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1370 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1371 */
1372 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1373 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1374 goto fail;
1375 *id = STM32F7_SLAVE_HOSTNOTIFY;
1376 return 0;
1377 }
1378
1379 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1380 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1381 (slave->flags & I2C_CLIENT_TEN))
1382 continue;
1383 if (!i2c_dev->slave[i]) {
1384 *id = i;
1385 return 0;
1386 }
1387 }
1388
1389 fail:
1390 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1391
1392 return -EINVAL;
1393 }
1394
stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev * i2c_dev)1395 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1396 {
1397 int i;
1398
1399 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1400 if (i2c_dev->slave[i])
1401 return true;
1402 }
1403
1404 return false;
1405 }
1406
stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev * i2c_dev)1407 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1408 {
1409 int i, busy;
1410
1411 busy = 0;
1412 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1413 if (i2c_dev->slave[i])
1414 busy++;
1415 }
1416
1417 return i == busy;
1418 }
1419
stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev * i2c_dev)1420 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1421 {
1422 void __iomem *base = i2c_dev->base;
1423 u32 cr2, status, mask;
1424 u8 val;
1425 int ret;
1426
1427 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1428
1429 /* Slave transmitter mode */
1430 if (status & STM32F7_I2C_ISR_TXIS) {
1431 i2c_slave_event(i2c_dev->slave_running,
1432 I2C_SLAVE_READ_PROCESSED,
1433 &val);
1434
1435 /* Write data byte */
1436 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1437 }
1438
1439 /* Transfer Complete Reload for Slave receiver mode */
1440 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1441 /*
1442 * Read data byte then set NBYTES to receive next byte or NACK
1443 * the current received byte
1444 */
1445 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1446 ret = i2c_slave_event(i2c_dev->slave_running,
1447 I2C_SLAVE_WRITE_RECEIVED,
1448 &val);
1449 if (!ret) {
1450 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1451 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1452 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1453 } else {
1454 mask = STM32F7_I2C_CR2_NACK;
1455 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1456 }
1457 }
1458
1459 /* NACK received */
1460 if (status & STM32F7_I2C_ISR_NACKF) {
1461 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1462 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1463 }
1464
1465 /* STOP received */
1466 if (status & STM32F7_I2C_ISR_STOPF) {
1467 /* Disable interrupts */
1468 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1469
1470 if (i2c_dev->slave_dir) {
1471 /*
1472 * Flush TX buffer in order to not used the byte in
1473 * TXDR for the next transfer
1474 */
1475 mask = STM32F7_I2C_ISR_TXE;
1476 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1477 }
1478
1479 /* Clear STOP flag */
1480 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1481
1482 /* Notify i2c slave that a STOP flag has been detected */
1483 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1484
1485 i2c_dev->slave_running = NULL;
1486 }
1487
1488 /* Address match received */
1489 if (status & STM32F7_I2C_ISR_ADDR)
1490 stm32f7_i2c_slave_addr(i2c_dev);
1491
1492 return IRQ_HANDLED;
1493 }
1494
stm32f7_i2c_isr_event(int irq,void * data)1495 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1496 {
1497 struct stm32f7_i2c_dev *i2c_dev = data;
1498 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1499 struct stm32_i2c_dma *dma = i2c_dev->dma;
1500 void __iomem *base = i2c_dev->base;
1501 u32 status, mask;
1502 int ret = IRQ_HANDLED;
1503
1504 /* Check if the interrupt if for a slave device */
1505 if (!i2c_dev->master_mode) {
1506 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1507 return ret;
1508 }
1509
1510 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1511
1512 /* Tx empty */
1513 if (status & STM32F7_I2C_ISR_TXIS)
1514 stm32f7_i2c_write_tx_data(i2c_dev);
1515
1516 /* RX not empty */
1517 if (status & STM32F7_I2C_ISR_RXNE)
1518 stm32f7_i2c_read_rx_data(i2c_dev);
1519
1520 /* NACK received */
1521 if (status & STM32F7_I2C_ISR_NACKF) {
1522 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1523 __func__, f7_msg->addr);
1524 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1525 if (i2c_dev->use_dma) {
1526 stm32f7_i2c_disable_dma_req(i2c_dev);
1527 dmaengine_terminate_all(dma->chan_using);
1528 }
1529 f7_msg->result = -ENXIO;
1530 }
1531
1532 /* STOP detection flag */
1533 if (status & STM32F7_I2C_ISR_STOPF) {
1534 /* Disable interrupts */
1535 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1536 mask = STM32F7_I2C_XFER_IRQ_MASK;
1537 else
1538 mask = STM32F7_I2C_ALL_IRQ_MASK;
1539 stm32f7_i2c_disable_irq(i2c_dev, mask);
1540
1541 /* Clear STOP flag */
1542 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1543
1544 if (i2c_dev->use_dma && !f7_msg->result) {
1545 ret = IRQ_WAKE_THREAD;
1546 } else {
1547 i2c_dev->master_mode = false;
1548 complete(&i2c_dev->complete);
1549 }
1550 }
1551
1552 /* Transfer complete */
1553 if (status & STM32F7_I2C_ISR_TC) {
1554 if (f7_msg->stop) {
1555 mask = STM32F7_I2C_CR2_STOP;
1556 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1557 } else if (i2c_dev->use_dma && !f7_msg->result) {
1558 ret = IRQ_WAKE_THREAD;
1559 } else if (f7_msg->smbus) {
1560 stm32f7_i2c_smbus_rep_start(i2c_dev);
1561 } else {
1562 i2c_dev->msg_id++;
1563 i2c_dev->msg++;
1564 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1565 }
1566 }
1567
1568 if (status & STM32F7_I2C_ISR_TCR) {
1569 if (f7_msg->smbus)
1570 stm32f7_i2c_smbus_reload(i2c_dev);
1571 else
1572 stm32f7_i2c_reload(i2c_dev);
1573 }
1574
1575 return ret;
1576 }
1577
stm32f7_i2c_isr_event_thread(int irq,void * data)1578 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1579 {
1580 struct stm32f7_i2c_dev *i2c_dev = data;
1581 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1582 struct stm32_i2c_dma *dma = i2c_dev->dma;
1583 u32 status;
1584 int ret;
1585
1586 /*
1587 * Wait for dma transfer completion before sending next message or
1588 * notity the end of xfer to the client
1589 */
1590 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1591 if (!ret) {
1592 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1593 stm32f7_i2c_disable_dma_req(i2c_dev);
1594 dmaengine_terminate_all(dma->chan_using);
1595 f7_msg->result = -ETIMEDOUT;
1596 }
1597
1598 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1599
1600 if (status & STM32F7_I2C_ISR_TC) {
1601 if (f7_msg->smbus) {
1602 stm32f7_i2c_smbus_rep_start(i2c_dev);
1603 } else {
1604 i2c_dev->msg_id++;
1605 i2c_dev->msg++;
1606 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1607 }
1608 } else {
1609 i2c_dev->master_mode = false;
1610 complete(&i2c_dev->complete);
1611 }
1612
1613 return IRQ_HANDLED;
1614 }
1615
stm32f7_i2c_isr_error(int irq,void * data)1616 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1617 {
1618 struct stm32f7_i2c_dev *i2c_dev = data;
1619 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1620 void __iomem *base = i2c_dev->base;
1621 struct device *dev = i2c_dev->dev;
1622 struct stm32_i2c_dma *dma = i2c_dev->dma;
1623 u32 status;
1624
1625 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1626
1627 /* Bus error */
1628 if (status & STM32F7_I2C_ISR_BERR) {
1629 dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n",
1630 __func__, f7_msg->addr);
1631 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1632 stm32f7_i2c_release_bus(&i2c_dev->adap);
1633 f7_msg->result = -EIO;
1634 }
1635
1636 /* Arbitration loss */
1637 if (status & STM32F7_I2C_ISR_ARLO) {
1638 dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n",
1639 __func__, f7_msg->addr);
1640 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1641 f7_msg->result = -EAGAIN;
1642 }
1643
1644 if (status & STM32F7_I2C_ISR_PECERR) {
1645 dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n",
1646 __func__, f7_msg->addr);
1647 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1648 f7_msg->result = -EINVAL;
1649 }
1650
1651 if (status & STM32F7_I2C_ISR_ALERT) {
1652 dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
1653 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1654 i2c_handle_smbus_alert(i2c_dev->alert->ara);
1655 return IRQ_HANDLED;
1656 }
1657
1658 if (!i2c_dev->slave_running) {
1659 u32 mask;
1660 /* Disable interrupts */
1661 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1662 mask = STM32F7_I2C_XFER_IRQ_MASK;
1663 else
1664 mask = STM32F7_I2C_ALL_IRQ_MASK;
1665 stm32f7_i2c_disable_irq(i2c_dev, mask);
1666 }
1667
1668 /* Disable dma */
1669 if (i2c_dev->use_dma) {
1670 stm32f7_i2c_disable_dma_req(i2c_dev);
1671 dmaengine_terminate_all(dma->chan_using);
1672 }
1673
1674 i2c_dev->master_mode = false;
1675 complete(&i2c_dev->complete);
1676
1677 return IRQ_HANDLED;
1678 }
1679
stm32f7_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1680 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1681 struct i2c_msg msgs[], int num)
1682 {
1683 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1684 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1685 struct stm32_i2c_dma *dma = i2c_dev->dma;
1686 unsigned long time_left;
1687 int ret;
1688
1689 i2c_dev->msg = msgs;
1690 i2c_dev->msg_num = num;
1691 i2c_dev->msg_id = 0;
1692 f7_msg->smbus = false;
1693
1694 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1695 if (ret < 0)
1696 return ret;
1697
1698 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1699 if (ret)
1700 goto pm_free;
1701
1702 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1703
1704 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1705 i2c_dev->adap.timeout);
1706 ret = f7_msg->result;
1707 if (ret) {
1708 /*
1709 * It is possible that some unsent data have already been
1710 * written into TXDR. To avoid sending old data in a
1711 * further transfer, flush TXDR in case of any error
1712 */
1713 writel_relaxed(STM32F7_I2C_ISR_TXE,
1714 i2c_dev->base + STM32F7_I2C_ISR);
1715 goto pm_free;
1716 }
1717
1718 if (!time_left) {
1719 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1720 i2c_dev->msg->addr);
1721 if (i2c_dev->use_dma)
1722 dmaengine_terminate_all(dma->chan_using);
1723 stm32f7_i2c_wait_free_bus(i2c_dev);
1724 ret = -ETIMEDOUT;
1725 }
1726
1727 pm_free:
1728 pm_runtime_mark_last_busy(i2c_dev->dev);
1729 pm_runtime_put_autosuspend(i2c_dev->dev);
1730
1731 return (ret < 0) ? ret : num;
1732 }
1733
stm32f7_i2c_smbus_xfer(struct i2c_adapter * adapter,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)1734 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1735 unsigned short flags, char read_write,
1736 u8 command, int size,
1737 union i2c_smbus_data *data)
1738 {
1739 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1740 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1741 struct stm32_i2c_dma *dma = i2c_dev->dma;
1742 struct device *dev = i2c_dev->dev;
1743 unsigned long timeout;
1744 int i, ret;
1745
1746 f7_msg->addr = addr;
1747 f7_msg->size = size;
1748 f7_msg->read_write = read_write;
1749 f7_msg->smbus = true;
1750
1751 ret = pm_runtime_resume_and_get(dev);
1752 if (ret < 0)
1753 return ret;
1754
1755 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1756 if (ret)
1757 goto pm_free;
1758
1759 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1760 if (ret)
1761 goto pm_free;
1762
1763 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1764 i2c_dev->adap.timeout);
1765 ret = f7_msg->result;
1766 if (ret) {
1767 /*
1768 * It is possible that some unsent data have already been
1769 * written into TXDR. To avoid sending old data in a
1770 * further transfer, flush TXDR in case of any error
1771 */
1772 writel_relaxed(STM32F7_I2C_ISR_TXE,
1773 i2c_dev->base + STM32F7_I2C_ISR);
1774 goto pm_free;
1775 }
1776
1777 if (!timeout) {
1778 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1779 if (i2c_dev->use_dma)
1780 dmaengine_terminate_all(dma->chan_using);
1781 stm32f7_i2c_wait_free_bus(i2c_dev);
1782 ret = -ETIMEDOUT;
1783 goto pm_free;
1784 }
1785
1786 /* Check PEC */
1787 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1788 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1789 if (ret)
1790 goto pm_free;
1791 }
1792
1793 if (read_write && size != I2C_SMBUS_QUICK) {
1794 switch (size) {
1795 case I2C_SMBUS_BYTE:
1796 case I2C_SMBUS_BYTE_DATA:
1797 data->byte = f7_msg->smbus_buf[0];
1798 break;
1799 case I2C_SMBUS_WORD_DATA:
1800 case I2C_SMBUS_PROC_CALL:
1801 data->word = f7_msg->smbus_buf[0] |
1802 (f7_msg->smbus_buf[1] << 8);
1803 break;
1804 case I2C_SMBUS_BLOCK_DATA:
1805 case I2C_SMBUS_BLOCK_PROC_CALL:
1806 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1807 data->block[i] = f7_msg->smbus_buf[i];
1808 break;
1809 default:
1810 dev_err(dev, "Unsupported smbus transaction\n");
1811 ret = -EINVAL;
1812 }
1813 }
1814
1815 pm_free:
1816 pm_runtime_mark_last_busy(dev);
1817 pm_runtime_put_autosuspend(dev);
1818 return ret;
1819 }
1820
stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev * i2c_dev,bool enable)1821 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1822 bool enable)
1823 {
1824 void __iomem *base = i2c_dev->base;
1825 u32 mask = STM32F7_I2C_CR1_WUPEN;
1826
1827 if (!i2c_dev->wakeup_src)
1828 return;
1829
1830 if (enable) {
1831 device_set_wakeup_enable(i2c_dev->dev, true);
1832 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1833 } else {
1834 device_set_wakeup_enable(i2c_dev->dev, false);
1835 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1836 }
1837 }
1838
stm32f7_i2c_reg_slave(struct i2c_client * slave)1839 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1840 {
1841 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1842 void __iomem *base = i2c_dev->base;
1843 struct device *dev = i2c_dev->dev;
1844 u32 oar1, oar2, mask;
1845 int id, ret;
1846
1847 if (slave->flags & I2C_CLIENT_PEC) {
1848 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1849 return -EINVAL;
1850 }
1851
1852 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1853 dev_err(dev, "Too much slave registered\n");
1854 return -EBUSY;
1855 }
1856
1857 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1858 if (ret)
1859 return ret;
1860
1861 ret = pm_runtime_resume_and_get(dev);
1862 if (ret < 0)
1863 return ret;
1864
1865 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1866 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1867
1868 switch (id) {
1869 case 0:
1870 /* Slave SMBus Host */
1871 i2c_dev->slave[id] = slave;
1872 break;
1873
1874 case 1:
1875 /* Configure Own Address 1 */
1876 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1877 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1878 if (slave->flags & I2C_CLIENT_TEN) {
1879 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1880 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1881 } else {
1882 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1883 }
1884 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1885 i2c_dev->slave[id] = slave;
1886 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1887 break;
1888
1889 case 2:
1890 /* Configure Own Address 2 */
1891 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1892 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1893 if (slave->flags & I2C_CLIENT_TEN) {
1894 ret = -EOPNOTSUPP;
1895 goto pm_free;
1896 }
1897
1898 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1899 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1900 i2c_dev->slave[id] = slave;
1901 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1902 break;
1903
1904 default:
1905 dev_err(dev, "I2C slave id not supported\n");
1906 ret = -ENODEV;
1907 goto pm_free;
1908 }
1909
1910 /* Enable ACK */
1911 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1912
1913 /* Enable Address match interrupt, error interrupt and enable I2C */
1914 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1915 STM32F7_I2C_CR1_PE;
1916 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1917
1918 ret = 0;
1919 pm_free:
1920 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1921 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1922
1923 pm_runtime_mark_last_busy(dev);
1924 pm_runtime_put_autosuspend(dev);
1925
1926 return ret;
1927 }
1928
stm32f7_i2c_unreg_slave(struct i2c_client * slave)1929 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1930 {
1931 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1932 void __iomem *base = i2c_dev->base;
1933 u32 mask;
1934 int id, ret;
1935
1936 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1937 if (ret)
1938 return ret;
1939
1940 WARN_ON(!i2c_dev->slave[id]);
1941
1942 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1943 if (ret < 0)
1944 return ret;
1945
1946 if (id == 1) {
1947 mask = STM32F7_I2C_OAR1_OA1EN;
1948 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1949 } else if (id == 2) {
1950 mask = STM32F7_I2C_OAR2_OA2EN;
1951 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1952 }
1953
1954 i2c_dev->slave[id] = NULL;
1955
1956 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1957 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1958 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1959 }
1960
1961 pm_runtime_mark_last_busy(i2c_dev->dev);
1962 pm_runtime_put_autosuspend(i2c_dev->dev);
1963
1964 return 0;
1965 }
1966
stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev * i2c_dev,bool enable)1967 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1968 bool enable)
1969 {
1970 int ret;
1971
1972 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1973 IS_ERR_OR_NULL(i2c_dev->regmap))
1974 /* Optional */
1975 return 0;
1976
1977 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1978 ret = regmap_update_bits(i2c_dev->regmap,
1979 i2c_dev->fmp_sreg,
1980 i2c_dev->fmp_mask,
1981 enable ? i2c_dev->fmp_mask : 0);
1982 else
1983 ret = regmap_write(i2c_dev->regmap,
1984 enable ? i2c_dev->fmp_sreg :
1985 i2c_dev->fmp_creg,
1986 i2c_dev->fmp_mask);
1987
1988 return ret;
1989 }
1990
stm32f7_i2c_setup_fm_plus_bits(struct platform_device * pdev,struct stm32f7_i2c_dev * i2c_dev)1991 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1992 struct stm32f7_i2c_dev *i2c_dev)
1993 {
1994 struct device_node *np = pdev->dev.of_node;
1995 int ret;
1996
1997 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1998 if (IS_ERR(i2c_dev->regmap))
1999 /* Optional */
2000 return 0;
2001
2002 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
2003 &i2c_dev->fmp_sreg);
2004 if (ret)
2005 return ret;
2006
2007 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
2008 i2c_dev->setup.fmp_clr_offset;
2009
2010 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
2011 &i2c_dev->fmp_mask);
2012 }
2013
stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2014 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2015 {
2016 struct i2c_adapter *adap = &i2c_dev->adap;
2017 void __iomem *base = i2c_dev->base;
2018 struct i2c_client *client;
2019
2020 client = i2c_new_slave_host_notify_device(adap);
2021 if (IS_ERR(client))
2022 return PTR_ERR(client);
2023
2024 i2c_dev->host_notify_client = client;
2025
2026 /* Enable SMBus Host address */
2027 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2028
2029 return 0;
2030 }
2031
stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2032 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2033 {
2034 void __iomem *base = i2c_dev->base;
2035
2036 if (i2c_dev->host_notify_client) {
2037 /* Disable SMBus Host address */
2038 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2039 STM32F7_I2C_CR1_SMBHEN);
2040 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2041 }
2042 }
2043
stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2044 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2045 {
2046 struct stm32f7_i2c_alert *alert;
2047 struct i2c_adapter *adap = &i2c_dev->adap;
2048 struct device *dev = i2c_dev->dev;
2049 void __iomem *base = i2c_dev->base;
2050
2051 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
2052 if (!alert)
2053 return -ENOMEM;
2054
2055 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
2056 if (IS_ERR(alert->ara))
2057 return PTR_ERR(alert->ara);
2058
2059 i2c_dev->alert = alert;
2060
2061 /* Enable SMBus Alert */
2062 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2063
2064 return 0;
2065 }
2066
stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2067 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2068 {
2069 struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2070 void __iomem *base = i2c_dev->base;
2071
2072 if (alert) {
2073 /* Disable SMBus Alert */
2074 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2075 STM32F7_I2C_CR1_ALERTEN);
2076 i2c_unregister_device(alert->ara);
2077 }
2078 }
2079
stm32f7_i2c_func(struct i2c_adapter * adap)2080 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2081 {
2082 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2083
2084 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2085 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2086 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2087 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2088 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2089 I2C_FUNC_SMBUS_I2C_BLOCK;
2090
2091 if (i2c_dev->smbus_mode)
2092 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2093
2094 return func;
2095 }
2096
2097 static const struct i2c_algorithm stm32f7_i2c_algo = {
2098 .master_xfer = stm32f7_i2c_xfer,
2099 .smbus_xfer = stm32f7_i2c_smbus_xfer,
2100 .functionality = stm32f7_i2c_func,
2101 .reg_slave = stm32f7_i2c_reg_slave,
2102 .unreg_slave = stm32f7_i2c_unreg_slave,
2103 };
2104
stm32f7_i2c_probe(struct platform_device * pdev)2105 static int stm32f7_i2c_probe(struct platform_device *pdev)
2106 {
2107 struct stm32f7_i2c_dev *i2c_dev;
2108 const struct stm32f7_i2c_setup *setup;
2109 struct resource *res;
2110 struct i2c_adapter *adap;
2111 struct reset_control *rst;
2112 dma_addr_t phy_addr;
2113 int irq_error, irq_event, ret;
2114
2115 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2116 if (!i2c_dev)
2117 return -ENOMEM;
2118
2119 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2120 if (IS_ERR(i2c_dev->base))
2121 return PTR_ERR(i2c_dev->base);
2122 phy_addr = (dma_addr_t)res->start;
2123
2124 irq_event = platform_get_irq(pdev, 0);
2125 if (irq_event <= 0)
2126 return irq_event ? : -ENOENT;
2127
2128 irq_error = platform_get_irq(pdev, 1);
2129 if (irq_error <= 0)
2130 return irq_error ? : -ENOENT;
2131
2132 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2133 "wakeup-source");
2134
2135 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2136 if (IS_ERR(i2c_dev->clk))
2137 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2138 "Failed to get controller clock\n");
2139
2140 ret = clk_prepare_enable(i2c_dev->clk);
2141 if (ret) {
2142 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2143 return ret;
2144 }
2145
2146 rst = devm_reset_control_get(&pdev->dev, NULL);
2147 if (IS_ERR(rst)) {
2148 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2149 "Error: Missing reset ctrl\n");
2150 goto clk_free;
2151 }
2152 reset_control_assert(rst);
2153 udelay(2);
2154 reset_control_deassert(rst);
2155
2156 i2c_dev->dev = &pdev->dev;
2157
2158 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2159 stm32f7_i2c_isr_event,
2160 stm32f7_i2c_isr_event_thread,
2161 IRQF_ONESHOT,
2162 pdev->name, i2c_dev);
2163 if (ret) {
2164 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2165 irq_event);
2166 goto clk_free;
2167 }
2168
2169 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2170 pdev->name, i2c_dev);
2171 if (ret) {
2172 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2173 irq_error);
2174 goto clk_free;
2175 }
2176
2177 setup = of_device_get_match_data(&pdev->dev);
2178 if (!setup) {
2179 dev_err(&pdev->dev, "Can't get device data\n");
2180 ret = -ENODEV;
2181 goto clk_free;
2182 }
2183 i2c_dev->setup = *setup;
2184
2185 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2186 if (ret)
2187 goto clk_free;
2188
2189 /* Setup Fast mode plus if necessary */
2190 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2191 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2192 if (ret)
2193 goto clk_free;
2194 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2195 if (ret)
2196 goto clk_free;
2197 }
2198
2199 adap = &i2c_dev->adap;
2200 i2c_set_adapdata(adap, i2c_dev);
2201 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2202 &res->start);
2203 adap->owner = THIS_MODULE;
2204 adap->timeout = 2 * HZ;
2205 adap->retries = 3;
2206 adap->algo = &stm32f7_i2c_algo;
2207 adap->dev.parent = &pdev->dev;
2208 adap->dev.of_node = pdev->dev.of_node;
2209
2210 init_completion(&i2c_dev->complete);
2211
2212 /* Init DMA config if supported */
2213 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2214 STM32F7_I2C_TXDR,
2215 STM32F7_I2C_RXDR);
2216 if (IS_ERR(i2c_dev->dma)) {
2217 ret = PTR_ERR(i2c_dev->dma);
2218 /* DMA support is optional, only report other errors */
2219 if (ret != -ENODEV)
2220 goto fmp_clear;
2221 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2222 i2c_dev->dma = NULL;
2223 }
2224
2225 if (i2c_dev->wakeup_src) {
2226 device_set_wakeup_capable(i2c_dev->dev, true);
2227
2228 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2229 if (ret) {
2230 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2231 goto clr_wakeup_capable;
2232 }
2233 }
2234
2235 platform_set_drvdata(pdev, i2c_dev);
2236
2237 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2238 STM32F7_AUTOSUSPEND_DELAY);
2239 pm_runtime_use_autosuspend(i2c_dev->dev);
2240 pm_runtime_set_active(i2c_dev->dev);
2241 pm_runtime_enable(i2c_dev->dev);
2242
2243 pm_runtime_get_noresume(&pdev->dev);
2244
2245 stm32f7_i2c_hw_config(i2c_dev);
2246
2247 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2248
2249 ret = i2c_add_adapter(adap);
2250 if (ret)
2251 goto pm_disable;
2252
2253 if (i2c_dev->smbus_mode) {
2254 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2255 if (ret) {
2256 dev_err(i2c_dev->dev,
2257 "failed to enable SMBus Host-Notify protocol (%d)\n",
2258 ret);
2259 goto i2c_adapter_remove;
2260 }
2261 }
2262
2263 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
2264 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2265 if (ret) {
2266 dev_err(i2c_dev->dev,
2267 "failed to enable SMBus alert protocol (%d)\n",
2268 ret);
2269 goto i2c_disable_smbus_host;
2270 }
2271 }
2272
2273 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2274
2275 pm_runtime_mark_last_busy(i2c_dev->dev);
2276 pm_runtime_put_autosuspend(i2c_dev->dev);
2277
2278 return 0;
2279
2280 i2c_disable_smbus_host:
2281 stm32f7_i2c_disable_smbus_host(i2c_dev);
2282
2283 i2c_adapter_remove:
2284 i2c_del_adapter(adap);
2285
2286 pm_disable:
2287 pm_runtime_put_noidle(i2c_dev->dev);
2288 pm_runtime_disable(i2c_dev->dev);
2289 pm_runtime_set_suspended(i2c_dev->dev);
2290 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2291
2292 if (i2c_dev->wakeup_src)
2293 dev_pm_clear_wake_irq(i2c_dev->dev);
2294
2295 clr_wakeup_capable:
2296 if (i2c_dev->wakeup_src)
2297 device_set_wakeup_capable(i2c_dev->dev, false);
2298
2299 if (i2c_dev->dma) {
2300 stm32_i2c_dma_free(i2c_dev->dma);
2301 i2c_dev->dma = NULL;
2302 }
2303
2304 fmp_clear:
2305 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2306
2307 clk_free:
2308 clk_disable_unprepare(i2c_dev->clk);
2309
2310 return ret;
2311 }
2312
stm32f7_i2c_remove(struct platform_device * pdev)2313 static int stm32f7_i2c_remove(struct platform_device *pdev)
2314 {
2315 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2316
2317 stm32f7_i2c_disable_smbus_alert(i2c_dev);
2318 stm32f7_i2c_disable_smbus_host(i2c_dev);
2319
2320 i2c_del_adapter(&i2c_dev->adap);
2321 pm_runtime_get_sync(i2c_dev->dev);
2322
2323 if (i2c_dev->wakeup_src) {
2324 dev_pm_clear_wake_irq(i2c_dev->dev);
2325 /*
2326 * enforce that wakeup is disabled and that the device
2327 * is marked as non wakeup capable
2328 */
2329 device_init_wakeup(i2c_dev->dev, false);
2330 }
2331
2332 pm_runtime_put_noidle(i2c_dev->dev);
2333 pm_runtime_disable(i2c_dev->dev);
2334 pm_runtime_set_suspended(i2c_dev->dev);
2335 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2336
2337 if (i2c_dev->dma) {
2338 stm32_i2c_dma_free(i2c_dev->dma);
2339 i2c_dev->dma = NULL;
2340 }
2341
2342 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2343
2344 clk_disable_unprepare(i2c_dev->clk);
2345
2346 return 0;
2347 }
2348
stm32f7_i2c_runtime_suspend(struct device * dev)2349 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2350 {
2351 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2352
2353 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2354 clk_disable_unprepare(i2c_dev->clk);
2355
2356 return 0;
2357 }
2358
stm32f7_i2c_runtime_resume(struct device * dev)2359 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2360 {
2361 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2362 int ret;
2363
2364 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2365 ret = clk_prepare_enable(i2c_dev->clk);
2366 if (ret) {
2367 dev_err(dev, "failed to prepare_enable clock\n");
2368 return ret;
2369 }
2370 }
2371
2372 return 0;
2373 }
2374
stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev * i2c_dev)2375 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2376 {
2377 int ret;
2378 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2379
2380 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2381 if (ret < 0)
2382 return ret;
2383
2384 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2385 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2386 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2387 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2388 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2389 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2390
2391 pm_runtime_put_sync(i2c_dev->dev);
2392
2393 return ret;
2394 }
2395
stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev * i2c_dev)2396 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2397 {
2398 u32 cr1;
2399 int ret;
2400 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2401
2402 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2403 if (ret < 0)
2404 return ret;
2405
2406 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2407 if (cr1 & STM32F7_I2C_CR1_PE)
2408 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2409 STM32F7_I2C_CR1_PE);
2410
2411 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2412 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2413 i2c_dev->base + STM32F7_I2C_CR1);
2414 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2415 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2416 STM32F7_I2C_CR1_PE);
2417 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2418 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2419 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2420 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2421
2422 pm_runtime_put_sync(i2c_dev->dev);
2423
2424 return ret;
2425 }
2426
stm32f7_i2c_suspend(struct device * dev)2427 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2428 {
2429 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2430 int ret;
2431
2432 i2c_mark_adapter_suspended(&i2c_dev->adap);
2433
2434 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2435 ret = stm32f7_i2c_regs_backup(i2c_dev);
2436 if (ret < 0) {
2437 i2c_mark_adapter_resumed(&i2c_dev->adap);
2438 return ret;
2439 }
2440
2441 pinctrl_pm_select_sleep_state(dev);
2442 pm_runtime_force_suspend(dev);
2443 }
2444
2445 return 0;
2446 }
2447
stm32f7_i2c_resume(struct device * dev)2448 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2449 {
2450 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2451 int ret;
2452
2453 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2454 ret = pm_runtime_force_resume(dev);
2455 if (ret < 0)
2456 return ret;
2457 pinctrl_pm_select_default_state(dev);
2458
2459 ret = stm32f7_i2c_regs_restore(i2c_dev);
2460 if (ret < 0)
2461 return ret;
2462 }
2463
2464 i2c_mark_adapter_resumed(&i2c_dev->adap);
2465
2466 return 0;
2467 }
2468
2469 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2470 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2471 stm32f7_i2c_runtime_resume, NULL)
2472 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2473 };
2474
2475 static const struct of_device_id stm32f7_i2c_match[] = {
2476 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2477 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2478 {},
2479 };
2480 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2481
2482 static struct platform_driver stm32f7_i2c_driver = {
2483 .driver = {
2484 .name = "stm32f7-i2c",
2485 .of_match_table = stm32f7_i2c_match,
2486 .pm = &stm32f7_i2c_pm_ops,
2487 },
2488 .probe = stm32f7_i2c_probe,
2489 .remove = stm32f7_i2c_remove,
2490 };
2491
2492 module_platform_driver(stm32f7_i2c_driver);
2493
2494 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2495 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2496 MODULE_LICENSE("GPL v2");
2497