1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for the ADC present in the Atmel AT91 evaluation boards.
4 *
5 * Copyright 2011 Free Electrons
6 */
7
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/input.h>
14 #include <linux/interrupt.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/wait.h>
24
25 #include <linux/iio/iio.h>
26 #include <linux/iio/buffer.h>
27 #include <linux/iio/trigger.h>
28 #include <linux/iio/trigger_consumer.h>
29 #include <linux/iio/triggered_buffer.h>
30 #include <linux/pinctrl/consumer.h>
31
32 /* Registers */
33 #define AT91_ADC_CR 0x00 /* Control Register */
34 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
35 #define AT91_ADC_START (1 << 1) /* Start Conversion */
36
37 #define AT91_ADC_MR 0x04 /* Mode Register */
38 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
39 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
40 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
41 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
42 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
43 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
44 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
45 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
46 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
47 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
48 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
49 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
50 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
51 #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
52 #define AT91_ADC_PRESCAL_(x) ((x) << 8)
53 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
54 #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
55 #define AT91_ADC_STARTUP_9X5 (0xf << 16)
56 #define AT91_ADC_STARTUP_(x) ((x) << 16)
57 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
58 #define AT91_ADC_SHTIM_(x) ((x) << 24)
59 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
60 #define AT91_ADC_PENDBC_(x) ((x) << 28)
61
62 #define AT91_ADC_TSR 0x0C
63 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
64 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
65
66 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
67 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
68 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
69 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
70
71 #define AT91_ADC_SR 0x1C /* Status Register */
72 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
73 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
74 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
75 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
76 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
77 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
78
79 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
80 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
81
82 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
83 #define AT91_ADC_LDATA (0x3ff)
84
85 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
86 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
87 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
88 #define AT91RL_ADC_IER_PEN (1 << 20)
89 #define AT91RL_ADC_IER_NOPEN (1 << 21)
90 #define AT91_ADC_IER_PEN (1 << 29)
91 #define AT91_ADC_IER_NOPEN (1 << 30)
92 #define AT91_ADC_IER_XRDY (1 << 20)
93 #define AT91_ADC_IER_YRDY (1 << 21)
94 #define AT91_ADC_IER_PRDY (1 << 22)
95 #define AT91_ADC_ISR_PENS (1 << 31)
96
97 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
98 #define AT91_ADC_DATA (0x3ff)
99
100 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
101
102 #define AT91_ADC_ACR 0x94 /* Analog Control Register */
103 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
104
105 #define AT91_ADC_TSMR 0xB0
106 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
107 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
108 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
109 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
110 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
111 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
112 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
113 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
114 #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
115 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
116 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
117 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
118 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
119 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
120
121 #define AT91_ADC_TSXPOSR 0xB4
122 #define AT91_ADC_TSYPOSR 0xB8
123 #define AT91_ADC_TSPRESSR 0xBC
124
125 #define AT91_ADC_TRGR_9260 AT91_ADC_MR
126 #define AT91_ADC_TRGR_9G45 0x08
127 #define AT91_ADC_TRGR_9X5 0xC0
128
129 /* Trigger Register bit field */
130 #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
131 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
132 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
133 #define AT91_ADC_TRGR_NONE (0 << 0)
134 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
135
136 #define AT91_ADC_CHAN(st, ch) \
137 (st->registers->channel_base + (ch * 4))
138 #define at91_adc_readl(st, reg) \
139 (readl_relaxed(st->reg_base + reg))
140 #define at91_adc_writel(st, reg, val) \
141 (writel_relaxed(val, st->reg_base + reg))
142
143 #define DRIVER_NAME "at91_adc"
144 #define MAX_POS_BITS 12
145
146 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
147 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
148
149 #define MAX_RLPOS_BITS 10
150 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
151 #define TOUCH_SHTIM 0xa
152 #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */
153
154 enum atmel_adc_ts_type {
155 ATMEL_ADC_TOUCHSCREEN_NONE = 0,
156 ATMEL_ADC_TOUCHSCREEN_4WIRE = 4,
157 ATMEL_ADC_TOUCHSCREEN_5WIRE = 5,
158 };
159
160 /**
161 * struct at91_adc_trigger - description of triggers
162 * @name: name of the trigger advertised to the user
163 * @value: value to set in the ADC's trigger setup register
164 * to enable the trigger
165 * @is_external: Does the trigger rely on an external pin?
166 */
167 struct at91_adc_trigger {
168 const char *name;
169 u8 value;
170 bool is_external;
171 };
172
173 /**
174 * struct at91_adc_reg_desc - Various informations relative to registers
175 * @channel_base: Base offset for the channel data registers
176 * @drdy_mask: Mask of the DRDY field in the relevant registers
177 * (Interruptions registers mostly)
178 * @status_register: Offset of the Interrupt Status Register
179 * @trigger_register: Offset of the Trigger setup register
180 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
181 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
182 */
183 struct at91_adc_reg_desc {
184 u8 channel_base;
185 u32 drdy_mask;
186 u8 status_register;
187 u8 trigger_register;
188 u32 mr_prescal_mask;
189 u32 mr_startup_mask;
190 };
191
192 struct at91_adc_caps {
193 bool has_ts; /* Support touch screen */
194 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
195 /*
196 * Numbers of sampling data will be averaged. Can be 0~3.
197 * Hardware can average (2 ^ ts_filter_average) sample data.
198 */
199 u8 ts_filter_average;
200 /* Pen Detection input pull-up resistor, can be 0~3 */
201 u8 ts_pen_detect_sensitivity;
202
203 /* startup time calculate function */
204 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
205
206 u8 num_channels;
207
208 u8 low_res_bits;
209 u8 high_res_bits;
210 u32 trigger_number;
211 const struct at91_adc_trigger *triggers;
212 struct at91_adc_reg_desc registers;
213 };
214
215 struct at91_adc_state {
216 struct clk *adc_clk;
217 u16 *buffer;
218 unsigned long channels_mask;
219 struct clk *clk;
220 bool done;
221 int irq;
222 u16 last_value;
223 int chnb;
224 struct mutex lock;
225 u8 num_channels;
226 void __iomem *reg_base;
227 const struct at91_adc_reg_desc *registers;
228 u32 startup_time;
229 u8 sample_hold_time;
230 bool sleep_mode;
231 struct iio_trigger **trig;
232 bool use_external;
233 u32 vref_mv;
234 u32 res; /* resolution used for convertions */
235 wait_queue_head_t wq_data_avail;
236 const struct at91_adc_caps *caps;
237
238 /*
239 * Following ADC channels are shared by touchscreen:
240 *
241 * CH0 -- Touch screen XP/UL
242 * CH1 -- Touch screen XM/UR
243 * CH2 -- Touch screen YP/LL
244 * CH3 -- Touch screen YM/Sense
245 * CH4 -- Touch screen LR(5-wire only)
246 *
247 * The bitfields below represents the reserved channel in the
248 * touchscreen mode.
249 */
250 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
251 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
252 enum atmel_adc_ts_type touchscreen_type;
253 struct input_dev *ts_input;
254
255 u16 ts_sample_period_val;
256 u32 ts_pressure_threshold;
257 u16 ts_pendbc;
258
259 bool ts_bufferedmeasure;
260 u32 ts_prev_absx;
261 u32 ts_prev_absy;
262 };
263
at91_adc_trigger_handler(int irq,void * p)264 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
265 {
266 struct iio_poll_func *pf = p;
267 struct iio_dev *idev = pf->indio_dev;
268 struct at91_adc_state *st = iio_priv(idev);
269 struct iio_chan_spec const *chan;
270 int i, j = 0;
271
272 for (i = 0; i < idev->masklength; i++) {
273 if (!test_bit(i, idev->active_scan_mask))
274 continue;
275 chan = idev->channels + i;
276 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
277 j++;
278 }
279
280 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
281
282 iio_trigger_notify_done(idev->trig);
283
284 /* Needed to ACK the DRDY interruption */
285 at91_adc_readl(st, AT91_ADC_LCDR);
286
287 enable_irq(st->irq);
288
289 return IRQ_HANDLED;
290 }
291
292 /* Handler for classic adc channel eoc trigger */
handle_adc_eoc_trigger(int irq,struct iio_dev * idev)293 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
294 {
295 struct at91_adc_state *st = iio_priv(idev);
296
297 if (iio_buffer_enabled(idev)) {
298 disable_irq_nosync(irq);
299 iio_trigger_poll(idev->trig);
300 } else {
301 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
302 /* Needed to ACK the DRDY interruption */
303 at91_adc_readl(st, AT91_ADC_LCDR);
304 st->done = true;
305 wake_up_interruptible(&st->wq_data_avail);
306 }
307 }
308
at91_ts_sample(struct iio_dev * idev)309 static int at91_ts_sample(struct iio_dev *idev)
310 {
311 struct at91_adc_state *st = iio_priv(idev);
312 unsigned int xscale, yscale, reg, z1, z2;
313 unsigned int x, y, pres, xpos, ypos;
314 unsigned int rxp = 1;
315 unsigned int factor = 1000;
316
317 unsigned int xyz_mask_bits = st->res;
318 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
319
320 /* calculate position */
321 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
322 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
323 xpos = reg & xyz_mask;
324 x = (xpos << MAX_POS_BITS) - xpos;
325 xscale = (reg >> 16) & xyz_mask;
326 if (xscale == 0) {
327 dev_err(&idev->dev, "Error: xscale == 0!\n");
328 return -1;
329 }
330 x /= xscale;
331
332 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
333 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
334 ypos = reg & xyz_mask;
335 y = (ypos << MAX_POS_BITS) - ypos;
336 yscale = (reg >> 16) & xyz_mask;
337 if (yscale == 0) {
338 dev_err(&idev->dev, "Error: yscale == 0!\n");
339 return -1;
340 }
341 y /= yscale;
342
343 /* calculate the pressure */
344 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
345 z1 = reg & xyz_mask;
346 z2 = (reg >> 16) & xyz_mask;
347
348 if (z1 != 0)
349 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
350 / factor;
351 else
352 pres = st->ts_pressure_threshold; /* no pen contacted */
353
354 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
355 xpos, xscale, ypos, yscale, z1, z2, pres);
356
357 if (pres < st->ts_pressure_threshold) {
358 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
359 x, y, pres / factor);
360 input_report_abs(st->ts_input, ABS_X, x);
361 input_report_abs(st->ts_input, ABS_Y, y);
362 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
363 input_report_key(st->ts_input, BTN_TOUCH, 1);
364 input_sync(st->ts_input);
365 } else {
366 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
367 }
368
369 return 0;
370 }
371
at91_adc_rl_interrupt(int irq,void * private)372 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
373 {
374 struct iio_dev *idev = private;
375 struct at91_adc_state *st = iio_priv(idev);
376 u32 status = at91_adc_readl(st, st->registers->status_register);
377 unsigned int reg;
378
379 status &= at91_adc_readl(st, AT91_ADC_IMR);
380 if (status & GENMASK(st->num_channels - 1, 0))
381 handle_adc_eoc_trigger(irq, idev);
382
383 if (status & AT91RL_ADC_IER_PEN) {
384 /* Disabling pen debounce is required to get a NOPEN irq */
385 reg = at91_adc_readl(st, AT91_ADC_MR);
386 reg &= ~AT91_ADC_PENDBC;
387 at91_adc_writel(st, AT91_ADC_MR, reg);
388
389 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
390 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
391 | AT91_ADC_EOC(3));
392 /* Set up period trigger for sampling */
393 at91_adc_writel(st, st->registers->trigger_register,
394 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
395 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
396 } else if (status & AT91RL_ADC_IER_NOPEN) {
397 reg = at91_adc_readl(st, AT91_ADC_MR);
398 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
399 at91_adc_writel(st, AT91_ADC_MR, reg);
400 at91_adc_writel(st, st->registers->trigger_register,
401 AT91_ADC_TRGR_NONE);
402
403 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
404 | AT91_ADC_EOC(3));
405 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
406 st->ts_bufferedmeasure = false;
407 input_report_key(st->ts_input, BTN_TOUCH, 0);
408 input_sync(st->ts_input);
409 } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
410 /* Conversion finished and we've a touchscreen */
411 if (st->ts_bufferedmeasure) {
412 /*
413 * Last measurement is always discarded, since it can
414 * be erroneous.
415 * Always report previous measurement
416 */
417 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
418 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
419 input_report_key(st->ts_input, BTN_TOUCH, 1);
420 input_sync(st->ts_input);
421 } else
422 st->ts_bufferedmeasure = true;
423
424 /* Now make new measurement */
425 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
426 << MAX_RLPOS_BITS;
427 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
428
429 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
430 << MAX_RLPOS_BITS;
431 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
432 }
433
434 return IRQ_HANDLED;
435 }
436
at91_adc_9x5_interrupt(int irq,void * private)437 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
438 {
439 struct iio_dev *idev = private;
440 struct at91_adc_state *st = iio_priv(idev);
441 u32 status = at91_adc_readl(st, st->registers->status_register);
442 const uint32_t ts_data_irq_mask =
443 AT91_ADC_IER_XRDY |
444 AT91_ADC_IER_YRDY |
445 AT91_ADC_IER_PRDY;
446
447 if (status & GENMASK(st->num_channels - 1, 0))
448 handle_adc_eoc_trigger(irq, idev);
449
450 if (status & AT91_ADC_IER_PEN) {
451 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
452 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
453 ts_data_irq_mask);
454 /* Set up period trigger for sampling */
455 at91_adc_writel(st, st->registers->trigger_register,
456 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
457 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
458 } else if (status & AT91_ADC_IER_NOPEN) {
459 at91_adc_writel(st, st->registers->trigger_register, 0);
460 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
461 ts_data_irq_mask);
462 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
463
464 input_report_key(st->ts_input, BTN_TOUCH, 0);
465 input_sync(st->ts_input);
466 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
467 /* Now all touchscreen data is ready */
468
469 if (status & AT91_ADC_ISR_PENS) {
470 /* validate data by pen contact */
471 at91_ts_sample(idev);
472 } else {
473 /* triggered by event that is no pen contact, just read
474 * them to clean the interrupt and discard all.
475 */
476 at91_adc_readl(st, AT91_ADC_TSXPOSR);
477 at91_adc_readl(st, AT91_ADC_TSYPOSR);
478 at91_adc_readl(st, AT91_ADC_TSPRESSR);
479 }
480 }
481
482 return IRQ_HANDLED;
483 }
484
at91_adc_channel_init(struct iio_dev * idev)485 static int at91_adc_channel_init(struct iio_dev *idev)
486 {
487 struct at91_adc_state *st = iio_priv(idev);
488 struct iio_chan_spec *chan_array, *timestamp;
489 int bit, idx = 0;
490 unsigned long rsvd_mask = 0;
491
492 /* If touchscreen is enable, then reserve the adc channels */
493 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
494 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
495 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
496 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
497
498 /* set up the channel mask to reserve touchscreen channels */
499 st->channels_mask &= ~rsvd_mask;
500
501 idev->num_channels = bitmap_weight(&st->channels_mask,
502 st->num_channels) + 1;
503
504 chan_array = devm_kzalloc(&idev->dev,
505 ((idev->num_channels + 1) *
506 sizeof(struct iio_chan_spec)),
507 GFP_KERNEL);
508
509 if (!chan_array)
510 return -ENOMEM;
511
512 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
513 struct iio_chan_spec *chan = chan_array + idx;
514
515 chan->type = IIO_VOLTAGE;
516 chan->indexed = 1;
517 chan->channel = bit;
518 chan->scan_index = idx;
519 chan->scan_type.sign = 'u';
520 chan->scan_type.realbits = st->res;
521 chan->scan_type.storagebits = 16;
522 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
523 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
524 idx++;
525 }
526 timestamp = chan_array + idx;
527
528 timestamp->type = IIO_TIMESTAMP;
529 timestamp->channel = -1;
530 timestamp->scan_index = idx;
531 timestamp->scan_type.sign = 's';
532 timestamp->scan_type.realbits = 64;
533 timestamp->scan_type.storagebits = 64;
534
535 idev->channels = chan_array;
536 return idev->num_channels;
537 }
538
at91_adc_get_trigger_value_by_name(struct iio_dev * idev,const struct at91_adc_trigger * triggers,const char * trigger_name)539 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
540 const struct at91_adc_trigger *triggers,
541 const char *trigger_name)
542 {
543 struct at91_adc_state *st = iio_priv(idev);
544 int i;
545
546 for (i = 0; i < st->caps->trigger_number; i++) {
547 char *name = kasprintf(GFP_KERNEL,
548 "%s-dev%d-%s",
549 idev->name,
550 iio_device_id(idev),
551 triggers[i].name);
552 if (!name)
553 return -ENOMEM;
554
555 if (strcmp(trigger_name, name) == 0) {
556 kfree(name);
557 if (triggers[i].value == 0)
558 return -EINVAL;
559 return triggers[i].value;
560 }
561
562 kfree(name);
563 }
564
565 return -EINVAL;
566 }
567
at91_adc_configure_trigger(struct iio_trigger * trig,bool state)568 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
569 {
570 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
571 struct at91_adc_state *st = iio_priv(idev);
572 const struct at91_adc_reg_desc *reg = st->registers;
573 u32 status = at91_adc_readl(st, reg->trigger_register);
574 int value;
575 u8 bit;
576
577 value = at91_adc_get_trigger_value_by_name(idev,
578 st->caps->triggers,
579 idev->trig->name);
580 if (value < 0)
581 return value;
582
583 if (state) {
584 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
585 if (st->buffer == NULL)
586 return -ENOMEM;
587
588 at91_adc_writel(st, reg->trigger_register,
589 status | value);
590
591 for_each_set_bit(bit, idev->active_scan_mask,
592 st->num_channels) {
593 struct iio_chan_spec const *chan = idev->channels + bit;
594 at91_adc_writel(st, AT91_ADC_CHER,
595 AT91_ADC_CH(chan->channel));
596 }
597
598 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
599
600 } else {
601 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
602
603 at91_adc_writel(st, reg->trigger_register,
604 status & ~value);
605
606 for_each_set_bit(bit, idev->active_scan_mask,
607 st->num_channels) {
608 struct iio_chan_spec const *chan = idev->channels + bit;
609 at91_adc_writel(st, AT91_ADC_CHDR,
610 AT91_ADC_CH(chan->channel));
611 }
612 kfree(st->buffer);
613 }
614
615 return 0;
616 }
617
618 static const struct iio_trigger_ops at91_adc_trigger_ops = {
619 .set_trigger_state = &at91_adc_configure_trigger,
620 };
621
at91_adc_allocate_trigger(struct iio_dev * idev,const struct at91_adc_trigger * trigger)622 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
623 const struct at91_adc_trigger *trigger)
624 {
625 struct iio_trigger *trig;
626 int ret;
627
628 trig = iio_trigger_alloc(idev->dev.parent, "%s-dev%d-%s", idev->name,
629 iio_device_id(idev), trigger->name);
630 if (trig == NULL)
631 return NULL;
632
633 iio_trigger_set_drvdata(trig, idev);
634 trig->ops = &at91_adc_trigger_ops;
635
636 ret = iio_trigger_register(trig);
637 if (ret) {
638 iio_trigger_free(trig);
639 return NULL;
640 }
641
642 return trig;
643 }
644
at91_adc_trigger_init(struct iio_dev * idev)645 static int at91_adc_trigger_init(struct iio_dev *idev)
646 {
647 struct at91_adc_state *st = iio_priv(idev);
648 int i, ret;
649
650 st->trig = devm_kcalloc(&idev->dev,
651 st->caps->trigger_number, sizeof(*st->trig),
652 GFP_KERNEL);
653
654 if (st->trig == NULL) {
655 ret = -ENOMEM;
656 goto error_ret;
657 }
658
659 for (i = 0; i < st->caps->trigger_number; i++) {
660 if (st->caps->triggers[i].is_external && !(st->use_external))
661 continue;
662
663 st->trig[i] = at91_adc_allocate_trigger(idev,
664 st->caps->triggers + i);
665 if (st->trig[i] == NULL) {
666 dev_err(&idev->dev,
667 "Could not allocate trigger %d\n", i);
668 ret = -ENOMEM;
669 goto error_trigger;
670 }
671 }
672
673 return 0;
674
675 error_trigger:
676 for (i--; i >= 0; i--) {
677 iio_trigger_unregister(st->trig[i]);
678 iio_trigger_free(st->trig[i]);
679 }
680 error_ret:
681 return ret;
682 }
683
at91_adc_trigger_remove(struct iio_dev * idev)684 static void at91_adc_trigger_remove(struct iio_dev *idev)
685 {
686 struct at91_adc_state *st = iio_priv(idev);
687 int i;
688
689 for (i = 0; i < st->caps->trigger_number; i++) {
690 iio_trigger_unregister(st->trig[i]);
691 iio_trigger_free(st->trig[i]);
692 }
693 }
694
at91_adc_buffer_init(struct iio_dev * idev)695 static int at91_adc_buffer_init(struct iio_dev *idev)
696 {
697 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
698 &at91_adc_trigger_handler, NULL);
699 }
700
at91_adc_buffer_remove(struct iio_dev * idev)701 static void at91_adc_buffer_remove(struct iio_dev *idev)
702 {
703 iio_triggered_buffer_cleanup(idev);
704 }
705
at91_adc_read_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)706 static int at91_adc_read_raw(struct iio_dev *idev,
707 struct iio_chan_spec const *chan,
708 int *val, int *val2, long mask)
709 {
710 struct at91_adc_state *st = iio_priv(idev);
711 int ret;
712
713 switch (mask) {
714 case IIO_CHAN_INFO_RAW:
715 mutex_lock(&st->lock);
716
717 st->chnb = chan->channel;
718 at91_adc_writel(st, AT91_ADC_CHER,
719 AT91_ADC_CH(chan->channel));
720 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
721 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
722
723 ret = wait_event_interruptible_timeout(st->wq_data_avail,
724 st->done,
725 msecs_to_jiffies(1000));
726
727 /* Disable interrupts, regardless if adc conversion was
728 * successful or not
729 */
730 at91_adc_writel(st, AT91_ADC_CHDR,
731 AT91_ADC_CH(chan->channel));
732 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
733
734 if (ret > 0) {
735 /* a valid conversion took place */
736 *val = st->last_value;
737 st->last_value = 0;
738 st->done = false;
739 ret = IIO_VAL_INT;
740 } else if (ret == 0) {
741 /* conversion timeout */
742 dev_err(&idev->dev, "ADC Channel %d timeout.\n",
743 chan->channel);
744 ret = -ETIMEDOUT;
745 }
746
747 mutex_unlock(&st->lock);
748 return ret;
749
750 case IIO_CHAN_INFO_SCALE:
751 *val = st->vref_mv;
752 *val2 = chan->scan_type.realbits;
753 return IIO_VAL_FRACTIONAL_LOG2;
754 default:
755 break;
756 }
757 return -EINVAL;
758 }
759
760
calc_startup_ticks_9260(u32 startup_time,u32 adc_clk_khz)761 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
762 {
763 /*
764 * Number of ticks needed to cover the startup time of the ADC
765 * as defined in the electrical characteristics of the board,
766 * divided by 8. The formula thus is :
767 * Startup Time = (ticks + 1) * 8 / ADC Clock
768 */
769 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
770 }
771
calc_startup_ticks_9x5(u32 startup_time,u32 adc_clk_khz)772 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
773 {
774 /*
775 * For sama5d3x and at91sam9x5, the formula changes to:
776 * Startup Time = <lookup_table_value> / ADC Clock
777 */
778 static const int startup_lookup[] = {
779 0, 8, 16, 24,
780 64, 80, 96, 112,
781 512, 576, 640, 704,
782 768, 832, 896, 960
783 };
784 int i, size = ARRAY_SIZE(startup_lookup);
785 unsigned int ticks;
786
787 ticks = startup_time * adc_clk_khz / 1000;
788 for (i = 0; i < size; i++)
789 if (ticks < startup_lookup[i])
790 break;
791
792 ticks = i;
793 if (ticks == size)
794 /* Reach the end of lookup table */
795 ticks = size - 1;
796
797 return ticks;
798 }
799
at91_adc_probe_dt_ts(struct device_node * node,struct at91_adc_state * st,struct device * dev)800 static int at91_adc_probe_dt_ts(struct device_node *node,
801 struct at91_adc_state *st, struct device *dev)
802 {
803 int ret;
804 u32 prop;
805
806 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
807 if (ret) {
808 dev_info(dev, "ADC Touch screen is disabled.\n");
809 return 0;
810 }
811
812 switch (prop) {
813 case 4:
814 case 5:
815 st->touchscreen_type = prop;
816 break;
817 default:
818 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
819 return -EINVAL;
820 }
821
822 if (!st->caps->has_tsmr)
823 return 0;
824 prop = 0;
825 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
826 st->ts_pressure_threshold = prop;
827 if (st->ts_pressure_threshold) {
828 return 0;
829 } else {
830 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
831 return -EINVAL;
832 }
833 }
834
835 static const struct iio_info at91_adc_info = {
836 .read_raw = &at91_adc_read_raw,
837 };
838
839 /* Touchscreen related functions */
atmel_ts_open(struct input_dev * dev)840 static int atmel_ts_open(struct input_dev *dev)
841 {
842 struct at91_adc_state *st = input_get_drvdata(dev);
843
844 if (st->caps->has_tsmr)
845 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
846 else
847 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
848 return 0;
849 }
850
atmel_ts_close(struct input_dev * dev)851 static void atmel_ts_close(struct input_dev *dev)
852 {
853 struct at91_adc_state *st = input_get_drvdata(dev);
854
855 if (st->caps->has_tsmr)
856 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
857 else
858 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
859 }
860
at91_ts_hw_init(struct iio_dev * idev,u32 adc_clk_khz)861 static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz)
862 {
863 struct at91_adc_state *st = iio_priv(idev);
864 u32 reg = 0;
865 u32 tssctim = 0;
866 int i = 0;
867
868 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
869 * pen detect noise.
870 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
871 */
872 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
873 1000, 1);
874
875 while (st->ts_pendbc >> ++i)
876 ; /* Empty! Find the shift offset */
877 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
878 st->ts_pendbc = i;
879 else
880 st->ts_pendbc = i - 1;
881
882 if (!st->caps->has_tsmr) {
883 reg = at91_adc_readl(st, AT91_ADC_MR);
884 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
885
886 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
887 at91_adc_writel(st, AT91_ADC_MR, reg);
888
889 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
890 at91_adc_writel(st, AT91_ADC_TSR, reg);
891
892 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
893 adc_clk_khz / 1000) - 1, 1);
894
895 return 0;
896 }
897
898 /* Touchscreen Switches Closure time needed for allowing the value to
899 * stabilize.
900 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
901 */
902 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
903 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
904 adc_clk_khz, tssctim);
905
906 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
907 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
908 else
909 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
910
911 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
912 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
913 & AT91_ADC_TSMR_TSAV;
914 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
915 reg |= AT91_ADC_TSMR_NOTSDMA;
916 reg |= AT91_ADC_TSMR_PENDET_ENA;
917 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
918
919 at91_adc_writel(st, AT91_ADC_TSMR, reg);
920
921 /* Change adc internal resistor value for better pen detection,
922 * default value is 100 kOhm.
923 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
924 * option only available on ES2 and higher
925 */
926 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
927 & AT91_ADC_ACR_PENDETSENS);
928
929 /* Sample Period Time = (TRGPER + 1) / ADCClock */
930 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
931 adc_clk_khz / 1000) - 1, 1);
932
933 return 0;
934 }
935
at91_ts_register(struct iio_dev * idev,struct platform_device * pdev)936 static int at91_ts_register(struct iio_dev *idev,
937 struct platform_device *pdev)
938 {
939 struct at91_adc_state *st = iio_priv(idev);
940 struct input_dev *input;
941 int ret;
942
943 input = input_allocate_device();
944 if (!input) {
945 dev_err(&idev->dev, "Failed to allocate TS device!\n");
946 return -ENOMEM;
947 }
948
949 input->name = DRIVER_NAME;
950 input->id.bustype = BUS_HOST;
951 input->dev.parent = &pdev->dev;
952 input->open = atmel_ts_open;
953 input->close = atmel_ts_close;
954
955 __set_bit(EV_ABS, input->evbit);
956 __set_bit(EV_KEY, input->evbit);
957 __set_bit(BTN_TOUCH, input->keybit);
958 if (st->caps->has_tsmr) {
959 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
960 0, 0);
961 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
962 0, 0);
963 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
964 } else {
965 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
966 dev_err(&pdev->dev,
967 "This touchscreen controller only support 4 wires\n");
968 ret = -EINVAL;
969 goto err;
970 }
971
972 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
973 0, 0);
974 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
975 0, 0);
976 }
977
978 st->ts_input = input;
979 input_set_drvdata(input, st);
980
981 ret = input_register_device(input);
982 if (ret)
983 goto err;
984
985 return ret;
986
987 err:
988 input_free_device(st->ts_input);
989 return ret;
990 }
991
at91_ts_unregister(struct at91_adc_state * st)992 static void at91_ts_unregister(struct at91_adc_state *st)
993 {
994 input_unregister_device(st->ts_input);
995 }
996
at91_adc_probe(struct platform_device * pdev)997 static int at91_adc_probe(struct platform_device *pdev)
998 {
999 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1000 struct device_node *node = pdev->dev.of_node;
1001 int ret;
1002 struct iio_dev *idev;
1003 struct at91_adc_state *st;
1004 u32 reg, prop;
1005 char *s;
1006
1007 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1008 if (!idev)
1009 return -ENOMEM;
1010
1011 st = iio_priv(idev);
1012
1013 st->caps = of_device_get_match_data(&pdev->dev);
1014
1015 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
1016
1017 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
1018 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
1019 return -EINVAL;
1020 }
1021 st->channels_mask = prop;
1022
1023 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
1024
1025 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
1026 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
1027 return -EINVAL;
1028 }
1029 st->startup_time = prop;
1030
1031 prop = 0;
1032 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
1033 st->sample_hold_time = prop;
1034
1035 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
1036 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
1037 return -EINVAL;
1038 }
1039 st->vref_mv = prop;
1040
1041 st->res = st->caps->high_res_bits;
1042 if (st->caps->low_res_bits &&
1043 !of_property_read_string(node, "atmel,adc-use-res", (const char **)&s)
1044 && !strcmp(s, "lowres"))
1045 st->res = st->caps->low_res_bits;
1046
1047 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
1048
1049 st->registers = &st->caps->registers;
1050 st->num_channels = st->caps->num_channels;
1051
1052 /* Check if touchscreen is supported. */
1053 if (st->caps->has_ts) {
1054 ret = at91_adc_probe_dt_ts(node, st, &idev->dev);
1055 if (ret)
1056 return ret;
1057 }
1058
1059 platform_set_drvdata(pdev, idev);
1060
1061 idev->name = dev_name(&pdev->dev);
1062 idev->modes = INDIO_DIRECT_MODE;
1063 idev->info = &at91_adc_info;
1064
1065 st->irq = platform_get_irq(pdev, 0);
1066 if (st->irq < 0)
1067 return -ENODEV;
1068
1069 st->reg_base = devm_platform_ioremap_resource(pdev, 0);
1070 if (IS_ERR(st->reg_base))
1071 return PTR_ERR(st->reg_base);
1072
1073
1074 /*
1075 * Disable all IRQs before setting up the handler
1076 */
1077 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1078 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1079
1080 if (st->caps->has_tsmr)
1081 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1082 pdev->dev.driver->name, idev);
1083 else
1084 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1085 pdev->dev.driver->name, idev);
1086 if (ret) {
1087 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1088 return ret;
1089 }
1090
1091 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1092 if (IS_ERR(st->clk)) {
1093 dev_err(&pdev->dev, "Failed to get the clock.\n");
1094 ret = PTR_ERR(st->clk);
1095 goto error_free_irq;
1096 }
1097
1098 ret = clk_prepare_enable(st->clk);
1099 if (ret) {
1100 dev_err(&pdev->dev,
1101 "Could not prepare or enable the clock.\n");
1102 goto error_free_irq;
1103 }
1104
1105 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1106 if (IS_ERR(st->adc_clk)) {
1107 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1108 ret = PTR_ERR(st->adc_clk);
1109 goto error_disable_clk;
1110 }
1111
1112 ret = clk_prepare_enable(st->adc_clk);
1113 if (ret) {
1114 dev_err(&pdev->dev,
1115 "Could not prepare or enable the ADC clock.\n");
1116 goto error_disable_clk;
1117 }
1118
1119 /*
1120 * Prescaler rate computation using the formula from the Atmel's
1121 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1122 * specified by the electrical characteristics of the board.
1123 */
1124 mstrclk = clk_get_rate(st->clk);
1125 adc_clk = clk_get_rate(st->adc_clk);
1126 adc_clk_khz = adc_clk / 1000;
1127
1128 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1129 mstrclk, adc_clk);
1130
1131 prsc = (mstrclk / (2 * adc_clk)) - 1;
1132
1133 if (!st->startup_time) {
1134 dev_err(&pdev->dev, "No startup time available.\n");
1135 ret = -EINVAL;
1136 goto error_disable_adc_clk;
1137 }
1138 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1139
1140 /*
1141 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1142 * the best converted final value between two channels selection
1143 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1144 */
1145 if (st->sample_hold_time > 0)
1146 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1147 - 1, 1);
1148 else
1149 shtim = 0;
1150
1151 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1152 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1153 if (st->res == st->caps->low_res_bits)
1154 reg |= AT91_ADC_LOWRES;
1155 if (st->sleep_mode)
1156 reg |= AT91_ADC_SLEEP;
1157 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1158 at91_adc_writel(st, AT91_ADC_MR, reg);
1159
1160 /* Setup the ADC channels available on the board */
1161 ret = at91_adc_channel_init(idev);
1162 if (ret < 0) {
1163 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1164 goto error_disable_adc_clk;
1165 }
1166
1167 init_waitqueue_head(&st->wq_data_avail);
1168 mutex_init(&st->lock);
1169
1170 /*
1171 * Since touch screen will set trigger register as period trigger. So
1172 * when touch screen is enabled, then we have to disable hardware
1173 * trigger for classic adc.
1174 */
1175 if (!st->touchscreen_type) {
1176 ret = at91_adc_buffer_init(idev);
1177 if (ret < 0) {
1178 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1179 goto error_disable_adc_clk;
1180 }
1181
1182 ret = at91_adc_trigger_init(idev);
1183 if (ret < 0) {
1184 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1185 at91_adc_buffer_remove(idev);
1186 goto error_disable_adc_clk;
1187 }
1188 } else {
1189 ret = at91_ts_register(idev, pdev);
1190 if (ret)
1191 goto error_disable_adc_clk;
1192
1193 at91_ts_hw_init(idev, adc_clk_khz);
1194 }
1195
1196 ret = iio_device_register(idev);
1197 if (ret < 0) {
1198 dev_err(&pdev->dev, "Couldn't register the device.\n");
1199 goto error_iio_device_register;
1200 }
1201
1202 return 0;
1203
1204 error_iio_device_register:
1205 if (!st->touchscreen_type) {
1206 at91_adc_trigger_remove(idev);
1207 at91_adc_buffer_remove(idev);
1208 } else {
1209 at91_ts_unregister(st);
1210 }
1211 error_disable_adc_clk:
1212 clk_disable_unprepare(st->adc_clk);
1213 error_disable_clk:
1214 clk_disable_unprepare(st->clk);
1215 error_free_irq:
1216 free_irq(st->irq, idev);
1217 return ret;
1218 }
1219
at91_adc_remove(struct platform_device * pdev)1220 static int at91_adc_remove(struct platform_device *pdev)
1221 {
1222 struct iio_dev *idev = platform_get_drvdata(pdev);
1223 struct at91_adc_state *st = iio_priv(idev);
1224
1225 iio_device_unregister(idev);
1226 if (!st->touchscreen_type) {
1227 at91_adc_trigger_remove(idev);
1228 at91_adc_buffer_remove(idev);
1229 } else {
1230 at91_ts_unregister(st);
1231 }
1232 clk_disable_unprepare(st->adc_clk);
1233 clk_disable_unprepare(st->clk);
1234 free_irq(st->irq, idev);
1235
1236 return 0;
1237 }
1238
1239 #ifdef CONFIG_PM_SLEEP
at91_adc_suspend(struct device * dev)1240 static int at91_adc_suspend(struct device *dev)
1241 {
1242 struct iio_dev *idev = dev_get_drvdata(dev);
1243 struct at91_adc_state *st = iio_priv(idev);
1244
1245 pinctrl_pm_select_sleep_state(dev);
1246 clk_disable_unprepare(st->clk);
1247
1248 return 0;
1249 }
1250
at91_adc_resume(struct device * dev)1251 static int at91_adc_resume(struct device *dev)
1252 {
1253 struct iio_dev *idev = dev_get_drvdata(dev);
1254 struct at91_adc_state *st = iio_priv(idev);
1255
1256 clk_prepare_enable(st->clk);
1257 pinctrl_pm_select_default_state(dev);
1258
1259 return 0;
1260 }
1261 #endif
1262
1263 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1264
1265 static const struct at91_adc_trigger at91sam9260_triggers[] = {
1266 { .name = "timer-counter-0", .value = 0x1 },
1267 { .name = "timer-counter-1", .value = 0x3 },
1268 { .name = "timer-counter-2", .value = 0x5 },
1269 { .name = "external", .value = 0xd, .is_external = true },
1270 };
1271
1272 static struct at91_adc_caps at91sam9260_caps = {
1273 .calc_startup_ticks = calc_startup_ticks_9260,
1274 .num_channels = 4,
1275 .low_res_bits = 8,
1276 .high_res_bits = 10,
1277 .registers = {
1278 .channel_base = AT91_ADC_CHR(0),
1279 .drdy_mask = AT91_ADC_DRDY,
1280 .status_register = AT91_ADC_SR,
1281 .trigger_register = AT91_ADC_TRGR_9260,
1282 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1283 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1284 },
1285 .triggers = at91sam9260_triggers,
1286 .trigger_number = ARRAY_SIZE(at91sam9260_triggers),
1287 };
1288
1289 static const struct at91_adc_trigger at91sam9x5_triggers[] = {
1290 { .name = "external-rising", .value = 0x1, .is_external = true },
1291 { .name = "external-falling", .value = 0x2, .is_external = true },
1292 { .name = "external-any", .value = 0x3, .is_external = true },
1293 { .name = "continuous", .value = 0x6 },
1294 };
1295
1296 static struct at91_adc_caps at91sam9rl_caps = {
1297 .has_ts = true,
1298 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1299 .num_channels = 6,
1300 .low_res_bits = 8,
1301 .high_res_bits = 10,
1302 .registers = {
1303 .channel_base = AT91_ADC_CHR(0),
1304 .drdy_mask = AT91_ADC_DRDY,
1305 .status_register = AT91_ADC_SR,
1306 .trigger_register = AT91_ADC_TRGR_9G45,
1307 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1308 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1309 },
1310 .triggers = at91sam9x5_triggers,
1311 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1312 };
1313
1314 static struct at91_adc_caps at91sam9g45_caps = {
1315 .has_ts = true,
1316 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1317 .num_channels = 8,
1318 .low_res_bits = 8,
1319 .high_res_bits = 10,
1320 .registers = {
1321 .channel_base = AT91_ADC_CHR(0),
1322 .drdy_mask = AT91_ADC_DRDY,
1323 .status_register = AT91_ADC_SR,
1324 .trigger_register = AT91_ADC_TRGR_9G45,
1325 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1326 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1327 },
1328 .triggers = at91sam9x5_triggers,
1329 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1330 };
1331
1332 static struct at91_adc_caps at91sam9x5_caps = {
1333 .has_ts = true,
1334 .has_tsmr = true,
1335 .ts_filter_average = 3,
1336 .ts_pen_detect_sensitivity = 2,
1337 .calc_startup_ticks = calc_startup_ticks_9x5,
1338 .num_channels = 12,
1339 .low_res_bits = 8,
1340 .high_res_bits = 10,
1341 .registers = {
1342 .channel_base = AT91_ADC_CDR0_9X5,
1343 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1344 .status_register = AT91_ADC_SR_9X5,
1345 .trigger_register = AT91_ADC_TRGR_9X5,
1346 /* prescal mask is same as 9G45 */
1347 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1348 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1349 },
1350 .triggers = at91sam9x5_triggers,
1351 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1352 };
1353
1354 static struct at91_adc_caps sama5d3_caps = {
1355 .has_ts = true,
1356 .has_tsmr = true,
1357 .ts_filter_average = 3,
1358 .ts_pen_detect_sensitivity = 2,
1359 .calc_startup_ticks = calc_startup_ticks_9x5,
1360 .num_channels = 12,
1361 .low_res_bits = 0,
1362 .high_res_bits = 12,
1363 .registers = {
1364 .channel_base = AT91_ADC_CDR0_9X5,
1365 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1366 .status_register = AT91_ADC_SR_9X5,
1367 .trigger_register = AT91_ADC_TRGR_9X5,
1368 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1369 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1370 },
1371 .triggers = at91sam9x5_triggers,
1372 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1373 };
1374
1375 static const struct of_device_id at91_adc_dt_ids[] = {
1376 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1377 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1378 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1379 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1380 { .compatible = "atmel,sama5d3-adc", .data = &sama5d3_caps },
1381 {},
1382 };
1383 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1384
1385 static struct platform_driver at91_adc_driver = {
1386 .probe = at91_adc_probe,
1387 .remove = at91_adc_remove,
1388 .driver = {
1389 .name = DRIVER_NAME,
1390 .of_match_table = at91_adc_dt_ids,
1391 .pm = &at91_adc_pm_ops,
1392 },
1393 };
1394
1395 module_platform_driver(at91_adc_driver);
1396
1397 MODULE_LICENSE("GPL");
1398 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1399 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1400