1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
35
36 #include <rdma/ib_verbs.h>
37 #include <rdma/hns-abi.h>
38
39 #define DRV_NAME "hns_roce"
40
41 #define PCI_REVISION_ID_HIP08 0x21
42 #define PCI_REVISION_ID_HIP09 0x30
43
44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
45
46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
47
48 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
49
50 #define BA_BYTE_LEN 8
51
52 /* Hardware specification only for v1 engine */
53 #define HNS_ROCE_MIN_CQE_NUM 0x40
54 #define HNS_ROCE_MIN_WQE_NUM 0x20
55 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1
56
57 /* Hardware specification only for v1 engine */
58 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
59 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000
60
61 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20
62 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \
63 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
64 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
65 #define HNS_ROCE_MIN_CQE_CNT 16
66
67 #define HNS_ROCE_RESERVED_SGE 1
68
69 #define HNS_ROCE_MAX_IRQ_NUM 128
70
71 #define HNS_ROCE_SGE_IN_WQE 2
72 #define HNS_ROCE_SGE_SHIFT 4
73
74 #define EQ_ENABLE 1
75 #define EQ_DISABLE 0
76
77 #define HNS_ROCE_CEQ 0
78 #define HNS_ROCE_AEQ 1
79
80 #define HNS_ROCE_CEQE_SIZE 0x4
81 #define HNS_ROCE_AEQE_SIZE 0x10
82
83 #define HNS_ROCE_V3_EQE_SIZE 0x40
84
85 #define HNS_ROCE_V2_CQE_SIZE 32
86 #define HNS_ROCE_V3_CQE_SIZE 64
87
88 #define HNS_ROCE_V2_QPC_SZ 256
89 #define HNS_ROCE_V3_QPC_SZ 512
90
91 #define HNS_ROCE_MAX_PORTS 6
92 #define HNS_ROCE_GID_SIZE 16
93 #define HNS_ROCE_SGE_SIZE 16
94 #define HNS_ROCE_DWQE_SIZE 65536
95
96 #define HNS_ROCE_HOP_NUM_0 0xff
97
98 #define MR_TYPE_MR 0x00
99 #define MR_TYPE_FRMR 0x01
100 #define MR_TYPE_DMA 0x03
101
102 #define HNS_ROCE_FRMR_MAX_PA 512
103
104 #define PKEY_ID 0xffff
105 #define GUID_LEN 8
106 #define NODE_DESC_SIZE 64
107 #define DB_REG_OFFSET 0x1000
108
109 /* Configure to HW for PAGE_SIZE larger than 4KB */
110 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
111
112 #define PAGES_SHIFT_8 8
113 #define PAGES_SHIFT_16 16
114 #define PAGES_SHIFT_24 24
115 #define PAGES_SHIFT_32 32
116
117 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
118 #define SRQ_DB_REG 0x230
119
120 #define HNS_ROCE_QP_BANK_NUM 8
121 #define HNS_ROCE_CQ_BANK_NUM 4
122
123 #define CQ_BANKID_SHIFT 2
124 #define CQ_BANKID_MASK GENMASK(1, 0)
125
126 /* The chip implementation of the consumer index is calculated
127 * according to twice the actual EQ depth
128 */
129 #define EQ_DEPTH_COEFF 2
130
131 enum {
132 SERV_TYPE_RC,
133 SERV_TYPE_UC,
134 SERV_TYPE_RD,
135 SERV_TYPE_UD,
136 SERV_TYPE_XRC = 5,
137 };
138
139 enum hns_roce_qp_state {
140 HNS_ROCE_QP_STATE_RST,
141 HNS_ROCE_QP_STATE_INIT,
142 HNS_ROCE_QP_STATE_RTR,
143 HNS_ROCE_QP_STATE_RTS,
144 HNS_ROCE_QP_STATE_SQD,
145 HNS_ROCE_QP_STATE_ERR,
146 HNS_ROCE_QP_NUM_STATE,
147 };
148
149 enum hns_roce_event {
150 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
151 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
152 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
153 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
154 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
155 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
156 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
157 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
158 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
159 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
160 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
161 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
162 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
163 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
164 /* 0x10 and 0x11 is unused in currently application case */
165 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
166 HNS_ROCE_EVENT_TYPE_MB = 0x13,
167 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
168 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16,
169 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17,
170 };
171
172 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
173
174 enum {
175 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
176 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
177 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
178 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3),
179 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4),
180 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
181 HNS_ROCE_CAP_FLAG_XRC = BIT(6),
182 HNS_ROCE_CAP_FLAG_MW = BIT(7),
183 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
184 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
185 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
186 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14),
187 HNS_ROCE_CAP_FLAG_STASH = BIT(17),
188 };
189
190 #define HNS_ROCE_DB_TYPE_COUNT 2
191 #define HNS_ROCE_DB_UNIT_SIZE 4
192
193 enum {
194 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
195 };
196
197 enum hns_roce_reset_stage {
198 HNS_ROCE_STATE_NON_RST,
199 HNS_ROCE_STATE_RST_BEF_DOWN,
200 HNS_ROCE_STATE_RST_DOWN,
201 HNS_ROCE_STATE_RST_UNINIT,
202 HNS_ROCE_STATE_RST_INIT,
203 HNS_ROCE_STATE_RST_INITED,
204 };
205
206 enum hns_roce_instance_state {
207 HNS_ROCE_STATE_NON_INIT,
208 HNS_ROCE_STATE_INIT,
209 HNS_ROCE_STATE_INITED,
210 HNS_ROCE_STATE_UNINIT,
211 };
212
213 enum {
214 HNS_ROCE_RST_DIRECT_RETURN = 0,
215 };
216
217 #define HNS_ROCE_CMD_SUCCESS 1
218
219 /* The minimum page size is 4K for hardware */
220 #define HNS_HW_PAGE_SHIFT 12
221 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
222
223 struct hns_roce_uar {
224 u64 pfn;
225 unsigned long index;
226 unsigned long logic_idx;
227 };
228
229 struct hns_roce_ucontext {
230 struct ib_ucontext ibucontext;
231 struct hns_roce_uar uar;
232 struct list_head page_list;
233 struct mutex page_mutex;
234 };
235
236 struct hns_roce_pd {
237 struct ib_pd ibpd;
238 unsigned long pdn;
239 };
240
241 struct hns_roce_xrcd {
242 struct ib_xrcd ibxrcd;
243 u32 xrcdn;
244 };
245
246 struct hns_roce_bitmap {
247 /* Bitmap Traversal last a bit which is 1 */
248 unsigned long last;
249 unsigned long top;
250 unsigned long max;
251 unsigned long reserved_top;
252 unsigned long mask;
253 spinlock_t lock;
254 unsigned long *table;
255 };
256
257 struct hns_roce_ida {
258 struct ida ida;
259 u32 min; /* Lowest ID to allocate. */
260 u32 max; /* Highest ID to allocate. */
261 };
262
263 /* For Hardware Entry Memory */
264 struct hns_roce_hem_table {
265 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
266 u32 type;
267 /* HEM array elment num */
268 unsigned long num_hem;
269 /* Single obj size */
270 unsigned long obj_size;
271 unsigned long table_chunk_size;
272 int lowmem;
273 struct mutex mutex;
274 struct hns_roce_hem **hem;
275 u64 **bt_l1;
276 dma_addr_t *bt_l1_dma_addr;
277 u64 **bt_l0;
278 dma_addr_t *bt_l0_dma_addr;
279 };
280
281 struct hns_roce_buf_region {
282 u32 offset; /* page offset */
283 u32 count; /* page count */
284 int hopnum; /* addressing hop num */
285 };
286
287 #define HNS_ROCE_MAX_BT_REGION 3
288 #define HNS_ROCE_MAX_BT_LEVEL 3
289 struct hns_roce_hem_list {
290 struct list_head root_bt;
291 /* link all bt dma mem by hop config */
292 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
293 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
294 dma_addr_t root_ba; /* pointer to the root ba table */
295 };
296
297 struct hns_roce_buf_attr {
298 struct {
299 size_t size; /* region size */
300 int hopnum; /* multi-hop addressing hop num */
301 } region[HNS_ROCE_MAX_BT_REGION];
302 unsigned int region_count; /* valid region count */
303 unsigned int page_shift; /* buffer page shift */
304 unsigned int user_access; /* umem access flag */
305 bool mtt_only; /* only alloc buffer-required MTT memory */
306 };
307
308 struct hns_roce_hem_cfg {
309 dma_addr_t root_ba; /* root BA table's address */
310 bool is_direct; /* addressing without BA table */
311 unsigned int ba_pg_shift; /* BA table page shift */
312 unsigned int buf_pg_shift; /* buffer page shift */
313 unsigned int buf_pg_count; /* buffer page count */
314 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
315 unsigned int region_count;
316 };
317
318 /* memory translate region */
319 struct hns_roce_mtr {
320 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
321 struct ib_umem *umem; /* user space buffer */
322 struct hns_roce_buf *kmem; /* kernel space buffer */
323 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
324 };
325
326 struct hns_roce_mw {
327 struct ib_mw ibmw;
328 u32 pdn;
329 u32 rkey;
330 int enabled; /* MW's active status */
331 u32 pbl_hop_num;
332 u32 pbl_ba_pg_sz;
333 u32 pbl_buf_pg_sz;
334 };
335
336 /* Only support 4K page size for mr register */
337 #define MR_SIZE_4K 0
338
339 struct hns_roce_mr {
340 struct ib_mr ibmr;
341 u64 iova; /* MR's virtual original addr */
342 u64 size; /* Address range of MR */
343 u32 key; /* Key of MR */
344 u32 pd; /* PD num of MR */
345 u32 access; /* Access permission of MR */
346 int enabled; /* MR's active status */
347 int type; /* MR's register type */
348 u32 pbl_hop_num; /* multi-hop number */
349 struct hns_roce_mtr pbl_mtr;
350 u32 npages;
351 dma_addr_t *page_list;
352 };
353
354 struct hns_roce_mr_table {
355 struct hns_roce_ida mtpt_ida;
356 struct hns_roce_hem_table mtpt_table;
357 };
358
359 struct hns_roce_wq {
360 u64 *wrid; /* Work request ID */
361 spinlock_t lock;
362 u32 wqe_cnt; /* WQE num */
363 u32 max_gs;
364 u32 rsv_sge;
365 int offset;
366 int wqe_shift; /* WQE size */
367 u32 head;
368 u32 tail;
369 void __iomem *db_reg;
370 };
371
372 struct hns_roce_sge {
373 unsigned int sge_cnt; /* SGE num */
374 int offset;
375 int sge_shift; /* SGE size */
376 };
377
378 struct hns_roce_buf_list {
379 void *buf;
380 dma_addr_t map;
381 };
382
383 /*
384 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
385 * dma address range.
386 *
387 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
388 *
389 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
390 * the allocated size is smaller than the required size.
391 */
392 enum {
393 HNS_ROCE_BUF_DIRECT = BIT(0),
394 HNS_ROCE_BUF_NOSLEEP = BIT(1),
395 HNS_ROCE_BUF_NOFAIL = BIT(2),
396 };
397
398 struct hns_roce_buf {
399 struct hns_roce_buf_list *trunk_list;
400 u32 ntrunks;
401 u32 npages;
402 unsigned int trunk_shift;
403 unsigned int page_shift;
404 };
405
406 struct hns_roce_db_pgdir {
407 struct list_head list;
408 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
409 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
410 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
411 u32 *page;
412 dma_addr_t db_dma;
413 };
414
415 struct hns_roce_user_db_page {
416 struct list_head list;
417 struct ib_umem *umem;
418 unsigned long user_virt;
419 refcount_t refcount;
420 };
421
422 struct hns_roce_db {
423 u32 *db_record;
424 union {
425 struct hns_roce_db_pgdir *pgdir;
426 struct hns_roce_user_db_page *user_page;
427 } u;
428 dma_addr_t dma;
429 void *virt_addr;
430 unsigned long index;
431 unsigned long order;
432 };
433
434 struct hns_roce_cq {
435 struct ib_cq ib_cq;
436 struct hns_roce_mtr mtr;
437 struct hns_roce_db db;
438 u32 flags;
439 spinlock_t lock;
440 u32 cq_depth;
441 u32 cons_index;
442 u32 *set_ci_db;
443 void __iomem *db_reg;
444 u16 *tptr_addr;
445 int arm_sn;
446 int cqe_size;
447 unsigned long cqn;
448 u32 vector;
449 refcount_t refcount;
450 struct completion free;
451 struct list_head sq_list; /* all qps on this send cq */
452 struct list_head rq_list; /* all qps on this recv cq */
453 int is_armed; /* cq is armed */
454 struct list_head node; /* all armed cqs are on a list */
455 };
456
457 struct hns_roce_idx_que {
458 struct hns_roce_mtr mtr;
459 int entry_shift;
460 unsigned long *bitmap;
461 u32 head;
462 u32 tail;
463 };
464
465 struct hns_roce_srq {
466 struct ib_srq ibsrq;
467 unsigned long srqn;
468 u32 wqe_cnt;
469 int max_gs;
470 u32 rsv_sge;
471 int wqe_shift;
472 u32 cqn;
473 u32 xrcdn;
474 void __iomem *db_reg;
475
476 refcount_t refcount;
477 struct completion free;
478
479 struct hns_roce_mtr buf_mtr;
480
481 u64 *wrid;
482 struct hns_roce_idx_que idx_que;
483 spinlock_t lock;
484 struct mutex mutex;
485 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
486 };
487
488 struct hns_roce_uar_table {
489 struct hns_roce_bitmap bitmap;
490 };
491
492 struct hns_roce_bank {
493 struct ida ida;
494 u32 inuse; /* Number of IDs allocated */
495 u32 min; /* Lowest ID to allocate. */
496 u32 max; /* Highest ID to allocate. */
497 u32 next; /* Next ID to allocate. */
498 };
499
500 struct hns_roce_idx_table {
501 u32 *spare_idx;
502 u32 head;
503 u32 tail;
504 };
505
506 struct hns_roce_qp_table {
507 struct hns_roce_hem_table qp_table;
508 struct hns_roce_hem_table irrl_table;
509 struct hns_roce_hem_table trrl_table;
510 struct hns_roce_hem_table sccc_table;
511 struct mutex scc_mutex;
512 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
513 struct mutex bank_mutex;
514 struct hns_roce_idx_table idx_table;
515 };
516
517 struct hns_roce_cq_table {
518 struct xarray array;
519 struct hns_roce_hem_table table;
520 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
521 struct mutex bank_mutex;
522 };
523
524 struct hns_roce_srq_table {
525 struct hns_roce_ida srq_ida;
526 struct xarray xa;
527 struct hns_roce_hem_table table;
528 };
529
530 struct hns_roce_raq_table {
531 struct hns_roce_buf_list *e_raq_buf;
532 };
533
534 struct hns_roce_av {
535 u8 port;
536 u8 gid_index;
537 u8 stat_rate;
538 u8 hop_limit;
539 u32 flowlabel;
540 u16 udp_sport;
541 u8 sl;
542 u8 tclass;
543 u8 dgid[HNS_ROCE_GID_SIZE];
544 u8 mac[ETH_ALEN];
545 u16 vlan_id;
546 u8 vlan_en;
547 };
548
549 struct hns_roce_ah {
550 struct ib_ah ibah;
551 struct hns_roce_av av;
552 };
553
554 struct hns_roce_cmd_context {
555 struct completion done;
556 int result;
557 int next;
558 u64 out_param;
559 u16 token;
560 u16 busy;
561 };
562
563 enum hns_roce_cmdq_state {
564 HNS_ROCE_CMDQ_STATE_NORMAL,
565 HNS_ROCE_CMDQ_STATE_FATAL_ERR,
566 };
567
568 struct hns_roce_cmdq {
569 struct dma_pool *pool;
570 struct semaphore poll_sem;
571 /*
572 * Event mode: cmd register mutex protection,
573 * ensure to not exceed max_cmds and user use limit region
574 */
575 struct semaphore event_sem;
576 int max_cmds;
577 spinlock_t context_lock;
578 int free_head;
579 struct hns_roce_cmd_context *context;
580 /*
581 * Process whether use event mode, init default non-zero
582 * After the event queue of cmd event ready,
583 * can switch into event mode
584 * close device, switch into poll mode(non event mode)
585 */
586 u8 use_events;
587 enum hns_roce_cmdq_state state;
588 };
589
590 struct hns_roce_cmd_mailbox {
591 void *buf;
592 dma_addr_t dma;
593 };
594
595 struct hns_roce_dev;
596
597 struct hns_roce_rinl_sge {
598 void *addr;
599 u32 len;
600 };
601
602 struct hns_roce_rinl_wqe {
603 struct hns_roce_rinl_sge *sg_list;
604 u32 sge_cnt;
605 };
606
607 struct hns_roce_rinl_buf {
608 struct hns_roce_rinl_wqe *wqe_list;
609 u32 wqe_cnt;
610 };
611
612 enum {
613 HNS_ROCE_FLUSH_FLAG = 0,
614 };
615
616 struct hns_roce_work {
617 struct hns_roce_dev *hr_dev;
618 struct work_struct work;
619 int event_type;
620 int sub_type;
621 u32 queue_num;
622 };
623
624 enum {
625 HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5),
626 };
627
628 struct hns_roce_qp {
629 struct ib_qp ibqp;
630 struct hns_roce_wq rq;
631 struct hns_roce_db rdb;
632 struct hns_roce_db sdb;
633 unsigned long en_flags;
634 u32 doorbell_qpn;
635 enum ib_sig_type sq_signal_bits;
636 struct hns_roce_wq sq;
637
638 struct hns_roce_mtr mtr;
639
640 u32 buff_size;
641 struct mutex mutex;
642 u8 port;
643 u8 phy_port;
644 u8 sl;
645 u8 resp_depth;
646 u8 state;
647 u32 access_flags;
648 u32 atomic_rd_en;
649 u32 pkey_index;
650 u32 qkey;
651 void (*event)(struct hns_roce_qp *qp,
652 enum hns_roce_event event_type);
653 unsigned long qpn;
654
655 u32 xrcdn;
656
657 refcount_t refcount;
658 struct completion free;
659
660 struct hns_roce_sge sge;
661 u32 next_sge;
662 enum ib_mtu path_mtu;
663 u32 max_inline_data;
664
665 /* 0: flush needed, 1: unneeded */
666 unsigned long flush_flag;
667 struct hns_roce_work flush_work;
668 struct hns_roce_rinl_buf rq_inl_buf;
669 struct list_head node; /* all qps are on a list */
670 struct list_head rq_node; /* all recv qps are on a list */
671 struct list_head sq_node; /* all send qps are on a list */
672 };
673
674 struct hns_roce_ib_iboe {
675 spinlock_t lock;
676 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
677 struct notifier_block nb;
678 u8 phy_port[HNS_ROCE_MAX_PORTS];
679 };
680
681 enum {
682 HNS_ROCE_EQ_STAT_INVALID = 0,
683 HNS_ROCE_EQ_STAT_VALID = 2,
684 };
685
686 struct hns_roce_ceqe {
687 __le32 comp;
688 __le32 rsv[15];
689 };
690
691 struct hns_roce_aeqe {
692 __le32 asyn;
693 union {
694 struct {
695 __le32 num;
696 u32 rsv0;
697 u32 rsv1;
698 } queue_event;
699
700 struct {
701 __le64 out_param;
702 __le16 token;
703 u8 status;
704 u8 rsv0;
705 } __packed cmd;
706 } event;
707 __le32 rsv[12];
708 };
709
710 struct hns_roce_eq {
711 struct hns_roce_dev *hr_dev;
712 void __iomem *db_reg;
713
714 int type_flag; /* Aeq:1 ceq:0 */
715 int eqn;
716 u32 entries;
717 u32 log_entries;
718 int eqe_size;
719 int irq;
720 int log_page_size;
721 u32 cons_index;
722 struct hns_roce_buf_list *buf_list;
723 int over_ignore;
724 int coalesce;
725 int arm_st;
726 int hop_num;
727 struct hns_roce_mtr mtr;
728 u16 eq_max_cnt;
729 u32 eq_period;
730 int shift;
731 int event_type;
732 int sub_type;
733 };
734
735 struct hns_roce_eq_table {
736 struct hns_roce_eq *eq;
737 void __iomem **eqc_base; /* only for hw v1 */
738 };
739
740 enum cong_type {
741 CONG_TYPE_DCQCN,
742 CONG_TYPE_LDCP,
743 CONG_TYPE_HC3,
744 CONG_TYPE_DIP,
745 };
746
747 struct hns_roce_caps {
748 u64 fw_ver;
749 u8 num_ports;
750 int gid_table_len[HNS_ROCE_MAX_PORTS];
751 int pkey_table_len[HNS_ROCE_MAX_PORTS];
752 int local_ca_ack_delay;
753 int num_uars;
754 u32 phy_num_uars;
755 u32 max_sq_sg;
756 u32 max_sq_inline;
757 u32 max_rq_sg;
758 u32 max_extend_sg;
759 u32 num_qps;
760 u32 num_pi_qps;
761 u32 reserved_qps;
762 int num_qpc_timer;
763 int num_srqs;
764 u32 max_wqes;
765 u32 max_srq_wrs;
766 u32 max_srq_sges;
767 u32 max_sq_desc_sz;
768 u32 max_rq_desc_sz;
769 u32 max_srq_desc_sz;
770 int max_qp_init_rdma;
771 int max_qp_dest_rdma;
772 u32 num_cqs;
773 u32 max_cqes;
774 u32 min_cqes;
775 u32 min_wqes;
776 u32 reserved_cqs;
777 int reserved_srqs;
778 int num_aeq_vectors;
779 int num_comp_vectors;
780 int num_other_vectors;
781 u32 num_mtpts;
782 u32 num_mtt_segs;
783 u32 num_srqwqe_segs;
784 u32 num_idx_segs;
785 int reserved_mrws;
786 int reserved_uars;
787 int num_pds;
788 int reserved_pds;
789 u32 num_xrcds;
790 u32 reserved_xrcds;
791 u32 mtt_entry_sz;
792 u32 cqe_sz;
793 u32 page_size_cap;
794 u32 reserved_lkey;
795 int mtpt_entry_sz;
796 int qpc_sz;
797 int irrl_entry_sz;
798 int trrl_entry_sz;
799 int cqc_entry_sz;
800 int sccc_sz;
801 int qpc_timer_entry_sz;
802 int cqc_timer_entry_sz;
803 int srqc_entry_sz;
804 int idx_entry_sz;
805 u32 pbl_ba_pg_sz;
806 u32 pbl_buf_pg_sz;
807 u32 pbl_hop_num;
808 int aeqe_depth;
809 int ceqe_depth;
810 u32 aeqe_size;
811 u32 ceqe_size;
812 enum ib_mtu max_mtu;
813 u32 qpc_bt_num;
814 u32 qpc_timer_bt_num;
815 u32 srqc_bt_num;
816 u32 cqc_bt_num;
817 u32 cqc_timer_bt_num;
818 u32 mpt_bt_num;
819 u32 eqc_bt_num;
820 u32 smac_bt_num;
821 u32 sgid_bt_num;
822 u32 sccc_bt_num;
823 u32 gmv_bt_num;
824 u32 qpc_ba_pg_sz;
825 u32 qpc_buf_pg_sz;
826 u32 qpc_hop_num;
827 u32 srqc_ba_pg_sz;
828 u32 srqc_buf_pg_sz;
829 u32 srqc_hop_num;
830 u32 cqc_ba_pg_sz;
831 u32 cqc_buf_pg_sz;
832 u32 cqc_hop_num;
833 u32 mpt_ba_pg_sz;
834 u32 mpt_buf_pg_sz;
835 u32 mpt_hop_num;
836 u32 mtt_ba_pg_sz;
837 u32 mtt_buf_pg_sz;
838 u32 mtt_hop_num;
839 u32 wqe_sq_hop_num;
840 u32 wqe_sge_hop_num;
841 u32 wqe_rq_hop_num;
842 u32 sccc_ba_pg_sz;
843 u32 sccc_buf_pg_sz;
844 u32 sccc_hop_num;
845 u32 qpc_timer_ba_pg_sz;
846 u32 qpc_timer_buf_pg_sz;
847 u32 qpc_timer_hop_num;
848 u32 cqc_timer_ba_pg_sz;
849 u32 cqc_timer_buf_pg_sz;
850 u32 cqc_timer_hop_num;
851 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
852 u32 cqe_buf_pg_sz;
853 u32 cqe_hop_num;
854 u32 srqwqe_ba_pg_sz;
855 u32 srqwqe_buf_pg_sz;
856 u32 srqwqe_hop_num;
857 u32 idx_ba_pg_sz;
858 u32 idx_buf_pg_sz;
859 u32 idx_hop_num;
860 u32 eqe_ba_pg_sz;
861 u32 eqe_buf_pg_sz;
862 u32 eqe_hop_num;
863 u32 gmv_entry_num;
864 u32 gmv_entry_sz;
865 u32 gmv_ba_pg_sz;
866 u32 gmv_buf_pg_sz;
867 u32 gmv_hop_num;
868 u32 sl_num;
869 u32 llm_buf_pg_sz;
870 u32 chunk_sz; /* chunk size in non multihop mode */
871 u64 flags;
872 u16 default_ceq_max_cnt;
873 u16 default_ceq_period;
874 u16 default_aeq_max_cnt;
875 u16 default_aeq_period;
876 u16 default_aeq_arm_st;
877 u16 default_ceq_arm_st;
878 enum cong_type cong_type;
879 };
880
881 struct hns_roce_dfx_hw {
882 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
883 int *buffer);
884 };
885
886 enum hns_roce_device_state {
887 HNS_ROCE_DEVICE_STATE_INITED,
888 HNS_ROCE_DEVICE_STATE_RST_DOWN,
889 HNS_ROCE_DEVICE_STATE_UNINIT,
890 };
891
892 struct hns_roce_hw {
893 int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
894 int (*cmq_init)(struct hns_roce_dev *hr_dev);
895 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
896 int (*hw_profile)(struct hns_roce_dev *hr_dev);
897 int (*hw_init)(struct hns_roce_dev *hr_dev);
898 void (*hw_exit)(struct hns_roce_dev *hr_dev);
899 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
900 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
901 u16 token, int event);
902 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev,
903 unsigned int timeout);
904 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
905 int (*set_gid)(struct hns_roce_dev *hr_dev, u32 port, int gid_index,
906 const union ib_gid *gid, const struct ib_gid_attr *attr);
907 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
908 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
909 enum ib_mtu mtu);
910 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
911 struct hns_roce_mr *mr, unsigned long mtpt_idx);
912 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
913 struct hns_roce_mr *mr, int flags,
914 void *mb_buf);
915 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
916 struct hns_roce_mr *mr);
917 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
918 void (*write_cqc)(struct hns_roce_dev *hr_dev,
919 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
920 dma_addr_t dma_handle);
921 int (*set_hem)(struct hns_roce_dev *hr_dev,
922 struct hns_roce_hem_table *table, int obj, int step_idx);
923 int (*clear_hem)(struct hns_roce_dev *hr_dev,
924 struct hns_roce_hem_table *table, int obj,
925 int step_idx);
926 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
927 int attr_mask, enum ib_qp_state cur_state,
928 enum ib_qp_state new_state);
929 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
930 struct hns_roce_qp *hr_qp);
931 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
932 struct ib_udata *udata);
933 int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
934 int (*init_eq)(struct hns_roce_dev *hr_dev);
935 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
936 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
937 const struct ib_device_ops *hns_roce_dev_ops;
938 const struct ib_device_ops *hns_roce_dev_srq_ops;
939 };
940
941 struct hns_roce_dev {
942 struct ib_device ib_dev;
943 struct platform_device *pdev;
944 struct pci_dev *pci_dev;
945 struct device *dev;
946 struct hns_roce_uar priv_uar;
947 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
948 spinlock_t sm_lock;
949 spinlock_t bt_cmd_lock;
950 bool active;
951 bool is_reset;
952 bool dis_db;
953 unsigned long reset_cnt;
954 struct hns_roce_ib_iboe iboe;
955 enum hns_roce_device_state state;
956 struct list_head qp_list; /* list of all qps on this dev */
957 spinlock_t qp_list_lock; /* protect qp_list */
958 struct list_head dip_list; /* list of all dest ips on this dev */
959 spinlock_t dip_list_lock; /* protect dip_list */
960
961 struct list_head pgdir_list;
962 struct mutex pgdir_mutex;
963 int irq[HNS_ROCE_MAX_IRQ_NUM];
964 u8 __iomem *reg_base;
965 void __iomem *mem_base;
966 struct hns_roce_caps caps;
967 struct xarray qp_table_xa;
968
969 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
970 u64 sys_image_guid;
971 u32 vendor_id;
972 u32 vendor_part_id;
973 u32 hw_rev;
974 void __iomem *priv_addr;
975
976 struct hns_roce_cmdq cmd;
977 struct hns_roce_ida pd_ida;
978 struct hns_roce_ida xrcd_ida;
979 struct hns_roce_ida uar_ida;
980 struct hns_roce_mr_table mr_table;
981 struct hns_roce_cq_table cq_table;
982 struct hns_roce_srq_table srq_table;
983 struct hns_roce_qp_table qp_table;
984 struct hns_roce_eq_table eq_table;
985 struct hns_roce_hem_table qpc_timer_table;
986 struct hns_roce_hem_table cqc_timer_table;
987 /* GMV is the memory area that the driver allocates for the hardware
988 * to store SGID, SMAC and VLAN information.
989 */
990 struct hns_roce_hem_table gmv_table;
991
992 int cmd_mod;
993 int loop_idc;
994 u32 sdb_offset;
995 u32 odb_offset;
996 dma_addr_t tptr_dma_addr; /* only for hw v1 */
997 u32 tptr_size; /* only for hw v1 */
998 const struct hns_roce_hw *hw;
999 void *priv;
1000 struct workqueue_struct *irq_workq;
1001 const struct hns_roce_dfx_hw *dfx;
1002 u32 func_num;
1003 u32 is_vf;
1004 u32 cong_algo_tmpl_id;
1005 };
1006
to_hr_dev(struct ib_device * ib_dev)1007 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1008 {
1009 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1010 }
1011
1012 static inline struct hns_roce_ucontext
to_hr_ucontext(struct ib_ucontext * ibucontext)1013 *to_hr_ucontext(struct ib_ucontext *ibucontext)
1014 {
1015 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1016 }
1017
to_hr_pd(struct ib_pd * ibpd)1018 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1019 {
1020 return container_of(ibpd, struct hns_roce_pd, ibpd);
1021 }
1022
to_hr_xrcd(struct ib_xrcd * ibxrcd)1023 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
1024 {
1025 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
1026 }
1027
to_hr_ah(struct ib_ah * ibah)1028 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1029 {
1030 return container_of(ibah, struct hns_roce_ah, ibah);
1031 }
1032
to_hr_mr(struct ib_mr * ibmr)1033 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1034 {
1035 return container_of(ibmr, struct hns_roce_mr, ibmr);
1036 }
1037
to_hr_mw(struct ib_mw * ibmw)1038 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1039 {
1040 return container_of(ibmw, struct hns_roce_mw, ibmw);
1041 }
1042
to_hr_qp(struct ib_qp * ibqp)1043 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1044 {
1045 return container_of(ibqp, struct hns_roce_qp, ibqp);
1046 }
1047
to_hr_cq(struct ib_cq * ib_cq)1048 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1049 {
1050 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1051 }
1052
to_hr_srq(struct ib_srq * ibsrq)1053 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1054 {
1055 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1056 }
1057
hns_roce_write64_k(__le32 val[2],void __iomem * dest)1058 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1059 {
1060 writeq(*(u64 *)val, dest);
1061 }
1062
1063 static inline struct hns_roce_qp
__hns_roce_qp_lookup(struct hns_roce_dev * hr_dev,u32 qpn)1064 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1065 {
1066 return xa_load(&hr_dev->qp_table_xa, qpn);
1067 }
1068
hns_roce_buf_offset(struct hns_roce_buf * buf,unsigned int offset)1069 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1070 unsigned int offset)
1071 {
1072 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1073 (offset & ((1 << buf->trunk_shift) - 1));
1074 }
1075
hns_roce_buf_dma_addr(struct hns_roce_buf * buf,unsigned int offset)1076 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
1077 unsigned int offset)
1078 {
1079 return buf->trunk_list[offset >> buf->trunk_shift].map +
1080 (offset & ((1 << buf->trunk_shift) - 1));
1081 }
1082
hns_roce_buf_page(struct hns_roce_buf * buf,u32 idx)1083 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1084 {
1085 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
1086 }
1087
1088 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1089
to_hr_hw_page_addr(u64 addr)1090 static inline u64 to_hr_hw_page_addr(u64 addr)
1091 {
1092 return addr >> HNS_HW_PAGE_SHIFT;
1093 }
1094
to_hr_hw_page_shift(u32 page_shift)1095 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1096 {
1097 return page_shift - HNS_HW_PAGE_SHIFT;
1098 }
1099
to_hr_hem_hopnum(u32 hopnum,u32 count)1100 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1101 {
1102 if (count > 0)
1103 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1104
1105 return 0;
1106 }
1107
to_hr_hem_entries_size(u32 count,u32 buf_shift)1108 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1109 {
1110 return hr_hw_page_align(count << buf_shift);
1111 }
1112
to_hr_hem_entries_count(u32 count,u32 buf_shift)1113 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1114 {
1115 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1116 }
1117
to_hr_hem_entries_shift(u32 count,u32 buf_shift)1118 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1119 {
1120 if (!count)
1121 return 0;
1122
1123 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1124 }
1125
1126 #define DSCP_SHIFT 2
1127
get_tclass(const struct ib_global_route * grh)1128 static inline u8 get_tclass(const struct ib_global_route *grh)
1129 {
1130 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1131 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1132 }
1133
1134 void hns_roce_init_uar_table(struct hns_roce_dev *dev);
1135 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1136
1137 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1138 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1139 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1140 u64 out_param);
1141 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1142 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1143
1144 /* hns roce hw need current block and next block addr from mtt */
1145 #define MTT_MIN_COUNT 2
1146 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1147 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1148 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1149 struct hns_roce_buf_attr *buf_attr,
1150 unsigned int page_shift, struct ib_udata *udata,
1151 unsigned long user_addr);
1152 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1153 struct hns_roce_mtr *mtr);
1154 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1155 dma_addr_t *pages, unsigned int page_cnt);
1156
1157 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1158 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1159 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1160 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1161 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1162 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1163
1164 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1165 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1166 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1167
1168 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1169
1170 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1171 struct ib_udata *udata);
1172 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
hns_roce_destroy_ah(struct ib_ah * ah,u32 flags)1173 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1174 {
1175 return 0;
1176 }
1177
1178 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1179 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1180
1181 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1182 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1183 u64 virt_addr, int access_flags,
1184 struct ib_udata *udata);
1185 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1186 u64 length, u64 virt_addr,
1187 int mr_access_flags, struct ib_pd *pd,
1188 struct ib_udata *udata);
1189 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1190 u32 max_num_sg);
1191 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1192 unsigned int *sg_offset);
1193 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1194 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1195 struct hns_roce_cmd_mailbox *mailbox,
1196 unsigned long mpt_index);
1197 unsigned long key_to_hw_index(u32 key);
1198
1199 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1200 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1201
1202 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1203 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1204 u32 page_shift, u32 flags);
1205
1206 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1207 int buf_cnt, struct hns_roce_buf *buf,
1208 unsigned int page_shift);
1209 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1210 int buf_cnt, struct ib_umem *umem,
1211 unsigned int page_shift);
1212
1213 int hns_roce_create_srq(struct ib_srq *srq,
1214 struct ib_srq_init_attr *srq_init_attr,
1215 struct ib_udata *udata);
1216 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1217 enum ib_srq_attr_mask srq_attr_mask,
1218 struct ib_udata *udata);
1219 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1220
1221 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1222 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1223
1224 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr,
1225 struct ib_udata *udata);
1226 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1227 int attr_mask, struct ib_udata *udata);
1228 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1229 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1230 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1231 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1232 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1233 struct ib_cq *ib_cq);
1234 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1235 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1236 struct hns_roce_cq *recv_cq);
1237 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1238 struct hns_roce_cq *recv_cq);
1239 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1240 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1241 struct ib_udata *udata);
1242 __be32 send_ieth(const struct ib_send_wr *wr);
1243 int to_hr_qp_type(int qp_type);
1244
1245 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1246 struct ib_udata *udata);
1247
1248 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1249 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1250 struct hns_roce_db *db);
1251 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1252 struct hns_roce_db *db);
1253 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1254 int order);
1255 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1256
1257 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1258 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1259 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1260 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1261 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1262 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index);
1263 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1264 int hns_roce_init(struct hns_roce_dev *hr_dev);
1265 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1266 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1267 struct ib_cq *ib_cq);
1268 #endif /* _HNS_ROCE_DEVICE_H */
1269