1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
3 #include "osdep.h"
4 #include "status.h"
5 #include "hmc.h"
6 #include "defs.h"
7 #include "type.h"
8 #include "ws.h"
9 #include "protos.h"
10
11 /**
12 * irdma_get_qp_from_list - get next qp from a list
13 * @head: Listhead of qp's
14 * @qp: current qp
15 */
irdma_get_qp_from_list(struct list_head * head,struct irdma_sc_qp * qp)16 struct irdma_sc_qp *irdma_get_qp_from_list(struct list_head *head,
17 struct irdma_sc_qp *qp)
18 {
19 struct list_head *lastentry;
20 struct list_head *entry = NULL;
21
22 if (list_empty(head))
23 return NULL;
24
25 if (!qp) {
26 entry = head->next;
27 } else {
28 lastentry = &qp->list;
29 entry = lastentry->next;
30 if (entry == head)
31 return NULL;
32 }
33
34 return container_of(entry, struct irdma_sc_qp, list);
35 }
36
37 /**
38 * irdma_sc_suspend_resume_qps - suspend/resume all qp's on VSI
39 * @vsi: the VSI struct pointer
40 * @op: Set to IRDMA_OP_RESUME or IRDMA_OP_SUSPEND
41 */
irdma_sc_suspend_resume_qps(struct irdma_sc_vsi * vsi,u8 op)42 void irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 op)
43 {
44 struct irdma_sc_qp *qp = NULL;
45 u8 i;
46
47 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
48 mutex_lock(&vsi->qos[i].qos_mutex);
49 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp);
50 while (qp) {
51 if (op == IRDMA_OP_RESUME) {
52 if (!qp->dev->ws_add(vsi, i)) {
53 qp->qs_handle =
54 vsi->qos[qp->user_pri].qs_handle;
55 irdma_cqp_qp_suspend_resume(qp, op);
56 } else {
57 irdma_cqp_qp_suspend_resume(qp, op);
58 irdma_modify_qp_to_err(qp);
59 }
60 } else if (op == IRDMA_OP_SUSPEND) {
61 /* issue cqp suspend command */
62 if (!irdma_cqp_qp_suspend_resume(qp, op))
63 atomic_inc(&vsi->qp_suspend_reqs);
64 }
65 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp);
66 }
67 mutex_unlock(&vsi->qos[i].qos_mutex);
68 }
69 }
70
71 /**
72 * irdma_change_l2params - given the new l2 parameters, change all qp
73 * @vsi: RDMA VSI pointer
74 * @l2params: New parameters from l2
75 */
irdma_change_l2params(struct irdma_sc_vsi * vsi,struct irdma_l2params * l2params)76 void irdma_change_l2params(struct irdma_sc_vsi *vsi,
77 struct irdma_l2params *l2params)
78 {
79 if (l2params->mtu_changed) {
80 vsi->mtu = l2params->mtu;
81 if (vsi->ieq)
82 irdma_reinitialize_ieq(vsi);
83 }
84
85 if (!l2params->tc_changed)
86 return;
87
88 vsi->tc_change_pending = false;
89 irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME);
90 }
91
92 /**
93 * irdma_qp_rem_qos - remove qp from qos lists during destroy qp
94 * @qp: qp to be removed from qos
95 */
irdma_qp_rem_qos(struct irdma_sc_qp * qp)96 void irdma_qp_rem_qos(struct irdma_sc_qp *qp)
97 {
98 struct irdma_sc_vsi *vsi = qp->vsi;
99
100 ibdev_dbg(to_ibdev(qp->dev),
101 "DCB: DCB: Remove qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n",
102 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle,
103 qp->on_qoslist);
104 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex);
105 if (qp->on_qoslist) {
106 qp->on_qoslist = false;
107 list_del(&qp->list);
108 }
109 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex);
110 }
111
112 /**
113 * irdma_qp_add_qos - called during setctx for qp to be added to qos
114 * @qp: qp to be added to qos
115 */
irdma_qp_add_qos(struct irdma_sc_qp * qp)116 void irdma_qp_add_qos(struct irdma_sc_qp *qp)
117 {
118 struct irdma_sc_vsi *vsi = qp->vsi;
119
120 ibdev_dbg(to_ibdev(qp->dev),
121 "DCB: DCB: Add qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n",
122 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle,
123 qp->on_qoslist);
124 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex);
125 if (!qp->on_qoslist) {
126 list_add(&qp->list, &vsi->qos[qp->user_pri].qplist);
127 qp->on_qoslist = true;
128 qp->qs_handle = vsi->qos[qp->user_pri].qs_handle;
129 }
130 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex);
131 }
132
133 /**
134 * irdma_sc_pd_init - initialize sc pd struct
135 * @dev: sc device struct
136 * @pd: sc pd ptr
137 * @pd_id: pd_id for allocated pd
138 * @abi_ver: User/Kernel ABI version
139 */
irdma_sc_pd_init(struct irdma_sc_dev * dev,struct irdma_sc_pd * pd,u32 pd_id,int abi_ver)140 void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id,
141 int abi_ver)
142 {
143 pd->pd_id = pd_id;
144 pd->abi_ver = abi_ver;
145 pd->dev = dev;
146 }
147
148 /**
149 * irdma_sc_add_arp_cache_entry - cqp wqe add arp cache entry
150 * @cqp: struct for cqp hw
151 * @info: arp entry information
152 * @scratch: u64 saved to be used during cqp completion
153 * @post_sq: flag for cqp db to ring
154 */
155 static enum irdma_status_code
irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp * cqp,struct irdma_add_arp_cache_entry_info * info,u64 scratch,bool post_sq)156 irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp *cqp,
157 struct irdma_add_arp_cache_entry_info *info,
158 u64 scratch, bool post_sq)
159 {
160 __le64 *wqe;
161 u64 hdr;
162
163 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
164 if (!wqe)
165 return IRDMA_ERR_RING_FULL;
166 set_64bit_val(wqe, 8, info->reach_max);
167 set_64bit_val(wqe, 16, ether_addr_to_u64(info->mac_addr));
168
169 hdr = info->arp_index |
170 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) |
171 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, (info->permanent ? 1 : 0)) |
172 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, 1) |
173 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
174 dma_wmb(); /* make sure WQE is written before valid bit is set */
175
176 set_64bit_val(wqe, 24, hdr);
177
178 print_hex_dump_debug("WQE: ARP_CACHE_ENTRY WQE", DUMP_PREFIX_OFFSET,
179 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
180 if (post_sq)
181 irdma_sc_cqp_post_sq(cqp);
182
183 return 0;
184 }
185
186 /**
187 * irdma_sc_del_arp_cache_entry - dele arp cache entry
188 * @cqp: struct for cqp hw
189 * @scratch: u64 saved to be used during cqp completion
190 * @arp_index: arp index to delete arp entry
191 * @post_sq: flag for cqp db to ring
192 */
193 static enum irdma_status_code
irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp * cqp,u64 scratch,u16 arp_index,bool post_sq)194 irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch,
195 u16 arp_index, bool post_sq)
196 {
197 __le64 *wqe;
198 u64 hdr;
199
200 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
201 if (!wqe)
202 return IRDMA_ERR_RING_FULL;
203
204 hdr = arp_index |
205 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) |
206 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
207 dma_wmb(); /* make sure WQE is written before valid bit is set */
208
209 set_64bit_val(wqe, 24, hdr);
210
211 print_hex_dump_debug("WQE: ARP_CACHE_DEL_ENTRY WQE",
212 DUMP_PREFIX_OFFSET, 16, 8, wqe,
213 IRDMA_CQP_WQE_SIZE * 8, false);
214 if (post_sq)
215 irdma_sc_cqp_post_sq(cqp);
216
217 return 0;
218 }
219
220 /**
221 * irdma_sc_manage_apbvt_entry - for adding and deleting apbvt entries
222 * @cqp: struct for cqp hw
223 * @info: info for apbvt entry to add or delete
224 * @scratch: u64 saved to be used during cqp completion
225 * @post_sq: flag for cqp db to ring
226 */
227 static enum irdma_status_code
irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp * cqp,struct irdma_apbvt_info * info,u64 scratch,bool post_sq)228 irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp *cqp,
229 struct irdma_apbvt_info *info, u64 scratch,
230 bool post_sq)
231 {
232 __le64 *wqe;
233 u64 hdr;
234
235 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
236 if (!wqe)
237 return IRDMA_ERR_RING_FULL;
238
239 set_64bit_val(wqe, 16, info->port);
240
241 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) |
242 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) |
243 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
244 dma_wmb(); /* make sure WQE is written before valid bit is set */
245
246 set_64bit_val(wqe, 24, hdr);
247
248 print_hex_dump_debug("WQE: MANAGE_APBVT WQE", DUMP_PREFIX_OFFSET, 16,
249 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
250 if (post_sq)
251 irdma_sc_cqp_post_sq(cqp);
252
253 return 0;
254 }
255
256 /**
257 * irdma_sc_manage_qhash_table_entry - manage quad hash entries
258 * @cqp: struct for cqp hw
259 * @info: info for quad hash to manage
260 * @scratch: u64 saved to be used during cqp completion
261 * @post_sq: flag for cqp db to ring
262 *
263 * This is called before connection establishment is started.
264 * For passive connections, when listener is created, it will
265 * call with entry type of IRDMA_QHASH_TYPE_TCP_SYN with local
266 * ip address and tcp port. When SYN is received (passive
267 * connections) or sent (active connections), this routine is
268 * called with entry type of IRDMA_QHASH_TYPE_TCP_ESTABLISHED
269 * and quad is passed in info.
270 *
271 * When iwarp connection is done and its state moves to RTS, the
272 * quad hash entry in the hardware will point to iwarp's qp
273 * number and requires no calls from the driver.
274 */
275 static enum irdma_status_code
irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp * cqp,struct irdma_qhash_table_info * info,u64 scratch,bool post_sq)276 irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp *cqp,
277 struct irdma_qhash_table_info *info,
278 u64 scratch, bool post_sq)
279 {
280 __le64 *wqe;
281 u64 qw1 = 0;
282 u64 qw2 = 0;
283 u64 temp;
284 struct irdma_sc_vsi *vsi = info->vsi;
285
286 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
287 if (!wqe)
288 return IRDMA_ERR_RING_FULL;
289
290 set_64bit_val(wqe, 0, ether_addr_to_u64(info->mac_addr));
291
292 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) |
293 FIELD_PREP(IRDMA_CQPSQ_QHASH_DEST_PORT, info->dest_port);
294 if (info->ipv4_valid) {
295 set_64bit_val(wqe, 48,
296 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[0]));
297 } else {
298 set_64bit_val(wqe, 56,
299 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->dest_ip[0]) |
300 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->dest_ip[1]));
301
302 set_64bit_val(wqe, 48,
303 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->dest_ip[2]) |
304 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[3]));
305 }
306 qw2 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QS_HANDLE,
307 vsi->qos[info->user_pri].qs_handle);
308 if (info->vlan_valid)
309 qw2 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANID, info->vlan_id);
310 set_64bit_val(wqe, 16, qw2);
311 if (info->entry_type == IRDMA_QHASH_TYPE_TCP_ESTABLISHED) {
312 qw1 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_SRC_PORT, info->src_port);
313 if (!info->ipv4_valid) {
314 set_64bit_val(wqe, 40,
315 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->src_ip[0]) |
316 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->src_ip[1]));
317 set_64bit_val(wqe, 32,
318 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->src_ip[2]) |
319 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[3]));
320 } else {
321 set_64bit_val(wqe, 32,
322 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[0]));
323 }
324 }
325
326 set_64bit_val(wqe, 8, qw1);
327 temp = FIELD_PREP(IRDMA_CQPSQ_QHASH_WQEVALID, cqp->polarity) |
328 FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE,
329 IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY) |
330 FIELD_PREP(IRDMA_CQPSQ_QHASH_MANAGE, info->manage) |
331 FIELD_PREP(IRDMA_CQPSQ_QHASH_IPV4VALID, info->ipv4_valid) |
332 FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANVALID, info->vlan_valid) |
333 FIELD_PREP(IRDMA_CQPSQ_QHASH_ENTRYTYPE, info->entry_type);
334 dma_wmb(); /* make sure WQE is written before valid bit is set */
335
336 set_64bit_val(wqe, 24, temp);
337
338 print_hex_dump_debug("WQE: MANAGE_QHASH WQE", DUMP_PREFIX_OFFSET, 16,
339 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
340 if (post_sq)
341 irdma_sc_cqp_post_sq(cqp);
342
343 return 0;
344 }
345
346 /**
347 * irdma_sc_qp_init - initialize qp
348 * @qp: sc qp
349 * @info: initialization qp info
350 */
irdma_sc_qp_init(struct irdma_sc_qp * qp,struct irdma_qp_init_info * info)351 enum irdma_status_code irdma_sc_qp_init(struct irdma_sc_qp *qp,
352 struct irdma_qp_init_info *info)
353 {
354 enum irdma_status_code ret_code;
355 u32 pble_obj_cnt;
356 u16 wqe_size;
357
358 if (info->qp_uk_init_info.max_sq_frag_cnt >
359 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags ||
360 info->qp_uk_init_info.max_rq_frag_cnt >
361 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags)
362 return IRDMA_ERR_INVALID_FRAG_COUNT;
363
364 qp->dev = info->pd->dev;
365 qp->vsi = info->vsi;
366 qp->ieq_qp = info->vsi->exception_lan_q;
367 qp->sq_pa = info->sq_pa;
368 qp->rq_pa = info->rq_pa;
369 qp->hw_host_ctx_pa = info->host_ctx_pa;
370 qp->q2_pa = info->q2_pa;
371 qp->shadow_area_pa = info->shadow_area_pa;
372 qp->q2_buf = info->q2;
373 qp->pd = info->pd;
374 qp->hw_host_ctx = info->host_ctx;
375 info->qp_uk_init_info.wqe_alloc_db = qp->pd->dev->wqe_alloc_db;
376 ret_code = irdma_uk_qp_init(&qp->qp_uk, &info->qp_uk_init_info);
377 if (ret_code)
378 return ret_code;
379
380 qp->virtual_map = info->virtual_map;
381 pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
382
383 if ((info->virtual_map && info->sq_pa >= pble_obj_cnt) ||
384 (info->virtual_map && info->rq_pa >= pble_obj_cnt))
385 return IRDMA_ERR_INVALID_PBLE_INDEX;
386
387 qp->llp_stream_handle = (void *)(-1);
388 qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size,
389 IRDMA_QUEUE_TYPE_SQ_RQ);
390 ibdev_dbg(to_ibdev(qp->dev),
391 "WQE: hw_sq_size[%04d] sq_ring.size[%04d]\n",
392 qp->hw_sq_size, qp->qp_uk.sq_ring.size);
393 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1 && qp->pd->abi_ver > 4)
394 wqe_size = IRDMA_WQE_SIZE_128;
395 else
396 ret_code = irdma_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt,
397 &wqe_size);
398 if (ret_code)
399 return ret_code;
400
401 qp->hw_rq_size = irdma_get_encoded_wqe_size(qp->qp_uk.rq_size *
402 (wqe_size / IRDMA_QP_WQE_MIN_SIZE), IRDMA_QUEUE_TYPE_SQ_RQ);
403 ibdev_dbg(to_ibdev(qp->dev),
404 "WQE: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n",
405 qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size);
406 qp->sq_tph_val = info->sq_tph_val;
407 qp->rq_tph_val = info->rq_tph_val;
408 qp->sq_tph_en = info->sq_tph_en;
409 qp->rq_tph_en = info->rq_tph_en;
410 qp->rcv_tph_en = info->rcv_tph_en;
411 qp->xmit_tph_en = info->xmit_tph_en;
412 qp->qp_uk.first_sq_wq = info->qp_uk_init_info.first_sq_wq;
413 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle;
414
415 return 0;
416 }
417
418 /**
419 * irdma_sc_qp_create - create qp
420 * @qp: sc qp
421 * @info: qp create info
422 * @scratch: u64 saved to be used during cqp completion
423 * @post_sq: flag for cqp db to ring
424 */
irdma_sc_qp_create(struct irdma_sc_qp * qp,struct irdma_create_qp_info * info,u64 scratch,bool post_sq)425 enum irdma_status_code irdma_sc_qp_create(struct irdma_sc_qp *qp, struct irdma_create_qp_info *info,
426 u64 scratch, bool post_sq)
427 {
428 struct irdma_sc_cqp *cqp;
429 __le64 *wqe;
430 u64 hdr;
431
432 cqp = qp->dev->cqp;
433 if (qp->qp_uk.qp_id < cqp->dev->hw_attrs.min_hw_qp_id ||
434 qp->qp_uk.qp_id >= (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt))
435 return IRDMA_ERR_INVALID_QP_ID;
436
437 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
438 if (!wqe)
439 return IRDMA_ERR_RING_FULL;
440
441 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
442 set_64bit_val(wqe, 40, qp->shadow_area_pa);
443
444 hdr = qp->qp_uk.qp_id |
445 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) |
446 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, (info->ord_valid ? 1 : 0)) |
447 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) |
448 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) |
449 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) |
450 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) |
451 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) |
452 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) |
453 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID,
454 info->arp_cache_idx_valid) |
455 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) |
456 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
457 dma_wmb(); /* make sure WQE is written before valid bit is set */
458
459 set_64bit_val(wqe, 24, hdr);
460
461 print_hex_dump_debug("WQE: QP_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8,
462 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
463 if (post_sq)
464 irdma_sc_cqp_post_sq(cqp);
465
466 return 0;
467 }
468
469 /**
470 * irdma_sc_qp_modify - modify qp cqp wqe
471 * @qp: sc qp
472 * @info: modify qp info
473 * @scratch: u64 saved to be used during cqp completion
474 * @post_sq: flag for cqp db to ring
475 */
irdma_sc_qp_modify(struct irdma_sc_qp * qp,struct irdma_modify_qp_info * info,u64 scratch,bool post_sq)476 enum irdma_status_code irdma_sc_qp_modify(struct irdma_sc_qp *qp,
477 struct irdma_modify_qp_info *info,
478 u64 scratch, bool post_sq)
479 {
480 __le64 *wqe;
481 struct irdma_sc_cqp *cqp;
482 u64 hdr;
483 u8 term_actions = 0;
484 u8 term_len = 0;
485
486 cqp = qp->dev->cqp;
487 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
488 if (!wqe)
489 return IRDMA_ERR_RING_FULL;
490
491 if (info->next_iwarp_state == IRDMA_QP_STATE_TERMINATE) {
492 if (info->dont_send_fin)
493 term_actions += IRDMAQP_TERM_SEND_TERM_ONLY;
494 if (info->dont_send_term)
495 term_actions += IRDMAQP_TERM_SEND_FIN_ONLY;
496 if (term_actions == IRDMAQP_TERM_SEND_TERM_AND_FIN ||
497 term_actions == IRDMAQP_TERM_SEND_TERM_ONLY)
498 term_len = info->termlen;
499 }
500
501 set_64bit_val(wqe, 8,
502 FIELD_PREP(IRDMA_CQPSQ_QP_NEWMSS, info->new_mss) |
503 FIELD_PREP(IRDMA_CQPSQ_QP_TERMLEN, term_len));
504 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
505 set_64bit_val(wqe, 40, qp->shadow_area_pa);
506
507 hdr = qp->qp_uk.qp_id |
508 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_QP) |
509 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) |
510 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) |
511 FIELD_PREP(IRDMA_CQPSQ_QP_CACHEDVARVALID,
512 info->cached_var_valid) |
513 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) |
514 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) |
515 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) |
516 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) |
517 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) |
518 FIELD_PREP(IRDMA_CQPSQ_QP_MSSCHANGE, info->mss_change) |
519 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY,
520 info->remove_hash_idx) |
521 FIELD_PREP(IRDMA_CQPSQ_QP_TERMACT, term_actions) |
522 FIELD_PREP(IRDMA_CQPSQ_QP_RESETCON, info->reset_tcp_conn) |
523 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID,
524 info->arp_cache_idx_valid) |
525 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) |
526 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
527 dma_wmb(); /* make sure WQE is written before valid bit is set */
528
529 set_64bit_val(wqe, 24, hdr);
530
531 print_hex_dump_debug("WQE: QP_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8,
532 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
533 if (post_sq)
534 irdma_sc_cqp_post_sq(cqp);
535
536 return 0;
537 }
538
539 /**
540 * irdma_sc_qp_destroy - cqp destroy qp
541 * @qp: sc qp
542 * @scratch: u64 saved to be used during cqp completion
543 * @remove_hash_idx: flag if to remove hash idx
544 * @ignore_mw_bnd: memory window bind flag
545 * @post_sq: flag for cqp db to ring
546 */
irdma_sc_qp_destroy(struct irdma_sc_qp * qp,u64 scratch,bool remove_hash_idx,bool ignore_mw_bnd,bool post_sq)547 enum irdma_status_code irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch,
548 bool remove_hash_idx, bool ignore_mw_bnd,
549 bool post_sq)
550 {
551 __le64 *wqe;
552 struct irdma_sc_cqp *cqp;
553 u64 hdr;
554
555 cqp = qp->dev->cqp;
556 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
557 if (!wqe)
558 return IRDMA_ERR_RING_FULL;
559
560 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
561 set_64bit_val(wqe, 40, qp->shadow_area_pa);
562
563 hdr = qp->qp_uk.qp_id |
564 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_QP) |
565 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) |
566 FIELD_PREP(IRDMA_CQPSQ_QP_IGNOREMWBOUND, ignore_mw_bnd) |
567 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, remove_hash_idx) |
568 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
569 dma_wmb(); /* make sure WQE is written before valid bit is set */
570
571 set_64bit_val(wqe, 24, hdr);
572
573 print_hex_dump_debug("WQE: QP_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8,
574 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
575 if (post_sq)
576 irdma_sc_cqp_post_sq(cqp);
577
578 return 0;
579 }
580
581 /**
582 * irdma_sc_get_encoded_ird_size -
583 * @ird_size: IRD size
584 * The ird from the connection is rounded to a supported HW setting and then encoded
585 * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based
586 * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input
587 */
irdma_sc_get_encoded_ird_size(u16 ird_size)588 static u8 irdma_sc_get_encoded_ird_size(u16 ird_size)
589 {
590 switch (ird_size ?
591 roundup_pow_of_two(2 * ird_size) : 4) {
592 case 256:
593 return IRDMA_IRD_HW_SIZE_256;
594 case 128:
595 return IRDMA_IRD_HW_SIZE_128;
596 case 64:
597 case 32:
598 return IRDMA_IRD_HW_SIZE_64;
599 case 16:
600 case 8:
601 return IRDMA_IRD_HW_SIZE_16;
602 case 4:
603 default:
604 break;
605 }
606
607 return IRDMA_IRD_HW_SIZE_4;
608 }
609
610 /**
611 * irdma_sc_qp_setctx_roce - set qp's context
612 * @qp: sc qp
613 * @qp_ctx: context ptr
614 * @info: ctx info
615 */
irdma_sc_qp_setctx_roce(struct irdma_sc_qp * qp,__le64 * qp_ctx,struct irdma_qp_host_ctx_info * info)616 void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx,
617 struct irdma_qp_host_ctx_info *info)
618 {
619 struct irdma_roce_offload_info *roce_info;
620 struct irdma_udp_offload_info *udp;
621 u8 push_mode_en;
622 u32 push_idx;
623
624 roce_info = info->roce_info;
625 udp = info->udp_info;
626 qp->user_pri = info->user_pri;
627 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) {
628 push_mode_en = 0;
629 push_idx = 0;
630 } else {
631 push_mode_en = 1;
632 push_idx = qp->push_idx;
633 }
634 set_64bit_val(qp_ctx, 0,
635 FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) |
636 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) |
637 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) |
638 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) |
639 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) |
640 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) |
641 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) |
642 FIELD_PREP(IRDMAQPC_PDIDXHI, roce_info->pd_id >> 16) |
643 FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) |
644 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, roce_info->err_rq_idx_valid) |
645 FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) |
646 FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) |
647 FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) |
648 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag));
649 set_64bit_val(qp_ctx, 8, qp->sq_pa);
650 set_64bit_val(qp_ctx, 16, qp->rq_pa);
651 if ((roce_info->dcqcn_en || roce_info->dctcp_en) &&
652 !(udp->tos & 0x03))
653 udp->tos |= ECN_CODE_PT_VAL;
654 set_64bit_val(qp_ctx, 24,
655 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) |
656 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) |
657 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | FIELD_PREP(IRDMAQPC_TOS, udp->tos) |
658 FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) |
659 FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port));
660 set_64bit_val(qp_ctx, 32,
661 FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) |
662 FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3]));
663 set_64bit_val(qp_ctx, 40,
664 FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) |
665 FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1]));
666 set_64bit_val(qp_ctx, 48,
667 FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) |
668 FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) |
669 FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx));
670 set_64bit_val(qp_ctx, 56,
671 FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) |
672 FIELD_PREP(IRDMAQPC_PDIDX, roce_info->pd_id) |
673 FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) |
674 FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label));
675 set_64bit_val(qp_ctx, 64,
676 FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) |
677 FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp));
678 set_64bit_val(qp_ctx, 80,
679 FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) |
680 FIELD_PREP(IRDMAQPC_LSN, udp->lsn));
681 set_64bit_val(qp_ctx, 88,
682 FIELD_PREP(IRDMAQPC_EPSN, udp->epsn));
683 set_64bit_val(qp_ctx, 96,
684 FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) |
685 FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una));
686 set_64bit_val(qp_ctx, 112,
687 FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd));
688 set_64bit_val(qp_ctx, 128,
689 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, roce_info->err_rq_idx) |
690 FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) |
691 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) |
692 FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin));
693 set_64bit_val(qp_ctx, 136,
694 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) |
695 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num));
696 set_64bit_val(qp_ctx, 144,
697 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx));
698 set_64bit_val(qp_ctx, 152, ether_addr_to_u64(roce_info->mac_addr) << 16);
699 set_64bit_val(qp_ctx, 160,
700 FIELD_PREP(IRDMAQPC_ORDSIZE, roce_info->ord_size) |
701 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(roce_info->ird_size)) |
702 FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) |
703 FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) |
704 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) |
705 FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) |
706 FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) |
707 FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) |
708 FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) |
709 FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, roce_info->fw_cc_enable) |
710 FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, roce_info->udprivcq_en) |
711 FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) |
712 FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en));
713 set_64bit_val(qp_ctx, 168,
714 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx));
715 set_64bit_val(qp_ctx, 176,
716 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) |
717 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) |
718 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle));
719 set_64bit_val(qp_ctx, 184,
720 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) |
721 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2]));
722 set_64bit_val(qp_ctx, 192,
723 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) |
724 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0]));
725 set_64bit_val(qp_ctx, 200,
726 FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) |
727 FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low));
728 set_64bit_val(qp_ctx, 208,
729 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx));
730
731 print_hex_dump_debug("WQE: QP_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16,
732 8, qp_ctx, IRDMA_QP_CTX_SIZE, false);
733 }
734
735 /* irdma_sc_alloc_local_mac_entry - allocate a mac entry
736 * @cqp: struct for cqp hw
737 * @scratch: u64 saved to be used during cqp completion
738 * @post_sq: flag for cqp db to ring
739 */
740 static enum irdma_status_code
irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp * cqp,u64 scratch,bool post_sq)741 irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,
742 bool post_sq)
743 {
744 __le64 *wqe;
745 u64 hdr;
746
747 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
748 if (!wqe)
749 return IRDMA_ERR_RING_FULL;
750
751 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE,
752 IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY) |
753 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
754
755 dma_wmb(); /* make sure WQE is written before valid bit is set */
756
757 set_64bit_val(wqe, 24, hdr);
758
759 print_hex_dump_debug("WQE: ALLOCATE_LOCAL_MAC WQE",
760 DUMP_PREFIX_OFFSET, 16, 8, wqe,
761 IRDMA_CQP_WQE_SIZE * 8, false);
762
763 if (post_sq)
764 irdma_sc_cqp_post_sq(cqp);
765 return 0;
766 }
767
768 /**
769 * irdma_sc_add_local_mac_entry - add mac enry
770 * @cqp: struct for cqp hw
771 * @info:mac addr info
772 * @scratch: u64 saved to be used during cqp completion
773 * @post_sq: flag for cqp db to ring
774 */
775 static enum irdma_status_code
irdma_sc_add_local_mac_entry(struct irdma_sc_cqp * cqp,struct irdma_local_mac_entry_info * info,u64 scratch,bool post_sq)776 irdma_sc_add_local_mac_entry(struct irdma_sc_cqp *cqp,
777 struct irdma_local_mac_entry_info *info,
778 u64 scratch, bool post_sq)
779 {
780 __le64 *wqe;
781 u64 header;
782
783 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
784 if (!wqe)
785 return IRDMA_ERR_RING_FULL;
786
787 set_64bit_val(wqe, 32, ether_addr_to_u64(info->mac_addr));
788
789 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, info->entry_idx) |
790 FIELD_PREP(IRDMA_CQPSQ_OPCODE,
791 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) |
792 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
793
794 dma_wmb(); /* make sure WQE is written before valid bit is set */
795
796 set_64bit_val(wqe, 24, header);
797
798 print_hex_dump_debug("WQE: ADD_LOCAL_MAC WQE", DUMP_PREFIX_OFFSET, 16,
799 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
800
801 if (post_sq)
802 irdma_sc_cqp_post_sq(cqp);
803 return 0;
804 }
805
806 /**
807 * irdma_sc_del_local_mac_entry - cqp wqe to dele local mac
808 * @cqp: struct for cqp hw
809 * @scratch: u64 saved to be used during cqp completion
810 * @entry_idx: index of mac entry
811 * @ignore_ref_count: to force mac adde delete
812 * @post_sq: flag for cqp db to ring
813 */
814 static enum irdma_status_code
irdma_sc_del_local_mac_entry(struct irdma_sc_cqp * cqp,u64 scratch,u16 entry_idx,u8 ignore_ref_count,bool post_sq)815 irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch,
816 u16 entry_idx, u8 ignore_ref_count, bool post_sq)
817 {
818 __le64 *wqe;
819 u64 header;
820
821 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
822 if (!wqe)
823 return IRDMA_ERR_RING_FULL;
824 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, entry_idx) |
825 FIELD_PREP(IRDMA_CQPSQ_OPCODE,
826 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) |
827 FIELD_PREP(IRDMA_CQPSQ_MLM_FREEENTRY, 1) |
828 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) |
829 FIELD_PREP(IRDMA_CQPSQ_MLM_IGNORE_REF_CNT, ignore_ref_count);
830
831 dma_wmb(); /* make sure WQE is written before valid bit is set */
832
833 set_64bit_val(wqe, 24, header);
834
835 print_hex_dump_debug("WQE: DEL_LOCAL_MAC_IPADDR WQE",
836 DUMP_PREFIX_OFFSET, 16, 8, wqe,
837 IRDMA_CQP_WQE_SIZE * 8, false);
838
839 if (post_sq)
840 irdma_sc_cqp_post_sq(cqp);
841 return 0;
842 }
843
844 /**
845 * irdma_sc_qp_setctx - set qp's context
846 * @qp: sc qp
847 * @qp_ctx: context ptr
848 * @info: ctx info
849 */
irdma_sc_qp_setctx(struct irdma_sc_qp * qp,__le64 * qp_ctx,struct irdma_qp_host_ctx_info * info)850 void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx,
851 struct irdma_qp_host_ctx_info *info)
852 {
853 struct irdma_iwarp_offload_info *iw;
854 struct irdma_tcp_offload_info *tcp;
855 struct irdma_sc_dev *dev;
856 u8 push_mode_en;
857 u32 push_idx;
858 u64 qw0, qw3, qw7 = 0, qw16 = 0;
859 u64 mac = 0;
860
861 iw = info->iwarp_info;
862 tcp = info->tcp_info;
863 dev = qp->dev;
864 if (iw->rcv_mark_en) {
865 qp->pfpdu.marker_len = 4;
866 qp->pfpdu.rcv_start_seq = tcp->rcv_nxt;
867 }
868 qp->user_pri = info->user_pri;
869 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) {
870 push_mode_en = 0;
871 push_idx = 0;
872 } else {
873 push_mode_en = 1;
874 push_idx = qp->push_idx;
875 }
876 qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) |
877 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) |
878 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) |
879 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) |
880 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) |
881 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) |
882 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en);
883
884 set_64bit_val(qp_ctx, 8, qp->sq_pa);
885 set_64bit_val(qp_ctx, 16, qp->rq_pa);
886
887 qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) |
888 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size);
889 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
890 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX,
891 qp->src_mac_addr_idx);
892 set_64bit_val(qp_ctx, 136,
893 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) |
894 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num));
895 set_64bit_val(qp_ctx, 168,
896 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx));
897 set_64bit_val(qp_ctx, 176,
898 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) |
899 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) |
900 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle) |
901 FIELD_PREP(IRDMAQPC_EXCEPTION_LAN_QUEUE, qp->ieq_qp));
902 if (info->iwarp_info_valid) {
903 qw0 |= FIELD_PREP(IRDMAQPC_DDP_VER, iw->ddp_ver) |
904 FIELD_PREP(IRDMAQPC_RDMAP_VER, iw->rdmap_ver) |
905 FIELD_PREP(IRDMAQPC_DC_TCP_EN, iw->dctcp_en) |
906 FIELD_PREP(IRDMAQPC_ECN_EN, iw->ecn_en) |
907 FIELD_PREP(IRDMAQPC_IBRDENABLE, iw->ib_rd_en) |
908 FIELD_PREP(IRDMAQPC_PDIDXHI, iw->pd_id >> 16) |
909 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID,
910 iw->err_rq_idx_valid);
911 qw7 |= FIELD_PREP(IRDMAQPC_PDIDX, iw->pd_id);
912 qw16 |= FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, iw->err_rq_idx) |
913 FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin);
914 set_64bit_val(qp_ctx, 144,
915 FIELD_PREP(IRDMAQPC_Q2ADDR, qp->q2_pa >> 8) |
916 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx));
917
918 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
919 mac = ether_addr_to_u64(iw->mac_addr);
920
921 set_64bit_val(qp_ctx, 152,
922 mac << 16 | FIELD_PREP(IRDMAQPC_LASTBYTESENT, iw->last_byte_sent));
923 set_64bit_val(qp_ctx, 160,
924 FIELD_PREP(IRDMAQPC_ORDSIZE, iw->ord_size) |
925 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(iw->ird_size)) |
926 FIELD_PREP(IRDMAQPC_WRRDRSPOK, iw->wr_rdresp_en) |
927 FIELD_PREP(IRDMAQPC_RDOK, iw->rd_en) |
928 FIELD_PREP(IRDMAQPC_SNDMARKERS, iw->snd_mark_en) |
929 FIELD_PREP(IRDMAQPC_BINDEN, iw->bind_en) |
930 FIELD_PREP(IRDMAQPC_FASTREGEN, iw->fast_reg_en) |
931 FIELD_PREP(IRDMAQPC_PRIVEN, iw->priv_mode_en) |
932 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) |
933 FIELD_PREP(IRDMAQPC_IWARPMODE, 1) |
934 FIELD_PREP(IRDMAQPC_RCVMARKERS, iw->rcv_mark_en) |
935 FIELD_PREP(IRDMAQPC_ALIGNHDRS, iw->align_hdrs) |
936 FIELD_PREP(IRDMAQPC_RCVNOMPACRC, iw->rcv_no_mpa_crc) |
937 FIELD_PREP(IRDMAQPC_RCVMARKOFFSET, iw->rcv_mark_offset || !tcp ? iw->rcv_mark_offset : tcp->rcv_nxt) |
938 FIELD_PREP(IRDMAQPC_SNDMARKOFFSET, iw->snd_mark_offset || !tcp ? iw->snd_mark_offset : tcp->snd_nxt) |
939 FIELD_PREP(IRDMAQPC_TIMELYENABLE, iw->timely_en));
940 }
941 if (info->tcp_info_valid) {
942 qw0 |= FIELD_PREP(IRDMAQPC_IPV4, tcp->ipv4) |
943 FIELD_PREP(IRDMAQPC_NONAGLE, tcp->no_nagle) |
944 FIELD_PREP(IRDMAQPC_INSERTVLANTAG,
945 tcp->insert_vlan_tag) |
946 FIELD_PREP(IRDMAQPC_TIMESTAMP, tcp->time_stamp) |
947 FIELD_PREP(IRDMAQPC_LIMIT, tcp->cwnd_inc_limit) |
948 FIELD_PREP(IRDMAQPC_DROPOOOSEG, tcp->drop_ooo_seg) |
949 FIELD_PREP(IRDMAQPC_DUPACK_THRESH, tcp->dup_ack_thresh);
950
951 if ((iw->ecn_en || iw->dctcp_en) && !(tcp->tos & 0x03))
952 tcp->tos |= ECN_CODE_PT_VAL;
953
954 qw3 |= FIELD_PREP(IRDMAQPC_TTL, tcp->ttl) |
955 FIELD_PREP(IRDMAQPC_AVOIDSTRETCHACK, tcp->avoid_stretch_ack) |
956 FIELD_PREP(IRDMAQPC_TOS, tcp->tos) |
957 FIELD_PREP(IRDMAQPC_SRCPORTNUM, tcp->src_port) |
958 FIELD_PREP(IRDMAQPC_DESTPORTNUM, tcp->dst_port);
959 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) {
960 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, tcp->src_mac_addr_idx);
961
962 qp->src_mac_addr_idx = tcp->src_mac_addr_idx;
963 }
964 set_64bit_val(qp_ctx, 32,
965 FIELD_PREP(IRDMAQPC_DESTIPADDR2, tcp->dest_ip_addr[2]) |
966 FIELD_PREP(IRDMAQPC_DESTIPADDR3, tcp->dest_ip_addr[3]));
967 set_64bit_val(qp_ctx, 40,
968 FIELD_PREP(IRDMAQPC_DESTIPADDR0, tcp->dest_ip_addr[0]) |
969 FIELD_PREP(IRDMAQPC_DESTIPADDR1, tcp->dest_ip_addr[1]));
970 set_64bit_val(qp_ctx, 48,
971 FIELD_PREP(IRDMAQPC_SNDMSS, tcp->snd_mss) |
972 FIELD_PREP(IRDMAQPC_SYN_RST_HANDLING, tcp->syn_rst_handling) |
973 FIELD_PREP(IRDMAQPC_VLANTAG, tcp->vlan_tag) |
974 FIELD_PREP(IRDMAQPC_ARPIDX, tcp->arp_idx));
975 qw7 |= FIELD_PREP(IRDMAQPC_FLOWLABEL, tcp->flow_label) |
976 FIELD_PREP(IRDMAQPC_WSCALE, tcp->wscale) |
977 FIELD_PREP(IRDMAQPC_IGNORE_TCP_OPT,
978 tcp->ignore_tcp_opt) |
979 FIELD_PREP(IRDMAQPC_IGNORE_TCP_UNS_OPT,
980 tcp->ignore_tcp_uns_opt) |
981 FIELD_PREP(IRDMAQPC_TCPSTATE, tcp->tcp_state) |
982 FIELD_PREP(IRDMAQPC_RCVSCALE, tcp->rcv_wscale) |
983 FIELD_PREP(IRDMAQPC_SNDSCALE, tcp->snd_wscale);
984 set_64bit_val(qp_ctx, 72,
985 FIELD_PREP(IRDMAQPC_TIMESTAMP_RECENT, tcp->time_stamp_recent) |
986 FIELD_PREP(IRDMAQPC_TIMESTAMP_AGE, tcp->time_stamp_age));
987 set_64bit_val(qp_ctx, 80,
988 FIELD_PREP(IRDMAQPC_SNDNXT, tcp->snd_nxt) |
989 FIELD_PREP(IRDMAQPC_SNDWND, tcp->snd_wnd));
990 set_64bit_val(qp_ctx, 88,
991 FIELD_PREP(IRDMAQPC_RCVNXT, tcp->rcv_nxt) |
992 FIELD_PREP(IRDMAQPC_RCVWND, tcp->rcv_wnd));
993 set_64bit_val(qp_ctx, 96,
994 FIELD_PREP(IRDMAQPC_SNDMAX, tcp->snd_max) |
995 FIELD_PREP(IRDMAQPC_SNDUNA, tcp->snd_una));
996 set_64bit_val(qp_ctx, 104,
997 FIELD_PREP(IRDMAQPC_SRTT, tcp->srtt) |
998 FIELD_PREP(IRDMAQPC_RTTVAR, tcp->rtt_var));
999 set_64bit_val(qp_ctx, 112,
1000 FIELD_PREP(IRDMAQPC_SSTHRESH, tcp->ss_thresh) |
1001 FIELD_PREP(IRDMAQPC_CWND, tcp->cwnd));
1002 set_64bit_val(qp_ctx, 120,
1003 FIELD_PREP(IRDMAQPC_SNDWL1, tcp->snd_wl1) |
1004 FIELD_PREP(IRDMAQPC_SNDWL2, tcp->snd_wl2));
1005 qw16 |= FIELD_PREP(IRDMAQPC_MAXSNDWND, tcp->max_snd_window) |
1006 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, tcp->rexmit_thresh);
1007 set_64bit_val(qp_ctx, 184,
1008 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, tcp->local_ipaddr[3]) |
1009 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, tcp->local_ipaddr[2]));
1010 set_64bit_val(qp_ctx, 192,
1011 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, tcp->local_ipaddr[1]) |
1012 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, tcp->local_ipaddr[0]));
1013 set_64bit_val(qp_ctx, 200,
1014 FIELD_PREP(IRDMAQPC_THIGH, iw->t_high) |
1015 FIELD_PREP(IRDMAQPC_TLOW, iw->t_low));
1016 set_64bit_val(qp_ctx, 208,
1017 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx));
1018 }
1019
1020 set_64bit_val(qp_ctx, 0, qw0);
1021 set_64bit_val(qp_ctx, 24, qw3);
1022 set_64bit_val(qp_ctx, 56, qw7);
1023 set_64bit_val(qp_ctx, 128, qw16);
1024
1025 print_hex_dump_debug("WQE: QP_HOST CTX", DUMP_PREFIX_OFFSET, 16, 8,
1026 qp_ctx, IRDMA_QP_CTX_SIZE, false);
1027 }
1028
1029 /**
1030 * irdma_sc_alloc_stag - mr stag alloc
1031 * @dev: sc device struct
1032 * @info: stag info
1033 * @scratch: u64 saved to be used during cqp completion
1034 * @post_sq: flag for cqp db to ring
1035 */
1036 static enum irdma_status_code
irdma_sc_alloc_stag(struct irdma_sc_dev * dev,struct irdma_allocate_stag_info * info,u64 scratch,bool post_sq)1037 irdma_sc_alloc_stag(struct irdma_sc_dev *dev,
1038 struct irdma_allocate_stag_info *info, u64 scratch,
1039 bool post_sq)
1040 {
1041 __le64 *wqe;
1042 struct irdma_sc_cqp *cqp;
1043 u64 hdr;
1044 enum irdma_page_size page_size;
1045
1046 if (!info->total_len && !info->all_memory)
1047 return -EINVAL;
1048
1049 if (info->page_size == 0x40000000)
1050 page_size = IRDMA_PAGE_SIZE_1G;
1051 else if (info->page_size == 0x200000)
1052 page_size = IRDMA_PAGE_SIZE_2M;
1053 else
1054 page_size = IRDMA_PAGE_SIZE_4K;
1055
1056 cqp = dev->cqp;
1057 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
1058 if (!wqe)
1059 return IRDMA_ERR_RING_FULL;
1060
1061 set_64bit_val(wqe, 8,
1062 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) |
1063 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len));
1064 set_64bit_val(wqe, 16,
1065 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx));
1066 set_64bit_val(wqe, 40,
1067 FIELD_PREP(IRDMA_CQPSQ_STAG_HMCFNIDX, info->hmc_fcn_index));
1068
1069 if (info->chunk_size)
1070 set_64bit_val(wqe, 48,
1071 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_idx));
1072
1073 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) |
1074 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) |
1075 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) |
1076 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) |
1077 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) |
1078 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, info->remote_access) |
1079 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) |
1080 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) |
1081 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
1082 dma_wmb(); /* make sure WQE is written before valid bit is set */
1083
1084 set_64bit_val(wqe, 24, hdr);
1085
1086 print_hex_dump_debug("WQE: ALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 8,
1087 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
1088 if (post_sq)
1089 irdma_sc_cqp_post_sq(cqp);
1090
1091 return 0;
1092 }
1093
1094 /**
1095 * irdma_sc_mr_reg_non_shared - non-shared mr registration
1096 * @dev: sc device struct
1097 * @info: mr info
1098 * @scratch: u64 saved to be used during cqp completion
1099 * @post_sq: flag for cqp db to ring
1100 */
1101 static enum irdma_status_code
irdma_sc_mr_reg_non_shared(struct irdma_sc_dev * dev,struct irdma_reg_ns_stag_info * info,u64 scratch,bool post_sq)1102 irdma_sc_mr_reg_non_shared(struct irdma_sc_dev *dev,
1103 struct irdma_reg_ns_stag_info *info, u64 scratch,
1104 bool post_sq)
1105 {
1106 __le64 *wqe;
1107 u64 fbo;
1108 struct irdma_sc_cqp *cqp;
1109 u64 hdr;
1110 u32 pble_obj_cnt;
1111 bool remote_access;
1112 u8 addr_type;
1113 enum irdma_page_size page_size;
1114
1115 if (!info->total_len && !info->all_memory)
1116 return -EINVAL;
1117
1118 if (info->page_size == 0x40000000)
1119 page_size = IRDMA_PAGE_SIZE_1G;
1120 else if (info->page_size == 0x200000)
1121 page_size = IRDMA_PAGE_SIZE_2M;
1122 else if (info->page_size == 0x1000)
1123 page_size = IRDMA_PAGE_SIZE_4K;
1124 else
1125 return IRDMA_ERR_PARAM;
1126
1127 if (info->access_rights & (IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY |
1128 IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY))
1129 remote_access = true;
1130 else
1131 remote_access = false;
1132
1133 pble_obj_cnt = dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
1134 if (info->chunk_size && info->first_pm_pbl_index >= pble_obj_cnt)
1135 return IRDMA_ERR_INVALID_PBLE_INDEX;
1136
1137 cqp = dev->cqp;
1138 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
1139 if (!wqe)
1140 return IRDMA_ERR_RING_FULL;
1141 fbo = info->va & (info->page_size - 1);
1142
1143 set_64bit_val(wqe, 0,
1144 (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED ?
1145 info->va : fbo));
1146 set_64bit_val(wqe, 8,
1147 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len) |
1148 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
1149 set_64bit_val(wqe, 16,
1150 FIELD_PREP(IRDMA_CQPSQ_STAG_KEY, info->stag_key) |
1151 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx));
1152 if (!info->chunk_size) {
1153 set_64bit_val(wqe, 32, info->reg_addr_pa);
1154 set_64bit_val(wqe, 48, 0);
1155 } else {
1156 set_64bit_val(wqe, 32, 0);
1157 set_64bit_val(wqe, 48,
1158 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_index));
1159 }
1160 set_64bit_val(wqe, 40, info->hmc_fcn_index);
1161 set_64bit_val(wqe, 56, 0);
1162
1163 addr_type = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1 : 0;
1164 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_REG_MR) |
1165 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) |
1166 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) |
1167 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) |
1168 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) |
1169 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, remote_access) |
1170 FIELD_PREP(IRDMA_CQPSQ_STAG_VABASEDTO, addr_type) |
1171 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) |
1172 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) |
1173 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
1174 dma_wmb(); /* make sure WQE is written before valid bit is set */
1175
1176 set_64bit_val(wqe, 24, hdr);
1177
1178 print_hex_dump_debug("WQE: MR_REG_NS WQE", DUMP_PREFIX_OFFSET, 16, 8,
1179 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
1180 if (post_sq)
1181 irdma_sc_cqp_post_sq(cqp);
1182
1183 return 0;
1184 }
1185
1186 /**
1187 * irdma_sc_dealloc_stag - deallocate stag
1188 * @dev: sc device struct
1189 * @info: dealloc stag info
1190 * @scratch: u64 saved to be used during cqp completion
1191 * @post_sq: flag for cqp db to ring
1192 */
1193 static enum irdma_status_code
irdma_sc_dealloc_stag(struct irdma_sc_dev * dev,struct irdma_dealloc_stag_info * info,u64 scratch,bool post_sq)1194 irdma_sc_dealloc_stag(struct irdma_sc_dev *dev,
1195 struct irdma_dealloc_stag_info *info, u64 scratch,
1196 bool post_sq)
1197 {
1198 u64 hdr;
1199 __le64 *wqe;
1200 struct irdma_sc_cqp *cqp;
1201
1202 cqp = dev->cqp;
1203 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
1204 if (!wqe)
1205 return IRDMA_ERR_RING_FULL;
1206
1207 set_64bit_val(wqe, 8,
1208 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
1209 set_64bit_val(wqe, 16,
1210 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx));
1211
1212 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DEALLOC_STAG) |
1213 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, info->mr) |
1214 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
1215 dma_wmb(); /* make sure WQE is written before valid bit is set */
1216
1217 set_64bit_val(wqe, 24, hdr);
1218
1219 print_hex_dump_debug("WQE: DEALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16,
1220 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
1221 if (post_sq)
1222 irdma_sc_cqp_post_sq(cqp);
1223
1224 return 0;
1225 }
1226
1227 /**
1228 * irdma_sc_mw_alloc - mw allocate
1229 * @dev: sc device struct
1230 * @info: memory window allocation information
1231 * @scratch: u64 saved to be used during cqp completion
1232 * @post_sq: flag for cqp db to ring
1233 */
1234 static enum irdma_status_code
irdma_sc_mw_alloc(struct irdma_sc_dev * dev,struct irdma_mw_alloc_info * info,u64 scratch,bool post_sq)1235 irdma_sc_mw_alloc(struct irdma_sc_dev *dev, struct irdma_mw_alloc_info *info,
1236 u64 scratch, bool post_sq)
1237 {
1238 u64 hdr;
1239 struct irdma_sc_cqp *cqp;
1240 __le64 *wqe;
1241
1242 cqp = dev->cqp;
1243 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
1244 if (!wqe)
1245 return IRDMA_ERR_RING_FULL;
1246
1247 set_64bit_val(wqe, 8,
1248 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
1249 set_64bit_val(wqe, 16,
1250 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->mw_stag_index));
1251
1252 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) |
1253 FIELD_PREP(IRDMA_CQPSQ_STAG_MWTYPE, info->mw_wide) |
1254 FIELD_PREP(IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY,
1255 info->mw1_bind_dont_vldt_key) |
1256 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
1257 dma_wmb(); /* make sure WQE is written before valid bit is set */
1258
1259 set_64bit_val(wqe, 24, hdr);
1260
1261 print_hex_dump_debug("WQE: MW_ALLOC WQE", DUMP_PREFIX_OFFSET, 16, 8,
1262 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
1263 if (post_sq)
1264 irdma_sc_cqp_post_sq(cqp);
1265
1266 return 0;
1267 }
1268
1269 /**
1270 * irdma_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp
1271 * @qp: sc qp struct
1272 * @info: fast mr info
1273 * @post_sq: flag for cqp db to ring
1274 */
1275 enum irdma_status_code
irdma_sc_mr_fast_register(struct irdma_sc_qp * qp,struct irdma_fast_reg_stag_info * info,bool post_sq)1276 irdma_sc_mr_fast_register(struct irdma_sc_qp *qp,
1277 struct irdma_fast_reg_stag_info *info, bool post_sq)
1278 {
1279 u64 temp, hdr;
1280 __le64 *wqe;
1281 u32 wqe_idx;
1282 enum irdma_page_size page_size;
1283 struct irdma_post_sq_info sq_info = {};
1284
1285 if (info->page_size == 0x40000000)
1286 page_size = IRDMA_PAGE_SIZE_1G;
1287 else if (info->page_size == 0x200000)
1288 page_size = IRDMA_PAGE_SIZE_2M;
1289 else
1290 page_size = IRDMA_PAGE_SIZE_4K;
1291
1292 sq_info.wr_id = info->wr_id;
1293 sq_info.signaled = info->signaled;
1294 sq_info.push_wqe = info->push_wqe;
1295
1296 wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx,
1297 IRDMA_QP_WQE_MIN_QUANTA, 0, &sq_info);
1298 if (!wqe)
1299 return IRDMA_ERR_QP_TOOMANY_WRS_POSTED;
1300
1301 irdma_clr_wqes(&qp->qp_uk, wqe_idx);
1302
1303 ibdev_dbg(to_ibdev(qp->dev),
1304 "MR: wr_id[%llxh] wqe_idx[%04d] location[%p]\n",
1305 info->wr_id, wqe_idx,
1306 &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid);
1307
1308 temp = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ?
1309 (uintptr_t)info->va : info->fbo;
1310 set_64bit_val(wqe, 0, temp);
1311
1312 temp = FIELD_GET(IRDMAQPSQ_FIRSTPMPBLIDXHI,
1313 info->first_pm_pbl_index >> 16);
1314 set_64bit_val(wqe, 8,
1315 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXHI, temp) |
1316 FIELD_PREP(IRDMAQPSQ_PBLADDR >> IRDMA_HW_PAGE_SHIFT, info->reg_addr_pa));
1317 set_64bit_val(wqe, 16,
1318 info->total_len |
1319 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXLO, info->first_pm_pbl_index));
1320
1321 hdr = FIELD_PREP(IRDMAQPSQ_STAGKEY, info->stag_key) |
1322 FIELD_PREP(IRDMAQPSQ_STAGINDEX, info->stag_idx) |
1323 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FAST_REGISTER) |
1324 FIELD_PREP(IRDMAQPSQ_LPBLSIZE, info->chunk_size) |
1325 FIELD_PREP(IRDMAQPSQ_HPAGESIZE, page_size) |
1326 FIELD_PREP(IRDMAQPSQ_STAGRIGHTS, info->access_rights) |
1327 FIELD_PREP(IRDMAQPSQ_VABASEDTO, info->addr_type) |
1328 FIELD_PREP(IRDMAQPSQ_PUSHWQE, (sq_info.push_wqe ? 1 : 0)) |
1329 FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) |
1330 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) |
1331 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) |
1332 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1333 dma_wmb(); /* make sure WQE is written before valid bit is set */
1334
1335 set_64bit_val(wqe, 24, hdr);
1336
1337 print_hex_dump_debug("WQE: FAST_REG WQE", DUMP_PREFIX_OFFSET, 16, 8,
1338 wqe, IRDMA_QP_WQE_MIN_SIZE, false);
1339 if (sq_info.push_wqe) {
1340 irdma_qp_push_wqe(&qp->qp_uk, wqe, IRDMA_QP_WQE_MIN_QUANTA,
1341 wqe_idx, post_sq);
1342 } else {
1343 if (post_sq)
1344 irdma_uk_qp_post_wr(&qp->qp_uk);
1345 }
1346
1347 return 0;
1348 }
1349
1350 /**
1351 * irdma_sc_gen_rts_ae - request AE generated after RTS
1352 * @qp: sc qp struct
1353 */
irdma_sc_gen_rts_ae(struct irdma_sc_qp * qp)1354 static void irdma_sc_gen_rts_ae(struct irdma_sc_qp *qp)
1355 {
1356 __le64 *wqe;
1357 u64 hdr;
1358 struct irdma_qp_uk *qp_uk;
1359
1360 qp_uk = &qp->qp_uk;
1361
1362 wqe = qp_uk->sq_base[1].elem;
1363
1364 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) |
1365 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) |
1366 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1367 dma_wmb(); /* make sure WQE is written before valid bit is set */
1368
1369 set_64bit_val(wqe, 24, hdr);
1370 print_hex_dump_debug("QP: NOP W/LOCAL FENCE WQE", DUMP_PREFIX_OFFSET,
1371 16, 8, wqe, IRDMA_QP_WQE_MIN_SIZE, false);
1372
1373 wqe = qp_uk->sq_base[2].elem;
1374 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_GEN_RTS_AE) |
1375 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1376 dma_wmb(); /* make sure WQE is written before valid bit is set */
1377
1378 set_64bit_val(wqe, 24, hdr);
1379 print_hex_dump_debug("QP: CONN EST WQE", DUMP_PREFIX_OFFSET, 16, 8,
1380 wqe, IRDMA_QP_WQE_MIN_SIZE, false);
1381 }
1382
1383 /**
1384 * irdma_sc_send_lsmm - send last streaming mode message
1385 * @qp: sc qp struct
1386 * @lsmm_buf: buffer with lsmm message
1387 * @size: size of lsmm buffer
1388 * @stag: stag of lsmm buffer
1389 */
irdma_sc_send_lsmm(struct irdma_sc_qp * qp,void * lsmm_buf,u32 size,irdma_stag stag)1390 void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size,
1391 irdma_stag stag)
1392 {
1393 __le64 *wqe;
1394 u64 hdr;
1395 struct irdma_qp_uk *qp_uk;
1396
1397 qp_uk = &qp->qp_uk;
1398 wqe = qp_uk->sq_base->elem;
1399
1400 set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf);
1401 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {
1402 set_64bit_val(wqe, 8,
1403 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size) |
1404 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, stag));
1405 } else {
1406 set_64bit_val(wqe, 8,
1407 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) |
1408 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, stag) |
1409 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity));
1410 }
1411 set_64bit_val(wqe, 16, 0);
1412
1413 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) |
1414 FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) |
1415 FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) |
1416 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1417 dma_wmb(); /* make sure WQE is written before valid bit is set */
1418
1419 set_64bit_val(wqe, 24, hdr);
1420
1421 print_hex_dump_debug("WQE: SEND_LSMM WQE", DUMP_PREFIX_OFFSET, 16, 8,
1422 wqe, IRDMA_QP_WQE_MIN_SIZE, false);
1423
1424 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE)
1425 irdma_sc_gen_rts_ae(qp);
1426 }
1427
1428 /**
1429 * irdma_sc_send_lsmm_nostag - for privilege qp
1430 * @qp: sc qp struct
1431 * @lsmm_buf: buffer with lsmm message
1432 * @size: size of lsmm buffer
1433 */
irdma_sc_send_lsmm_nostag(struct irdma_sc_qp * qp,void * lsmm_buf,u32 size)1434 void irdma_sc_send_lsmm_nostag(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size)
1435 {
1436 __le64 *wqe;
1437 u64 hdr;
1438 struct irdma_qp_uk *qp_uk;
1439
1440 qp_uk = &qp->qp_uk;
1441 wqe = qp_uk->sq_base->elem;
1442
1443 set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf);
1444
1445 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1)
1446 set_64bit_val(wqe, 8,
1447 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size));
1448 else
1449 set_64bit_val(wqe, 8,
1450 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) |
1451 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity));
1452 set_64bit_val(wqe, 16, 0);
1453
1454 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) |
1455 FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) |
1456 FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) |
1457 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1458 dma_wmb(); /* make sure WQE is written before valid bit is set */
1459
1460 set_64bit_val(wqe, 24, hdr);
1461
1462 print_hex_dump_debug("WQE: SEND_LSMM_NOSTAG WQE", DUMP_PREFIX_OFFSET,
1463 16, 8, wqe, IRDMA_QP_WQE_MIN_SIZE, false);
1464 }
1465
1466 /**
1467 * irdma_sc_send_rtt - send last read0 or write0
1468 * @qp: sc qp struct
1469 * @read: Do read0 or write0
1470 */
irdma_sc_send_rtt(struct irdma_sc_qp * qp,bool read)1471 void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read)
1472 {
1473 __le64 *wqe;
1474 u64 hdr;
1475 struct irdma_qp_uk *qp_uk;
1476
1477 qp_uk = &qp->qp_uk;
1478 wqe = qp_uk->sq_base->elem;
1479
1480 set_64bit_val(wqe, 0, 0);
1481 set_64bit_val(wqe, 16, 0);
1482 if (read) {
1483 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {
1484 set_64bit_val(wqe, 8,
1485 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, 0xabcd));
1486 } else {
1487 set_64bit_val(wqe, 8,
1488 (u64)0xabcd | FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity));
1489 }
1490 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, 0x1234) |
1491 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_READ) |
1492 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1493
1494 } else {
1495 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {
1496 set_64bit_val(wqe, 8, 0);
1497 } else {
1498 set_64bit_val(wqe, 8,
1499 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity));
1500 }
1501 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_WRITE) |
1502 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
1503 }
1504
1505 dma_wmb(); /* make sure WQE is written before valid bit is set */
1506
1507 set_64bit_val(wqe, 24, hdr);
1508
1509 print_hex_dump_debug("WQE: RTR WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe,
1510 IRDMA_QP_WQE_MIN_SIZE, false);
1511
1512 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE)
1513 irdma_sc_gen_rts_ae(qp);
1514 }
1515
1516 /**
1517 * irdma_iwarp_opcode - determine if incoming is rdma layer
1518 * @info: aeq info for the packet
1519 * @pkt: packet for error
1520 */
irdma_iwarp_opcode(struct irdma_aeqe_info * info,u8 * pkt)1521 static u32 irdma_iwarp_opcode(struct irdma_aeqe_info *info, u8 *pkt)
1522 {
1523 __be16 *mpa;
1524 u32 opcode = 0xffffffff;
1525
1526 if (info->q2_data_written) {
1527 mpa = (__be16 *)pkt;
1528 opcode = ntohs(mpa[1]) & 0xf;
1529 }
1530
1531 return opcode;
1532 }
1533
1534 /**
1535 * irdma_locate_mpa - return pointer to mpa in the pkt
1536 * @pkt: packet with data
1537 */
irdma_locate_mpa(u8 * pkt)1538 static u8 *irdma_locate_mpa(u8 *pkt)
1539 {
1540 /* skip over ethernet header */
1541 pkt += IRDMA_MAC_HLEN;
1542
1543 /* Skip over IP and TCP headers */
1544 pkt += 4 * (pkt[0] & 0x0f);
1545 pkt += 4 * ((pkt[12] >> 4) & 0x0f);
1546
1547 return pkt;
1548 }
1549
1550 /**
1551 * irdma_bld_termhdr_ctrl - setup terminate hdr control fields
1552 * @qp: sc qp ptr for pkt
1553 * @hdr: term hdr
1554 * @opcode: flush opcode for termhdr
1555 * @layer_etype: error layer + error type
1556 * @err: error cod ein the header
1557 */
irdma_bld_termhdr_ctrl(struct irdma_sc_qp * qp,struct irdma_terminate_hdr * hdr,enum irdma_flush_opcode opcode,u8 layer_etype,u8 err)1558 static void irdma_bld_termhdr_ctrl(struct irdma_sc_qp *qp,
1559 struct irdma_terminate_hdr *hdr,
1560 enum irdma_flush_opcode opcode,
1561 u8 layer_etype, u8 err)
1562 {
1563 qp->flush_code = opcode;
1564 hdr->layer_etype = layer_etype;
1565 hdr->error_code = err;
1566 }
1567
1568 /**
1569 * irdma_bld_termhdr_ddp_rdma - setup ddp and rdma hdrs in terminate hdr
1570 * @pkt: ptr to mpa in offending pkt
1571 * @hdr: term hdr
1572 * @copy_len: offending pkt length to be copied to term hdr
1573 * @is_tagged: DDP tagged or untagged
1574 */
irdma_bld_termhdr_ddp_rdma(u8 * pkt,struct irdma_terminate_hdr * hdr,int * copy_len,u8 * is_tagged)1575 static void irdma_bld_termhdr_ddp_rdma(u8 *pkt, struct irdma_terminate_hdr *hdr,
1576 int *copy_len, u8 *is_tagged)
1577 {
1578 u16 ddp_seg_len;
1579
1580 ddp_seg_len = ntohs(*(__be16 *)pkt);
1581 if (ddp_seg_len) {
1582 *copy_len = 2;
1583 hdr->hdrct = DDP_LEN_FLAG;
1584 if (pkt[2] & 0x80) {
1585 *is_tagged = 1;
1586 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) {
1587 *copy_len += TERM_DDP_LEN_TAGGED;
1588 hdr->hdrct |= DDP_HDR_FLAG;
1589 }
1590 } else {
1591 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) {
1592 *copy_len += TERM_DDP_LEN_UNTAGGED;
1593 hdr->hdrct |= DDP_HDR_FLAG;
1594 }
1595 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN) &&
1596 ((pkt[3] & RDMA_OPCODE_M) == RDMA_READ_REQ_OPCODE)) {
1597 *copy_len += TERM_RDMA_LEN;
1598 hdr->hdrct |= RDMA_HDR_FLAG;
1599 }
1600 }
1601 }
1602 }
1603
1604 /**
1605 * irdma_bld_terminate_hdr - build terminate message header
1606 * @qp: qp associated with received terminate AE
1607 * @info: the struct contiaing AE information
1608 */
irdma_bld_terminate_hdr(struct irdma_sc_qp * qp,struct irdma_aeqe_info * info)1609 static int irdma_bld_terminate_hdr(struct irdma_sc_qp *qp,
1610 struct irdma_aeqe_info *info)
1611 {
1612 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
1613 int copy_len = 0;
1614 u8 is_tagged = 0;
1615 u32 opcode;
1616 struct irdma_terminate_hdr *termhdr;
1617
1618 termhdr = (struct irdma_terminate_hdr *)qp->q2_buf;
1619 memset(termhdr, 0, Q2_BAD_FRAME_OFFSET);
1620
1621 if (info->q2_data_written) {
1622 pkt = irdma_locate_mpa(pkt);
1623 irdma_bld_termhdr_ddp_rdma(pkt, termhdr, ©_len, &is_tagged);
1624 }
1625
1626 opcode = irdma_iwarp_opcode(info, pkt);
1627 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
1628 qp->sq_flush_code = info->sq;
1629 qp->rq_flush_code = info->rq;
1630
1631 switch (info->ae_id) {
1632 case IRDMA_AE_AMP_UNALLOCATED_STAG:
1633 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1634 if (opcode == IRDMA_OP_TYPE_RDMA_WRITE)
1635 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR,
1636 (LAYER_DDP << 4) | DDP_TAGGED_BUF,
1637 DDP_TAGGED_INV_STAG);
1638 else
1639 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1640 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1641 RDMAP_INV_STAG);
1642 break;
1643 case IRDMA_AE_AMP_BOUNDS_VIOLATION:
1644 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1645 if (info->q2_data_written)
1646 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR,
1647 (LAYER_DDP << 4) | DDP_TAGGED_BUF,
1648 DDP_TAGGED_BOUNDS);
1649 else
1650 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1651 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1652 RDMAP_INV_BOUNDS);
1653 break;
1654 case IRDMA_AE_AMP_BAD_PD:
1655 switch (opcode) {
1656 case IRDMA_OP_TYPE_RDMA_WRITE:
1657 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR,
1658 (LAYER_DDP << 4) | DDP_TAGGED_BUF,
1659 DDP_TAGGED_UNASSOC_STAG);
1660 break;
1661 case IRDMA_OP_TYPE_SEND_INV:
1662 case IRDMA_OP_TYPE_SEND_SOL_INV:
1663 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1664 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1665 RDMAP_CANT_INV_STAG);
1666 break;
1667 default:
1668 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1669 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1670 RDMAP_UNASSOC_STAG);
1671 }
1672 break;
1673 case IRDMA_AE_AMP_INVALID_STAG:
1674 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1675 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1676 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1677 RDMAP_INV_STAG);
1678 break;
1679 case IRDMA_AE_AMP_BAD_QP:
1680 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_QP_OP_ERR,
1681 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1682 DDP_UNTAGGED_INV_QN);
1683 break;
1684 case IRDMA_AE_AMP_BAD_STAG_KEY:
1685 case IRDMA_AE_AMP_BAD_STAG_INDEX:
1686 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1687 switch (opcode) {
1688 case IRDMA_OP_TYPE_SEND_INV:
1689 case IRDMA_OP_TYPE_SEND_SOL_INV:
1690 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR,
1691 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP,
1692 RDMAP_CANT_INV_STAG);
1693 break;
1694 default:
1695 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1696 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP,
1697 RDMAP_INV_STAG);
1698 }
1699 break;
1700 case IRDMA_AE_AMP_RIGHTS_VIOLATION:
1701 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
1702 case IRDMA_AE_PRIV_OPERATION_DENIED:
1703 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1704 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1705 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1706 RDMAP_ACCESS);
1707 break;
1708 case IRDMA_AE_AMP_TO_WRAP:
1709 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1710 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR,
1711 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT,
1712 RDMAP_TO_WRAP);
1713 break;
1714 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
1715 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1716 (LAYER_MPA << 4) | DDP_LLP, MPA_CRC);
1717 break;
1718 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
1719 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR,
1720 (LAYER_DDP << 4) | DDP_CATASTROPHIC,
1721 DDP_CATASTROPHIC_LOCAL);
1722 break;
1723 case IRDMA_AE_LCE_QP_CATASTROPHIC:
1724 case IRDMA_AE_DDP_NO_L_BIT:
1725 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR,
1726 (LAYER_DDP << 4) | DDP_CATASTROPHIC,
1727 DDP_CATASTROPHIC_LOCAL);
1728 break;
1729 case IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN:
1730 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1731 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1732 DDP_UNTAGGED_INV_MSN_RANGE);
1733 break;
1734 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
1735 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
1736 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR,
1737 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1738 DDP_UNTAGGED_INV_TOO_LONG);
1739 break;
1740 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION:
1741 if (is_tagged)
1742 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1743 (LAYER_DDP << 4) | DDP_TAGGED_BUF,
1744 DDP_TAGGED_INV_DDP_VER);
1745 else
1746 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1747 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1748 DDP_UNTAGGED_INV_DDP_VER);
1749 break;
1750 case IRDMA_AE_DDP_UBE_INVALID_MO:
1751 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1752 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1753 DDP_UNTAGGED_INV_MO);
1754 break;
1755 case IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
1756 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR,
1757 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1758 DDP_UNTAGGED_INV_MSN_NO_BUF);
1759 break;
1760 case IRDMA_AE_DDP_UBE_INVALID_QN:
1761 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1762 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF,
1763 DDP_UNTAGGED_INV_QN);
1764 break;
1765 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
1766 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR,
1767 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP,
1768 RDMAP_INV_RDMAP_VER);
1769 break;
1770 default:
1771 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR,
1772 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP,
1773 RDMAP_UNSPECIFIED);
1774 break;
1775 }
1776
1777 if (copy_len)
1778 memcpy(termhdr + 1, pkt, copy_len);
1779
1780 return sizeof(struct irdma_terminate_hdr) + copy_len;
1781 }
1782
1783 /**
1784 * irdma_terminate_send_fin() - Send fin for terminate message
1785 * @qp: qp associated with received terminate AE
1786 */
irdma_terminate_send_fin(struct irdma_sc_qp * qp)1787 void irdma_terminate_send_fin(struct irdma_sc_qp *qp)
1788 {
1789 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE,
1790 IRDMAQP_TERM_SEND_FIN_ONLY, 0);
1791 }
1792
1793 /**
1794 * irdma_terminate_connection() - Bad AE and send terminate to remote QP
1795 * @qp: qp associated with received terminate AE
1796 * @info: the struct contiaing AE information
1797 */
irdma_terminate_connection(struct irdma_sc_qp * qp,struct irdma_aeqe_info * info)1798 void irdma_terminate_connection(struct irdma_sc_qp *qp,
1799 struct irdma_aeqe_info *info)
1800 {
1801 u8 termlen = 0;
1802
1803 if (qp->term_flags & IRDMA_TERM_SENT)
1804 return;
1805
1806 termlen = irdma_bld_terminate_hdr(qp, info);
1807 irdma_terminate_start_timer(qp);
1808 qp->term_flags |= IRDMA_TERM_SENT;
1809 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE,
1810 IRDMAQP_TERM_SEND_TERM_ONLY, termlen);
1811 }
1812
1813 /**
1814 * irdma_terminate_received - handle terminate received AE
1815 * @qp: qp associated with received terminate AE
1816 * @info: the struct contiaing AE information
1817 */
irdma_terminate_received(struct irdma_sc_qp * qp,struct irdma_aeqe_info * info)1818 void irdma_terminate_received(struct irdma_sc_qp *qp,
1819 struct irdma_aeqe_info *info)
1820 {
1821 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
1822 __be32 *mpa;
1823 u8 ddp_ctl;
1824 u8 rdma_ctl;
1825 u16 aeq_id = 0;
1826 struct irdma_terminate_hdr *termhdr;
1827
1828 mpa = (__be32 *)irdma_locate_mpa(pkt);
1829 if (info->q2_data_written) {
1830 /* did not validate the frame - do it now */
1831 ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff;
1832 rdma_ctl = ntohl(mpa[0]) & 0xff;
1833 if ((ddp_ctl & 0xc0) != 0x40)
1834 aeq_id = IRDMA_AE_LCE_QP_CATASTROPHIC;
1835 else if ((ddp_ctl & 0x03) != 1)
1836 aeq_id = IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION;
1837 else if (ntohl(mpa[2]) != 2)
1838 aeq_id = IRDMA_AE_DDP_UBE_INVALID_QN;
1839 else if (ntohl(mpa[3]) != 1)
1840 aeq_id = IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN;
1841 else if (ntohl(mpa[4]) != 0)
1842 aeq_id = IRDMA_AE_DDP_UBE_INVALID_MO;
1843 else if ((rdma_ctl & 0xc0) != 0x40)
1844 aeq_id = IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION;
1845
1846 info->ae_id = aeq_id;
1847 if (info->ae_id) {
1848 /* Bad terminate recvd - send back a terminate */
1849 irdma_terminate_connection(qp, info);
1850 return;
1851 }
1852 }
1853
1854 qp->term_flags |= IRDMA_TERM_RCVD;
1855 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
1856 termhdr = (struct irdma_terminate_hdr *)&mpa[5];
1857 if (termhdr->layer_etype == RDMAP_REMOTE_PROT ||
1858 termhdr->layer_etype == RDMAP_REMOTE_OP) {
1859 irdma_terminate_done(qp, 0);
1860 } else {
1861 irdma_terminate_start_timer(qp);
1862 irdma_terminate_send_fin(qp);
1863 }
1864 }
1865
irdma_null_ws_add(struct irdma_sc_vsi * vsi,u8 user_pri)1866 static enum irdma_status_code irdma_null_ws_add(struct irdma_sc_vsi *vsi,
1867 u8 user_pri)
1868 {
1869 return 0;
1870 }
1871
irdma_null_ws_remove(struct irdma_sc_vsi * vsi,u8 user_pri)1872 static void irdma_null_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri)
1873 {
1874 /* do nothing */
1875 }
1876
irdma_null_ws_reset(struct irdma_sc_vsi * vsi)1877 static void irdma_null_ws_reset(struct irdma_sc_vsi *vsi)
1878 {
1879 /* do nothing */
1880 }
1881
1882 /**
1883 * irdma_sc_vsi_init - Init the vsi structure
1884 * @vsi: pointer to vsi structure to initialize
1885 * @info: the info used to initialize the vsi struct
1886 */
irdma_sc_vsi_init(struct irdma_sc_vsi * vsi,struct irdma_vsi_init_info * info)1887 void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi,
1888 struct irdma_vsi_init_info *info)
1889 {
1890 struct irdma_l2params *l2p;
1891 int i;
1892
1893 vsi->dev = info->dev;
1894 vsi->back_vsi = info->back_vsi;
1895 vsi->register_qset = info->register_qset;
1896 vsi->unregister_qset = info->unregister_qset;
1897 vsi->mtu = info->params->mtu;
1898 vsi->exception_lan_q = info->exception_lan_q;
1899 vsi->vsi_idx = info->pf_data_vsi_num;
1900 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1901 vsi->fcn_id = info->dev->hmc_fn_id;
1902
1903 l2p = info->params;
1904 vsi->qos_rel_bw = l2p->vsi_rel_bw;
1905 vsi->qos_prio_type = l2p->vsi_prio_type;
1906 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
1907 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1908 vsi->qos[i].qs_handle = l2p->qs_handle_list[i];
1909 vsi->qos[i].traffic_class = info->params->up2tc[i];
1910 vsi->qos[i].rel_bw =
1911 l2p->tc_info[vsi->qos[i].traffic_class].rel_bw;
1912 vsi->qos[i].prio_type =
1913 l2p->tc_info[vsi->qos[i].traffic_class].prio_type;
1914 vsi->qos[i].valid = false;
1915 mutex_init(&vsi->qos[i].qos_mutex);
1916 INIT_LIST_HEAD(&vsi->qos[i].qplist);
1917 }
1918 if (vsi->register_qset) {
1919 vsi->dev->ws_add = irdma_ws_add;
1920 vsi->dev->ws_remove = irdma_ws_remove;
1921 vsi->dev->ws_reset = irdma_ws_reset;
1922 } else {
1923 vsi->dev->ws_add = irdma_null_ws_add;
1924 vsi->dev->ws_remove = irdma_null_ws_remove;
1925 vsi->dev->ws_reset = irdma_null_ws_reset;
1926 }
1927 }
1928
1929 /**
1930 * irdma_get_fcn_id - Return the function id
1931 * @vsi: pointer to the vsi
1932 */
irdma_get_fcn_id(struct irdma_sc_vsi * vsi)1933 static u8 irdma_get_fcn_id(struct irdma_sc_vsi *vsi)
1934 {
1935 struct irdma_stats_inst_info stats_info = {};
1936 struct irdma_sc_dev *dev = vsi->dev;
1937 u8 fcn_id = IRDMA_INVALID_FCN_ID;
1938 u8 start_idx, max_stats, i;
1939
1940 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) {
1941 if (!irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_ALLOCATE,
1942 &stats_info))
1943 return stats_info.stats_idx;
1944 }
1945
1946 start_idx = 1;
1947 max_stats = 16;
1948 for (i = start_idx; i < max_stats; i++)
1949 if (!dev->fcn_id_array[i]) {
1950 fcn_id = i;
1951 dev->fcn_id_array[i] = true;
1952 break;
1953 }
1954
1955 return fcn_id;
1956 }
1957
1958 /**
1959 * irdma_vsi_stats_init - Initialize the vsi statistics
1960 * @vsi: pointer to the vsi structure
1961 * @info: The info structure used for initialization
1962 */
irdma_vsi_stats_init(struct irdma_sc_vsi * vsi,struct irdma_vsi_stats_info * info)1963 enum irdma_status_code irdma_vsi_stats_init(struct irdma_sc_vsi *vsi,
1964 struct irdma_vsi_stats_info *info)
1965 {
1966 u8 fcn_id = info->fcn_id;
1967 struct irdma_dma_mem *stats_buff_mem;
1968
1969 vsi->pestat = info->pestat;
1970 vsi->pestat->hw = vsi->dev->hw;
1971 vsi->pestat->vsi = vsi;
1972 stats_buff_mem = &vsi->pestat->gather_info.stats_buff_mem;
1973 stats_buff_mem->size = ALIGN(IRDMA_GATHER_STATS_BUF_SIZE * 2, 1);
1974 stats_buff_mem->va = dma_alloc_coherent(vsi->pestat->hw->device,
1975 stats_buff_mem->size,
1976 &stats_buff_mem->pa,
1977 GFP_KERNEL);
1978 if (!stats_buff_mem->va)
1979 return IRDMA_ERR_NO_MEMORY;
1980
1981 vsi->pestat->gather_info.gather_stats_va = stats_buff_mem->va;
1982 vsi->pestat->gather_info.last_gather_stats_va =
1983 (void *)((uintptr_t)stats_buff_mem->va +
1984 IRDMA_GATHER_STATS_BUF_SIZE);
1985
1986 irdma_hw_stats_start_timer(vsi);
1987 if (info->alloc_fcn_id)
1988 fcn_id = irdma_get_fcn_id(vsi);
1989 if (fcn_id == IRDMA_INVALID_FCN_ID)
1990 goto stats_error;
1991
1992 vsi->stats_fcn_id_alloc = info->alloc_fcn_id;
1993 vsi->fcn_id = fcn_id;
1994 if (info->alloc_fcn_id) {
1995 vsi->pestat->gather_info.use_stats_inst = true;
1996 vsi->pestat->gather_info.stats_inst_index = fcn_id;
1997 }
1998
1999 return 0;
2000
2001 stats_error:
2002 dma_free_coherent(vsi->pestat->hw->device, stats_buff_mem->size,
2003 stats_buff_mem->va, stats_buff_mem->pa);
2004 stats_buff_mem->va = NULL;
2005
2006 return IRDMA_ERR_CQP_COMPL_ERROR;
2007 }
2008
2009 /**
2010 * irdma_vsi_stats_free - Free the vsi stats
2011 * @vsi: pointer to the vsi structure
2012 */
irdma_vsi_stats_free(struct irdma_sc_vsi * vsi)2013 void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi)
2014 {
2015 struct irdma_stats_inst_info stats_info = {};
2016 u8 fcn_id = vsi->fcn_id;
2017 struct irdma_sc_dev *dev = vsi->dev;
2018
2019 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) {
2020 if (vsi->stats_fcn_id_alloc) {
2021 stats_info.stats_idx = vsi->fcn_id;
2022 irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_FREE,
2023 &stats_info);
2024 }
2025 } else {
2026 if (vsi->stats_fcn_id_alloc &&
2027 fcn_id < vsi->dev->hw_attrs.max_stat_inst)
2028 vsi->dev->fcn_id_array[fcn_id] = false;
2029 }
2030
2031 if (!vsi->pestat)
2032 return;
2033 irdma_hw_stats_stop_timer(vsi);
2034 dma_free_coherent(vsi->pestat->hw->device,
2035 vsi->pestat->gather_info.stats_buff_mem.size,
2036 vsi->pestat->gather_info.stats_buff_mem.va,
2037 vsi->pestat->gather_info.stats_buff_mem.pa);
2038 vsi->pestat->gather_info.stats_buff_mem.va = NULL;
2039 }
2040
2041 /**
2042 * irdma_get_encoded_wqe_size - given wq size, returns hardware encoded size
2043 * @wqsize: size of the wq (sq, rq) to encoded_size
2044 * @queue_type: queue type selected for the calculation algorithm
2045 */
irdma_get_encoded_wqe_size(u32 wqsize,enum irdma_queue_type queue_type)2046 u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type)
2047 {
2048 u8 encoded_size = 0;
2049
2050 /* cqp sq's hw coded value starts from 1 for size of 4
2051 * while it starts from 0 for qp' wq's.
2052 */
2053 if (queue_type == IRDMA_QUEUE_TYPE_CQP)
2054 encoded_size = 1;
2055 wqsize >>= 2;
2056 while (wqsize >>= 1)
2057 encoded_size++;
2058
2059 return encoded_size;
2060 }
2061
2062 /**
2063 * irdma_sc_gather_stats - collect the statistics
2064 * @cqp: struct for cqp hw
2065 * @info: gather stats info structure
2066 * @scratch: u64 saved to be used during cqp completion
2067 */
2068 static enum irdma_status_code
irdma_sc_gather_stats(struct irdma_sc_cqp * cqp,struct irdma_stats_gather_info * info,u64 scratch)2069 irdma_sc_gather_stats(struct irdma_sc_cqp *cqp,
2070 struct irdma_stats_gather_info *info, u64 scratch)
2071 {
2072 __le64 *wqe;
2073 u64 temp;
2074
2075 if (info->stats_buff_mem.size < IRDMA_GATHER_STATS_BUF_SIZE)
2076 return IRDMA_ERR_BUF_TOO_SHORT;
2077
2078 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2079 if (!wqe)
2080 return IRDMA_ERR_RING_FULL;
2081
2082 set_64bit_val(wqe, 40,
2083 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fcn_index));
2084 set_64bit_val(wqe, 32, info->stats_buff_mem.pa);
2085
2086 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) |
2087 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_INST, info->use_stats_inst) |
2088 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX,
2089 info->stats_inst_index) |
2090 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX,
2091 info->use_hmc_fcn_index) |
2092 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_GATHER_STATS);
2093 dma_wmb(); /* make sure WQE is written before valid bit is set */
2094
2095 set_64bit_val(wqe, 24, temp);
2096
2097 print_hex_dump_debug("STATS: GATHER_STATS WQE", DUMP_PREFIX_OFFSET,
2098 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2099
2100 irdma_sc_cqp_post_sq(cqp);
2101 ibdev_dbg(to_ibdev(cqp->dev),
2102 "STATS: CQP SQ head 0x%x tail 0x%x size 0x%x\n",
2103 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size);
2104
2105 return 0;
2106 }
2107
2108 /**
2109 * irdma_sc_manage_stats_inst - allocate or free stats instance
2110 * @cqp: struct for cqp hw
2111 * @info: stats info structure
2112 * @alloc: alloc vs. delete flag
2113 * @scratch: u64 saved to be used during cqp completion
2114 */
2115 static enum irdma_status_code
irdma_sc_manage_stats_inst(struct irdma_sc_cqp * cqp,struct irdma_stats_inst_info * info,bool alloc,u64 scratch)2116 irdma_sc_manage_stats_inst(struct irdma_sc_cqp *cqp,
2117 struct irdma_stats_inst_info *info, bool alloc,
2118 u64 scratch)
2119 {
2120 __le64 *wqe;
2121 u64 temp;
2122
2123 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2124 if (!wqe)
2125 return IRDMA_ERR_RING_FULL;
2126
2127 set_64bit_val(wqe, 40,
2128 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fn_id));
2129 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) |
2130 FIELD_PREP(IRDMA_CQPSQ_STATS_ALLOC_INST, alloc) |
2131 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX,
2132 info->use_hmc_fcn_index) |
2133 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, info->stats_idx) |
2134 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_MANAGE_STATS);
2135
2136 dma_wmb(); /* make sure WQE is written before valid bit is set */
2137
2138 set_64bit_val(wqe, 24, temp);
2139
2140 print_hex_dump_debug("WQE: MANAGE_STATS WQE", DUMP_PREFIX_OFFSET, 16,
2141 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2142
2143 irdma_sc_cqp_post_sq(cqp);
2144 return 0;
2145 }
2146
2147 /**
2148 * irdma_sc_set_up_map - set the up map table
2149 * @cqp: struct for cqp hw
2150 * @info: User priority map info
2151 * @scratch: u64 saved to be used during cqp completion
2152 */
irdma_sc_set_up_map(struct irdma_sc_cqp * cqp,struct irdma_up_info * info,u64 scratch)2153 static enum irdma_status_code irdma_sc_set_up_map(struct irdma_sc_cqp *cqp,
2154 struct irdma_up_info *info,
2155 u64 scratch)
2156 {
2157 __le64 *wqe;
2158 u64 temp = 0;
2159 int i;
2160
2161 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2162 if (!wqe)
2163 return IRDMA_ERR_RING_FULL;
2164
2165 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++)
2166 temp |= (u64)info->map[i] << (i * 8);
2167
2168 set_64bit_val(wqe, 0, temp);
2169 set_64bit_val(wqe, 40,
2170 FIELD_PREP(IRDMA_CQPSQ_UP_CNPOVERRIDE, info->cnp_up_override) |
2171 FIELD_PREP(IRDMA_CQPSQ_UP_HMCFCNIDX, info->hmc_fcn_idx));
2172
2173 temp = FIELD_PREP(IRDMA_CQPSQ_UP_WQEVALID, cqp->polarity) |
2174 FIELD_PREP(IRDMA_CQPSQ_UP_USEVLAN, info->use_vlan) |
2175 FIELD_PREP(IRDMA_CQPSQ_UP_USEOVERRIDE,
2176 info->use_cnp_up_override) |
2177 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_UP_MAP);
2178 dma_wmb(); /* make sure WQE is written before valid bit is set */
2179
2180 set_64bit_val(wqe, 24, temp);
2181
2182 print_hex_dump_debug("WQE: UPMAP WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe,
2183 IRDMA_CQP_WQE_SIZE * 8, false);
2184 irdma_sc_cqp_post_sq(cqp);
2185
2186 return 0;
2187 }
2188
2189 /**
2190 * irdma_sc_manage_ws_node - create/modify/destroy WS node
2191 * @cqp: struct for cqp hw
2192 * @info: node info structure
2193 * @node_op: 0 for add 1 for modify, 2 for delete
2194 * @scratch: u64 saved to be used during cqp completion
2195 */
2196 static enum irdma_status_code
irdma_sc_manage_ws_node(struct irdma_sc_cqp * cqp,struct irdma_ws_node_info * info,enum irdma_ws_node_op node_op,u64 scratch)2197 irdma_sc_manage_ws_node(struct irdma_sc_cqp *cqp,
2198 struct irdma_ws_node_info *info,
2199 enum irdma_ws_node_op node_op, u64 scratch)
2200 {
2201 __le64 *wqe;
2202 u64 temp = 0;
2203
2204 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2205 if (!wqe)
2206 return IRDMA_ERR_RING_FULL;
2207
2208 set_64bit_val(wqe, 32,
2209 FIELD_PREP(IRDMA_CQPSQ_WS_VSI, info->vsi) |
2210 FIELD_PREP(IRDMA_CQPSQ_WS_WEIGHT, info->weight));
2211
2212 temp = FIELD_PREP(IRDMA_CQPSQ_WS_WQEVALID, cqp->polarity) |
2213 FIELD_PREP(IRDMA_CQPSQ_WS_NODEOP, node_op) |
2214 FIELD_PREP(IRDMA_CQPSQ_WS_ENABLENODE, info->enable) |
2215 FIELD_PREP(IRDMA_CQPSQ_WS_NODETYPE, info->type_leaf) |
2216 FIELD_PREP(IRDMA_CQPSQ_WS_PRIOTYPE, info->prio_type) |
2217 FIELD_PREP(IRDMA_CQPSQ_WS_TC, info->tc) |
2218 FIELD_PREP(IRDMA_CQPSQ_WS_OP, IRDMA_CQP_OP_WORK_SCHED_NODE) |
2219 FIELD_PREP(IRDMA_CQPSQ_WS_PARENTID, info->parent_id) |
2220 FIELD_PREP(IRDMA_CQPSQ_WS_NODEID, info->id);
2221 dma_wmb(); /* make sure WQE is written before valid bit is set */
2222
2223 set_64bit_val(wqe, 24, temp);
2224
2225 print_hex_dump_debug("WQE: MANAGE_WS WQE", DUMP_PREFIX_OFFSET, 16, 8,
2226 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2227 irdma_sc_cqp_post_sq(cqp);
2228
2229 return 0;
2230 }
2231
2232 /**
2233 * irdma_sc_qp_flush_wqes - flush qp's wqe
2234 * @qp: sc qp
2235 * @info: dlush information
2236 * @scratch: u64 saved to be used during cqp completion
2237 * @post_sq: flag for cqp db to ring
2238 */
irdma_sc_qp_flush_wqes(struct irdma_sc_qp * qp,struct irdma_qp_flush_info * info,u64 scratch,bool post_sq)2239 enum irdma_status_code irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp,
2240 struct irdma_qp_flush_info *info,
2241 u64 scratch, bool post_sq)
2242 {
2243 u64 temp = 0;
2244 __le64 *wqe;
2245 struct irdma_sc_cqp *cqp;
2246 u64 hdr;
2247 bool flush_sq = false, flush_rq = false;
2248
2249 if (info->rq && !qp->flush_rq)
2250 flush_rq = true;
2251 if (info->sq && !qp->flush_sq)
2252 flush_sq = true;
2253 qp->flush_sq |= flush_sq;
2254 qp->flush_rq |= flush_rq;
2255
2256 if (!flush_sq && !flush_rq) {
2257 ibdev_dbg(to_ibdev(qp->dev),
2258 "CQP: Additional flush request ignored for qp %x\n",
2259 qp->qp_uk.qp_id);
2260 return IRDMA_ERR_FLUSHED_Q;
2261 }
2262
2263 cqp = qp->pd->dev->cqp;
2264 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2265 if (!wqe)
2266 return IRDMA_ERR_RING_FULL;
2267
2268 if (info->userflushcode) {
2269 if (flush_rq)
2270 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMNERR,
2271 info->rq_minor_code) |
2272 FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR,
2273 info->rq_major_code);
2274 if (flush_sq)
2275 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMNERR,
2276 info->sq_minor_code) |
2277 FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR,
2278 info->sq_major_code);
2279 }
2280 set_64bit_val(wqe, 16, temp);
2281
2282 temp = (info->generate_ae) ?
2283 info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE,
2284 info->ae_src) : 0;
2285 set_64bit_val(wqe, 8, temp);
2286
2287 hdr = qp->qp_uk.qp_id |
2288 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_FLUSH_WQES) |
2289 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, info->generate_ae) |
2290 FIELD_PREP(IRDMA_CQPSQ_FWQE_USERFLCODE, info->userflushcode) |
2291 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHSQ, flush_sq) |
2292 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHRQ, flush_rq) |
2293 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2294 dma_wmb(); /* make sure WQE is written before valid bit is set */
2295
2296 set_64bit_val(wqe, 24, hdr);
2297
2298 print_hex_dump_debug("WQE: QP_FLUSH WQE", DUMP_PREFIX_OFFSET, 16, 8,
2299 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2300 if (post_sq)
2301 irdma_sc_cqp_post_sq(cqp);
2302
2303 return 0;
2304 }
2305
2306 /**
2307 * irdma_sc_gen_ae - generate AE, uses flush WQE CQP OP
2308 * @qp: sc qp
2309 * @info: gen ae information
2310 * @scratch: u64 saved to be used during cqp completion
2311 * @post_sq: flag for cqp db to ring
2312 */
irdma_sc_gen_ae(struct irdma_sc_qp * qp,struct irdma_gen_ae_info * info,u64 scratch,bool post_sq)2313 static enum irdma_status_code irdma_sc_gen_ae(struct irdma_sc_qp *qp,
2314 struct irdma_gen_ae_info *info,
2315 u64 scratch, bool post_sq)
2316 {
2317 u64 temp;
2318 __le64 *wqe;
2319 struct irdma_sc_cqp *cqp;
2320 u64 hdr;
2321
2322 cqp = qp->pd->dev->cqp;
2323 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2324 if (!wqe)
2325 return IRDMA_ERR_RING_FULL;
2326
2327 temp = info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE,
2328 info->ae_src);
2329 set_64bit_val(wqe, 8, temp);
2330
2331 hdr = qp->qp_uk.qp_id | FIELD_PREP(IRDMA_CQPSQ_OPCODE,
2332 IRDMA_CQP_OP_GEN_AE) |
2333 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, 1) |
2334 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2335 dma_wmb(); /* make sure WQE is written before valid bit is set */
2336
2337 set_64bit_val(wqe, 24, hdr);
2338
2339 print_hex_dump_debug("WQE: GEN_AE WQE", DUMP_PREFIX_OFFSET, 16, 8,
2340 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2341 if (post_sq)
2342 irdma_sc_cqp_post_sq(cqp);
2343
2344 return 0;
2345 }
2346
2347 /*** irdma_sc_qp_upload_context - upload qp's context
2348 * @dev: sc device struct
2349 * @info: upload context info ptr for return
2350 * @scratch: u64 saved to be used during cqp completion
2351 * @post_sq: flag for cqp db to ring
2352 */
2353 static enum irdma_status_code
irdma_sc_qp_upload_context(struct irdma_sc_dev * dev,struct irdma_upload_context_info * info,u64 scratch,bool post_sq)2354 irdma_sc_qp_upload_context(struct irdma_sc_dev *dev,
2355 struct irdma_upload_context_info *info, u64 scratch,
2356 bool post_sq)
2357 {
2358 __le64 *wqe;
2359 struct irdma_sc_cqp *cqp;
2360 u64 hdr;
2361
2362 cqp = dev->cqp;
2363 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2364 if (!wqe)
2365 return IRDMA_ERR_RING_FULL;
2366
2367 set_64bit_val(wqe, 16, info->buf_pa);
2368
2369 hdr = FIELD_PREP(IRDMA_CQPSQ_UCTX_QPID, info->qp_id) |
2370 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPLOAD_CONTEXT) |
2371 FIELD_PREP(IRDMA_CQPSQ_UCTX_QPTYPE, info->qp_type) |
2372 FIELD_PREP(IRDMA_CQPSQ_UCTX_RAWFORMAT, info->raw_format) |
2373 FIELD_PREP(IRDMA_CQPSQ_UCTX_FREEZEQP, info->freeze_qp) |
2374 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2375 dma_wmb(); /* make sure WQE is written before valid bit is set */
2376
2377 set_64bit_val(wqe, 24, hdr);
2378
2379 print_hex_dump_debug("WQE: QP_UPLOAD_CTX WQE", DUMP_PREFIX_OFFSET, 16,
2380 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2381 if (post_sq)
2382 irdma_sc_cqp_post_sq(cqp);
2383
2384 return 0;
2385 }
2386
2387 /**
2388 * irdma_sc_manage_push_page - Handle push page
2389 * @cqp: struct for cqp hw
2390 * @info: push page info
2391 * @scratch: u64 saved to be used during cqp completion
2392 * @post_sq: flag for cqp db to ring
2393 */
2394 static enum irdma_status_code
irdma_sc_manage_push_page(struct irdma_sc_cqp * cqp,struct irdma_cqp_manage_push_page_info * info,u64 scratch,bool post_sq)2395 irdma_sc_manage_push_page(struct irdma_sc_cqp *cqp,
2396 struct irdma_cqp_manage_push_page_info *info,
2397 u64 scratch, bool post_sq)
2398 {
2399 __le64 *wqe;
2400 u64 hdr;
2401
2402 if (info->free_page &&
2403 info->push_idx >= cqp->dev->hw_attrs.max_hw_device_pages)
2404 return IRDMA_ERR_INVALID_PUSH_PAGE_INDEX;
2405
2406 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2407 if (!wqe)
2408 return IRDMA_ERR_RING_FULL;
2409
2410 set_64bit_val(wqe, 16, info->qs_handle);
2411 hdr = FIELD_PREP(IRDMA_CQPSQ_MPP_PPIDX, info->push_idx) |
2412 FIELD_PREP(IRDMA_CQPSQ_MPP_PPTYPE, info->push_page_type) |
2413 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_PUSH_PAGES) |
2414 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) |
2415 FIELD_PREP(IRDMA_CQPSQ_MPP_FREE_PAGE, info->free_page);
2416 dma_wmb(); /* make sure WQE is written before valid bit is set */
2417
2418 set_64bit_val(wqe, 24, hdr);
2419
2420 print_hex_dump_debug("WQE: MANAGE_PUSH_PAGES WQE", DUMP_PREFIX_OFFSET,
2421 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2422 if (post_sq)
2423 irdma_sc_cqp_post_sq(cqp);
2424
2425 return 0;
2426 }
2427
2428 /**
2429 * irdma_sc_suspend_qp - suspend qp for param change
2430 * @cqp: struct for cqp hw
2431 * @qp: sc qp struct
2432 * @scratch: u64 saved to be used during cqp completion
2433 */
irdma_sc_suspend_qp(struct irdma_sc_cqp * cqp,struct irdma_sc_qp * qp,u64 scratch)2434 static enum irdma_status_code irdma_sc_suspend_qp(struct irdma_sc_cqp *cqp,
2435 struct irdma_sc_qp *qp,
2436 u64 scratch)
2437 {
2438 u64 hdr;
2439 __le64 *wqe;
2440
2441 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2442 if (!wqe)
2443 return IRDMA_ERR_RING_FULL;
2444
2445 hdr = FIELD_PREP(IRDMA_CQPSQ_SUSPENDQP_QPID, qp->qp_uk.qp_id) |
2446 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_SUSPEND_QP) |
2447 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2448 dma_wmb(); /* make sure WQE is written before valid bit is set */
2449
2450 set_64bit_val(wqe, 24, hdr);
2451
2452 print_hex_dump_debug("WQE: SUSPEND_QP WQE", DUMP_PREFIX_OFFSET, 16, 8,
2453 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2454 irdma_sc_cqp_post_sq(cqp);
2455
2456 return 0;
2457 }
2458
2459 /**
2460 * irdma_sc_resume_qp - resume qp after suspend
2461 * @cqp: struct for cqp hw
2462 * @qp: sc qp struct
2463 * @scratch: u64 saved to be used during cqp completion
2464 */
irdma_sc_resume_qp(struct irdma_sc_cqp * cqp,struct irdma_sc_qp * qp,u64 scratch)2465 static enum irdma_status_code irdma_sc_resume_qp(struct irdma_sc_cqp *cqp,
2466 struct irdma_sc_qp *qp,
2467 u64 scratch)
2468 {
2469 u64 hdr;
2470 __le64 *wqe;
2471
2472 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2473 if (!wqe)
2474 return IRDMA_ERR_RING_FULL;
2475
2476 set_64bit_val(wqe, 16,
2477 FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QSHANDLE, qp->qs_handle));
2478
2479 hdr = FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QPID, qp->qp_uk.qp_id) |
2480 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_RESUME_QP) |
2481 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2482 dma_wmb(); /* make sure WQE is written before valid bit is set */
2483
2484 set_64bit_val(wqe, 24, hdr);
2485
2486 print_hex_dump_debug("WQE: RESUME_QP WQE", DUMP_PREFIX_OFFSET, 16, 8,
2487 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2488 irdma_sc_cqp_post_sq(cqp);
2489
2490 return 0;
2491 }
2492
2493 /**
2494 * irdma_sc_cq_ack - acknowledge completion q
2495 * @cq: cq struct
2496 */
irdma_sc_cq_ack(struct irdma_sc_cq * cq)2497 static inline void irdma_sc_cq_ack(struct irdma_sc_cq *cq)
2498 {
2499 writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);
2500 }
2501
2502 /**
2503 * irdma_sc_cq_init - initialize completion q
2504 * @cq: cq struct
2505 * @info: cq initialization info
2506 */
irdma_sc_cq_init(struct irdma_sc_cq * cq,struct irdma_cq_init_info * info)2507 enum irdma_status_code irdma_sc_cq_init(struct irdma_sc_cq *cq,
2508 struct irdma_cq_init_info *info)
2509 {
2510 enum irdma_status_code ret_code;
2511 u32 pble_obj_cnt;
2512
2513 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
2514 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
2515 return IRDMA_ERR_INVALID_PBLE_INDEX;
2516
2517 cq->cq_pa = info->cq_base_pa;
2518 cq->dev = info->dev;
2519 cq->ceq_id = info->ceq_id;
2520 info->cq_uk_init_info.cqe_alloc_db = cq->dev->cq_arm_db;
2521 info->cq_uk_init_info.cq_ack_db = cq->dev->cq_ack_db;
2522 ret_code = irdma_uk_cq_init(&cq->cq_uk, &info->cq_uk_init_info);
2523 if (ret_code)
2524 return ret_code;
2525
2526 cq->virtual_map = info->virtual_map;
2527 cq->pbl_chunk_size = info->pbl_chunk_size;
2528 cq->ceqe_mask = info->ceqe_mask;
2529 cq->cq_type = (info->type) ? info->type : IRDMA_CQ_TYPE_IWARP;
2530 cq->shadow_area_pa = info->shadow_area_pa;
2531 cq->shadow_read_threshold = info->shadow_read_threshold;
2532 cq->ceq_id_valid = info->ceq_id_valid;
2533 cq->tph_en = info->tph_en;
2534 cq->tph_val = info->tph_val;
2535 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2536 cq->vsi = info->vsi;
2537
2538 return 0;
2539 }
2540
2541 /**
2542 * irdma_sc_cq_create - create completion q
2543 * @cq: cq struct
2544 * @scratch: u64 saved to be used during cqp completion
2545 * @check_overflow: flag for overflow check
2546 * @post_sq: flag for cqp db to ring
2547 */
irdma_sc_cq_create(struct irdma_sc_cq * cq,u64 scratch,bool check_overflow,bool post_sq)2548 static enum irdma_status_code irdma_sc_cq_create(struct irdma_sc_cq *cq,
2549 u64 scratch,
2550 bool check_overflow,
2551 bool post_sq)
2552 {
2553 __le64 *wqe;
2554 struct irdma_sc_cqp *cqp;
2555 u64 hdr;
2556 struct irdma_sc_ceq *ceq;
2557 enum irdma_status_code ret_code = 0;
2558
2559 cqp = cq->dev->cqp;
2560 if (cq->cq_uk.cq_id >= (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt))
2561 return IRDMA_ERR_INVALID_CQ_ID;
2562
2563 if (cq->ceq_id >= (cq->dev->hmc_fpm_misc.max_ceqs))
2564 return IRDMA_ERR_INVALID_CEQ_ID;
2565
2566 ceq = cq->dev->ceq[cq->ceq_id];
2567 if (ceq && ceq->reg_cq)
2568 ret_code = irdma_sc_add_cq_ctx(ceq, cq);
2569
2570 if (ret_code)
2571 return ret_code;
2572
2573 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2574 if (!wqe) {
2575 if (ceq && ceq->reg_cq)
2576 irdma_sc_remove_cq_ctx(ceq, cq);
2577 return IRDMA_ERR_RING_FULL;
2578 }
2579
2580 set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
2581 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1);
2582 set_64bit_val(wqe, 16,
2583 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold));
2584 set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));
2585 set_64bit_val(wqe, 40, cq->shadow_area_pa);
2586 set_64bit_val(wqe, 48,
2587 FIELD_PREP(IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX, (cq->virtual_map ? cq->first_pm_pbl_idx : 0)));
2588 set_64bit_val(wqe, 56,
2589 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) |
2590 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx));
2591
2592 hdr = FLD_LS_64(cq->dev, cq->cq_uk.cq_id, IRDMA_CQPSQ_CQ_CQID) |
2593 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0),
2594 IRDMA_CQPSQ_CQ_CEQID) |
2595 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) |
2596 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) |
2597 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, check_overflow) |
2598 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) |
2599 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) |
2600 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) |
2601 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) |
2602 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT,
2603 cq->cq_uk.avoid_mem_cflct) |
2604 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2605 dma_wmb(); /* make sure WQE is written before valid bit is set */
2606
2607 set_64bit_val(wqe, 24, hdr);
2608
2609 print_hex_dump_debug("WQE: CQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8,
2610 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2611 if (post_sq)
2612 irdma_sc_cqp_post_sq(cqp);
2613
2614 return 0;
2615 }
2616
2617 /**
2618 * irdma_sc_cq_destroy - destroy completion q
2619 * @cq: cq struct
2620 * @scratch: u64 saved to be used during cqp completion
2621 * @post_sq: flag for cqp db to ring
2622 */
irdma_sc_cq_destroy(struct irdma_sc_cq * cq,u64 scratch,bool post_sq)2623 enum irdma_status_code irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch,
2624 bool post_sq)
2625 {
2626 struct irdma_sc_cqp *cqp;
2627 __le64 *wqe;
2628 u64 hdr;
2629 struct irdma_sc_ceq *ceq;
2630
2631 cqp = cq->dev->cqp;
2632 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2633 if (!wqe)
2634 return IRDMA_ERR_RING_FULL;
2635
2636 ceq = cq->dev->ceq[cq->ceq_id];
2637 if (ceq && ceq->reg_cq)
2638 irdma_sc_remove_cq_ctx(ceq, cq);
2639
2640 set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
2641 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1);
2642 set_64bit_val(wqe, 40, cq->shadow_area_pa);
2643 set_64bit_val(wqe, 48,
2644 (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2645
2646 hdr = cq->cq_uk.cq_id |
2647 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0),
2648 IRDMA_CQPSQ_CQ_CEQID) |
2649 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) |
2650 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) |
2651 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) |
2652 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) |
2653 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) |
2654 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) |
2655 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, cq->cq_uk.avoid_mem_cflct) |
2656 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2657 dma_wmb(); /* make sure WQE is written before valid bit is set */
2658
2659 set_64bit_val(wqe, 24, hdr);
2660
2661 print_hex_dump_debug("WQE: CQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8,
2662 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2663 if (post_sq)
2664 irdma_sc_cqp_post_sq(cqp);
2665
2666 return 0;
2667 }
2668
2669 /**
2670 * irdma_sc_cq_resize - set resized cq buffer info
2671 * @cq: resized cq
2672 * @info: resized cq buffer info
2673 */
irdma_sc_cq_resize(struct irdma_sc_cq * cq,struct irdma_modify_cq_info * info)2674 void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info)
2675 {
2676 cq->virtual_map = info->virtual_map;
2677 cq->cq_pa = info->cq_pa;
2678 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2679 cq->pbl_chunk_size = info->pbl_chunk_size;
2680 irdma_uk_cq_resize(&cq->cq_uk, info->cq_base, info->cq_size);
2681 }
2682
2683 /**
2684 * irdma_sc_cq_modify - modify a Completion Queue
2685 * @cq: cq struct
2686 * @info: modification info struct
2687 * @scratch: u64 saved to be used during cqp completion
2688 * @post_sq: flag to post to sq
2689 */
2690 static enum irdma_status_code
irdma_sc_cq_modify(struct irdma_sc_cq * cq,struct irdma_modify_cq_info * info,u64 scratch,bool post_sq)2691 irdma_sc_cq_modify(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info,
2692 u64 scratch, bool post_sq)
2693 {
2694 struct irdma_sc_cqp *cqp;
2695 __le64 *wqe;
2696 u64 hdr;
2697 u32 pble_obj_cnt;
2698
2699 pble_obj_cnt = cq->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
2700 if (info->cq_resize && info->virtual_map &&
2701 info->first_pm_pbl_idx >= pble_obj_cnt)
2702 return IRDMA_ERR_INVALID_PBLE_INDEX;
2703
2704 cqp = cq->dev->cqp;
2705 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
2706 if (!wqe)
2707 return IRDMA_ERR_RING_FULL;
2708
2709 set_64bit_val(wqe, 0, info->cq_size);
2710 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1);
2711 set_64bit_val(wqe, 16,
2712 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, info->shadow_read_threshold));
2713 set_64bit_val(wqe, 32, info->cq_pa);
2714 set_64bit_val(wqe, 40, cq->shadow_area_pa);
2715 set_64bit_val(wqe, 48, info->first_pm_pbl_idx);
2716 set_64bit_val(wqe, 56,
2717 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) |
2718 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx));
2719
2720 hdr = cq->cq_uk.cq_id |
2721 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_CQ) |
2722 FIELD_PREP(IRDMA_CQPSQ_CQ_CQRESIZE, info->cq_resize) |
2723 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, info->pbl_chunk_size) |
2724 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, info->check_overflow) |
2725 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, info->virtual_map) |
2726 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) |
2727 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) |
2728 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT,
2729 cq->cq_uk.avoid_mem_cflct) |
2730 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
2731 dma_wmb(); /* make sure WQE is written before valid bit is set */
2732
2733 set_64bit_val(wqe, 24, hdr);
2734
2735 print_hex_dump_debug("WQE: CQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8,
2736 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
2737 if (post_sq)
2738 irdma_sc_cqp_post_sq(cqp);
2739
2740 return 0;
2741 }
2742
2743 /**
2744 * irdma_check_cqp_progress - check cqp processing progress
2745 * @timeout: timeout info struct
2746 * @dev: sc device struct
2747 */
irdma_check_cqp_progress(struct irdma_cqp_timeout * timeout,struct irdma_sc_dev * dev)2748 void irdma_check_cqp_progress(struct irdma_cqp_timeout *timeout, struct irdma_sc_dev *dev)
2749 {
2750 u64 completed_ops = atomic64_read(&dev->cqp->completed_ops);
2751
2752 if (timeout->compl_cqp_cmds != completed_ops) {
2753 timeout->compl_cqp_cmds = completed_ops;
2754 timeout->count = 0;
2755 } else if (timeout->compl_cqp_cmds != dev->cqp->requested_ops) {
2756 timeout->count++;
2757 }
2758 }
2759
2760 /**
2761 * irdma_get_cqp_reg_info - get head and tail for cqp using registers
2762 * @cqp: struct for cqp hw
2763 * @val: cqp tail register value
2764 * @tail: wqtail register value
2765 * @error: cqp processing err
2766 */
irdma_get_cqp_reg_info(struct irdma_sc_cqp * cqp,u32 * val,u32 * tail,u32 * error)2767 static inline void irdma_get_cqp_reg_info(struct irdma_sc_cqp *cqp, u32 *val,
2768 u32 *tail, u32 *error)
2769 {
2770 *val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]);
2771 *tail = FIELD_GET(IRDMA_CQPTAIL_WQTAIL, *val);
2772 *error = FIELD_GET(IRDMA_CQPTAIL_CQP_OP_ERR, *val);
2773 }
2774
2775 /**
2776 * irdma_cqp_poll_registers - poll cqp registers
2777 * @cqp: struct for cqp hw
2778 * @tail: wqtail register value
2779 * @count: how many times to try for completion
2780 */
irdma_cqp_poll_registers(struct irdma_sc_cqp * cqp,u32 tail,u32 count)2781 static enum irdma_status_code irdma_cqp_poll_registers(struct irdma_sc_cqp *cqp,
2782 u32 tail, u32 count)
2783 {
2784 u32 i = 0;
2785 u32 newtail, error, val;
2786
2787 while (i++ < count) {
2788 irdma_get_cqp_reg_info(cqp, &val, &newtail, &error);
2789 if (error) {
2790 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
2791 ibdev_dbg(to_ibdev(cqp->dev),
2792 "CQP: CQPERRCODES error_code[x%08X]\n",
2793 error);
2794 return IRDMA_ERR_CQP_COMPL_ERROR;
2795 }
2796 if (newtail != tail) {
2797 /* SUCCESS */
2798 IRDMA_RING_MOVE_TAIL(cqp->sq_ring);
2799 atomic64_inc(&cqp->completed_ops);
2800 return 0;
2801 }
2802 udelay(cqp->dev->hw_attrs.max_sleep_count);
2803 }
2804
2805 return IRDMA_ERR_TIMEOUT;
2806 }
2807
2808 /**
2809 * irdma_sc_decode_fpm_commit - decode a 64 bit value into count and base
2810 * @dev: sc device struct
2811 * @buf: pointer to commit buffer
2812 * @buf_idx: buffer index
2813 * @obj_info: object info pointer
2814 * @rsrc_idx: indexs of memory resource
2815 */
irdma_sc_decode_fpm_commit(struct irdma_sc_dev * dev,__le64 * buf,u32 buf_idx,struct irdma_hmc_obj_info * obj_info,u32 rsrc_idx)2816 static u64 irdma_sc_decode_fpm_commit(struct irdma_sc_dev *dev, __le64 *buf,
2817 u32 buf_idx, struct irdma_hmc_obj_info *obj_info,
2818 u32 rsrc_idx)
2819 {
2820 u64 temp;
2821
2822 get_64bit_val(buf, buf_idx, &temp);
2823
2824 switch (rsrc_idx) {
2825 case IRDMA_HMC_IW_QP:
2826 obj_info[rsrc_idx].cnt = (u32)FIELD_GET(IRDMA_COMMIT_FPM_QPCNT, temp);
2827 break;
2828 case IRDMA_HMC_IW_CQ:
2829 obj_info[rsrc_idx].cnt = (u32)FLD_RS_64(dev, temp, IRDMA_COMMIT_FPM_CQCNT);
2830 break;
2831 case IRDMA_HMC_IW_APBVT_ENTRY:
2832 obj_info[rsrc_idx].cnt = 1;
2833 break;
2834 default:
2835 obj_info[rsrc_idx].cnt = (u32)temp;
2836 break;
2837 }
2838
2839 obj_info[rsrc_idx].base = (temp >> IRDMA_COMMIT_FPM_BASE_S) * 512;
2840
2841 return temp;
2842 }
2843
2844 /**
2845 * irdma_sc_parse_fpm_commit_buf - parse fpm commit buffer
2846 * @dev: pointer to dev struct
2847 * @buf: ptr to fpm commit buffer
2848 * @info: ptr to irdma_hmc_obj_info struct
2849 * @sd: number of SDs for HMC objects
2850 *
2851 * parses fpm commit info and copy base value
2852 * of hmc objects in hmc_info
2853 */
2854 static void
irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev * dev,__le64 * buf,struct irdma_hmc_obj_info * info,u32 * sd)2855 irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 *buf,
2856 struct irdma_hmc_obj_info *info, u32 *sd)
2857 {
2858 u64 size;
2859 u32 i;
2860 u64 max_base = 0;
2861 u32 last_hmc_obj = 0;
2862
2863 irdma_sc_decode_fpm_commit(dev, buf, 0, info,
2864 IRDMA_HMC_IW_QP);
2865 irdma_sc_decode_fpm_commit(dev, buf, 8, info,
2866 IRDMA_HMC_IW_CQ);
2867 /* skiping RSRVD */
2868 irdma_sc_decode_fpm_commit(dev, buf, 24, info,
2869 IRDMA_HMC_IW_HTE);
2870 irdma_sc_decode_fpm_commit(dev, buf, 32, info,
2871 IRDMA_HMC_IW_ARP);
2872 irdma_sc_decode_fpm_commit(dev, buf, 40, info,
2873 IRDMA_HMC_IW_APBVT_ENTRY);
2874 irdma_sc_decode_fpm_commit(dev, buf, 48, info,
2875 IRDMA_HMC_IW_MR);
2876 irdma_sc_decode_fpm_commit(dev, buf, 56, info,
2877 IRDMA_HMC_IW_XF);
2878 irdma_sc_decode_fpm_commit(dev, buf, 64, info,
2879 IRDMA_HMC_IW_XFFL);
2880 irdma_sc_decode_fpm_commit(dev, buf, 72, info,
2881 IRDMA_HMC_IW_Q1);
2882 irdma_sc_decode_fpm_commit(dev, buf, 80, info,
2883 IRDMA_HMC_IW_Q1FL);
2884 irdma_sc_decode_fpm_commit(dev, buf, 88, info,
2885 IRDMA_HMC_IW_TIMER);
2886 irdma_sc_decode_fpm_commit(dev, buf, 112, info,
2887 IRDMA_HMC_IW_PBLE);
2888 /* skipping RSVD. */
2889 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) {
2890 irdma_sc_decode_fpm_commit(dev, buf, 96, info,
2891 IRDMA_HMC_IW_FSIMC);
2892 irdma_sc_decode_fpm_commit(dev, buf, 104, info,
2893 IRDMA_HMC_IW_FSIAV);
2894 irdma_sc_decode_fpm_commit(dev, buf, 128, info,
2895 IRDMA_HMC_IW_RRF);
2896 irdma_sc_decode_fpm_commit(dev, buf, 136, info,
2897 IRDMA_HMC_IW_RRFFL);
2898 irdma_sc_decode_fpm_commit(dev, buf, 144, info,
2899 IRDMA_HMC_IW_HDR);
2900 irdma_sc_decode_fpm_commit(dev, buf, 152, info,
2901 IRDMA_HMC_IW_MD);
2902 irdma_sc_decode_fpm_commit(dev, buf, 160, info,
2903 IRDMA_HMC_IW_OOISC);
2904 irdma_sc_decode_fpm_commit(dev, buf, 168, info,
2905 IRDMA_HMC_IW_OOISCFFL);
2906 }
2907
2908 /* searching for the last object in HMC to find the size of the HMC area. */
2909 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) {
2910 if (info[i].base > max_base) {
2911 max_base = info[i].base;
2912 last_hmc_obj = i;
2913 }
2914 }
2915
2916 size = info[last_hmc_obj].cnt * info[last_hmc_obj].size +
2917 info[last_hmc_obj].base;
2918
2919 if (size & 0x1FFFFF)
2920 *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */
2921 else
2922 *sd = (u32)(size >> 21);
2923
2924 }
2925
2926 /**
2927 * irdma_sc_decode_fpm_query() - Decode a 64 bit value into max count and size
2928 * @buf: ptr to fpm query buffer
2929 * @buf_idx: index into buf
2930 * @obj_info: ptr to irdma_hmc_obj_info struct
2931 * @rsrc_idx: resource index into info
2932 *
2933 * Decode a 64 bit value from fpm query buffer into max count and size
2934 */
irdma_sc_decode_fpm_query(__le64 * buf,u32 buf_idx,struct irdma_hmc_obj_info * obj_info,u32 rsrc_idx)2935 static u64 irdma_sc_decode_fpm_query(__le64 *buf, u32 buf_idx,
2936 struct irdma_hmc_obj_info *obj_info,
2937 u32 rsrc_idx)
2938 {
2939 u64 temp;
2940 u32 size;
2941
2942 get_64bit_val(buf, buf_idx, &temp);
2943 obj_info[rsrc_idx].max_cnt = (u32)temp;
2944 size = (u32)(temp >> 32);
2945 obj_info[rsrc_idx].size = BIT_ULL(size);
2946
2947 return temp;
2948 }
2949
2950 /**
2951 * irdma_sc_parse_fpm_query_buf() - parses fpm query buffer
2952 * @dev: ptr to shared code device
2953 * @buf: ptr to fpm query buffer
2954 * @hmc_info: ptr to irdma_hmc_obj_info struct
2955 * @hmc_fpm_misc: ptr to fpm data
2956 *
2957 * parses fpm query buffer and copy max_cnt and
2958 * size value of hmc objects in hmc_info
2959 */
2960 static enum irdma_status_code
irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev * dev,__le64 * buf,struct irdma_hmc_info * hmc_info,struct irdma_hmc_fpm_misc * hmc_fpm_misc)2961 irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev *dev, __le64 *buf,
2962 struct irdma_hmc_info *hmc_info,
2963 struct irdma_hmc_fpm_misc *hmc_fpm_misc)
2964 {
2965 struct irdma_hmc_obj_info *obj_info;
2966 u64 temp;
2967 u32 size;
2968 u16 max_pe_sds;
2969
2970 obj_info = hmc_info->hmc_obj;
2971
2972 get_64bit_val(buf, 0, &temp);
2973 hmc_info->first_sd_index = (u16)FIELD_GET(IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX, temp);
2974 max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS, temp);
2975
2976 hmc_fpm_misc->max_sds = max_pe_sds;
2977 hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index;
2978 get_64bit_val(buf, 8, &temp);
2979 obj_info[IRDMA_HMC_IW_QP].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_QPS, temp);
2980 size = (u32)(temp >> 32);
2981 obj_info[IRDMA_HMC_IW_QP].size = BIT_ULL(size);
2982
2983 get_64bit_val(buf, 16, &temp);
2984 obj_info[IRDMA_HMC_IW_CQ].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_CQS, temp);
2985 size = (u32)(temp >> 32);
2986 obj_info[IRDMA_HMC_IW_CQ].size = BIT_ULL(size);
2987
2988 irdma_sc_decode_fpm_query(buf, 32, obj_info, IRDMA_HMC_IW_HTE);
2989 irdma_sc_decode_fpm_query(buf, 40, obj_info, IRDMA_HMC_IW_ARP);
2990
2991 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 8192;
2992 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 1;
2993
2994 irdma_sc_decode_fpm_query(buf, 48, obj_info, IRDMA_HMC_IW_MR);
2995 irdma_sc_decode_fpm_query(buf, 56, obj_info, IRDMA_HMC_IW_XF);
2996
2997 get_64bit_val(buf, 64, &temp);
2998 obj_info[IRDMA_HMC_IW_XFFL].max_cnt = (u32)temp;
2999 obj_info[IRDMA_HMC_IW_XFFL].size = 4;
3000 hmc_fpm_misc->xf_block_size = FIELD_GET(IRDMA_QUERY_FPM_XFBLOCKSIZE, temp);
3001 if (!hmc_fpm_misc->xf_block_size)
3002 return IRDMA_ERR_INVALID_SIZE;
3003
3004 irdma_sc_decode_fpm_query(buf, 72, obj_info, IRDMA_HMC_IW_Q1);
3005 get_64bit_val(buf, 80, &temp);
3006 obj_info[IRDMA_HMC_IW_Q1FL].max_cnt = (u32)temp;
3007 obj_info[IRDMA_HMC_IW_Q1FL].size = 4;
3008
3009 hmc_fpm_misc->q1_block_size = FIELD_GET(IRDMA_QUERY_FPM_Q1BLOCKSIZE, temp);
3010 if (!hmc_fpm_misc->q1_block_size)
3011 return IRDMA_ERR_INVALID_SIZE;
3012
3013 irdma_sc_decode_fpm_query(buf, 88, obj_info, IRDMA_HMC_IW_TIMER);
3014
3015 get_64bit_val(buf, 112, &temp);
3016 obj_info[IRDMA_HMC_IW_PBLE].max_cnt = (u32)temp;
3017 obj_info[IRDMA_HMC_IW_PBLE].size = 8;
3018
3019 get_64bit_val(buf, 120, &temp);
3020 hmc_fpm_misc->max_ceqs = FIELD_GET(IRDMA_QUERY_FPM_MAX_CEQS, temp);
3021 hmc_fpm_misc->ht_multiplier = FIELD_GET(IRDMA_QUERY_FPM_HTMULTIPLIER, temp);
3022 hmc_fpm_misc->timer_bucket = FIELD_GET(IRDMA_QUERY_FPM_TIMERBUCKET, temp);
3023 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
3024 return 0;
3025 irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC);
3026 irdma_sc_decode_fpm_query(buf, 104, obj_info, IRDMA_HMC_IW_FSIAV);
3027 irdma_sc_decode_fpm_query(buf, 128, obj_info, IRDMA_HMC_IW_RRF);
3028
3029 get_64bit_val(buf, 136, &temp);
3030 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt = (u32)temp;
3031 obj_info[IRDMA_HMC_IW_RRFFL].size = 4;
3032 hmc_fpm_misc->rrf_block_size = FIELD_GET(IRDMA_QUERY_FPM_RRFBLOCKSIZE, temp);
3033 if (!hmc_fpm_misc->rrf_block_size &&
3034 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt)
3035 return IRDMA_ERR_INVALID_SIZE;
3036
3037 irdma_sc_decode_fpm_query(buf, 144, obj_info, IRDMA_HMC_IW_HDR);
3038 irdma_sc_decode_fpm_query(buf, 152, obj_info, IRDMA_HMC_IW_MD);
3039 irdma_sc_decode_fpm_query(buf, 160, obj_info, IRDMA_HMC_IW_OOISC);
3040
3041 get_64bit_val(buf, 168, &temp);
3042 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt = (u32)temp;
3043 obj_info[IRDMA_HMC_IW_OOISCFFL].size = 4;
3044 hmc_fpm_misc->ooiscf_block_size = FIELD_GET(IRDMA_QUERY_FPM_OOISCFBLOCKSIZE, temp);
3045 if (!hmc_fpm_misc->ooiscf_block_size &&
3046 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt)
3047 return IRDMA_ERR_INVALID_SIZE;
3048
3049 return 0;
3050 }
3051
3052 /**
3053 * irdma_sc_find_reg_cq - find cq ctx index
3054 * @ceq: ceq sc structure
3055 * @cq: cq sc structure
3056 */
irdma_sc_find_reg_cq(struct irdma_sc_ceq * ceq,struct irdma_sc_cq * cq)3057 static u32 irdma_sc_find_reg_cq(struct irdma_sc_ceq *ceq,
3058 struct irdma_sc_cq *cq)
3059 {
3060 u32 i;
3061
3062 for (i = 0; i < ceq->reg_cq_size; i++) {
3063 if (cq == ceq->reg_cq[i])
3064 return i;
3065 }
3066
3067 return IRDMA_INVALID_CQ_IDX;
3068 }
3069
3070 /**
3071 * irdma_sc_add_cq_ctx - add cq ctx tracking for ceq
3072 * @ceq: ceq sc structure
3073 * @cq: cq sc structure
3074 */
irdma_sc_add_cq_ctx(struct irdma_sc_ceq * ceq,struct irdma_sc_cq * cq)3075 enum irdma_status_code irdma_sc_add_cq_ctx(struct irdma_sc_ceq *ceq,
3076 struct irdma_sc_cq *cq)
3077 {
3078 unsigned long flags;
3079
3080 spin_lock_irqsave(&ceq->req_cq_lock, flags);
3081
3082 if (ceq->reg_cq_size == ceq->elem_cnt) {
3083 spin_unlock_irqrestore(&ceq->req_cq_lock, flags);
3084 return IRDMA_ERR_REG_CQ_FULL;
3085 }
3086
3087 ceq->reg_cq[ceq->reg_cq_size++] = cq;
3088
3089 spin_unlock_irqrestore(&ceq->req_cq_lock, flags);
3090
3091 return 0;
3092 }
3093
3094 /**
3095 * irdma_sc_remove_cq_ctx - remove cq ctx tracking for ceq
3096 * @ceq: ceq sc structure
3097 * @cq: cq sc structure
3098 */
irdma_sc_remove_cq_ctx(struct irdma_sc_ceq * ceq,struct irdma_sc_cq * cq)3099 void irdma_sc_remove_cq_ctx(struct irdma_sc_ceq *ceq, struct irdma_sc_cq *cq)
3100 {
3101 unsigned long flags;
3102 u32 cq_ctx_idx;
3103
3104 spin_lock_irqsave(&ceq->req_cq_lock, flags);
3105 cq_ctx_idx = irdma_sc_find_reg_cq(ceq, cq);
3106 if (cq_ctx_idx == IRDMA_INVALID_CQ_IDX)
3107 goto exit;
3108
3109 ceq->reg_cq_size--;
3110 if (cq_ctx_idx != ceq->reg_cq_size)
3111 ceq->reg_cq[cq_ctx_idx] = ceq->reg_cq[ceq->reg_cq_size];
3112 ceq->reg_cq[ceq->reg_cq_size] = NULL;
3113
3114 exit:
3115 spin_unlock_irqrestore(&ceq->req_cq_lock, flags);
3116 }
3117
3118 /**
3119 * irdma_sc_cqp_init - Initialize buffers for a control Queue Pair
3120 * @cqp: IWARP control queue pair pointer
3121 * @info: IWARP control queue pair init info pointer
3122 *
3123 * Initializes the object and context buffers for a control Queue Pair.
3124 */
irdma_sc_cqp_init(struct irdma_sc_cqp * cqp,struct irdma_cqp_init_info * info)3125 enum irdma_status_code irdma_sc_cqp_init(struct irdma_sc_cqp *cqp,
3126 struct irdma_cqp_init_info *info)
3127 {
3128 u8 hw_sq_size;
3129
3130 if (info->sq_size > IRDMA_CQP_SW_SQSIZE_2048 ||
3131 info->sq_size < IRDMA_CQP_SW_SQSIZE_4 ||
3132 ((info->sq_size & (info->sq_size - 1))))
3133 return IRDMA_ERR_INVALID_SIZE;
3134
3135 hw_sq_size = irdma_get_encoded_wqe_size(info->sq_size,
3136 IRDMA_QUEUE_TYPE_CQP);
3137 cqp->size = sizeof(*cqp);
3138 cqp->sq_size = info->sq_size;
3139 cqp->hw_sq_size = hw_sq_size;
3140 cqp->sq_base = info->sq;
3141 cqp->host_ctx = info->host_ctx;
3142 cqp->sq_pa = info->sq_pa;
3143 cqp->host_ctx_pa = info->host_ctx_pa;
3144 cqp->dev = info->dev;
3145 cqp->struct_ver = info->struct_ver;
3146 cqp->hw_maj_ver = info->hw_maj_ver;
3147 cqp->hw_min_ver = info->hw_min_ver;
3148 cqp->scratch_array = info->scratch_array;
3149 cqp->polarity = 0;
3150 cqp->en_datacenter_tcp = info->en_datacenter_tcp;
3151 cqp->ena_vf_count = info->ena_vf_count;
3152 cqp->hmc_profile = info->hmc_profile;
3153 cqp->ceqs_per_vf = info->ceqs_per_vf;
3154 cqp->disable_packed = info->disable_packed;
3155 cqp->rocev2_rto_policy = info->rocev2_rto_policy;
3156 cqp->protocol_used = info->protocol_used;
3157 memcpy(&cqp->dcqcn_params, &info->dcqcn_params, sizeof(cqp->dcqcn_params));
3158 info->dev->cqp = cqp;
3159
3160 IRDMA_RING_INIT(cqp->sq_ring, cqp->sq_size);
3161 cqp->requested_ops = 0;
3162 atomic64_set(&cqp->completed_ops, 0);
3163 /* for the cqp commands backlog. */
3164 INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head);
3165
3166 writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]);
3167 writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]);
3168 writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
3169
3170 ibdev_dbg(to_ibdev(cqp->dev),
3171 "WQE: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%pK] cqp[%p] polarity[x%04x]\n",
3172 cqp->sq_size, cqp->hw_sq_size, cqp->sq_base,
3173 (u64 *)(uintptr_t)cqp->sq_pa, cqp, cqp->polarity);
3174 return 0;
3175 }
3176
3177 /**
3178 * irdma_sc_cqp_create - create cqp during bringup
3179 * @cqp: struct for cqp hw
3180 * @maj_err: If error, major err number
3181 * @min_err: If error, minor err number
3182 */
irdma_sc_cqp_create(struct irdma_sc_cqp * cqp,u16 * maj_err,u16 * min_err)3183 enum irdma_status_code irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err,
3184 u16 *min_err)
3185 {
3186 u64 temp;
3187 u8 hw_rev;
3188 u32 cnt = 0, p1, p2, val = 0, err_code;
3189 enum irdma_status_code ret_code;
3190
3191 hw_rev = cqp->dev->hw_attrs.uk_attrs.hw_rev;
3192 cqp->sdbuf.size = ALIGN(IRDMA_UPDATE_SD_BUFF_SIZE * cqp->sq_size,
3193 IRDMA_SD_BUF_ALIGNMENT);
3194 cqp->sdbuf.va = dma_alloc_coherent(cqp->dev->hw->device,
3195 cqp->sdbuf.size, &cqp->sdbuf.pa,
3196 GFP_KERNEL);
3197 if (!cqp->sdbuf.va)
3198 return IRDMA_ERR_NO_MEMORY;
3199
3200 spin_lock_init(&cqp->dev->cqp_lock);
3201
3202 temp = FIELD_PREP(IRDMA_CQPHC_SQSIZE, cqp->hw_sq_size) |
3203 FIELD_PREP(IRDMA_CQPHC_SVER, cqp->struct_ver) |
3204 FIELD_PREP(IRDMA_CQPHC_DISABLE_PFPDUS, cqp->disable_packed) |
3205 FIELD_PREP(IRDMA_CQPHC_CEQPERVF, cqp->ceqs_per_vf);
3206 if (hw_rev >= IRDMA_GEN_2) {
3207 temp |= FIELD_PREP(IRDMA_CQPHC_ROCEV2_RTO_POLICY,
3208 cqp->rocev2_rto_policy) |
3209 FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED,
3210 cqp->protocol_used);
3211 }
3212
3213 set_64bit_val(cqp->host_ctx, 0, temp);
3214 set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa);
3215
3216 temp = FIELD_PREP(IRDMA_CQPHC_ENABLED_VFS, cqp->ena_vf_count) |
3217 FIELD_PREP(IRDMA_CQPHC_HMC_PROFILE, cqp->hmc_profile);
3218 set_64bit_val(cqp->host_ctx, 16, temp);
3219 set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp);
3220 temp = FIELD_PREP(IRDMA_CQPHC_HW_MAJVER, cqp->hw_maj_ver) |
3221 FIELD_PREP(IRDMA_CQPHC_HW_MINVER, cqp->hw_min_ver);
3222 if (hw_rev >= IRDMA_GEN_2) {
3223 temp |= FIELD_PREP(IRDMA_CQPHC_MIN_RATE, cqp->dcqcn_params.min_rate) |
3224 FIELD_PREP(IRDMA_CQPHC_MIN_DEC_FACTOR, cqp->dcqcn_params.min_dec_factor);
3225 }
3226 set_64bit_val(cqp->host_ctx, 32, temp);
3227 set_64bit_val(cqp->host_ctx, 40, 0);
3228 temp = 0;
3229 if (hw_rev >= IRDMA_GEN_2) {
3230 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_T, cqp->dcqcn_params.dcqcn_t) |
3231 FIELD_PREP(IRDMA_CQPHC_RAI_FACTOR, cqp->dcqcn_params.rai_factor) |
3232 FIELD_PREP(IRDMA_CQPHC_HAI_FACTOR, cqp->dcqcn_params.hai_factor);
3233 }
3234 set_64bit_val(cqp->host_ctx, 48, temp);
3235 temp = 0;
3236 if (hw_rev >= IRDMA_GEN_2) {
3237 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_B, cqp->dcqcn_params.dcqcn_b) |
3238 FIELD_PREP(IRDMA_CQPHC_DCQCN_F, cqp->dcqcn_params.dcqcn_f) |
3239 FIELD_PREP(IRDMA_CQPHC_CC_CFG_VALID, cqp->dcqcn_params.cc_cfg_valid) |
3240 FIELD_PREP(IRDMA_CQPHC_RREDUCE_MPERIOD, cqp->dcqcn_params.rreduce_mperiod);
3241 }
3242 set_64bit_val(cqp->host_ctx, 56, temp);
3243 print_hex_dump_debug("WQE: CQP_HOST_CTX WQE", DUMP_PREFIX_OFFSET, 16,
3244 8, cqp->host_ctx, IRDMA_CQP_CTX_SIZE * 8, false);
3245 p1 = cqp->host_ctx_pa >> 32;
3246 p2 = (u32)cqp->host_ctx_pa;
3247
3248 writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
3249 writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
3250
3251 do {
3252 if (cnt++ > cqp->dev->hw_attrs.max_done_count) {
3253 ret_code = IRDMA_ERR_TIMEOUT;
3254 goto err;
3255 }
3256 udelay(cqp->dev->hw_attrs.max_sleep_count);
3257 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
3258 } while (!val);
3259
3260 if (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_ERR)) {
3261 ret_code = IRDMA_ERR_DEVICE_NOT_SUPPORTED;
3262 goto err;
3263 }
3264
3265 cqp->process_cqp_sds = irdma_update_sds_noccq;
3266 return 0;
3267
3268 err:
3269 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size,
3270 cqp->sdbuf.va, cqp->sdbuf.pa);
3271 cqp->sdbuf.va = NULL;
3272 err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
3273 *min_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MINOR_CODE, err_code);
3274 *maj_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MAJOR_CODE, err_code);
3275 return ret_code;
3276 }
3277
3278 /**
3279 * irdma_sc_cqp_post_sq - post of cqp's sq
3280 * @cqp: struct for cqp hw
3281 */
irdma_sc_cqp_post_sq(struct irdma_sc_cqp * cqp)3282 void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp)
3283 {
3284 writel(IRDMA_RING_CURRENT_HEAD(cqp->sq_ring), cqp->dev->cqp_db);
3285
3286 ibdev_dbg(to_ibdev(cqp->dev),
3287 "WQE: CQP SQ head 0x%x tail 0x%x size 0x%x\n",
3288 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size);
3289 }
3290
3291 /**
3292 * irdma_sc_cqp_get_next_send_wqe_idx - get next wqe on cqp sq
3293 * and pass back index
3294 * @cqp: CQP HW structure
3295 * @scratch: private data for CQP WQE
3296 * @wqe_idx: WQE index of CQP SQ
3297 */
irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp * cqp,u64 scratch,u32 * wqe_idx)3298 __le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch,
3299 u32 *wqe_idx)
3300 {
3301 __le64 *wqe = NULL;
3302 enum irdma_status_code ret_code;
3303
3304 if (IRDMA_RING_FULL_ERR(cqp->sq_ring)) {
3305 ibdev_dbg(to_ibdev(cqp->dev),
3306 "WQE: CQP SQ is full, head 0x%x tail 0x%x size 0x%x\n",
3307 cqp->sq_ring.head, cqp->sq_ring.tail,
3308 cqp->sq_ring.size);
3309 return NULL;
3310 }
3311 IRDMA_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code);
3312 if (ret_code)
3313 return NULL;
3314
3315 cqp->requested_ops++;
3316 if (!*wqe_idx)
3317 cqp->polarity = !cqp->polarity;
3318 wqe = cqp->sq_base[*wqe_idx].elem;
3319 cqp->scratch_array[*wqe_idx] = scratch;
3320 IRDMA_CQP_INIT_WQE(wqe);
3321
3322 return wqe;
3323 }
3324
3325 /**
3326 * irdma_sc_cqp_destroy - destroy cqp during close
3327 * @cqp: struct for cqp hw
3328 */
irdma_sc_cqp_destroy(struct irdma_sc_cqp * cqp)3329 enum irdma_status_code irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp)
3330 {
3331 u32 cnt = 0, val;
3332 enum irdma_status_code ret_code = 0;
3333
3334 writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
3335 writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
3336 do {
3337 if (cnt++ > cqp->dev->hw_attrs.max_done_count) {
3338 ret_code = IRDMA_ERR_TIMEOUT;
3339 break;
3340 }
3341 udelay(cqp->dev->hw_attrs.max_sleep_count);
3342 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
3343 } while (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_DONE));
3344
3345 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size,
3346 cqp->sdbuf.va, cqp->sdbuf.pa);
3347 cqp->sdbuf.va = NULL;
3348 return ret_code;
3349 }
3350
3351 /**
3352 * irdma_sc_ccq_arm - enable intr for control cq
3353 * @ccq: ccq sc struct
3354 */
irdma_sc_ccq_arm(struct irdma_sc_cq * ccq)3355 void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq)
3356 {
3357 u64 temp_val;
3358 u16 sw_cq_sel;
3359 u8 arm_next_se;
3360 u8 arm_seq_num;
3361
3362 get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val);
3363 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val);
3364 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val);
3365 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val);
3366 arm_seq_num++;
3367 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) |
3368 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) |
3369 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) |
3370 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, 1);
3371 set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val);
3372
3373 dma_wmb(); /* make sure shadow area is updated before arming */
3374
3375 writel(ccq->cq_uk.cq_id, ccq->dev->cq_arm_db);
3376 }
3377
3378 /**
3379 * irdma_sc_ccq_get_cqe_info - get ccq's cq entry
3380 * @ccq: ccq sc struct
3381 * @info: completion q entry to return
3382 */
irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq * ccq,struct irdma_ccq_cqe_info * info)3383 enum irdma_status_code irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq,
3384 struct irdma_ccq_cqe_info *info)
3385 {
3386 u64 qp_ctx, temp, temp1;
3387 __le64 *cqe;
3388 struct irdma_sc_cqp *cqp;
3389 u32 wqe_idx;
3390 u32 error;
3391 u8 polarity;
3392 enum irdma_status_code ret_code = 0;
3393
3394 if (ccq->cq_uk.avoid_mem_cflct)
3395 cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(&ccq->cq_uk);
3396 else
3397 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&ccq->cq_uk);
3398
3399 get_64bit_val(cqe, 24, &temp);
3400 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, temp);
3401 if (polarity != ccq->cq_uk.polarity)
3402 return IRDMA_ERR_Q_EMPTY;
3403
3404 /* Ensure CEQE contents are read after valid bit is checked */
3405 dma_rmb();
3406
3407 get_64bit_val(cqe, 8, &qp_ctx);
3408 cqp = (struct irdma_sc_cqp *)(unsigned long)qp_ctx;
3409 info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, temp);
3410 info->maj_err_code = IRDMA_CQPSQ_MAJ_NO_ERROR;
3411 info->min_err_code = (u16)FIELD_GET(IRDMA_CQ_MINERR, temp);
3412 if (info->error) {
3413 info->maj_err_code = (u16)FIELD_GET(IRDMA_CQ_MAJERR, temp);
3414 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
3415 ibdev_dbg(to_ibdev(cqp->dev),
3416 "CQP: CQPERRCODES error_code[x%08X]\n", error);
3417 }
3418
3419 wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, temp);
3420 info->scratch = cqp->scratch_array[wqe_idx];
3421
3422 get_64bit_val(cqe, 16, &temp1);
3423 info->op_ret_val = (u32)FIELD_GET(IRDMA_CCQ_OPRETVAL, temp1);
3424 get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1);
3425 info->op_code = (u8)FIELD_GET(IRDMA_CQPSQ_OPCODE, temp1);
3426 info->cqp = cqp;
3427
3428 /* move the head for cq */
3429 IRDMA_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code);
3430 if (!IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring))
3431 ccq->cq_uk.polarity ^= 1;
3432
3433 /* update cq tail in cq shadow memory also */
3434 IRDMA_RING_MOVE_TAIL(ccq->cq_uk.cq_ring);
3435 set_64bit_val(ccq->cq_uk.shadow_area, 0,
3436 IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring));
3437
3438 dma_wmb(); /* make sure shadow area is updated before moving tail */
3439
3440 IRDMA_RING_MOVE_TAIL(cqp->sq_ring);
3441 atomic64_inc(&cqp->completed_ops);
3442
3443 return ret_code;
3444 }
3445
3446 /**
3447 * irdma_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ
3448 * @cqp: struct for cqp hw
3449 * @op_code: cqp opcode for completion
3450 * @compl_info: completion q entry to return
3451 */
irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp * cqp,u8 op_code,struct irdma_ccq_cqe_info * compl_info)3452 enum irdma_status_code irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 op_code,
3453 struct irdma_ccq_cqe_info *compl_info)
3454 {
3455 struct irdma_ccq_cqe_info info = {};
3456 struct irdma_sc_cq *ccq;
3457 enum irdma_status_code ret_code = 0;
3458 u32 cnt = 0;
3459
3460 ccq = cqp->dev->ccq;
3461 while (1) {
3462 if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count)
3463 return IRDMA_ERR_TIMEOUT;
3464
3465 if (irdma_sc_ccq_get_cqe_info(ccq, &info)) {
3466 udelay(cqp->dev->hw_attrs.max_sleep_count);
3467 continue;
3468 }
3469 if (info.error && info.op_code != IRDMA_CQP_OP_QUERY_STAG) {
3470 ret_code = IRDMA_ERR_CQP_COMPL_ERROR;
3471 break;
3472 }
3473 /* make sure op code matches*/
3474 if (op_code == info.op_code)
3475 break;
3476 ibdev_dbg(to_ibdev(cqp->dev),
3477 "WQE: opcode mismatch for my op code 0x%x, returned opcode %x\n",
3478 op_code, info.op_code);
3479 }
3480
3481 if (compl_info)
3482 memcpy(compl_info, &info, sizeof(*compl_info));
3483
3484 return ret_code;
3485 }
3486
3487 /**
3488 * irdma_sc_manage_hmc_pm_func_table - manage of function table
3489 * @cqp: struct for cqp hw
3490 * @scratch: u64 saved to be used during cqp completion
3491 * @info: info for the manage function table operation
3492 * @post_sq: flag for cqp db to ring
3493 */
3494 static enum irdma_status_code
irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp * cqp,struct irdma_hmc_fcn_info * info,u64 scratch,bool post_sq)3495 irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp *cqp,
3496 struct irdma_hmc_fcn_info *info,
3497 u64 scratch, bool post_sq)
3498 {
3499 __le64 *wqe;
3500 u64 hdr;
3501
3502 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3503 if (!wqe)
3504 return IRDMA_ERR_RING_FULL;
3505
3506 set_64bit_val(wqe, 0, 0);
3507 set_64bit_val(wqe, 8, 0);
3508 set_64bit_val(wqe, 16, 0);
3509 set_64bit_val(wqe, 32, 0);
3510 set_64bit_val(wqe, 40, 0);
3511 set_64bit_val(wqe, 48, 0);
3512 set_64bit_val(wqe, 56, 0);
3513
3514 hdr = FIELD_PREP(IRDMA_CQPSQ_MHMC_VFIDX, info->vf_id) |
3515 FIELD_PREP(IRDMA_CQPSQ_OPCODE,
3516 IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE) |
3517 FIELD_PREP(IRDMA_CQPSQ_MHMC_FREEPMFN, info->free_fcn) |
3518 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3519 dma_wmb(); /* make sure WQE is written before valid bit is set */
3520
3521 set_64bit_val(wqe, 24, hdr);
3522
3523 print_hex_dump_debug("WQE: MANAGE_HMC_PM_FUNC_TABLE WQE",
3524 DUMP_PREFIX_OFFSET, 16, 8, wqe,
3525 IRDMA_CQP_WQE_SIZE * 8, false);
3526 if (post_sq)
3527 irdma_sc_cqp_post_sq(cqp);
3528
3529 return 0;
3530 }
3531
3532 /**
3533 * irdma_sc_commit_fpm_val_done - wait for cqp eqe completion
3534 * for fpm commit
3535 * @cqp: struct for cqp hw
3536 */
3537 static enum irdma_status_code
irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp * cqp)3538 irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp *cqp)
3539 {
3540 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_COMMIT_FPM_VAL,
3541 NULL);
3542 }
3543
3544 /**
3545 * irdma_sc_commit_fpm_val - cqp wqe for commit fpm values
3546 * @cqp: struct for cqp hw
3547 * @scratch: u64 saved to be used during cqp completion
3548 * @hmc_fn_id: hmc function id
3549 * @commit_fpm_mem: Memory for fpm values
3550 * @post_sq: flag for cqp db to ring
3551 * @wait_type: poll ccq or cqp registers for cqp completion
3552 */
3553 static enum irdma_status_code
irdma_sc_commit_fpm_val(struct irdma_sc_cqp * cqp,u64 scratch,u8 hmc_fn_id,struct irdma_dma_mem * commit_fpm_mem,bool post_sq,u8 wait_type)3554 irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, u8 hmc_fn_id,
3555 struct irdma_dma_mem *commit_fpm_mem, bool post_sq,
3556 u8 wait_type)
3557 {
3558 __le64 *wqe;
3559 u64 hdr;
3560 u32 tail, val, error;
3561 enum irdma_status_code ret_code = 0;
3562
3563 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3564 if (!wqe)
3565 return IRDMA_ERR_RING_FULL;
3566
3567 set_64bit_val(wqe, 16, hmc_fn_id);
3568 set_64bit_val(wqe, 32, commit_fpm_mem->pa);
3569
3570 hdr = FIELD_PREP(IRDMA_CQPSQ_BUFSIZE, IRDMA_COMMIT_FPM_BUF_SIZE) |
3571 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_COMMIT_FPM_VAL) |
3572 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3573
3574 dma_wmb(); /* make sure WQE is written before valid bit is set */
3575
3576 set_64bit_val(wqe, 24, hdr);
3577
3578 print_hex_dump_debug("WQE: COMMIT_FPM_VAL WQE", DUMP_PREFIX_OFFSET,
3579 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
3580 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
3581
3582 if (post_sq) {
3583 irdma_sc_cqp_post_sq(cqp);
3584 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS)
3585 ret_code = irdma_cqp_poll_registers(cqp, tail,
3586 cqp->dev->hw_attrs.max_done_count);
3587 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ)
3588 ret_code = irdma_sc_commit_fpm_val_done(cqp);
3589 }
3590
3591 return ret_code;
3592 }
3593
3594 /**
3595 * irdma_sc_query_fpm_val_done - poll for cqp wqe completion for
3596 * query fpm
3597 * @cqp: struct for cqp hw
3598 */
3599 static enum irdma_status_code
irdma_sc_query_fpm_val_done(struct irdma_sc_cqp * cqp)3600 irdma_sc_query_fpm_val_done(struct irdma_sc_cqp *cqp)
3601 {
3602 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_QUERY_FPM_VAL,
3603 NULL);
3604 }
3605
3606 /**
3607 * irdma_sc_query_fpm_val - cqp wqe query fpm values
3608 * @cqp: struct for cqp hw
3609 * @scratch: u64 saved to be used during cqp completion
3610 * @hmc_fn_id: hmc function id
3611 * @query_fpm_mem: memory for return fpm values
3612 * @post_sq: flag for cqp db to ring
3613 * @wait_type: poll ccq or cqp registers for cqp completion
3614 */
3615 static enum irdma_status_code
irdma_sc_query_fpm_val(struct irdma_sc_cqp * cqp,u64 scratch,u8 hmc_fn_id,struct irdma_dma_mem * query_fpm_mem,bool post_sq,u8 wait_type)3616 irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, u8 hmc_fn_id,
3617 struct irdma_dma_mem *query_fpm_mem, bool post_sq,
3618 u8 wait_type)
3619 {
3620 __le64 *wqe;
3621 u64 hdr;
3622 u32 tail, val, error;
3623 enum irdma_status_code ret_code = 0;
3624
3625 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3626 if (!wqe)
3627 return IRDMA_ERR_RING_FULL;
3628
3629 set_64bit_val(wqe, 16, hmc_fn_id);
3630 set_64bit_val(wqe, 32, query_fpm_mem->pa);
3631
3632 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_QUERY_FPM_VAL) |
3633 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3634 dma_wmb(); /* make sure WQE is written before valid bit is set */
3635
3636 set_64bit_val(wqe, 24, hdr);
3637
3638 print_hex_dump_debug("WQE: QUERY_FPM WQE", DUMP_PREFIX_OFFSET, 16, 8,
3639 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
3640 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
3641
3642 if (post_sq) {
3643 irdma_sc_cqp_post_sq(cqp);
3644 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS)
3645 ret_code = irdma_cqp_poll_registers(cqp, tail,
3646 cqp->dev->hw_attrs.max_done_count);
3647 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ)
3648 ret_code = irdma_sc_query_fpm_val_done(cqp);
3649 }
3650
3651 return ret_code;
3652 }
3653
3654 /**
3655 * irdma_sc_ceq_init - initialize ceq
3656 * @ceq: ceq sc structure
3657 * @info: ceq initialization info
3658 */
irdma_sc_ceq_init(struct irdma_sc_ceq * ceq,struct irdma_ceq_init_info * info)3659 enum irdma_status_code irdma_sc_ceq_init(struct irdma_sc_ceq *ceq,
3660 struct irdma_ceq_init_info *info)
3661 {
3662 u32 pble_obj_cnt;
3663
3664 if (info->elem_cnt < info->dev->hw_attrs.min_hw_ceq_size ||
3665 info->elem_cnt > info->dev->hw_attrs.max_hw_ceq_size)
3666 return IRDMA_ERR_INVALID_SIZE;
3667
3668 if (info->ceq_id >= (info->dev->hmc_fpm_misc.max_ceqs))
3669 return IRDMA_ERR_INVALID_CEQ_ID;
3670 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
3671
3672 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
3673 return IRDMA_ERR_INVALID_PBLE_INDEX;
3674
3675 ceq->size = sizeof(*ceq);
3676 ceq->ceqe_base = (struct irdma_ceqe *)info->ceqe_base;
3677 ceq->ceq_id = info->ceq_id;
3678 ceq->dev = info->dev;
3679 ceq->elem_cnt = info->elem_cnt;
3680 ceq->ceq_elem_pa = info->ceqe_pa;
3681 ceq->virtual_map = info->virtual_map;
3682 ceq->itr_no_expire = info->itr_no_expire;
3683 ceq->reg_cq = info->reg_cq;
3684 ceq->reg_cq_size = 0;
3685 spin_lock_init(&ceq->req_cq_lock);
3686 ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0);
3687 ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0);
3688 ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL);
3689 ceq->tph_en = info->tph_en;
3690 ceq->tph_val = info->tph_val;
3691 ceq->vsi = info->vsi;
3692 ceq->polarity = 1;
3693 IRDMA_RING_INIT(ceq->ceq_ring, ceq->elem_cnt);
3694 ceq->dev->ceq[info->ceq_id] = ceq;
3695
3696 return 0;
3697 }
3698
3699 /**
3700 * irdma_sc_ceq_create - create ceq wqe
3701 * @ceq: ceq sc structure
3702 * @scratch: u64 saved to be used during cqp completion
3703 * @post_sq: flag for cqp db to ring
3704 */
3705
irdma_sc_ceq_create(struct irdma_sc_ceq * ceq,u64 scratch,bool post_sq)3706 static enum irdma_status_code irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch,
3707 bool post_sq)
3708 {
3709 struct irdma_sc_cqp *cqp;
3710 __le64 *wqe;
3711 u64 hdr;
3712
3713 cqp = ceq->dev->cqp;
3714 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3715 if (!wqe)
3716 return IRDMA_ERR_RING_FULL;
3717 set_64bit_val(wqe, 16, ceq->elem_cnt);
3718 set_64bit_val(wqe, 32,
3719 (ceq->virtual_map ? 0 : ceq->ceq_elem_pa));
3720 set_64bit_val(wqe, 48,
3721 (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0));
3722 set_64bit_val(wqe, 56,
3723 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, ceq->tph_val) |
3724 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, ceq->vsi->vsi_idx));
3725 hdr = FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID, ceq->ceq_id) |
3726 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CEQ) |
3727 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) |
3728 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) |
3729 FIELD_PREP(IRDMA_CQPSQ_CEQ_ITRNOEXPIRE, ceq->itr_no_expire) |
3730 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) |
3731 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3732 dma_wmb(); /* make sure WQE is written before valid bit is set */
3733
3734 set_64bit_val(wqe, 24, hdr);
3735
3736 print_hex_dump_debug("WQE: CEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8,
3737 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
3738 if (post_sq)
3739 irdma_sc_cqp_post_sq(cqp);
3740
3741 return 0;
3742 }
3743
3744 /**
3745 * irdma_sc_cceq_create_done - poll for control ceq wqe to complete
3746 * @ceq: ceq sc structure
3747 */
3748 static enum irdma_status_code
irdma_sc_cceq_create_done(struct irdma_sc_ceq * ceq)3749 irdma_sc_cceq_create_done(struct irdma_sc_ceq *ceq)
3750 {
3751 struct irdma_sc_cqp *cqp;
3752
3753 cqp = ceq->dev->cqp;
3754 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CEQ,
3755 NULL);
3756 }
3757
3758 /**
3759 * irdma_sc_cceq_destroy_done - poll for destroy cceq to complete
3760 * @ceq: ceq sc structure
3761 */
irdma_sc_cceq_destroy_done(struct irdma_sc_ceq * ceq)3762 enum irdma_status_code irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq)
3763 {
3764 struct irdma_sc_cqp *cqp;
3765
3766 if (ceq->reg_cq)
3767 irdma_sc_remove_cq_ctx(ceq, ceq->dev->ccq);
3768
3769 cqp = ceq->dev->cqp;
3770 cqp->process_cqp_sds = irdma_update_sds_noccq;
3771
3772 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_DESTROY_CEQ,
3773 NULL);
3774 }
3775
3776 /**
3777 * irdma_sc_cceq_create - create cceq
3778 * @ceq: ceq sc structure
3779 * @scratch: u64 saved to be used during cqp completion
3780 */
irdma_sc_cceq_create(struct irdma_sc_ceq * ceq,u64 scratch)3781 enum irdma_status_code irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch)
3782 {
3783 enum irdma_status_code ret_code;
3784 struct irdma_sc_dev *dev = ceq->dev;
3785
3786 dev->ccq->vsi = ceq->vsi;
3787 if (ceq->reg_cq) {
3788 ret_code = irdma_sc_add_cq_ctx(ceq, ceq->dev->ccq);
3789 if (ret_code)
3790 return ret_code;
3791 }
3792
3793 ret_code = irdma_sc_ceq_create(ceq, scratch, true);
3794 if (!ret_code)
3795 return irdma_sc_cceq_create_done(ceq);
3796
3797 return ret_code;
3798 }
3799
3800 /**
3801 * irdma_sc_ceq_destroy - destroy ceq
3802 * @ceq: ceq sc structure
3803 * @scratch: u64 saved to be used during cqp completion
3804 * @post_sq: flag for cqp db to ring
3805 */
irdma_sc_ceq_destroy(struct irdma_sc_ceq * ceq,u64 scratch,bool post_sq)3806 enum irdma_status_code irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch,
3807 bool post_sq)
3808 {
3809 struct irdma_sc_cqp *cqp;
3810 __le64 *wqe;
3811 u64 hdr;
3812
3813 cqp = ceq->dev->cqp;
3814 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3815 if (!wqe)
3816 return IRDMA_ERR_RING_FULL;
3817
3818 set_64bit_val(wqe, 16, ceq->elem_cnt);
3819 set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx);
3820 hdr = ceq->ceq_id |
3821 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CEQ) |
3822 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) |
3823 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) |
3824 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) |
3825 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3826 dma_wmb(); /* make sure WQE is written before valid bit is set */
3827
3828 set_64bit_val(wqe, 24, hdr);
3829
3830 print_hex_dump_debug("WQE: CEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16,
3831 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
3832 if (post_sq)
3833 irdma_sc_cqp_post_sq(cqp);
3834
3835 return 0;
3836 }
3837
3838 /**
3839 * irdma_sc_process_ceq - process ceq
3840 * @dev: sc device struct
3841 * @ceq: ceq sc structure
3842 *
3843 * It is expected caller serializes this function with cleanup_ceqes()
3844 * because these functions manipulate the same ceq
3845 */
irdma_sc_process_ceq(struct irdma_sc_dev * dev,struct irdma_sc_ceq * ceq)3846 void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq)
3847 {
3848 u64 temp;
3849 __le64 *ceqe;
3850 struct irdma_sc_cq *cq = NULL;
3851 struct irdma_sc_cq *temp_cq;
3852 u8 polarity;
3853 u32 cq_idx;
3854 unsigned long flags;
3855
3856 do {
3857 cq_idx = 0;
3858 ceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq);
3859 get_64bit_val(ceqe, 0, &temp);
3860 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp);
3861 if (polarity != ceq->polarity)
3862 return NULL;
3863
3864 temp_cq = (struct irdma_sc_cq *)(unsigned long)(temp << 1);
3865 if (!temp_cq) {
3866 cq_idx = IRDMA_INVALID_CQ_IDX;
3867 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring);
3868
3869 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring))
3870 ceq->polarity ^= 1;
3871 continue;
3872 }
3873
3874 cq = temp_cq;
3875 if (ceq->reg_cq) {
3876 spin_lock_irqsave(&ceq->req_cq_lock, flags);
3877 cq_idx = irdma_sc_find_reg_cq(ceq, cq);
3878 spin_unlock_irqrestore(&ceq->req_cq_lock, flags);
3879 }
3880
3881 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring);
3882 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring))
3883 ceq->polarity ^= 1;
3884 } while (cq_idx == IRDMA_INVALID_CQ_IDX);
3885
3886 if (cq)
3887 irdma_sc_cq_ack(cq);
3888 return cq;
3889 }
3890
3891 /**
3892 * irdma_sc_cleanup_ceqes - clear the valid ceqes ctx matching the cq
3893 * @cq: cq for which the ceqes need to be cleaned up
3894 * @ceq: ceq ptr
3895 *
3896 * The function is called after the cq is destroyed to cleanup
3897 * its pending ceqe entries. It is expected caller serializes this
3898 * function with process_ceq() in interrupt context.
3899 */
irdma_sc_cleanup_ceqes(struct irdma_sc_cq * cq,struct irdma_sc_ceq * ceq)3900 void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq)
3901 {
3902 struct irdma_sc_cq *next_cq;
3903 u8 ceq_polarity = ceq->polarity;
3904 __le64 *ceqe;
3905 u8 polarity;
3906 u64 temp;
3907 int next;
3908 u32 i;
3909
3910 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, 0);
3911
3912 for (i = 1; i <= IRDMA_RING_SIZE(*ceq); i++) {
3913 ceqe = IRDMA_GET_CEQ_ELEM_AT_POS(ceq, next);
3914
3915 get_64bit_val(ceqe, 0, &temp);
3916 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp);
3917 if (polarity != ceq_polarity)
3918 return;
3919
3920 next_cq = (struct irdma_sc_cq *)(unsigned long)(temp << 1);
3921 if (cq == next_cq)
3922 set_64bit_val(ceqe, 0, temp & IRDMA_CEQE_VALID);
3923
3924 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i);
3925 if (!next)
3926 ceq_polarity ^= 1;
3927 }
3928 }
3929
3930 /**
3931 * irdma_sc_aeq_init - initialize aeq
3932 * @aeq: aeq structure ptr
3933 * @info: aeq initialization info
3934 */
irdma_sc_aeq_init(struct irdma_sc_aeq * aeq,struct irdma_aeq_init_info * info)3935 enum irdma_status_code irdma_sc_aeq_init(struct irdma_sc_aeq *aeq,
3936 struct irdma_aeq_init_info *info)
3937 {
3938 u32 pble_obj_cnt;
3939
3940 if (info->elem_cnt < info->dev->hw_attrs.min_hw_aeq_size ||
3941 info->elem_cnt > info->dev->hw_attrs.max_hw_aeq_size)
3942 return IRDMA_ERR_INVALID_SIZE;
3943
3944 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
3945
3946 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
3947 return IRDMA_ERR_INVALID_PBLE_INDEX;
3948
3949 aeq->size = sizeof(*aeq);
3950 aeq->polarity = 1;
3951 aeq->aeqe_base = (struct irdma_sc_aeqe *)info->aeqe_base;
3952 aeq->dev = info->dev;
3953 aeq->elem_cnt = info->elem_cnt;
3954 aeq->aeq_elem_pa = info->aeq_elem_pa;
3955 IRDMA_RING_INIT(aeq->aeq_ring, aeq->elem_cnt);
3956 aeq->virtual_map = info->virtual_map;
3957 aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL);
3958 aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0);
3959 aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0);
3960 aeq->msix_idx = info->msix_idx;
3961 info->dev->aeq = aeq;
3962
3963 return 0;
3964 }
3965
3966 /**
3967 * irdma_sc_aeq_create - create aeq
3968 * @aeq: aeq structure ptr
3969 * @scratch: u64 saved to be used during cqp completion
3970 * @post_sq: flag for cqp db to ring
3971 */
irdma_sc_aeq_create(struct irdma_sc_aeq * aeq,u64 scratch,bool post_sq)3972 static enum irdma_status_code irdma_sc_aeq_create(struct irdma_sc_aeq *aeq,
3973 u64 scratch, bool post_sq)
3974 {
3975 __le64 *wqe;
3976 struct irdma_sc_cqp *cqp;
3977 u64 hdr;
3978
3979 cqp = aeq->dev->cqp;
3980 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
3981 if (!wqe)
3982 return IRDMA_ERR_RING_FULL;
3983 set_64bit_val(wqe, 16, aeq->elem_cnt);
3984 set_64bit_val(wqe, 32,
3985 (aeq->virtual_map ? 0 : aeq->aeq_elem_pa));
3986 set_64bit_val(wqe, 48,
3987 (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0));
3988
3989 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_AEQ) |
3990 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) |
3991 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) |
3992 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
3993 dma_wmb(); /* make sure WQE is written before valid bit is set */
3994
3995 set_64bit_val(wqe, 24, hdr);
3996
3997 print_hex_dump_debug("WQE: AEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8,
3998 wqe, IRDMA_CQP_WQE_SIZE * 8, false);
3999 if (post_sq)
4000 irdma_sc_cqp_post_sq(cqp);
4001
4002 return 0;
4003 }
4004
4005 /**
4006 * irdma_sc_aeq_destroy - destroy aeq during close
4007 * @aeq: aeq structure ptr
4008 * @scratch: u64 saved to be used during cqp completion
4009 * @post_sq: flag for cqp db to ring
4010 */
irdma_sc_aeq_destroy(struct irdma_sc_aeq * aeq,u64 scratch,bool post_sq)4011 static enum irdma_status_code irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq,
4012 u64 scratch, bool post_sq)
4013 {
4014 __le64 *wqe;
4015 struct irdma_sc_cqp *cqp;
4016 struct irdma_sc_dev *dev;
4017 u64 hdr;
4018
4019 dev = aeq->dev;
4020 writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
4021
4022 cqp = dev->cqp;
4023 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
4024 if (!wqe)
4025 return IRDMA_ERR_RING_FULL;
4026 set_64bit_val(wqe, 16, aeq->elem_cnt);
4027 set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx);
4028 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_AEQ) |
4029 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) |
4030 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) |
4031 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
4032 dma_wmb(); /* make sure WQE is written before valid bit is set */
4033
4034 set_64bit_val(wqe, 24, hdr);
4035
4036 print_hex_dump_debug("WQE: AEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16,
4037 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
4038 if (post_sq)
4039 irdma_sc_cqp_post_sq(cqp);
4040 return 0;
4041 }
4042
4043 /**
4044 * irdma_sc_get_next_aeqe - get next aeq entry
4045 * @aeq: aeq structure ptr
4046 * @info: aeqe info to be returned
4047 */
irdma_sc_get_next_aeqe(struct irdma_sc_aeq * aeq,struct irdma_aeqe_info * info)4048 enum irdma_status_code irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,
4049 struct irdma_aeqe_info *info)
4050 {
4051 u64 temp, compl_ctx;
4052 __le64 *aeqe;
4053 u16 wqe_idx;
4054 u8 ae_src;
4055 u8 polarity;
4056
4057 aeqe = IRDMA_GET_CURRENT_AEQ_ELEM(aeq);
4058 get_64bit_val(aeqe, 8, &temp);
4059 polarity = (u8)FIELD_GET(IRDMA_AEQE_VALID, temp);
4060
4061 if (aeq->polarity != polarity)
4062 return IRDMA_ERR_Q_EMPTY;
4063
4064 /* Ensure AEQE contents are read after valid bit is checked */
4065 dma_rmb();
4066
4067 get_64bit_val(aeqe, 0, &compl_ctx);
4068
4069 print_hex_dump_debug("WQE: AEQ_ENTRY WQE", DUMP_PREFIX_OFFSET, 16, 8,
4070 aeqe, 16, false);
4071
4072 ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC, temp);
4073 wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX, temp);
4074 info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_LOW, temp) |
4075 ((u32)FIELD_GET(IRDMA_AEQE_QPCQID_HI, temp) << 18);
4076 info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE, temp);
4077 info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE, temp);
4078 info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE, temp);
4079 info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA, temp);
4080 info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW, temp);
4081
4082 info->ae_src = ae_src;
4083 switch (info->ae_id) {
4084 case IRDMA_AE_PRIV_OPERATION_DENIED:
4085 case IRDMA_AE_AMP_INVALIDATE_TYPE1_MW:
4086 case IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW:
4087 case IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG:
4088 case IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH:
4089 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
4090 case IRDMA_AE_UDA_XMIT_BAD_PD:
4091 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT:
4092 case IRDMA_AE_BAD_CLOSE:
4093 case IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO:
4094 case IRDMA_AE_STAG_ZERO_INVALID:
4095 case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
4096 case IRDMA_AE_IB_INVALID_REQUEST:
4097 case IRDMA_AE_WQE_UNEXPECTED_OPCODE:
4098 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR:
4099 case IRDMA_AE_IB_REMOTE_OP_ERROR:
4100 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION:
4101 case IRDMA_AE_DDP_UBE_INVALID_MO:
4102 case IRDMA_AE_DDP_UBE_INVALID_QN:
4103 case IRDMA_AE_DDP_NO_L_BIT:
4104 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
4105 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
4106 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST:
4107 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
4108 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR:
4109 case IRDMA_AE_INVALID_ARP_ENTRY:
4110 case IRDMA_AE_INVALID_TCP_OPTION_RCVD:
4111 case IRDMA_AE_STALE_ARP_ENTRY:
4112 case IRDMA_AE_INVALID_AH_ENTRY:
4113 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
4114 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
4115 case IRDMA_AE_LLP_TOO_MANY_RETRIES:
4116 case IRDMA_AE_LLP_DOUBT_REACHABILITY:
4117 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED:
4118 case IRDMA_AE_RESET_SENT:
4119 case IRDMA_AE_TERMINATE_SENT:
4120 case IRDMA_AE_RESET_NOT_SENT:
4121 case IRDMA_AE_LCE_QP_CATASTROPHIC:
4122 case IRDMA_AE_QP_SUSPEND_COMPLETE:
4123 case IRDMA_AE_UDA_L4LEN_INVALID:
4124 info->qp = true;
4125 info->compl_ctx = compl_ctx;
4126 break;
4127 case IRDMA_AE_LCE_CQ_CATASTROPHIC:
4128 info->cq = true;
4129 info->compl_ctx = compl_ctx << 1;
4130 ae_src = IRDMA_AE_SOURCE_RSVD;
4131 break;
4132 case IRDMA_AE_ROCE_EMPTY_MCG:
4133 case IRDMA_AE_ROCE_BAD_MC_IP_ADDR:
4134 case IRDMA_AE_ROCE_BAD_MC_QPID:
4135 case IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH:
4136 fallthrough;
4137 case IRDMA_AE_LLP_CONNECTION_RESET:
4138 case IRDMA_AE_LLP_SYN_RECEIVED:
4139 case IRDMA_AE_LLP_FIN_RECEIVED:
4140 case IRDMA_AE_LLP_CLOSE_COMPLETE:
4141 case IRDMA_AE_LLP_TERMINATE_RECEIVED:
4142 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE:
4143 ae_src = IRDMA_AE_SOURCE_RSVD;
4144 info->qp = true;
4145 info->compl_ctx = compl_ctx;
4146 break;
4147 default:
4148 break;
4149 }
4150
4151 switch (ae_src) {
4152 case IRDMA_AE_SOURCE_RQ:
4153 case IRDMA_AE_SOURCE_RQ_0011:
4154 info->qp = true;
4155 info->rq = true;
4156 info->wqe_idx = wqe_idx;
4157 info->compl_ctx = compl_ctx;
4158 break;
4159 case IRDMA_AE_SOURCE_CQ:
4160 case IRDMA_AE_SOURCE_CQ_0110:
4161 case IRDMA_AE_SOURCE_CQ_1010:
4162 case IRDMA_AE_SOURCE_CQ_1110:
4163 info->cq = true;
4164 info->compl_ctx = compl_ctx << 1;
4165 break;
4166 case IRDMA_AE_SOURCE_SQ:
4167 case IRDMA_AE_SOURCE_SQ_0111:
4168 info->qp = true;
4169 info->sq = true;
4170 info->wqe_idx = wqe_idx;
4171 info->compl_ctx = compl_ctx;
4172 break;
4173 case IRDMA_AE_SOURCE_IN_RR_WR:
4174 case IRDMA_AE_SOURCE_IN_RR_WR_1011:
4175 info->qp = true;
4176 info->compl_ctx = compl_ctx;
4177 info->in_rdrsp_wr = true;
4178 break;
4179 case IRDMA_AE_SOURCE_OUT_RR:
4180 case IRDMA_AE_SOURCE_OUT_RR_1111:
4181 info->qp = true;
4182 info->compl_ctx = compl_ctx;
4183 info->out_rdrsp = true;
4184 break;
4185 case IRDMA_AE_SOURCE_RSVD:
4186 default:
4187 break;
4188 }
4189
4190 IRDMA_RING_MOVE_TAIL(aeq->aeq_ring);
4191 if (!IRDMA_RING_CURRENT_TAIL(aeq->aeq_ring))
4192 aeq->polarity ^= 1;
4193
4194 return 0;
4195 }
4196
4197 /**
4198 * irdma_sc_repost_aeq_entries - repost completed aeq entries
4199 * @dev: sc device struct
4200 * @count: allocate count
4201 */
irdma_sc_repost_aeq_entries(struct irdma_sc_dev * dev,u32 count)4202 void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count)
4203 {
4204 writel(count, dev->hw_regs[IRDMA_AEQALLOC]);
4205 }
4206
4207 /**
4208 * irdma_sc_ccq_init - initialize control cq
4209 * @cq: sc's cq ctruct
4210 * @info: info for control cq initialization
4211 */
irdma_sc_ccq_init(struct irdma_sc_cq * cq,struct irdma_ccq_init_info * info)4212 enum irdma_status_code irdma_sc_ccq_init(struct irdma_sc_cq *cq,
4213 struct irdma_ccq_init_info *info)
4214 {
4215 u32 pble_obj_cnt;
4216
4217 if (info->num_elem < info->dev->hw_attrs.uk_attrs.min_hw_cq_size ||
4218 info->num_elem > info->dev->hw_attrs.uk_attrs.max_hw_cq_size)
4219 return IRDMA_ERR_INVALID_SIZE;
4220
4221 if (info->ceq_id >= (info->dev->hmc_fpm_misc.max_ceqs ))
4222 return IRDMA_ERR_INVALID_CEQ_ID;
4223
4224 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;
4225
4226 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt)
4227 return IRDMA_ERR_INVALID_PBLE_INDEX;
4228
4229 cq->cq_pa = info->cq_pa;
4230 cq->cq_uk.cq_base = info->cq_base;
4231 cq->shadow_area_pa = info->shadow_area_pa;
4232 cq->cq_uk.shadow_area = info->shadow_area;
4233 cq->shadow_read_threshold = info->shadow_read_threshold;
4234 cq->dev = info->dev;
4235 cq->ceq_id = info->ceq_id;
4236 cq->cq_uk.cq_size = info->num_elem;
4237 cq->cq_type = IRDMA_CQ_TYPE_CQP;
4238 cq->ceqe_mask = info->ceqe_mask;
4239 IRDMA_RING_INIT(cq->cq_uk.cq_ring, info->num_elem);
4240 cq->cq_uk.cq_id = 0; /* control cq is id 0 always */
4241 cq->ceq_id_valid = info->ceq_id_valid;
4242 cq->tph_en = info->tph_en;
4243 cq->tph_val = info->tph_val;
4244 cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct;
4245 cq->pbl_list = info->pbl_list;
4246 cq->virtual_map = info->virtual_map;
4247 cq->pbl_chunk_size = info->pbl_chunk_size;
4248 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
4249 cq->cq_uk.polarity = true;
4250 cq->vsi = info->vsi;
4251 cq->cq_uk.cq_ack_db = cq->dev->cq_ack_db;
4252
4253 /* Only applicable to CQs other than CCQ so initialize to zero */
4254 cq->cq_uk.cqe_alloc_db = NULL;
4255
4256 info->dev->ccq = cq;
4257 return 0;
4258 }
4259
4260 /**
4261 * irdma_sc_ccq_create_done - poll cqp for ccq create
4262 * @ccq: ccq sc struct
4263 */
irdma_sc_ccq_create_done(struct irdma_sc_cq * ccq)4264 static inline enum irdma_status_code irdma_sc_ccq_create_done(struct irdma_sc_cq *ccq)
4265 {
4266 struct irdma_sc_cqp *cqp;
4267
4268 cqp = ccq->dev->cqp;
4269
4270 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CQ, NULL);
4271 }
4272
4273 /**
4274 * irdma_sc_ccq_create - create control cq
4275 * @ccq: ccq sc struct
4276 * @scratch: u64 saved to be used during cqp completion
4277 * @check_overflow: overlow flag for ccq
4278 * @post_sq: flag for cqp db to ring
4279 */
irdma_sc_ccq_create(struct irdma_sc_cq * ccq,u64 scratch,bool check_overflow,bool post_sq)4280 enum irdma_status_code irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,
4281 bool check_overflow, bool post_sq)
4282 {
4283 enum irdma_status_code ret_code;
4284
4285 ret_code = irdma_sc_cq_create(ccq, scratch, check_overflow, post_sq);
4286 if (ret_code)
4287 return ret_code;
4288
4289 if (post_sq) {
4290 ret_code = irdma_sc_ccq_create_done(ccq);
4291 if (ret_code)
4292 return ret_code;
4293 }
4294 ccq->dev->cqp->process_cqp_sds = irdma_cqp_sds_cmd;
4295
4296 return 0;
4297 }
4298
4299 /**
4300 * irdma_sc_ccq_destroy - destroy ccq during close
4301 * @ccq: ccq sc struct
4302 * @scratch: u64 saved to be used during cqp completion
4303 * @post_sq: flag for cqp db to ring
4304 */
irdma_sc_ccq_destroy(struct irdma_sc_cq * ccq,u64 scratch,bool post_sq)4305 enum irdma_status_code irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch,
4306 bool post_sq)
4307 {
4308 struct irdma_sc_cqp *cqp;
4309 __le64 *wqe;
4310 u64 hdr;
4311 enum irdma_status_code ret_code = 0;
4312 u32 tail, val, error;
4313
4314 cqp = ccq->dev->cqp;
4315 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
4316 if (!wqe)
4317 return IRDMA_ERR_RING_FULL;
4318
4319 set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
4320 set_64bit_val(wqe, 8, (uintptr_t)ccq >> 1);
4321 set_64bit_val(wqe, 40, ccq->shadow_area_pa);
4322
4323 hdr = ccq->cq_uk.cq_id |
4324 FLD_LS_64(ccq->dev, (ccq->ceq_id_valid ? ccq->ceq_id : 0),
4325 IRDMA_CQPSQ_CQ_CEQID) |
4326 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) |
4327 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, ccq->ceqe_mask) |
4328 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, ccq->ceq_id_valid) |
4329 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ccq->tph_en) |
4330 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, ccq->cq_uk.avoid_mem_cflct) |
4331 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
4332 dma_wmb(); /* make sure WQE is written before valid bit is set */
4333
4334 set_64bit_val(wqe, 24, hdr);
4335
4336 print_hex_dump_debug("WQE: CCQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16,
4337 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
4338 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
4339
4340 if (post_sq) {
4341 irdma_sc_cqp_post_sq(cqp);
4342 ret_code = irdma_cqp_poll_registers(cqp, tail,
4343 cqp->dev->hw_attrs.max_done_count);
4344 }
4345
4346 cqp->process_cqp_sds = irdma_update_sds_noccq;
4347
4348 return ret_code;
4349 }
4350
4351 /**
4352 * irdma_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info
4353 * @dev : ptr to irdma_dev struct
4354 * @hmc_fn_id: hmc function id
4355 */
irdma_sc_init_iw_hmc(struct irdma_sc_dev * dev,u8 hmc_fn_id)4356 enum irdma_status_code irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev,
4357 u8 hmc_fn_id)
4358 {
4359 struct irdma_hmc_info *hmc_info;
4360 struct irdma_hmc_fpm_misc *hmc_fpm_misc;
4361 struct irdma_dma_mem query_fpm_mem;
4362 enum irdma_status_code ret_code = 0;
4363 u8 wait_type;
4364
4365 hmc_info = dev->hmc_info;
4366 hmc_fpm_misc = &dev->hmc_fpm_misc;
4367 query_fpm_mem.pa = dev->fpm_query_buf_pa;
4368 query_fpm_mem.va = dev->fpm_query_buf;
4369 hmc_info->hmc_fn_id = hmc_fn_id;
4370 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS;
4371
4372 ret_code = irdma_sc_query_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id,
4373 &query_fpm_mem, true, wait_type);
4374 if (ret_code)
4375 return ret_code;
4376
4377 /* parse the fpm_query_buf and fill hmc obj info */
4378 ret_code = irdma_sc_parse_fpm_query_buf(dev, query_fpm_mem.va, hmc_info,
4379 hmc_fpm_misc);
4380
4381 print_hex_dump_debug("HMC: QUERY FPM BUFFER", DUMP_PREFIX_OFFSET, 16,
4382 8, query_fpm_mem.va, IRDMA_QUERY_FPM_BUF_SIZE,
4383 false);
4384 return ret_code;
4385 }
4386
4387 /**
4388 * irdma_sc_cfg_iw_fpm() - commits hmc obj cnt values using cqp
4389 * command and populates fpm base address in hmc_info
4390 * @dev : ptr to irdma_dev struct
4391 * @hmc_fn_id: hmc function id
4392 */
irdma_sc_cfg_iw_fpm(struct irdma_sc_dev * dev,u8 hmc_fn_id)4393 static enum irdma_status_code irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev,
4394 u8 hmc_fn_id)
4395 {
4396 struct irdma_hmc_info *hmc_info;
4397 struct irdma_hmc_obj_info *obj_info;
4398 __le64 *buf;
4399 struct irdma_dma_mem commit_fpm_mem;
4400 enum irdma_status_code ret_code = 0;
4401 u8 wait_type;
4402
4403 hmc_info = dev->hmc_info;
4404 obj_info = hmc_info->hmc_obj;
4405 buf = dev->fpm_commit_buf;
4406
4407 set_64bit_val(buf, 0, (u64)obj_info[IRDMA_HMC_IW_QP].cnt);
4408 set_64bit_val(buf, 8, (u64)obj_info[IRDMA_HMC_IW_CQ].cnt);
4409 set_64bit_val(buf, 16, (u64)0); /* RSRVD */
4410 set_64bit_val(buf, 24, (u64)obj_info[IRDMA_HMC_IW_HTE].cnt);
4411 set_64bit_val(buf, 32, (u64)obj_info[IRDMA_HMC_IW_ARP].cnt);
4412 set_64bit_val(buf, 40, (u64)0); /* RSVD */
4413 set_64bit_val(buf, 48, (u64)obj_info[IRDMA_HMC_IW_MR].cnt);
4414 set_64bit_val(buf, 56, (u64)obj_info[IRDMA_HMC_IW_XF].cnt);
4415 set_64bit_val(buf, 64, (u64)obj_info[IRDMA_HMC_IW_XFFL].cnt);
4416 set_64bit_val(buf, 72, (u64)obj_info[IRDMA_HMC_IW_Q1].cnt);
4417 set_64bit_val(buf, 80, (u64)obj_info[IRDMA_HMC_IW_Q1FL].cnt);
4418 set_64bit_val(buf, 88,
4419 (u64)obj_info[IRDMA_HMC_IW_TIMER].cnt);
4420 set_64bit_val(buf, 96,
4421 (u64)obj_info[IRDMA_HMC_IW_FSIMC].cnt);
4422 set_64bit_val(buf, 104,
4423 (u64)obj_info[IRDMA_HMC_IW_FSIAV].cnt);
4424 set_64bit_val(buf, 112,
4425 (u64)obj_info[IRDMA_HMC_IW_PBLE].cnt);
4426 set_64bit_val(buf, 120, (u64)0); /* RSVD */
4427 set_64bit_val(buf, 128, (u64)obj_info[IRDMA_HMC_IW_RRF].cnt);
4428 set_64bit_val(buf, 136,
4429 (u64)obj_info[IRDMA_HMC_IW_RRFFL].cnt);
4430 set_64bit_val(buf, 144, (u64)obj_info[IRDMA_HMC_IW_HDR].cnt);
4431 set_64bit_val(buf, 152, (u64)obj_info[IRDMA_HMC_IW_MD].cnt);
4432 set_64bit_val(buf, 160,
4433 (u64)obj_info[IRDMA_HMC_IW_OOISC].cnt);
4434 set_64bit_val(buf, 168,
4435 (u64)obj_info[IRDMA_HMC_IW_OOISCFFL].cnt);
4436
4437 commit_fpm_mem.pa = dev->fpm_commit_buf_pa;
4438 commit_fpm_mem.va = dev->fpm_commit_buf;
4439
4440 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS;
4441 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16,
4442 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE,
4443 false);
4444 ret_code = irdma_sc_commit_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id,
4445 &commit_fpm_mem, true, wait_type);
4446 if (!ret_code)
4447 irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf,
4448 hmc_info->hmc_obj,
4449 &hmc_info->sd_table.sd_cnt);
4450 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16,
4451 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE,
4452 false);
4453
4454 return ret_code;
4455 }
4456
4457 /**
4458 * cqp_sds_wqe_fill - fill cqp wqe doe sd
4459 * @cqp: struct for cqp hw
4460 * @info: sd info for wqe
4461 * @scratch: u64 saved to be used during cqp completion
4462 */
4463 static enum irdma_status_code
cqp_sds_wqe_fill(struct irdma_sc_cqp * cqp,struct irdma_update_sds_info * info,u64 scratch)4464 cqp_sds_wqe_fill(struct irdma_sc_cqp *cqp, struct irdma_update_sds_info *info,
4465 u64 scratch)
4466 {
4467 u64 data;
4468 u64 hdr;
4469 __le64 *wqe;
4470 int mem_entries, wqe_entries;
4471 struct irdma_dma_mem *sdbuf = &cqp->sdbuf;
4472 u64 offset = 0;
4473 u32 wqe_idx;
4474
4475 wqe = irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
4476 if (!wqe)
4477 return IRDMA_ERR_RING_FULL;
4478
4479 wqe_entries = (info->cnt > 3) ? 3 : info->cnt;
4480 mem_entries = info->cnt - wqe_entries;
4481
4482 if (mem_entries) {
4483 offset = wqe_idx * IRDMA_UPDATE_SD_BUFF_SIZE;
4484 memcpy(((char *)sdbuf->va + offset), &info->entry[3], mem_entries << 4);
4485
4486 data = (u64)sdbuf->pa + offset;
4487 } else {
4488 data = 0;
4489 }
4490 data |= FIELD_PREP(IRDMA_CQPSQ_UPESD_HMCFNID, info->hmc_fn_id);
4491 set_64bit_val(wqe, 16, data);
4492
4493 switch (wqe_entries) {
4494 case 3:
4495 set_64bit_val(wqe, 48,
4496 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[2].cmd) |
4497 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1)));
4498
4499 set_64bit_val(wqe, 56, info->entry[2].data);
4500 fallthrough;
4501 case 2:
4502 set_64bit_val(wqe, 32,
4503 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[1].cmd) |
4504 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1)));
4505
4506 set_64bit_val(wqe, 40, info->entry[1].data);
4507 fallthrough;
4508 case 1:
4509 set_64bit_val(wqe, 0,
4510 FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[0].cmd));
4511
4512 set_64bit_val(wqe, 8, info->entry[0].data);
4513 break;
4514 default:
4515 break;
4516 }
4517
4518 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPDATE_PE_SDS) |
4519 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) |
4520 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_COUNT, mem_entries);
4521 dma_wmb(); /* make sure WQE is written before valid bit is set */
4522
4523 set_64bit_val(wqe, 24, hdr);
4524
4525 if (mem_entries)
4526 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE Buffer",
4527 DUMP_PREFIX_OFFSET, 16, 8,
4528 (char *)sdbuf->va + offset,
4529 mem_entries << 4, false);
4530
4531 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE", DUMP_PREFIX_OFFSET, 16,
4532 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
4533
4534 return 0;
4535 }
4536
4537 /**
4538 * irdma_update_pe_sds - cqp wqe for sd
4539 * @dev: ptr to irdma_dev struct
4540 * @info: sd info for sd's
4541 * @scratch: u64 saved to be used during cqp completion
4542 */
4543 static enum irdma_status_code
irdma_update_pe_sds(struct irdma_sc_dev * dev,struct irdma_update_sds_info * info,u64 scratch)4544 irdma_update_pe_sds(struct irdma_sc_dev *dev,
4545 struct irdma_update_sds_info *info, u64 scratch)
4546 {
4547 struct irdma_sc_cqp *cqp = dev->cqp;
4548 enum irdma_status_code ret_code;
4549
4550 ret_code = cqp_sds_wqe_fill(cqp, info, scratch);
4551 if (!ret_code)
4552 irdma_sc_cqp_post_sq(cqp);
4553
4554 return ret_code;
4555 }
4556
4557 /**
4558 * irdma_update_sds_noccq - update sd before ccq created
4559 * @dev: sc device struct
4560 * @info: sd info for sd's
4561 */
4562 enum irdma_status_code
irdma_update_sds_noccq(struct irdma_sc_dev * dev,struct irdma_update_sds_info * info)4563 irdma_update_sds_noccq(struct irdma_sc_dev *dev,
4564 struct irdma_update_sds_info *info)
4565 {
4566 u32 error, val, tail;
4567 struct irdma_sc_cqp *cqp = dev->cqp;
4568 enum irdma_status_code ret_code;
4569
4570 ret_code = cqp_sds_wqe_fill(cqp, info, 0);
4571 if (ret_code)
4572 return ret_code;
4573
4574 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
4575
4576 irdma_sc_cqp_post_sq(cqp);
4577 return irdma_cqp_poll_registers(cqp, tail,
4578 cqp->dev->hw_attrs.max_done_count);
4579 }
4580
4581 /**
4582 * irdma_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages
4583 * @cqp: struct for cqp hw
4584 * @scratch: u64 saved to be used during cqp completion
4585 * @hmc_fn_id: hmc function id
4586 * @post_sq: flag for cqp db to ring
4587 * @poll_registers: flag to poll register for cqp completion
4588 */
4589 enum irdma_status_code
irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp * cqp,u64 scratch,u8 hmc_fn_id,bool post_sq,bool poll_registers)4590 irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,
4591 u8 hmc_fn_id, bool post_sq,
4592 bool poll_registers)
4593 {
4594 u64 hdr;
4595 __le64 *wqe;
4596 u32 tail, val, error;
4597
4598 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
4599 if (!wqe)
4600 return IRDMA_ERR_RING_FULL;
4601
4602 set_64bit_val(wqe, 16,
4603 FIELD_PREP(IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID, hmc_fn_id));
4604
4605 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE,
4606 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED) |
4607 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
4608 dma_wmb(); /* make sure WQE is written before valid bit is set */
4609
4610 set_64bit_val(wqe, 24, hdr);
4611
4612 print_hex_dump_debug("WQE: SHMC_PAGES_ALLOCATED WQE",
4613 DUMP_PREFIX_OFFSET, 16, 8, wqe,
4614 IRDMA_CQP_WQE_SIZE * 8, false);
4615 irdma_get_cqp_reg_info(cqp, &val, &tail, &error);
4616
4617 if (post_sq) {
4618 irdma_sc_cqp_post_sq(cqp);
4619 if (poll_registers)
4620 /* check for cqp sq tail update */
4621 return irdma_cqp_poll_registers(cqp, tail,
4622 cqp->dev->hw_attrs.max_done_count);
4623 else
4624 return irdma_sc_poll_for_cqp_op_done(cqp,
4625 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED,
4626 NULL);
4627 }
4628
4629 return 0;
4630 }
4631
4632 /**
4633 * irdma_cqp_ring_full - check if cqp ring is full
4634 * @cqp: struct for cqp hw
4635 */
irdma_cqp_ring_full(struct irdma_sc_cqp * cqp)4636 static bool irdma_cqp_ring_full(struct irdma_sc_cqp *cqp)
4637 {
4638 return IRDMA_RING_FULL_ERR(cqp->sq_ring);
4639 }
4640
4641 /**
4642 * irdma_est_sd - returns approximate number of SDs for HMC
4643 * @dev: sc device struct
4644 * @hmc_info: hmc structure, size and count for HMC objects
4645 */
irdma_est_sd(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info)4646 static u32 irdma_est_sd(struct irdma_sc_dev *dev,
4647 struct irdma_hmc_info *hmc_info)
4648 {
4649 int i;
4650 u64 size = 0;
4651 u64 sd;
4652
4653 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++)
4654 if (i != IRDMA_HMC_IW_PBLE)
4655 size += round_up(hmc_info->hmc_obj[i].cnt *
4656 hmc_info->hmc_obj[i].size, 512);
4657 size += round_up(hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt *
4658 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].size, 512);
4659 if (size & 0x1FFFFF)
4660 sd = (size >> 21) + 1; /* add 1 for remainder */
4661 else
4662 sd = size >> 21;
4663 if (sd > 0xFFFFFFFF) {
4664 ibdev_dbg(to_ibdev(dev), "HMC: sd overflow[%lld]\n", sd);
4665 sd = 0xFFFFFFFF - 1;
4666 }
4667
4668 return (u32)sd;
4669 }
4670
4671 /**
4672 * irdma_sc_query_rdma_features_done - poll cqp for query features done
4673 * @cqp: struct for cqp hw
4674 */
4675 static enum irdma_status_code
irdma_sc_query_rdma_features_done(struct irdma_sc_cqp * cqp)4676 irdma_sc_query_rdma_features_done(struct irdma_sc_cqp *cqp)
4677 {
4678 return irdma_sc_poll_for_cqp_op_done(cqp,
4679 IRDMA_CQP_OP_QUERY_RDMA_FEATURES,
4680 NULL);
4681 }
4682
4683 /**
4684 * irdma_sc_query_rdma_features - query RDMA features and FW ver
4685 * @cqp: struct for cqp hw
4686 * @buf: buffer to hold query info
4687 * @scratch: u64 saved to be used during cqp completion
4688 */
4689 static enum irdma_status_code
irdma_sc_query_rdma_features(struct irdma_sc_cqp * cqp,struct irdma_dma_mem * buf,u64 scratch)4690 irdma_sc_query_rdma_features(struct irdma_sc_cqp *cqp,
4691 struct irdma_dma_mem *buf, u64 scratch)
4692 {
4693 __le64 *wqe;
4694 u64 temp;
4695
4696 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
4697 if (!wqe)
4698 return IRDMA_ERR_RING_FULL;
4699
4700 temp = buf->pa;
4701 set_64bit_val(wqe, 32, temp);
4702
4703 temp = FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID,
4704 cqp->polarity) |
4705 FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN, buf->size) |
4706 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_QUERY_RDMA_FEATURES);
4707 dma_wmb(); /* make sure WQE is written before valid bit is set */
4708
4709 set_64bit_val(wqe, 24, temp);
4710
4711 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET,
4712 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);
4713 irdma_sc_cqp_post_sq(cqp);
4714
4715 return 0;
4716 }
4717
4718 /**
4719 * irdma_get_rdma_features - get RDMA features
4720 * @dev: sc device struct
4721 */
irdma_get_rdma_features(struct irdma_sc_dev * dev)4722 enum irdma_status_code irdma_get_rdma_features(struct irdma_sc_dev *dev)
4723 {
4724 enum irdma_status_code ret_code;
4725 struct irdma_dma_mem feat_buf;
4726 u64 temp;
4727 u16 byte_idx, feat_type, feat_cnt, feat_idx;
4728
4729 feat_buf.size = ALIGN(IRDMA_FEATURE_BUF_SIZE,
4730 IRDMA_FEATURE_BUF_ALIGNMENT);
4731 feat_buf.va = dma_alloc_coherent(dev->hw->device, feat_buf.size,
4732 &feat_buf.pa, GFP_KERNEL);
4733 if (!feat_buf.va)
4734 return IRDMA_ERR_NO_MEMORY;
4735
4736 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0);
4737 if (!ret_code)
4738 ret_code = irdma_sc_query_rdma_features_done(dev->cqp);
4739 if (ret_code)
4740 goto exit;
4741
4742 get_64bit_val(feat_buf.va, 0, &temp);
4743 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp);
4744 if (feat_cnt < 2) {
4745 ret_code = IRDMA_ERR_INVALID_FEAT_CNT;
4746 goto exit;
4747 } else if (feat_cnt > IRDMA_MAX_FEATURES) {
4748 ibdev_dbg(to_ibdev(dev),
4749 "DEV: feature buf size insufficient, retrying with larger buffer\n");
4750 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va,
4751 feat_buf.pa);
4752 feat_buf.va = NULL;
4753 feat_buf.size = ALIGN(8 * feat_cnt,
4754 IRDMA_FEATURE_BUF_ALIGNMENT);
4755 feat_buf.va = dma_alloc_coherent(dev->hw->device,
4756 feat_buf.size, &feat_buf.pa,
4757 GFP_KERNEL);
4758 if (!feat_buf.va)
4759 return IRDMA_ERR_NO_MEMORY;
4760
4761 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0);
4762 if (!ret_code)
4763 ret_code = irdma_sc_query_rdma_features_done(dev->cqp);
4764 if (ret_code)
4765 goto exit;
4766
4767 get_64bit_val(feat_buf.va, 0, &temp);
4768 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp);
4769 if (feat_cnt < 2) {
4770 ret_code = IRDMA_ERR_INVALID_FEAT_CNT;
4771 goto exit;
4772 }
4773 }
4774
4775 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET,
4776 16, 8, feat_buf.va, feat_cnt * 8, false);
4777
4778 for (byte_idx = 0, feat_idx = 0; feat_idx < min(feat_cnt, (u16)IRDMA_MAX_FEATURES);
4779 feat_idx++, byte_idx += 8) {
4780 get_64bit_val(feat_buf.va, byte_idx, &temp);
4781 feat_type = FIELD_GET(IRDMA_FEATURE_TYPE, temp);
4782 if (feat_type >= IRDMA_MAX_FEATURES) {
4783 ibdev_dbg(to_ibdev(dev),
4784 "DEV: found unrecognized feature type %d\n",
4785 feat_type);
4786 continue;
4787 }
4788 dev->feature_info[feat_type] = temp;
4789 }
4790 exit:
4791 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va,
4792 feat_buf.pa);
4793 feat_buf.va = NULL;
4794 return ret_code;
4795 }
4796
irdma_q1_cnt(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info,u32 qpwanted)4797 static u32 irdma_q1_cnt(struct irdma_sc_dev *dev,
4798 struct irdma_hmc_info *hmc_info, u32 qpwanted)
4799 {
4800 u32 q1_cnt;
4801
4802 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) {
4803 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted);
4804 } else {
4805 if (dev->cqp->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY)
4806 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted + 512);
4807 else
4808 q1_cnt = dev->hw_attrs.max_hw_ird * 2 * qpwanted;
4809 }
4810
4811 return q1_cnt;
4812 }
4813
cfg_fpm_value_gen_1(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info,u32 qpwanted)4814 static void cfg_fpm_value_gen_1(struct irdma_sc_dev *dev,
4815 struct irdma_hmc_info *hmc_info, u32 qpwanted)
4816 {
4817 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = roundup_pow_of_two(qpwanted * dev->hw_attrs.max_hw_wqes);
4818 }
4819
cfg_fpm_value_gen_2(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info,u32 qpwanted)4820 static void cfg_fpm_value_gen_2(struct irdma_sc_dev *dev,
4821 struct irdma_hmc_info *hmc_info, u32 qpwanted)
4822 {
4823 struct irdma_hmc_fpm_misc *hmc_fpm_misc = &dev->hmc_fpm_misc;
4824
4825 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt =
4826 4 * hmc_fpm_misc->xf_block_size * qpwanted;
4827
4828 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted;
4829
4830 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt)
4831 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = 32 * qpwanted;
4832 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt)
4833 hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt =
4834 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt /
4835 hmc_fpm_misc->rrf_block_size;
4836 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt)
4837 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt = 32 * qpwanted;
4838 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt)
4839 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].cnt =
4840 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt /
4841 hmc_fpm_misc->ooiscf_block_size;
4842 }
4843
4844 /**
4845 * irdma_cfg_fpm_val - configure HMC objects
4846 * @dev: sc device struct
4847 * @qp_count: desired qp count
4848 */
irdma_cfg_fpm_val(struct irdma_sc_dev * dev,u32 qp_count)4849 enum irdma_status_code irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count)
4850 {
4851 struct irdma_virt_mem virt_mem;
4852 u32 i, mem_size;
4853 u32 qpwanted, mrwanted, pblewanted;
4854 u32 powerof2, hte;
4855 u32 sd_needed;
4856 u32 sd_diff;
4857 u32 loop_count = 0;
4858 struct irdma_hmc_info *hmc_info;
4859 struct irdma_hmc_fpm_misc *hmc_fpm_misc;
4860 enum irdma_status_code ret_code = 0;
4861
4862 hmc_info = dev->hmc_info;
4863 hmc_fpm_misc = &dev->hmc_fpm_misc;
4864
4865 ret_code = irdma_sc_init_iw_hmc(dev, dev->hmc_fn_id);
4866 if (ret_code) {
4867 ibdev_dbg(to_ibdev(dev),
4868 "HMC: irdma_sc_init_iw_hmc returned error_code = %d\n",
4869 ret_code);
4870 return ret_code;
4871 }
4872
4873 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++)
4874 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt;
4875 sd_needed = irdma_est_sd(dev, hmc_info);
4876 ibdev_dbg(to_ibdev(dev),
4877 "HMC: FW max resources sd_needed[%08d] first_sd_index[%04d]\n",
4878 sd_needed, hmc_info->first_sd_index);
4879 ibdev_dbg(to_ibdev(dev), "HMC: sd count %d where max sd is %d\n",
4880 hmc_info->sd_table.sd_cnt, hmc_fpm_misc->max_sds);
4881
4882 qpwanted = min(qp_count, hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt);
4883
4884 powerof2 = 1;
4885 while (powerof2 <= qpwanted)
4886 powerof2 *= 2;
4887 powerof2 /= 2;
4888 qpwanted = powerof2;
4889
4890 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt;
4891 pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt;
4892
4893 ibdev_dbg(to_ibdev(dev),
4894 "HMC: req_qp=%d max_sd=%d, max_qp = %d, max_cq=%d, max_mr=%d, max_pble=%d, mc=%d, av=%d\n",
4895 qp_count, hmc_fpm_misc->max_sds,
4896 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt,
4897 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt,
4898 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt,
4899 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt,
4900 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt,
4901 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt);
4902 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt =
4903 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt;
4904 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt =
4905 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt;
4906 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt =
4907 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].max_cnt;
4908
4909 hmc_info->hmc_obj[IRDMA_HMC_IW_APBVT_ENTRY].cnt = 1;
4910
4911 while (irdma_q1_cnt(dev, hmc_info, qpwanted) > hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].max_cnt)
4912 qpwanted /= 2;
4913
4914 do {
4915 ++loop_count;
4916 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted;
4917 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt =
4918 min(2 * qpwanted, hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt);
4919 hmc_info->hmc_obj[IRDMA_HMC_IW_RESERVED].cnt = 0; /* Reserved */
4920 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted;
4921
4922 hte = round_up(qpwanted + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 512);
4923 powerof2 = 1;
4924 while (powerof2 < hte)
4925 powerof2 *= 2;
4926 hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].cnt =
4927 powerof2 * hmc_fpm_misc->ht_multiplier;
4928 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
4929 cfg_fpm_value_gen_1(dev, hmc_info, qpwanted);
4930 else
4931 cfg_fpm_value_gen_2(dev, hmc_info, qpwanted);
4932
4933 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = irdma_q1_cnt(dev, hmc_info, qpwanted);
4934 hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt =
4935 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size;
4936 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt =
4937 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size;
4938 hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt =
4939 (round_up(qpwanted, 512) / 512 + 1) * hmc_fpm_misc->timer_bucket;
4940
4941 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted;
4942 sd_needed = irdma_est_sd(dev, hmc_info);
4943 ibdev_dbg(to_ibdev(dev),
4944 "HMC: sd_needed = %d, hmc_fpm_misc->max_sds=%d, mrwanted=%d, pblewanted=%d qpwanted=%d\n",
4945 sd_needed, hmc_fpm_misc->max_sds, mrwanted,
4946 pblewanted, qpwanted);
4947
4948 /* Do not reduce resources further. All objects fit with max SDs */
4949 if (sd_needed <= hmc_fpm_misc->max_sds)
4950 break;
4951
4952 sd_diff = sd_needed - hmc_fpm_misc->max_sds;
4953 if (sd_diff > 128) {
4954 if (qpwanted > 128 && sd_diff > 144)
4955 qpwanted /= 2;
4956 mrwanted /= 2;
4957 pblewanted /= 2;
4958 continue;
4959 }
4960 if (dev->cqp->hmc_profile != IRDMA_HMC_PROFILE_FAVOR_VF &&
4961 pblewanted > (512 * FPM_MULTIPLIER * sd_diff)) {
4962 pblewanted -= 256 * FPM_MULTIPLIER * sd_diff;
4963 continue;
4964 } else if (pblewanted > (100 * FPM_MULTIPLIER)) {
4965 pblewanted -= 10 * FPM_MULTIPLIER;
4966 } else if (pblewanted > FPM_MULTIPLIER) {
4967 pblewanted -= FPM_MULTIPLIER;
4968 } else if (qpwanted <= 128) {
4969 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt > 256)
4970 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt /= 2;
4971 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256)
4972 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2;
4973 }
4974 if (mrwanted > FPM_MULTIPLIER)
4975 mrwanted -= FPM_MULTIPLIER;
4976 if (!(loop_count % 10) && qpwanted > 128) {
4977 qpwanted /= 2;
4978 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256)
4979 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2;
4980 }
4981 } while (loop_count < 2000);
4982
4983 if (sd_needed > hmc_fpm_misc->max_sds) {
4984 ibdev_dbg(to_ibdev(dev),
4985 "HMC: cfg_fpm failed loop_cnt=%d, sd_needed=%d, max sd count %d\n",
4986 loop_count, sd_needed, hmc_info->sd_table.sd_cnt);
4987 return IRDMA_ERR_CFG;
4988 }
4989
4990 if (loop_count > 1 && sd_needed < hmc_fpm_misc->max_sds) {
4991 pblewanted += (hmc_fpm_misc->max_sds - sd_needed) * 256 *
4992 FPM_MULTIPLIER;
4993 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted;
4994 sd_needed = irdma_est_sd(dev, hmc_info);
4995 }
4996
4997 ibdev_dbg(to_ibdev(dev),
4998 "HMC: loop_cnt=%d, sd_needed=%d, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d, mc=%d, ah=%d, max sd count %d, first sd index %d\n",
4999 loop_count, sd_needed,
5000 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt,
5001 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt,
5002 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt,
5003 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt,
5004 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt,
5005 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt,
5006 hmc_info->sd_table.sd_cnt, hmc_info->first_sd_index);
5007
5008 ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id);
5009 if (ret_code) {
5010 ibdev_dbg(to_ibdev(dev),
5011 "HMC: cfg_iw_fpm returned error_code[x%08X]\n",
5012 readl(dev->hw_regs[IRDMA_CQPERRCODES]));
5013 return ret_code;
5014 }
5015
5016 mem_size = sizeof(struct irdma_hmc_sd_entry) *
5017 (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1);
5018 virt_mem.size = mem_size;
5019 virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL);
5020 if (!virt_mem.va) {
5021 ibdev_dbg(to_ibdev(dev),
5022 "HMC: failed to allocate memory for sd_entry buffer\n");
5023 return IRDMA_ERR_NO_MEMORY;
5024 }
5025 hmc_info->sd_table.sd_entry = virt_mem.va;
5026
5027 return ret_code;
5028 }
5029
5030 /**
5031 * irdma_exec_cqp_cmd - execute cqp cmd when wqe are available
5032 * @dev: rdma device
5033 * @pcmdinfo: cqp command info
5034 */
irdma_exec_cqp_cmd(struct irdma_sc_dev * dev,struct cqp_cmds_info * pcmdinfo)5035 static enum irdma_status_code irdma_exec_cqp_cmd(struct irdma_sc_dev *dev,
5036 struct cqp_cmds_info *pcmdinfo)
5037 {
5038 enum irdma_status_code status;
5039 struct irdma_dma_mem val_mem;
5040 bool alloc = false;
5041
5042 dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++;
5043 switch (pcmdinfo->cqp_cmd) {
5044 case IRDMA_OP_CEQ_DESTROY:
5045 status = irdma_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq,
5046 pcmdinfo->in.u.ceq_destroy.scratch,
5047 pcmdinfo->post_sq);
5048 break;
5049 case IRDMA_OP_AEQ_DESTROY:
5050 status = irdma_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq,
5051 pcmdinfo->in.u.aeq_destroy.scratch,
5052 pcmdinfo->post_sq);
5053
5054 break;
5055 case IRDMA_OP_CEQ_CREATE:
5056 status = irdma_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq,
5057 pcmdinfo->in.u.ceq_create.scratch,
5058 pcmdinfo->post_sq);
5059 break;
5060 case IRDMA_OP_AEQ_CREATE:
5061 status = irdma_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq,
5062 pcmdinfo->in.u.aeq_create.scratch,
5063 pcmdinfo->post_sq);
5064 break;
5065 case IRDMA_OP_QP_UPLOAD_CONTEXT:
5066 status = irdma_sc_qp_upload_context(pcmdinfo->in.u.qp_upload_context.dev,
5067 &pcmdinfo->in.u.qp_upload_context.info,
5068 pcmdinfo->in.u.qp_upload_context.scratch,
5069 pcmdinfo->post_sq);
5070 break;
5071 case IRDMA_OP_CQ_CREATE:
5072 status = irdma_sc_cq_create(pcmdinfo->in.u.cq_create.cq,
5073 pcmdinfo->in.u.cq_create.scratch,
5074 pcmdinfo->in.u.cq_create.check_overflow,
5075 pcmdinfo->post_sq);
5076 break;
5077 case IRDMA_OP_CQ_MODIFY:
5078 status = irdma_sc_cq_modify(pcmdinfo->in.u.cq_modify.cq,
5079 &pcmdinfo->in.u.cq_modify.info,
5080 pcmdinfo->in.u.cq_modify.scratch,
5081 pcmdinfo->post_sq);
5082 break;
5083 case IRDMA_OP_CQ_DESTROY:
5084 status = irdma_sc_cq_destroy(pcmdinfo->in.u.cq_destroy.cq,
5085 pcmdinfo->in.u.cq_destroy.scratch,
5086 pcmdinfo->post_sq);
5087 break;
5088 case IRDMA_OP_QP_FLUSH_WQES:
5089 status = irdma_sc_qp_flush_wqes(pcmdinfo->in.u.qp_flush_wqes.qp,
5090 &pcmdinfo->in.u.qp_flush_wqes.info,
5091 pcmdinfo->in.u.qp_flush_wqes.scratch,
5092 pcmdinfo->post_sq);
5093 break;
5094 case IRDMA_OP_GEN_AE:
5095 status = irdma_sc_gen_ae(pcmdinfo->in.u.gen_ae.qp,
5096 &pcmdinfo->in.u.gen_ae.info,
5097 pcmdinfo->in.u.gen_ae.scratch,
5098 pcmdinfo->post_sq);
5099 break;
5100 case IRDMA_OP_MANAGE_PUSH_PAGE:
5101 status = irdma_sc_manage_push_page(pcmdinfo->in.u.manage_push_page.cqp,
5102 &pcmdinfo->in.u.manage_push_page.info,
5103 pcmdinfo->in.u.manage_push_page.scratch,
5104 pcmdinfo->post_sq);
5105 break;
5106 case IRDMA_OP_UPDATE_PE_SDS:
5107 status = irdma_update_pe_sds(pcmdinfo->in.u.update_pe_sds.dev,
5108 &pcmdinfo->in.u.update_pe_sds.info,
5109 pcmdinfo->in.u.update_pe_sds.scratch);
5110 break;
5111 case IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE:
5112 /* switch to calling through the call table */
5113 status =
5114 irdma_sc_manage_hmc_pm_func_table(pcmdinfo->in.u.manage_hmc_pm.dev->cqp,
5115 &pcmdinfo->in.u.manage_hmc_pm.info,
5116 pcmdinfo->in.u.manage_hmc_pm.scratch,
5117 true);
5118 break;
5119 case IRDMA_OP_SUSPEND:
5120 status = irdma_sc_suspend_qp(pcmdinfo->in.u.suspend_resume.cqp,
5121 pcmdinfo->in.u.suspend_resume.qp,
5122 pcmdinfo->in.u.suspend_resume.scratch);
5123 break;
5124 case IRDMA_OP_RESUME:
5125 status = irdma_sc_resume_qp(pcmdinfo->in.u.suspend_resume.cqp,
5126 pcmdinfo->in.u.suspend_resume.qp,
5127 pcmdinfo->in.u.suspend_resume.scratch);
5128 break;
5129 case IRDMA_OP_QUERY_FPM_VAL:
5130 val_mem.pa = pcmdinfo->in.u.query_fpm_val.fpm_val_pa;
5131 val_mem.va = pcmdinfo->in.u.query_fpm_val.fpm_val_va;
5132 status = irdma_sc_query_fpm_val(pcmdinfo->in.u.query_fpm_val.cqp,
5133 pcmdinfo->in.u.query_fpm_val.scratch,
5134 pcmdinfo->in.u.query_fpm_val.hmc_fn_id,
5135 &val_mem, true, IRDMA_CQP_WAIT_EVENT);
5136 break;
5137 case IRDMA_OP_COMMIT_FPM_VAL:
5138 val_mem.pa = pcmdinfo->in.u.commit_fpm_val.fpm_val_pa;
5139 val_mem.va = pcmdinfo->in.u.commit_fpm_val.fpm_val_va;
5140 status = irdma_sc_commit_fpm_val(pcmdinfo->in.u.commit_fpm_val.cqp,
5141 pcmdinfo->in.u.commit_fpm_val.scratch,
5142 pcmdinfo->in.u.commit_fpm_val.hmc_fn_id,
5143 &val_mem,
5144 true,
5145 IRDMA_CQP_WAIT_EVENT);
5146 break;
5147 case IRDMA_OP_STATS_ALLOCATE:
5148 alloc = true;
5149 fallthrough;
5150 case IRDMA_OP_STATS_FREE:
5151 status = irdma_sc_manage_stats_inst(pcmdinfo->in.u.stats_manage.cqp,
5152 &pcmdinfo->in.u.stats_manage.info,
5153 alloc,
5154 pcmdinfo->in.u.stats_manage.scratch);
5155 break;
5156 case IRDMA_OP_STATS_GATHER:
5157 status = irdma_sc_gather_stats(pcmdinfo->in.u.stats_gather.cqp,
5158 &pcmdinfo->in.u.stats_gather.info,
5159 pcmdinfo->in.u.stats_gather.scratch);
5160 break;
5161 case IRDMA_OP_WS_MODIFY_NODE:
5162 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp,
5163 &pcmdinfo->in.u.ws_node.info,
5164 IRDMA_MODIFY_NODE,
5165 pcmdinfo->in.u.ws_node.scratch);
5166 break;
5167 case IRDMA_OP_WS_DELETE_NODE:
5168 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp,
5169 &pcmdinfo->in.u.ws_node.info,
5170 IRDMA_DEL_NODE,
5171 pcmdinfo->in.u.ws_node.scratch);
5172 break;
5173 case IRDMA_OP_WS_ADD_NODE:
5174 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp,
5175 &pcmdinfo->in.u.ws_node.info,
5176 IRDMA_ADD_NODE,
5177 pcmdinfo->in.u.ws_node.scratch);
5178 break;
5179 case IRDMA_OP_SET_UP_MAP:
5180 status = irdma_sc_set_up_map(pcmdinfo->in.u.up_map.cqp,
5181 &pcmdinfo->in.u.up_map.info,
5182 pcmdinfo->in.u.up_map.scratch);
5183 break;
5184 case IRDMA_OP_QUERY_RDMA_FEATURES:
5185 status = irdma_sc_query_rdma_features(pcmdinfo->in.u.query_rdma.cqp,
5186 &pcmdinfo->in.u.query_rdma.query_buff_mem,
5187 pcmdinfo->in.u.query_rdma.scratch);
5188 break;
5189 case IRDMA_OP_DELETE_ARP_CACHE_ENTRY:
5190 status = irdma_sc_del_arp_cache_entry(pcmdinfo->in.u.del_arp_cache_entry.cqp,
5191 pcmdinfo->in.u.del_arp_cache_entry.scratch,
5192 pcmdinfo->in.u.del_arp_cache_entry.arp_index,
5193 pcmdinfo->post_sq);
5194 break;
5195 case IRDMA_OP_MANAGE_APBVT_ENTRY:
5196 status = irdma_sc_manage_apbvt_entry(pcmdinfo->in.u.manage_apbvt_entry.cqp,
5197 &pcmdinfo->in.u.manage_apbvt_entry.info,
5198 pcmdinfo->in.u.manage_apbvt_entry.scratch,
5199 pcmdinfo->post_sq);
5200 break;
5201 case IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY:
5202 status = irdma_sc_manage_qhash_table_entry(pcmdinfo->in.u.manage_qhash_table_entry.cqp,
5203 &pcmdinfo->in.u.manage_qhash_table_entry.info,
5204 pcmdinfo->in.u.manage_qhash_table_entry.scratch,
5205 pcmdinfo->post_sq);
5206 break;
5207 case IRDMA_OP_QP_MODIFY:
5208 status = irdma_sc_qp_modify(pcmdinfo->in.u.qp_modify.qp,
5209 &pcmdinfo->in.u.qp_modify.info,
5210 pcmdinfo->in.u.qp_modify.scratch,
5211 pcmdinfo->post_sq);
5212 break;
5213 case IRDMA_OP_QP_CREATE:
5214 status = irdma_sc_qp_create(pcmdinfo->in.u.qp_create.qp,
5215 &pcmdinfo->in.u.qp_create.info,
5216 pcmdinfo->in.u.qp_create.scratch,
5217 pcmdinfo->post_sq);
5218 break;
5219 case IRDMA_OP_QP_DESTROY:
5220 status = irdma_sc_qp_destroy(pcmdinfo->in.u.qp_destroy.qp,
5221 pcmdinfo->in.u.qp_destroy.scratch,
5222 pcmdinfo->in.u.qp_destroy.remove_hash_idx,
5223 pcmdinfo->in.u.qp_destroy.ignore_mw_bnd,
5224 pcmdinfo->post_sq);
5225 break;
5226 case IRDMA_OP_ALLOC_STAG:
5227 status = irdma_sc_alloc_stag(pcmdinfo->in.u.alloc_stag.dev,
5228 &pcmdinfo->in.u.alloc_stag.info,
5229 pcmdinfo->in.u.alloc_stag.scratch,
5230 pcmdinfo->post_sq);
5231 break;
5232 case IRDMA_OP_MR_REG_NON_SHARED:
5233 status = irdma_sc_mr_reg_non_shared(pcmdinfo->in.u.mr_reg_non_shared.dev,
5234 &pcmdinfo->in.u.mr_reg_non_shared.info,
5235 pcmdinfo->in.u.mr_reg_non_shared.scratch,
5236 pcmdinfo->post_sq);
5237 break;
5238 case IRDMA_OP_DEALLOC_STAG:
5239 status = irdma_sc_dealloc_stag(pcmdinfo->in.u.dealloc_stag.dev,
5240 &pcmdinfo->in.u.dealloc_stag.info,
5241 pcmdinfo->in.u.dealloc_stag.scratch,
5242 pcmdinfo->post_sq);
5243 break;
5244 case IRDMA_OP_MW_ALLOC:
5245 status = irdma_sc_mw_alloc(pcmdinfo->in.u.mw_alloc.dev,
5246 &pcmdinfo->in.u.mw_alloc.info,
5247 pcmdinfo->in.u.mw_alloc.scratch,
5248 pcmdinfo->post_sq);
5249 break;
5250 case IRDMA_OP_ADD_ARP_CACHE_ENTRY:
5251 status = irdma_sc_add_arp_cache_entry(pcmdinfo->in.u.add_arp_cache_entry.cqp,
5252 &pcmdinfo->in.u.add_arp_cache_entry.info,
5253 pcmdinfo->in.u.add_arp_cache_entry.scratch,
5254 pcmdinfo->post_sq);
5255 break;
5256 case IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY:
5257 status = irdma_sc_alloc_local_mac_entry(pcmdinfo->in.u.alloc_local_mac_entry.cqp,
5258 pcmdinfo->in.u.alloc_local_mac_entry.scratch,
5259 pcmdinfo->post_sq);
5260 break;
5261 case IRDMA_OP_ADD_LOCAL_MAC_ENTRY:
5262 status = irdma_sc_add_local_mac_entry(pcmdinfo->in.u.add_local_mac_entry.cqp,
5263 &pcmdinfo->in.u.add_local_mac_entry.info,
5264 pcmdinfo->in.u.add_local_mac_entry.scratch,
5265 pcmdinfo->post_sq);
5266 break;
5267 case IRDMA_OP_DELETE_LOCAL_MAC_ENTRY:
5268 status = irdma_sc_del_local_mac_entry(pcmdinfo->in.u.del_local_mac_entry.cqp,
5269 pcmdinfo->in.u.del_local_mac_entry.scratch,
5270 pcmdinfo->in.u.del_local_mac_entry.entry_idx,
5271 pcmdinfo->in.u.del_local_mac_entry.ignore_ref_count,
5272 pcmdinfo->post_sq);
5273 break;
5274 case IRDMA_OP_AH_CREATE:
5275 status = irdma_sc_create_ah(pcmdinfo->in.u.ah_create.cqp,
5276 &pcmdinfo->in.u.ah_create.info,
5277 pcmdinfo->in.u.ah_create.scratch);
5278 break;
5279 case IRDMA_OP_AH_DESTROY:
5280 status = irdma_sc_destroy_ah(pcmdinfo->in.u.ah_destroy.cqp,
5281 &pcmdinfo->in.u.ah_destroy.info,
5282 pcmdinfo->in.u.ah_destroy.scratch);
5283 break;
5284 case IRDMA_OP_MC_CREATE:
5285 status = irdma_sc_create_mcast_grp(pcmdinfo->in.u.mc_create.cqp,
5286 &pcmdinfo->in.u.mc_create.info,
5287 pcmdinfo->in.u.mc_create.scratch);
5288 break;
5289 case IRDMA_OP_MC_DESTROY:
5290 status = irdma_sc_destroy_mcast_grp(pcmdinfo->in.u.mc_destroy.cqp,
5291 &pcmdinfo->in.u.mc_destroy.info,
5292 pcmdinfo->in.u.mc_destroy.scratch);
5293 break;
5294 case IRDMA_OP_MC_MODIFY:
5295 status = irdma_sc_modify_mcast_grp(pcmdinfo->in.u.mc_modify.cqp,
5296 &pcmdinfo->in.u.mc_modify.info,
5297 pcmdinfo->in.u.mc_modify.scratch);
5298 break;
5299 default:
5300 status = IRDMA_NOT_SUPPORTED;
5301 break;
5302 }
5303
5304 return status;
5305 }
5306
5307 /**
5308 * irdma_process_cqp_cmd - process all cqp commands
5309 * @dev: sc device struct
5310 * @pcmdinfo: cqp command info
5311 */
irdma_process_cqp_cmd(struct irdma_sc_dev * dev,struct cqp_cmds_info * pcmdinfo)5312 enum irdma_status_code irdma_process_cqp_cmd(struct irdma_sc_dev *dev,
5313 struct cqp_cmds_info *pcmdinfo)
5314 {
5315 enum irdma_status_code status = 0;
5316 unsigned long flags;
5317
5318 spin_lock_irqsave(&dev->cqp_lock, flags);
5319 if (list_empty(&dev->cqp_cmd_head) && !irdma_cqp_ring_full(dev->cqp))
5320 status = irdma_exec_cqp_cmd(dev, pcmdinfo);
5321 else
5322 list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head);
5323 spin_unlock_irqrestore(&dev->cqp_lock, flags);
5324 return status;
5325 }
5326
5327 /**
5328 * irdma_process_bh - called from tasklet for cqp list
5329 * @dev: sc device struct
5330 */
irdma_process_bh(struct irdma_sc_dev * dev)5331 enum irdma_status_code irdma_process_bh(struct irdma_sc_dev *dev)
5332 {
5333 enum irdma_status_code status = 0;
5334 struct cqp_cmds_info *pcmdinfo;
5335 unsigned long flags;
5336
5337 spin_lock_irqsave(&dev->cqp_lock, flags);
5338 while (!list_empty(&dev->cqp_cmd_head) &&
5339 !irdma_cqp_ring_full(dev->cqp)) {
5340 pcmdinfo = (struct cqp_cmds_info *)irdma_remove_cqp_head(dev);
5341 status = irdma_exec_cqp_cmd(dev, pcmdinfo);
5342 if (status)
5343 break;
5344 }
5345 spin_unlock_irqrestore(&dev->cqp_lock, flags);
5346 return status;
5347 }
5348
5349 /**
5350 * irdma_cfg_aeq- Configure AEQ interrupt
5351 * @dev: pointer to the device structure
5352 * @idx: vector index
5353 * @enable: True to enable, False disables
5354 */
irdma_cfg_aeq(struct irdma_sc_dev * dev,u32 idx,bool enable)5355 void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable)
5356 {
5357 u32 reg_val;
5358
5359 reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) |
5360 FIELD_PREP(IRDMA_PFINT_AEQCTL_MSIX_INDX, idx) |
5361 FIELD_PREP(IRDMA_PFINT_AEQCTL_ITR_INDX, 3);
5362 writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
5363 }
5364
5365 /**
5366 * sc_vsi_update_stats - Update statistics
5367 * @vsi: sc_vsi instance to update
5368 */
sc_vsi_update_stats(struct irdma_sc_vsi * vsi)5369 void sc_vsi_update_stats(struct irdma_sc_vsi *vsi)
5370 {
5371 struct irdma_gather_stats *gather_stats;
5372 struct irdma_gather_stats *last_gather_stats;
5373
5374 gather_stats = vsi->pestat->gather_info.gather_stats_va;
5375 last_gather_stats = vsi->pestat->gather_info.last_gather_stats_va;
5376 irdma_update_stats(&vsi->pestat->hw_stats, gather_stats,
5377 last_gather_stats);
5378 }
5379
5380 /**
5381 * irdma_wait_pe_ready - Check if firmware is ready
5382 * @dev: provides access to registers
5383 */
irdma_wait_pe_ready(struct irdma_sc_dev * dev)5384 static int irdma_wait_pe_ready(struct irdma_sc_dev *dev)
5385 {
5386 u32 statuscpu0;
5387 u32 statuscpu1;
5388 u32 statuscpu2;
5389 u32 retrycount = 0;
5390
5391 do {
5392 statuscpu0 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS0]);
5393 statuscpu1 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS1]);
5394 statuscpu2 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS2]);
5395 if (statuscpu0 == 0x80 && statuscpu1 == 0x80 &&
5396 statuscpu2 == 0x80)
5397 return 0;
5398 mdelay(1000);
5399 } while (retrycount++ < dev->hw_attrs.max_pe_ready_count);
5400 return -1;
5401 }
5402
irdma_sc_init_hw(struct irdma_sc_dev * dev)5403 static inline void irdma_sc_init_hw(struct irdma_sc_dev *dev)
5404 {
5405 switch (dev->hw_attrs.uk_attrs.hw_rev) {
5406 case IRDMA_GEN_1:
5407 i40iw_init_hw(dev);
5408 break;
5409 case IRDMA_GEN_2:
5410 icrdma_init_hw(dev);
5411 break;
5412 }
5413 }
5414
5415 /**
5416 * irdma_sc_dev_init - Initialize control part of device
5417 * @ver: version
5418 * @dev: Device pointer
5419 * @info: Device init info
5420 */
irdma_sc_dev_init(enum irdma_vers ver,struct irdma_sc_dev * dev,struct irdma_device_init_info * info)5421 enum irdma_status_code irdma_sc_dev_init(enum irdma_vers ver,
5422 struct irdma_sc_dev *dev,
5423 struct irdma_device_init_info *info)
5424 {
5425 u32 val;
5426 enum irdma_status_code ret_code = 0;
5427 u8 db_size;
5428
5429 INIT_LIST_HEAD(&dev->cqp_cmd_head); /* for CQP command backlog */
5430 mutex_init(&dev->ws_mutex);
5431 dev->hmc_fn_id = info->hmc_fn_id;
5432 dev->fpm_query_buf_pa = info->fpm_query_buf_pa;
5433 dev->fpm_query_buf = info->fpm_query_buf;
5434 dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa;
5435 dev->fpm_commit_buf = info->fpm_commit_buf;
5436 dev->hw = info->hw;
5437 dev->hw->hw_addr = info->bar0;
5438 /* Setup the hardware limits, hmc may limit further */
5439 dev->hw_attrs.min_hw_qp_id = IRDMA_MIN_IW_QP_ID;
5440 dev->hw_attrs.min_hw_aeq_size = IRDMA_MIN_AEQ_ENTRIES;
5441 dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES;
5442 dev->hw_attrs.min_hw_ceq_size = IRDMA_MIN_CEQ_ENTRIES;
5443 dev->hw_attrs.max_hw_ceq_size = IRDMA_MAX_CEQ_ENTRIES;
5444 dev->hw_attrs.uk_attrs.min_hw_cq_size = IRDMA_MIN_CQ_SIZE;
5445 dev->hw_attrs.uk_attrs.max_hw_cq_size = IRDMA_MAX_CQ_SIZE;
5446 dev->hw_attrs.uk_attrs.max_hw_wq_frags = IRDMA_MAX_WQ_FRAGMENT_COUNT;
5447 dev->hw_attrs.uk_attrs.max_hw_read_sges = IRDMA_MAX_SGE_RD;
5448 dev->hw_attrs.max_hw_outbound_msg_size = IRDMA_MAX_OUTBOUND_MSG_SIZE;
5449 dev->hw_attrs.max_mr_size = IRDMA_MAX_MR_SIZE;
5450 dev->hw_attrs.max_hw_inbound_msg_size = IRDMA_MAX_INBOUND_MSG_SIZE;
5451 dev->hw_attrs.max_hw_device_pages = IRDMA_MAX_PUSH_PAGE_COUNT;
5452 dev->hw_attrs.uk_attrs.max_hw_inline = IRDMA_MAX_INLINE_DATA_SIZE;
5453 dev->hw_attrs.max_hw_wqes = IRDMA_MAX_WQ_ENTRIES;
5454 dev->hw_attrs.max_qp_wr = IRDMA_MAX_QP_WRS(IRDMA_MAX_QUANTA_PER_WR);
5455
5456 dev->hw_attrs.uk_attrs.max_hw_rq_quanta = IRDMA_QP_SW_MAX_RQ_QUANTA;
5457 dev->hw_attrs.uk_attrs.max_hw_wq_quanta = IRDMA_QP_SW_MAX_WQ_QUANTA;
5458 dev->hw_attrs.max_hw_pds = IRDMA_MAX_PDS;
5459 dev->hw_attrs.max_hw_ena_vf_count = IRDMA_MAX_PE_ENA_VF_COUNT;
5460
5461 dev->hw_attrs.max_pe_ready_count = 14;
5462 dev->hw_attrs.max_done_count = IRDMA_DONE_COUNT;
5463 dev->hw_attrs.max_sleep_count = IRDMA_SLEEP_COUNT;
5464 dev->hw_attrs.max_cqp_compl_wait_time_ms = CQP_COMPL_WAIT_TIME_MS;
5465
5466 dev->hw_attrs.uk_attrs.hw_rev = ver;
5467 irdma_sc_init_hw(dev);
5468
5469 if (irdma_wait_pe_ready(dev))
5470 return IRDMA_ERR_TIMEOUT;
5471
5472 val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]);
5473 db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val);
5474 if (db_size != IRDMA_PE_DB_SIZE_4M && db_size != IRDMA_PE_DB_SIZE_8M) {
5475 ibdev_dbg(to_ibdev(dev),
5476 "DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n",
5477 val, db_size);
5478 return IRDMA_ERR_PE_DOORBELL_NOT_ENA;
5479 }
5480 dev->db_addr = dev->hw->hw_addr + (uintptr_t)dev->hw_regs[IRDMA_DB_ADDR_OFFSET];
5481
5482 return ret_code;
5483 }
5484
5485 /**
5486 * irdma_update_stats - Update statistics
5487 * @hw_stats: hw_stats instance to update
5488 * @gather_stats: updated stat counters
5489 * @last_gather_stats: last stat counters
5490 */
irdma_update_stats(struct irdma_dev_hw_stats * hw_stats,struct irdma_gather_stats * gather_stats,struct irdma_gather_stats * last_gather_stats)5491 void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats,
5492 struct irdma_gather_stats *gather_stats,
5493 struct irdma_gather_stats *last_gather_stats)
5494 {
5495 u64 *stats_val = hw_stats->stats_val_32;
5496
5497 stats_val[IRDMA_HW_STAT_INDEX_RXVLANERR] +=
5498 IRDMA_STATS_DELTA(gather_stats->rxvlanerr,
5499 last_gather_stats->rxvlanerr,
5500 IRDMA_MAX_STATS_32);
5501 stats_val[IRDMA_HW_STAT_INDEX_IP4RXDISCARD] +=
5502 IRDMA_STATS_DELTA(gather_stats->ip4rxdiscard,
5503 last_gather_stats->ip4rxdiscard,
5504 IRDMA_MAX_STATS_32);
5505 stats_val[IRDMA_HW_STAT_INDEX_IP4RXTRUNC] +=
5506 IRDMA_STATS_DELTA(gather_stats->ip4rxtrunc,
5507 last_gather_stats->ip4rxtrunc,
5508 IRDMA_MAX_STATS_32);
5509 stats_val[IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] +=
5510 IRDMA_STATS_DELTA(gather_stats->ip4txnoroute,
5511 last_gather_stats->ip4txnoroute,
5512 IRDMA_MAX_STATS_32);
5513 stats_val[IRDMA_HW_STAT_INDEX_IP6RXDISCARD] +=
5514 IRDMA_STATS_DELTA(gather_stats->ip6rxdiscard,
5515 last_gather_stats->ip6rxdiscard,
5516 IRDMA_MAX_STATS_32);
5517 stats_val[IRDMA_HW_STAT_INDEX_IP6RXTRUNC] +=
5518 IRDMA_STATS_DELTA(gather_stats->ip6rxtrunc,
5519 last_gather_stats->ip6rxtrunc,
5520 IRDMA_MAX_STATS_32);
5521 stats_val[IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] +=
5522 IRDMA_STATS_DELTA(gather_stats->ip6txnoroute,
5523 last_gather_stats->ip6txnoroute,
5524 IRDMA_MAX_STATS_32);
5525 stats_val[IRDMA_HW_STAT_INDEX_TCPRTXSEG] +=
5526 IRDMA_STATS_DELTA(gather_stats->tcprtxseg,
5527 last_gather_stats->tcprtxseg,
5528 IRDMA_MAX_STATS_32);
5529 stats_val[IRDMA_HW_STAT_INDEX_TCPRXOPTERR] +=
5530 IRDMA_STATS_DELTA(gather_stats->tcprxopterr,
5531 last_gather_stats->tcprxopterr,
5532 IRDMA_MAX_STATS_32);
5533 stats_val[IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] +=
5534 IRDMA_STATS_DELTA(gather_stats->tcprxprotoerr,
5535 last_gather_stats->tcprxprotoerr,
5536 IRDMA_MAX_STATS_32);
5537 stats_val[IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED] +=
5538 IRDMA_STATS_DELTA(gather_stats->rxrpcnphandled,
5539 last_gather_stats->rxrpcnphandled,
5540 IRDMA_MAX_STATS_32);
5541 stats_val[IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED] +=
5542 IRDMA_STATS_DELTA(gather_stats->rxrpcnpignored,
5543 last_gather_stats->rxrpcnpignored,
5544 IRDMA_MAX_STATS_32);
5545 stats_val[IRDMA_HW_STAT_INDEX_TXNPCNPSENT] +=
5546 IRDMA_STATS_DELTA(gather_stats->txnpcnpsent,
5547 last_gather_stats->txnpcnpsent,
5548 IRDMA_MAX_STATS_32);
5549 stats_val = hw_stats->stats_val_64;
5550 stats_val[IRDMA_HW_STAT_INDEX_IP4RXOCTS] +=
5551 IRDMA_STATS_DELTA(gather_stats->ip4rxocts,
5552 last_gather_stats->ip4rxocts,
5553 IRDMA_MAX_STATS_48);
5554 stats_val[IRDMA_HW_STAT_INDEX_IP4RXPKTS] +=
5555 IRDMA_STATS_DELTA(gather_stats->ip4rxpkts,
5556 last_gather_stats->ip4rxpkts,
5557 IRDMA_MAX_STATS_48);
5558 stats_val[IRDMA_HW_STAT_INDEX_IP4RXFRAGS] +=
5559 IRDMA_STATS_DELTA(gather_stats->ip4txfrag,
5560 last_gather_stats->ip4txfrag,
5561 IRDMA_MAX_STATS_48);
5562 stats_val[IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] +=
5563 IRDMA_STATS_DELTA(gather_stats->ip4rxmcpkts,
5564 last_gather_stats->ip4rxmcpkts,
5565 IRDMA_MAX_STATS_48);
5566 stats_val[IRDMA_HW_STAT_INDEX_IP4TXOCTS] +=
5567 IRDMA_STATS_DELTA(gather_stats->ip4txocts,
5568 last_gather_stats->ip4txocts,
5569 IRDMA_MAX_STATS_48);
5570 stats_val[IRDMA_HW_STAT_INDEX_IP4TXPKTS] +=
5571 IRDMA_STATS_DELTA(gather_stats->ip4txpkts,
5572 last_gather_stats->ip4txpkts,
5573 IRDMA_MAX_STATS_48);
5574 stats_val[IRDMA_HW_STAT_INDEX_IP4TXFRAGS] +=
5575 IRDMA_STATS_DELTA(gather_stats->ip4txfrag,
5576 last_gather_stats->ip4txfrag,
5577 IRDMA_MAX_STATS_48);
5578 stats_val[IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] +=
5579 IRDMA_STATS_DELTA(gather_stats->ip4txmcpkts,
5580 last_gather_stats->ip4txmcpkts,
5581 IRDMA_MAX_STATS_48);
5582 stats_val[IRDMA_HW_STAT_INDEX_IP6RXOCTS] +=
5583 IRDMA_STATS_DELTA(gather_stats->ip6rxocts,
5584 last_gather_stats->ip6rxocts,
5585 IRDMA_MAX_STATS_48);
5586 stats_val[IRDMA_HW_STAT_INDEX_IP6RXPKTS] +=
5587 IRDMA_STATS_DELTA(gather_stats->ip6rxpkts,
5588 last_gather_stats->ip6rxpkts,
5589 IRDMA_MAX_STATS_48);
5590 stats_val[IRDMA_HW_STAT_INDEX_IP6RXFRAGS] +=
5591 IRDMA_STATS_DELTA(gather_stats->ip6txfrags,
5592 last_gather_stats->ip6txfrags,
5593 IRDMA_MAX_STATS_48);
5594 stats_val[IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] +=
5595 IRDMA_STATS_DELTA(gather_stats->ip6rxmcpkts,
5596 last_gather_stats->ip6rxmcpkts,
5597 IRDMA_MAX_STATS_48);
5598 stats_val[IRDMA_HW_STAT_INDEX_IP6TXOCTS] +=
5599 IRDMA_STATS_DELTA(gather_stats->ip6txocts,
5600 last_gather_stats->ip6txocts,
5601 IRDMA_MAX_STATS_48);
5602 stats_val[IRDMA_HW_STAT_INDEX_IP6TXPKTS] +=
5603 IRDMA_STATS_DELTA(gather_stats->ip6txpkts,
5604 last_gather_stats->ip6txpkts,
5605 IRDMA_MAX_STATS_48);
5606 stats_val[IRDMA_HW_STAT_INDEX_IP6TXFRAGS] +=
5607 IRDMA_STATS_DELTA(gather_stats->ip6txfrags,
5608 last_gather_stats->ip6txfrags,
5609 IRDMA_MAX_STATS_48);
5610 stats_val[IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] +=
5611 IRDMA_STATS_DELTA(gather_stats->ip6txmcpkts,
5612 last_gather_stats->ip6txmcpkts,
5613 IRDMA_MAX_STATS_48);
5614 stats_val[IRDMA_HW_STAT_INDEX_TCPRXSEGS] +=
5615 IRDMA_STATS_DELTA(gather_stats->tcprxsegs,
5616 last_gather_stats->tcprxsegs,
5617 IRDMA_MAX_STATS_48);
5618 stats_val[IRDMA_HW_STAT_INDEX_TCPTXSEG] +=
5619 IRDMA_STATS_DELTA(gather_stats->tcptxsegs,
5620 last_gather_stats->tcptxsegs,
5621 IRDMA_MAX_STATS_48);
5622 stats_val[IRDMA_HW_STAT_INDEX_RDMARXRDS] +=
5623 IRDMA_STATS_DELTA(gather_stats->rdmarxrds,
5624 last_gather_stats->rdmarxrds,
5625 IRDMA_MAX_STATS_48);
5626 stats_val[IRDMA_HW_STAT_INDEX_RDMARXSNDS] +=
5627 IRDMA_STATS_DELTA(gather_stats->rdmarxsnds,
5628 last_gather_stats->rdmarxsnds,
5629 IRDMA_MAX_STATS_48);
5630 stats_val[IRDMA_HW_STAT_INDEX_RDMARXWRS] +=
5631 IRDMA_STATS_DELTA(gather_stats->rdmarxwrs,
5632 last_gather_stats->rdmarxwrs,
5633 IRDMA_MAX_STATS_48);
5634 stats_val[IRDMA_HW_STAT_INDEX_RDMATXRDS] +=
5635 IRDMA_STATS_DELTA(gather_stats->rdmatxrds,
5636 last_gather_stats->rdmatxrds,
5637 IRDMA_MAX_STATS_48);
5638 stats_val[IRDMA_HW_STAT_INDEX_RDMATXSNDS] +=
5639 IRDMA_STATS_DELTA(gather_stats->rdmatxsnds,
5640 last_gather_stats->rdmatxsnds,
5641 IRDMA_MAX_STATS_48);
5642 stats_val[IRDMA_HW_STAT_INDEX_RDMATXWRS] +=
5643 IRDMA_STATS_DELTA(gather_stats->rdmatxwrs,
5644 last_gather_stats->rdmatxwrs,
5645 IRDMA_MAX_STATS_48);
5646 stats_val[IRDMA_HW_STAT_INDEX_RDMAVBND] +=
5647 IRDMA_STATS_DELTA(gather_stats->rdmavbn,
5648 last_gather_stats->rdmavbn,
5649 IRDMA_MAX_STATS_48);
5650 stats_val[IRDMA_HW_STAT_INDEX_RDMAVINV] +=
5651 IRDMA_STATS_DELTA(gather_stats->rdmavinv,
5652 last_gather_stats->rdmavinv,
5653 IRDMA_MAX_STATS_48);
5654 stats_val[IRDMA_HW_STAT_INDEX_UDPRXPKTS] +=
5655 IRDMA_STATS_DELTA(gather_stats->udprxpkts,
5656 last_gather_stats->udprxpkts,
5657 IRDMA_MAX_STATS_48);
5658 stats_val[IRDMA_HW_STAT_INDEX_UDPTXPKTS] +=
5659 IRDMA_STATS_DELTA(gather_stats->udptxpkts,
5660 last_gather_stats->udptxpkts,
5661 IRDMA_MAX_STATS_48);
5662 stats_val[IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS] +=
5663 IRDMA_STATS_DELTA(gather_stats->rxnpecnmrkpkts,
5664 last_gather_stats->rxnpecnmrkpkts,
5665 IRDMA_MAX_STATS_48);
5666 memcpy(last_gather_stats, gather_stats, sizeof(*last_gather_stats));
5667 }
5668