1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
4 *
5 * Copyright (C) 2013 ARM Limited
6 * Copyright (C) 2017 Red Hat
7 */
8
9 #include <linux/atomic.h>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
20 #include <linux/iopoll.h>
21 #include <linux/kconfig.h>
22 #include <linux/init.h>
23 #include <linux/mutex.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/qcom_scm.h>
31 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33
34 #include "arm-smmu.h"
35
36 #define SMMU_INTR_SEL_NS 0x2000
37
38 enum qcom_iommu_clk {
39 CLK_IFACE,
40 CLK_BUS,
41 CLK_TBU,
42 CLK_NUM,
43 };
44
45 struct qcom_iommu_ctx;
46
47 struct qcom_iommu_dev {
48 /* IOMMU core code handle */
49 struct iommu_device iommu;
50 struct device *dev;
51 struct clk_bulk_data clks[CLK_NUM];
52 void __iomem *local_base;
53 u32 sec_id;
54 u8 num_ctxs;
55 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid-1 */
56 };
57
58 struct qcom_iommu_ctx {
59 struct device *dev;
60 void __iomem *base;
61 bool secure_init;
62 u8 asid; /* asid and ctx bank # are 1:1 */
63 struct iommu_domain *domain;
64 };
65
66 struct qcom_iommu_domain {
67 struct io_pgtable_ops *pgtbl_ops;
68 spinlock_t pgtbl_lock;
69 struct mutex init_mutex; /* Protects iommu pointer */
70 struct iommu_domain domain;
71 struct qcom_iommu_dev *iommu;
72 struct iommu_fwspec *fwspec;
73 };
74
to_qcom_iommu_domain(struct iommu_domain * dom)75 static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
76 {
77 return container_of(dom, struct qcom_iommu_domain, domain);
78 }
79
80 static const struct iommu_ops qcom_iommu_ops;
81
to_iommu(struct device * dev)82 static struct qcom_iommu_dev * to_iommu(struct device *dev)
83 {
84 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
85
86 if (!fwspec || fwspec->ops != &qcom_iommu_ops)
87 return NULL;
88
89 return dev_iommu_priv_get(dev);
90 }
91
to_ctx(struct qcom_iommu_domain * d,unsigned asid)92 static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid)
93 {
94 struct qcom_iommu_dev *qcom_iommu = d->iommu;
95 if (!qcom_iommu)
96 return NULL;
97 return qcom_iommu->ctxs[asid - 1];
98 }
99
100 static inline void
iommu_writel(struct qcom_iommu_ctx * ctx,unsigned reg,u32 val)101 iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val)
102 {
103 writel_relaxed(val, ctx->base + reg);
104 }
105
106 static inline void
iommu_writeq(struct qcom_iommu_ctx * ctx,unsigned reg,u64 val)107 iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val)
108 {
109 writeq_relaxed(val, ctx->base + reg);
110 }
111
112 static inline u32
iommu_readl(struct qcom_iommu_ctx * ctx,unsigned reg)113 iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg)
114 {
115 return readl_relaxed(ctx->base + reg);
116 }
117
118 static inline u64
iommu_readq(struct qcom_iommu_ctx * ctx,unsigned reg)119 iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
120 {
121 return readq_relaxed(ctx->base + reg);
122 }
123
qcom_iommu_tlb_sync(void * cookie)124 static void qcom_iommu_tlb_sync(void *cookie)
125 {
126 struct qcom_iommu_domain *qcom_domain = cookie;
127 struct iommu_fwspec *fwspec = qcom_domain->fwspec;
128 unsigned i;
129
130 for (i = 0; i < fwspec->num_ids; i++) {
131 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
132 unsigned int val, ret;
133
134 iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
135
136 ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val,
137 (val & 0x1) == 0, 0, 5000000);
138 if (ret)
139 dev_err(ctx->dev, "timeout waiting for TLB SYNC\n");
140 }
141 }
142
qcom_iommu_tlb_inv_context(void * cookie)143 static void qcom_iommu_tlb_inv_context(void *cookie)
144 {
145 struct qcom_iommu_domain *qcom_domain = cookie;
146 struct iommu_fwspec *fwspec = qcom_domain->fwspec;
147 unsigned i;
148
149 for (i = 0; i < fwspec->num_ids; i++) {
150 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
151 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
152 }
153
154 qcom_iommu_tlb_sync(cookie);
155 }
156
qcom_iommu_tlb_inv_range_nosync(unsigned long iova,size_t size,size_t granule,bool leaf,void * cookie)157 static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
158 size_t granule, bool leaf, void *cookie)
159 {
160 struct qcom_iommu_domain *qcom_domain = cookie;
161 struct iommu_fwspec *fwspec = qcom_domain->fwspec;
162 unsigned i, reg;
163
164 reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
165
166 for (i = 0; i < fwspec->num_ids; i++) {
167 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
168 size_t s = size;
169
170 iova = (iova >> 12) << 12;
171 iova |= ctx->asid;
172 do {
173 iommu_writel(ctx, reg, iova);
174 iova += granule;
175 } while (s -= granule);
176 }
177 }
178
qcom_iommu_tlb_flush_walk(unsigned long iova,size_t size,size_t granule,void * cookie)179 static void qcom_iommu_tlb_flush_walk(unsigned long iova, size_t size,
180 size_t granule, void *cookie)
181 {
182 qcom_iommu_tlb_inv_range_nosync(iova, size, granule, false, cookie);
183 qcom_iommu_tlb_sync(cookie);
184 }
185
qcom_iommu_tlb_add_page(struct iommu_iotlb_gather * gather,unsigned long iova,size_t granule,void * cookie)186 static void qcom_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,
187 unsigned long iova, size_t granule,
188 void *cookie)
189 {
190 qcom_iommu_tlb_inv_range_nosync(iova, granule, granule, true, cookie);
191 }
192
193 static const struct iommu_flush_ops qcom_flush_ops = {
194 .tlb_flush_all = qcom_iommu_tlb_inv_context,
195 .tlb_flush_walk = qcom_iommu_tlb_flush_walk,
196 .tlb_add_page = qcom_iommu_tlb_add_page,
197 };
198
qcom_iommu_fault(int irq,void * dev)199 static irqreturn_t qcom_iommu_fault(int irq, void *dev)
200 {
201 struct qcom_iommu_ctx *ctx = dev;
202 u32 fsr, fsynr;
203 u64 iova;
204
205 fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
206
207 if (!(fsr & ARM_SMMU_FSR_FAULT))
208 return IRQ_NONE;
209
210 fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
211 iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
212
213 if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) {
214 dev_err_ratelimited(ctx->dev,
215 "Unhandled context fault: fsr=0x%x, "
216 "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
217 fsr, iova, fsynr, ctx->asid);
218 }
219
220 iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
221 iommu_writel(ctx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE);
222
223 return IRQ_HANDLED;
224 }
225
qcom_iommu_init_domain(struct iommu_domain * domain,struct qcom_iommu_dev * qcom_iommu,struct device * dev)226 static int qcom_iommu_init_domain(struct iommu_domain *domain,
227 struct qcom_iommu_dev *qcom_iommu,
228 struct device *dev)
229 {
230 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
231 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
232 struct io_pgtable_ops *pgtbl_ops;
233 struct io_pgtable_cfg pgtbl_cfg;
234 int i, ret = 0;
235 u32 reg;
236
237 mutex_lock(&qcom_domain->init_mutex);
238 if (qcom_domain->iommu)
239 goto out_unlock;
240
241 pgtbl_cfg = (struct io_pgtable_cfg) {
242 .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap,
243 .ias = 32,
244 .oas = 40,
245 .tlb = &qcom_flush_ops,
246 .iommu_dev = qcom_iommu->dev,
247 };
248
249 qcom_domain->iommu = qcom_iommu;
250 qcom_domain->fwspec = fwspec;
251
252 pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, qcom_domain);
253 if (!pgtbl_ops) {
254 dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
255 ret = -ENOMEM;
256 goto out_clear_iommu;
257 }
258
259 /* Update the domain's page sizes to reflect the page table format */
260 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
261 domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1;
262 domain->geometry.force_aperture = true;
263
264 for (i = 0; i < fwspec->num_ids; i++) {
265 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
266
267 if (!ctx->secure_init) {
268 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
269 if (ret) {
270 dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret);
271 goto out_clear_iommu;
272 }
273 ctx->secure_init = true;
274 }
275
276 /* Disable context bank before programming */
277 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
278
279 /* Clear context bank fault address fault status registers */
280 iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
281 iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
282
283 /* TTBRs */
284 iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
285 pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
286 FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
287 iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
288
289 /* TCR */
290 iommu_writel(ctx, ARM_SMMU_CB_TCR2,
291 arm_smmu_lpae_tcr2(&pgtbl_cfg));
292 iommu_writel(ctx, ARM_SMMU_CB_TCR,
293 arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE);
294
295 /* MAIRs (stage-1 only) */
296 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
297 pgtbl_cfg.arm_lpae_s1_cfg.mair);
298 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
299 pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32);
300
301 /* SCTLR */
302 reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE |
303 ARM_SMMU_SCTLR_AFE | ARM_SMMU_SCTLR_TRE |
304 ARM_SMMU_SCTLR_M | ARM_SMMU_SCTLR_S1_ASIDPNE |
305 ARM_SMMU_SCTLR_CFCFG;
306
307 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
308 reg |= ARM_SMMU_SCTLR_E;
309
310 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
311
312 ctx->domain = domain;
313 }
314
315 mutex_unlock(&qcom_domain->init_mutex);
316
317 /* Publish page table ops for map/unmap */
318 qcom_domain->pgtbl_ops = pgtbl_ops;
319
320 return 0;
321
322 out_clear_iommu:
323 qcom_domain->iommu = NULL;
324 out_unlock:
325 mutex_unlock(&qcom_domain->init_mutex);
326 return ret;
327 }
328
qcom_iommu_domain_alloc(unsigned type)329 static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type)
330 {
331 struct qcom_iommu_domain *qcom_domain;
332
333 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
334 return NULL;
335 /*
336 * Allocate the domain and initialise some of its data structures.
337 * We can't really do anything meaningful until we've added a
338 * master.
339 */
340 qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL);
341 if (!qcom_domain)
342 return NULL;
343
344 mutex_init(&qcom_domain->init_mutex);
345 spin_lock_init(&qcom_domain->pgtbl_lock);
346
347 return &qcom_domain->domain;
348 }
349
qcom_iommu_domain_free(struct iommu_domain * domain)350 static void qcom_iommu_domain_free(struct iommu_domain *domain)
351 {
352 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
353
354 if (qcom_domain->iommu) {
355 /*
356 * NOTE: unmap can be called after client device is powered
357 * off, for example, with GPUs or anything involving dma-buf.
358 * So we cannot rely on the device_link. Make sure the IOMMU
359 * is on to avoid unclocked accesses in the TLB inv path:
360 */
361 pm_runtime_get_sync(qcom_domain->iommu->dev);
362 free_io_pgtable_ops(qcom_domain->pgtbl_ops);
363 pm_runtime_put_sync(qcom_domain->iommu->dev);
364 }
365
366 kfree(qcom_domain);
367 }
368
qcom_iommu_attach_dev(struct iommu_domain * domain,struct device * dev)369 static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
370 {
371 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
372 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
373 int ret;
374
375 if (!qcom_iommu) {
376 dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n");
377 return -ENXIO;
378 }
379
380 /* Ensure that the domain is finalized */
381 pm_runtime_get_sync(qcom_iommu->dev);
382 ret = qcom_iommu_init_domain(domain, qcom_iommu, dev);
383 pm_runtime_put_sync(qcom_iommu->dev);
384 if (ret < 0)
385 return ret;
386
387 /*
388 * Sanity check the domain. We don't support domains across
389 * different IOMMUs.
390 */
391 if (qcom_domain->iommu != qcom_iommu) {
392 dev_err(dev, "cannot attach to IOMMU %s while already "
393 "attached to domain on IOMMU %s\n",
394 dev_name(qcom_domain->iommu->dev),
395 dev_name(qcom_iommu->dev));
396 return -EINVAL;
397 }
398
399 return 0;
400 }
401
qcom_iommu_detach_dev(struct iommu_domain * domain,struct device * dev)402 static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev)
403 {
404 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
405 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
406 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
407 unsigned i;
408
409 if (WARN_ON(!qcom_domain->iommu))
410 return;
411
412 pm_runtime_get_sync(qcom_iommu->dev);
413 for (i = 0; i < fwspec->num_ids; i++) {
414 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
415
416 /* Disable the context bank: */
417 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
418
419 ctx->domain = NULL;
420 }
421 pm_runtime_put_sync(qcom_iommu->dev);
422 }
423
qcom_iommu_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t size,int prot,gfp_t gfp)424 static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova,
425 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
426 {
427 int ret;
428 unsigned long flags;
429 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
430 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
431
432 if (!ops)
433 return -ENODEV;
434
435 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
436 ret = ops->map(ops, iova, paddr, size, prot, GFP_ATOMIC);
437 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
438 return ret;
439 }
440
qcom_iommu_unmap(struct iommu_domain * domain,unsigned long iova,size_t size,struct iommu_iotlb_gather * gather)441 static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
442 size_t size, struct iommu_iotlb_gather *gather)
443 {
444 size_t ret;
445 unsigned long flags;
446 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
447 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
448
449 if (!ops)
450 return 0;
451
452 /* NOTE: unmap can be called after client device is powered off,
453 * for example, with GPUs or anything involving dma-buf. So we
454 * cannot rely on the device_link. Make sure the IOMMU is on to
455 * avoid unclocked accesses in the TLB inv path:
456 */
457 pm_runtime_get_sync(qcom_domain->iommu->dev);
458 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
459 ret = ops->unmap(ops, iova, size, gather);
460 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
461 pm_runtime_put_sync(qcom_domain->iommu->dev);
462
463 return ret;
464 }
465
qcom_iommu_flush_iotlb_all(struct iommu_domain * domain)466 static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain)
467 {
468 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
469 struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
470 struct io_pgtable, ops);
471 if (!qcom_domain->pgtbl_ops)
472 return;
473
474 pm_runtime_get_sync(qcom_domain->iommu->dev);
475 qcom_iommu_tlb_sync(pgtable->cookie);
476 pm_runtime_put_sync(qcom_domain->iommu->dev);
477 }
478
qcom_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)479 static void qcom_iommu_iotlb_sync(struct iommu_domain *domain,
480 struct iommu_iotlb_gather *gather)
481 {
482 qcom_iommu_flush_iotlb_all(domain);
483 }
484
qcom_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)485 static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
486 dma_addr_t iova)
487 {
488 phys_addr_t ret;
489 unsigned long flags;
490 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
491 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
492
493 if (!ops)
494 return 0;
495
496 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
497 ret = ops->iova_to_phys(ops, iova);
498 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
499
500 return ret;
501 }
502
qcom_iommu_capable(enum iommu_cap cap)503 static bool qcom_iommu_capable(enum iommu_cap cap)
504 {
505 switch (cap) {
506 case IOMMU_CAP_CACHE_COHERENCY:
507 /*
508 * Return true here as the SMMU can always send out coherent
509 * requests.
510 */
511 return true;
512 case IOMMU_CAP_NOEXEC:
513 return true;
514 default:
515 return false;
516 }
517 }
518
qcom_iommu_probe_device(struct device * dev)519 static struct iommu_device *qcom_iommu_probe_device(struct device *dev)
520 {
521 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
522 struct device_link *link;
523
524 if (!qcom_iommu)
525 return ERR_PTR(-ENODEV);
526
527 /*
528 * Establish the link between iommu and master, so that the
529 * iommu gets runtime enabled/disabled as per the master's
530 * needs.
531 */
532 link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME);
533 if (!link) {
534 dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n",
535 dev_name(qcom_iommu->dev), dev_name(dev));
536 return ERR_PTR(-ENODEV);
537 }
538
539 return &qcom_iommu->iommu;
540 }
541
qcom_iommu_release_device(struct device * dev)542 static void qcom_iommu_release_device(struct device *dev)
543 {
544 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
545
546 if (!qcom_iommu)
547 return;
548
549 iommu_fwspec_free(dev);
550 }
551
qcom_iommu_of_xlate(struct device * dev,struct of_phandle_args * args)552 static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
553 {
554 struct qcom_iommu_dev *qcom_iommu;
555 struct platform_device *iommu_pdev;
556 unsigned asid = args->args[0];
557
558 if (args->args_count != 1) {
559 dev_err(dev, "incorrect number of iommu params found for %s "
560 "(found %d, expected 1)\n",
561 args->np->full_name, args->args_count);
562 return -EINVAL;
563 }
564
565 iommu_pdev = of_find_device_by_node(args->np);
566 if (WARN_ON(!iommu_pdev))
567 return -EINVAL;
568
569 qcom_iommu = platform_get_drvdata(iommu_pdev);
570
571 /* make sure the asid specified in dt is valid, so we don't have
572 * to sanity check this elsewhere, since 'asid - 1' is used to
573 * index into qcom_iommu->ctxs:
574 */
575 if (WARN_ON(asid < 1) ||
576 WARN_ON(asid > qcom_iommu->num_ctxs)) {
577 put_device(&iommu_pdev->dev);
578 return -EINVAL;
579 }
580
581 if (!dev_iommu_priv_get(dev)) {
582 dev_iommu_priv_set(dev, qcom_iommu);
583 } else {
584 /* make sure devices iommus dt node isn't referring to
585 * multiple different iommu devices. Multiple context
586 * banks are ok, but multiple devices are not:
587 */
588 if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev))) {
589 put_device(&iommu_pdev->dev);
590 return -EINVAL;
591 }
592 }
593
594 return iommu_fwspec_add_ids(dev, &asid, 1);
595 }
596
597 static const struct iommu_ops qcom_iommu_ops = {
598 .capable = qcom_iommu_capable,
599 .domain_alloc = qcom_iommu_domain_alloc,
600 .domain_free = qcom_iommu_domain_free,
601 .attach_dev = qcom_iommu_attach_dev,
602 .detach_dev = qcom_iommu_detach_dev,
603 .map = qcom_iommu_map,
604 .unmap = qcom_iommu_unmap,
605 .flush_iotlb_all = qcom_iommu_flush_iotlb_all,
606 .iotlb_sync = qcom_iommu_iotlb_sync,
607 .iova_to_phys = qcom_iommu_iova_to_phys,
608 .probe_device = qcom_iommu_probe_device,
609 .release_device = qcom_iommu_release_device,
610 .device_group = generic_device_group,
611 .of_xlate = qcom_iommu_of_xlate,
612 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
613 };
614
qcom_iommu_sec_ptbl_init(struct device * dev)615 static int qcom_iommu_sec_ptbl_init(struct device *dev)
616 {
617 size_t psize = 0;
618 unsigned int spare = 0;
619 void *cpu_addr;
620 dma_addr_t paddr;
621 unsigned long attrs;
622 static bool allocated = false;
623 int ret;
624
625 if (allocated)
626 return 0;
627
628 ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
629 if (ret) {
630 dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
631 ret);
632 return ret;
633 }
634
635 dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
636
637 attrs = DMA_ATTR_NO_KERNEL_MAPPING;
638
639 cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
640 if (!cpu_addr) {
641 dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
642 psize);
643 return -ENOMEM;
644 }
645
646 ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
647 if (ret) {
648 dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
649 goto free_mem;
650 }
651
652 allocated = true;
653 return 0;
654
655 free_mem:
656 dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
657 return ret;
658 }
659
get_asid(const struct device_node * np)660 static int get_asid(const struct device_node *np)
661 {
662 u32 reg;
663
664 /* read the "reg" property directly to get the relative address
665 * of the context bank, and calculate the asid from that:
666 */
667 if (of_property_read_u32_index(np, "reg", 0, ®))
668 return -ENODEV;
669
670 return reg / 0x1000; /* context banks are 0x1000 apart */
671 }
672
qcom_iommu_ctx_probe(struct platform_device * pdev)673 static int qcom_iommu_ctx_probe(struct platform_device *pdev)
674 {
675 struct qcom_iommu_ctx *ctx;
676 struct device *dev = &pdev->dev;
677 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent);
678 struct resource *res;
679 int ret, irq;
680
681 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
682 if (!ctx)
683 return -ENOMEM;
684
685 ctx->dev = dev;
686 platform_set_drvdata(pdev, ctx);
687
688 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
689 ctx->base = devm_ioremap_resource(dev, res);
690 if (IS_ERR(ctx->base))
691 return PTR_ERR(ctx->base);
692
693 irq = platform_get_irq(pdev, 0);
694 if (irq < 0)
695 return -ENODEV;
696
697 /* clear IRQs before registering fault handler, just in case the
698 * boot-loader left us a surprise:
699 */
700 iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
701
702 ret = devm_request_irq(dev, irq,
703 qcom_iommu_fault,
704 IRQF_SHARED,
705 "qcom-iommu-fault",
706 ctx);
707 if (ret) {
708 dev_err(dev, "failed to request IRQ %u\n", irq);
709 return ret;
710 }
711
712 ret = get_asid(dev->of_node);
713 if (ret < 0) {
714 dev_err(dev, "missing reg property\n");
715 return ret;
716 }
717
718 ctx->asid = ret;
719
720 dev_dbg(dev, "found asid %u\n", ctx->asid);
721
722 qcom_iommu->ctxs[ctx->asid - 1] = ctx;
723
724 return 0;
725 }
726
qcom_iommu_ctx_remove(struct platform_device * pdev)727 static int qcom_iommu_ctx_remove(struct platform_device *pdev)
728 {
729 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
730 struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev);
731
732 platform_set_drvdata(pdev, NULL);
733
734 qcom_iommu->ctxs[ctx->asid - 1] = NULL;
735
736 return 0;
737 }
738
739 static const struct of_device_id ctx_of_match[] = {
740 { .compatible = "qcom,msm-iommu-v1-ns" },
741 { .compatible = "qcom,msm-iommu-v1-sec" },
742 { /* sentinel */ }
743 };
744
745 static struct platform_driver qcom_iommu_ctx_driver = {
746 .driver = {
747 .name = "qcom-iommu-ctx",
748 .of_match_table = ctx_of_match,
749 },
750 .probe = qcom_iommu_ctx_probe,
751 .remove = qcom_iommu_ctx_remove,
752 };
753
qcom_iommu_has_secure_context(struct qcom_iommu_dev * qcom_iommu)754 static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
755 {
756 struct device_node *child;
757
758 for_each_child_of_node(qcom_iommu->dev->of_node, child) {
759 if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) {
760 of_node_put(child);
761 return true;
762 }
763 }
764
765 return false;
766 }
767
qcom_iommu_device_probe(struct platform_device * pdev)768 static int qcom_iommu_device_probe(struct platform_device *pdev)
769 {
770 struct device_node *child;
771 struct qcom_iommu_dev *qcom_iommu;
772 struct device *dev = &pdev->dev;
773 struct resource *res;
774 struct clk *clk;
775 int ret, max_asid = 0;
776
777 /* find the max asid (which is 1:1 to ctx bank idx), so we know how
778 * many child ctx devices we have:
779 */
780 for_each_child_of_node(dev->of_node, child)
781 max_asid = max(max_asid, get_asid(child));
782
783 qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid),
784 GFP_KERNEL);
785 if (!qcom_iommu)
786 return -ENOMEM;
787 qcom_iommu->num_ctxs = max_asid;
788 qcom_iommu->dev = dev;
789
790 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
791 if (res) {
792 qcom_iommu->local_base = devm_ioremap_resource(dev, res);
793 if (IS_ERR(qcom_iommu->local_base))
794 return PTR_ERR(qcom_iommu->local_base);
795 }
796
797 clk = devm_clk_get(dev, "iface");
798 if (IS_ERR(clk)) {
799 dev_err(dev, "failed to get iface clock\n");
800 return PTR_ERR(clk);
801 }
802 qcom_iommu->clks[CLK_IFACE].clk = clk;
803
804 clk = devm_clk_get(dev, "bus");
805 if (IS_ERR(clk)) {
806 dev_err(dev, "failed to get bus clock\n");
807 return PTR_ERR(clk);
808 }
809 qcom_iommu->clks[CLK_BUS].clk = clk;
810
811 clk = devm_clk_get_optional(dev, "tbu");
812 if (IS_ERR(clk)) {
813 dev_err(dev, "failed to get tbu clock\n");
814 return PTR_ERR(clk);
815 }
816 qcom_iommu->clks[CLK_TBU].clk = clk;
817
818 if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id",
819 &qcom_iommu->sec_id)) {
820 dev_err(dev, "missing qcom,iommu-secure-id property\n");
821 return -ENODEV;
822 }
823
824 if (qcom_iommu_has_secure_context(qcom_iommu)) {
825 ret = qcom_iommu_sec_ptbl_init(dev);
826 if (ret) {
827 dev_err(dev, "cannot init secure pg table(%d)\n", ret);
828 return ret;
829 }
830 }
831
832 platform_set_drvdata(pdev, qcom_iommu);
833
834 pm_runtime_enable(dev);
835
836 /* register context bank devices, which are child nodes: */
837 ret = devm_of_platform_populate(dev);
838 if (ret) {
839 dev_err(dev, "Failed to populate iommu contexts\n");
840 return ret;
841 }
842
843 ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL,
844 dev_name(dev));
845 if (ret) {
846 dev_err(dev, "Failed to register iommu in sysfs\n");
847 return ret;
848 }
849
850 ret = iommu_device_register(&qcom_iommu->iommu, &qcom_iommu_ops, dev);
851 if (ret) {
852 dev_err(dev, "Failed to register iommu\n");
853 return ret;
854 }
855
856 bus_set_iommu(&platform_bus_type, &qcom_iommu_ops);
857
858 if (qcom_iommu->local_base) {
859 pm_runtime_get_sync(dev);
860 writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
861 pm_runtime_put_sync(dev);
862 }
863
864 return 0;
865 }
866
qcom_iommu_device_remove(struct platform_device * pdev)867 static int qcom_iommu_device_remove(struct platform_device *pdev)
868 {
869 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
870
871 bus_set_iommu(&platform_bus_type, NULL);
872
873 pm_runtime_force_suspend(&pdev->dev);
874 platform_set_drvdata(pdev, NULL);
875 iommu_device_sysfs_remove(&qcom_iommu->iommu);
876 iommu_device_unregister(&qcom_iommu->iommu);
877
878 return 0;
879 }
880
qcom_iommu_resume(struct device * dev)881 static int __maybe_unused qcom_iommu_resume(struct device *dev)
882 {
883 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
884
885 return clk_bulk_prepare_enable(CLK_NUM, qcom_iommu->clks);
886 }
887
qcom_iommu_suspend(struct device * dev)888 static int __maybe_unused qcom_iommu_suspend(struct device *dev)
889 {
890 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
891
892 clk_bulk_disable_unprepare(CLK_NUM, qcom_iommu->clks);
893
894 return 0;
895 }
896
897 static const struct dev_pm_ops qcom_iommu_pm_ops = {
898 SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL)
899 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
900 pm_runtime_force_resume)
901 };
902
903 static const struct of_device_id qcom_iommu_of_match[] = {
904 { .compatible = "qcom,msm-iommu-v1" },
905 { /* sentinel */ }
906 };
907
908 static struct platform_driver qcom_iommu_driver = {
909 .driver = {
910 .name = "qcom-iommu",
911 .of_match_table = qcom_iommu_of_match,
912 .pm = &qcom_iommu_pm_ops,
913 },
914 .probe = qcom_iommu_device_probe,
915 .remove = qcom_iommu_device_remove,
916 };
917
qcom_iommu_init(void)918 static int __init qcom_iommu_init(void)
919 {
920 int ret;
921
922 ret = platform_driver_register(&qcom_iommu_ctx_driver);
923 if (ret)
924 return ret;
925
926 ret = platform_driver_register(&qcom_iommu_driver);
927 if (ret)
928 platform_driver_unregister(&qcom_iommu_ctx_driver);
929
930 return ret;
931 }
932 device_initcall(qcom_iommu_init);
933