1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
5 */
6 #include <linux/bitfield.h>
7 #include <linux/bug.h>
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/device.h>
11 #include <linux/dma-direct.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/iommu.h>
16 #include <linux/iopoll.h>
17 #include <linux/list.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regmap.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28 #include <linux/soc/mediatek/infracfg.h>
29 #include <asm/barrier.h>
30 #include <soc/mediatek/smi.h>
31
32 #include "mtk_iommu.h"
33
34 #define REG_MMU_PT_BASE_ADDR 0x000
35 #define MMU_PT_ADDR_MASK GENMASK(31, 7)
36
37 #define REG_MMU_INVALIDATE 0x020
38 #define F_ALL_INVLD 0x2
39 #define F_MMU_INV_RANGE 0x1
40
41 #define REG_MMU_INVLD_START_A 0x024
42 #define REG_MMU_INVLD_END_A 0x028
43
44 #define REG_MMU_INV_SEL_GEN2 0x02c
45 #define REG_MMU_INV_SEL_GEN1 0x038
46 #define F_INVLD_EN0 BIT(0)
47 #define F_INVLD_EN1 BIT(1)
48
49 #define REG_MMU_MISC_CTRL 0x048
50 #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17))
51 #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19))
52
53 #define REG_MMU_DCM_DIS 0x050
54 #define REG_MMU_WR_LEN_CTRL 0x054
55 #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21))
56
57 #define REG_MMU_CTRL_REG 0x110
58 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4)
59 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
60 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5)
61
62 #define REG_MMU_IVRP_PADDR 0x114
63
64 #define REG_MMU_VLD_PA_RNG 0x118
65 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA))
66
67 #define REG_MMU_INT_CONTROL0 0x120
68 #define F_L2_MULIT_HIT_EN BIT(0)
69 #define F_TABLE_WALK_FAULT_INT_EN BIT(1)
70 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
71 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3)
72 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
73 #define F_MISS_FIFO_ERR_INT_EN BIT(6)
74 #define F_INT_CLR_BIT BIT(12)
75
76 #define REG_MMU_INT_MAIN_CONTROL 0x124
77 /* mmu0 | mmu1 */
78 #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7))
79 #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8))
80 #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9))
81 #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10))
82 #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11))
83 #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12))
84 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13))
85
86 #define REG_MMU_CPE_DONE 0x12C
87
88 #define REG_MMU_FAULT_ST1 0x134
89 #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)
90 #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
91
92 #define REG_MMU0_FAULT_VA 0x13c
93 #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
94 #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
95 #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
96 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
97 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
98
99 #define REG_MMU0_INVLD_PA 0x140
100 #define REG_MMU1_FAULT_VA 0x144
101 #define REG_MMU1_INVLD_PA 0x148
102 #define REG_MMU0_INT_ID 0x150
103 #define REG_MMU1_INT_ID 0x154
104 #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7)
105 #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
106 #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
107 #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
108
109 #define MTK_PROTECT_PA_ALIGN 256
110
111 #define HAS_4GB_MODE BIT(0)
112 /* HW will use the EMI clock if there isn't the "bclk". */
113 #define HAS_BCLK BIT(1)
114 #define HAS_VLD_PA_RNG BIT(2)
115 #define RESET_AXI BIT(3)
116 #define OUT_ORDER_WR_EN BIT(4)
117 #define HAS_SUB_COMM BIT(5)
118 #define WR_THROT_EN BIT(6)
119 #define HAS_LEGACY_IVRP_PADDR BIT(7)
120 #define IOVA_34_EN BIT(8)
121 #define PGTABLE_PA_35_EN BIT(9)
122
123 #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
124 ((((pdata)->flags) & (_x)) == (_x))
125
126 struct mtk_iommu_domain {
127 struct io_pgtable_cfg cfg;
128 struct io_pgtable_ops *iop;
129 u32 ttbr;
130
131 struct mtk_iommu_data *data;
132 struct iommu_domain domain;
133 };
134
135 static const struct iommu_ops mtk_iommu_ops;
136
137 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);
138
139 #define MTK_IOMMU_TLB_ADDR(iova) ({ \
140 dma_addr_t _addr = iova; \
141 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
142 })
143
144 /*
145 * In M4U 4GB mode, the physical address is remapped as below:
146 *
147 * CPU Physical address:
148 * ====================
149 *
150 * 0 1G 2G 3G 4G 5G
151 * |---A---|---B---|---C---|---D---|---E---|
152 * +--I/O--+------------Memory-------------+
153 *
154 * IOMMU output physical address:
155 * =============================
156 *
157 * 4G 5G 6G 7G 8G
158 * |---E---|---B---|---C---|---D---|
159 * +------------Memory-------------+
160 *
161 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
162 * bit32 of the CPU physical address always is needed to set, and for Region
163 * 'E', the CPU physical address keep as is.
164 * Additionally, The iommu consumers always use the CPU phyiscal address.
165 */
166 #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL
167
168 static LIST_HEAD(m4ulist); /* List all the M4U HWs */
169
170 #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list)
171
172 struct mtk_iommu_iova_region {
173 dma_addr_t iova_base;
174 unsigned long long size;
175 };
176
177 static const struct mtk_iommu_iova_region single_domain[] = {
178 {.iova_base = 0, .size = SZ_4G},
179 };
180
181 static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
182 { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */
183 #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
184 { .iova_base = SZ_4G, .size = SZ_4G}, /* vdec: 4G ~ 8G */
185 { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* CAM/MDP: 8G ~ 12G */
186 { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
187 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
188 #endif
189 };
190
191 /*
192 * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
193 * for the performance.
194 *
195 * Here always return the mtk_iommu_data of the first probed M4U where the
196 * iommu domain information is recorded.
197 */
mtk_iommu_get_m4u_data(void)198 static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
199 {
200 struct mtk_iommu_data *data;
201
202 for_each_m4u(data)
203 return data;
204
205 return NULL;
206 }
207
to_mtk_domain(struct iommu_domain * dom)208 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
209 {
210 return container_of(dom, struct mtk_iommu_domain, domain);
211 }
212
mtk_iommu_tlb_flush_all(struct mtk_iommu_data * data)213 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
214 {
215 for_each_m4u(data) {
216 if (pm_runtime_get_if_in_use(data->dev) <= 0)
217 continue;
218
219 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
220 data->base + data->plat_data->inv_sel_reg);
221 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
222 wmb(); /* Make sure the tlb flush all done */
223
224 pm_runtime_put(data->dev);
225 }
226 }
227
mtk_iommu_tlb_flush_range_sync(unsigned long iova,size_t size,size_t granule,struct mtk_iommu_data * data)228 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
229 size_t granule,
230 struct mtk_iommu_data *data)
231 {
232 bool has_pm = !!data->dev->pm_domain;
233 unsigned long flags;
234 int ret;
235 u32 tmp;
236
237 for_each_m4u(data) {
238 if (has_pm) {
239 if (pm_runtime_get_if_in_use(data->dev) <= 0)
240 continue;
241 }
242
243 spin_lock_irqsave(&data->tlb_lock, flags);
244 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
245 data->base + data->plat_data->inv_sel_reg);
246
247 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova),
248 data->base + REG_MMU_INVLD_START_A);
249 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
250 data->base + REG_MMU_INVLD_END_A);
251 writel_relaxed(F_MMU_INV_RANGE,
252 data->base + REG_MMU_INVALIDATE);
253
254 /* tlb sync */
255 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
256 tmp, tmp != 0, 10, 1000);
257 if (ret) {
258 dev_warn(data->dev,
259 "Partial TLB flush timed out, falling back to full flush\n");
260 mtk_iommu_tlb_flush_all(data);
261 }
262 /* Clear the CPE status */
263 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
264 spin_unlock_irqrestore(&data->tlb_lock, flags);
265
266 if (has_pm)
267 pm_runtime_put(data->dev);
268 }
269 }
270
mtk_iommu_isr(int irq,void * dev_id)271 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
272 {
273 struct mtk_iommu_data *data = dev_id;
274 struct mtk_iommu_domain *dom = data->m4u_dom;
275 unsigned int fault_larb, fault_port, sub_comm = 0;
276 u32 int_state, regval, va34_32, pa34_32;
277 u64 fault_iova, fault_pa;
278 bool layer, write;
279
280 /* Read error info from registers */
281 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
282 if (int_state & F_REG_MMU0_FAULT_MASK) {
283 regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
284 fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
285 fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
286 } else {
287 regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
288 fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
289 fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
290 }
291 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
292 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
293 if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {
294 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
295 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
296 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
297 fault_iova |= (u64)va34_32 << 32;
298 fault_pa |= (u64)pa34_32 << 32;
299 }
300
301 fault_port = F_MMU_INT_ID_PORT_ID(regval);
302 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
303 fault_larb = F_MMU_INT_ID_COMM_ID(regval);
304 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
305 } else {
306 fault_larb = F_MMU_INT_ID_LARB_ID(regval);
307 }
308 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
309
310 if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
311 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
312 dev_err_ratelimited(
313 data->dev,
314 "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",
315 int_state, fault_iova, fault_pa, fault_larb, fault_port,
316 layer, write ? "write" : "read");
317 }
318
319 /* Interrupt clear */
320 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);
321 regval |= F_INT_CLR_BIT;
322 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
323
324 mtk_iommu_tlb_flush_all(data);
325
326 return IRQ_HANDLED;
327 }
328
mtk_iommu_get_domain_id(struct device * dev,const struct mtk_iommu_plat_data * plat_data)329 static int mtk_iommu_get_domain_id(struct device *dev,
330 const struct mtk_iommu_plat_data *plat_data)
331 {
332 const struct mtk_iommu_iova_region *rgn = plat_data->iova_region;
333 const struct bus_dma_region *dma_rgn = dev->dma_range_map;
334 int i, candidate = -1;
335 dma_addr_t dma_end;
336
337 if (!dma_rgn || plat_data->iova_region_nr == 1)
338 return 0;
339
340 dma_end = dma_rgn->dma_start + dma_rgn->size - 1;
341 for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) {
342 /* Best fit. */
343 if (dma_rgn->dma_start == rgn->iova_base &&
344 dma_end == rgn->iova_base + rgn->size - 1)
345 return i;
346 /* ok if it is inside this region. */
347 if (dma_rgn->dma_start >= rgn->iova_base &&
348 dma_end < rgn->iova_base + rgn->size)
349 candidate = i;
350 }
351
352 if (candidate >= 0)
353 return candidate;
354 dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n",
355 &dma_rgn->dma_start, dma_rgn->size);
356 return -EINVAL;
357 }
358
mtk_iommu_config(struct mtk_iommu_data * data,struct device * dev,bool enable,unsigned int domid)359 static void mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
360 bool enable, unsigned int domid)
361 {
362 struct mtk_smi_larb_iommu *larb_mmu;
363 unsigned int larbid, portid;
364 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
365 const struct mtk_iommu_iova_region *region;
366 int i;
367
368 for (i = 0; i < fwspec->num_ids; ++i) {
369 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
370 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
371
372 larb_mmu = &data->larb_imu[larbid];
373
374 region = data->plat_data->iova_region + domid;
375 larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
376
377 dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n",
378 enable ? "enable" : "disable", dev_name(larb_mmu->dev),
379 portid, domid, larb_mmu->bank[portid]);
380
381 if (enable)
382 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
383 else
384 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
385 }
386 }
387
mtk_iommu_domain_finalise(struct mtk_iommu_domain * dom,struct mtk_iommu_data * data,unsigned int domid)388 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
389 struct mtk_iommu_data *data,
390 unsigned int domid)
391 {
392 const struct mtk_iommu_iova_region *region;
393
394 /* Use the exist domain as there is only one pgtable here. */
395 if (data->m4u_dom) {
396 dom->iop = data->m4u_dom->iop;
397 dom->cfg = data->m4u_dom->cfg;
398 dom->ttbr = data->m4u_dom->ttbr;
399 dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap;
400 goto update_iova_region;
401 }
402
403 dom->cfg = (struct io_pgtable_cfg) {
404 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
405 IO_PGTABLE_QUIRK_NO_PERMS |
406 IO_PGTABLE_QUIRK_ARM_MTK_EXT,
407 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
408 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
409 .iommu_dev = data->dev,
410 };
411
412 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
413 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
414
415 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
416 dom->cfg.oas = data->enable_4GB ? 33 : 32;
417 else
418 dom->cfg.oas = 35;
419
420 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
421 if (!dom->iop) {
422 dev_err(data->dev, "Failed to alloc io pgtable\n");
423 return -EINVAL;
424 }
425 dom->ttbr = dom->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
426 dom->cfg.arm_v7s_cfg.ttbr :
427 dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK;
428
429 /* Update our support page sizes bitmap */
430 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
431
432 update_iova_region:
433 /* Update the iova region for this domain */
434 region = data->plat_data->iova_region + domid;
435 dom->domain.geometry.aperture_start = region->iova_base;
436 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
437 dom->domain.geometry.force_aperture = true;
438 return 0;
439 }
440
mtk_iommu_domain_alloc(unsigned type)441 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
442 {
443 struct mtk_iommu_domain *dom;
444
445 if (type != IOMMU_DOMAIN_DMA)
446 return NULL;
447
448 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
449 if (!dom)
450 return NULL;
451
452 return &dom->domain;
453 }
454
mtk_iommu_domain_free(struct iommu_domain * domain)455 static void mtk_iommu_domain_free(struct iommu_domain *domain)
456 {
457 kfree(to_mtk_domain(domain));
458 }
459
mtk_iommu_attach_device(struct iommu_domain * domain,struct device * dev)460 static int mtk_iommu_attach_device(struct iommu_domain *domain,
461 struct device *dev)
462 {
463 struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata;
464 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
465 struct device *m4udev = data->dev;
466 int ret, domid;
467
468 domid = mtk_iommu_get_domain_id(dev, data->plat_data);
469 if (domid < 0)
470 return domid;
471
472 if (!dom->data) {
473 /* Data is in the frstdata in sharing pgtable case. */
474 frstdata = mtk_iommu_get_m4u_data();
475
476 if (mtk_iommu_domain_finalise(dom, frstdata, domid))
477 return -ENODEV;
478 dom->data = data;
479 }
480
481 mutex_lock(&data->mutex);
482 if (!data->m4u_dom) { /* Initialize the M4U HW */
483 ret = pm_runtime_resume_and_get(m4udev);
484 if (ret < 0)
485 goto err_unlock;
486
487 ret = mtk_iommu_hw_init(data);
488 if (ret) {
489 pm_runtime_put(m4udev);
490 goto err_unlock;
491 }
492 data->m4u_dom = dom;
493 writel(data->m4u_dom->ttbr, data->base + REG_MMU_PT_BASE_ADDR);
494
495 pm_runtime_put(m4udev);
496 }
497 mutex_unlock(&data->mutex);
498
499 mtk_iommu_config(data, dev, true, domid);
500 return 0;
501
502 err_unlock:
503 mutex_unlock(&data->mutex);
504 return ret;
505 }
506
mtk_iommu_detach_device(struct iommu_domain * domain,struct device * dev)507 static void mtk_iommu_detach_device(struct iommu_domain *domain,
508 struct device *dev)
509 {
510 struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
511
512 mtk_iommu_config(data, dev, false, 0);
513 }
514
mtk_iommu_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t size,int prot,gfp_t gfp)515 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
516 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
517 {
518 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
519
520 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
521 if (dom->data->enable_4GB)
522 paddr |= BIT_ULL(32);
523
524 /* Synchronize with the tlb_lock */
525 return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp);
526 }
527
mtk_iommu_unmap(struct iommu_domain * domain,unsigned long iova,size_t size,struct iommu_iotlb_gather * gather)528 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
529 unsigned long iova, size_t size,
530 struct iommu_iotlb_gather *gather)
531 {
532 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
533
534 iommu_iotlb_gather_add_range(gather, iova, size);
535 return dom->iop->unmap(dom->iop, iova, size, gather);
536 }
537
mtk_iommu_flush_iotlb_all(struct iommu_domain * domain)538 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
539 {
540 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
541
542 mtk_iommu_tlb_flush_all(dom->data);
543 }
544
mtk_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)545 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
546 struct iommu_iotlb_gather *gather)
547 {
548 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
549 size_t length = gather->end - gather->start + 1;
550
551 mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize,
552 dom->data);
553 }
554
mtk_iommu_sync_map(struct iommu_domain * domain,unsigned long iova,size_t size)555 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
556 size_t size)
557 {
558 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
559
560 mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data);
561 }
562
mtk_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)563 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
564 dma_addr_t iova)
565 {
566 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
567 phys_addr_t pa;
568
569 pa = dom->iop->iova_to_phys(dom->iop, iova);
570 if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
571 dom->data->enable_4GB &&
572 pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
573 pa &= ~BIT_ULL(32);
574
575 return pa;
576 }
577
mtk_iommu_probe_device(struct device * dev)578 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
579 {
580 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
581 struct mtk_iommu_data *data;
582 struct device_link *link;
583 struct device *larbdev;
584 unsigned int larbid, larbidx, i;
585
586 if (!fwspec || fwspec->ops != &mtk_iommu_ops)
587 return ERR_PTR(-ENODEV); /* Not a iommu client device */
588
589 data = dev_iommu_priv_get(dev);
590
591 /*
592 * Link the consumer device with the smi-larb device(supplier).
593 * The device that connects with each a larb is a independent HW.
594 * All the ports in each a device should be in the same larbs.
595 */
596 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
597 if (larbid >= MTK_LARB_NR_MAX)
598 return ERR_PTR(-EINVAL);
599
600 for (i = 1; i < fwspec->num_ids; i++) {
601 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);
602 if (larbid != larbidx) {
603 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
604 larbid, larbidx);
605 return ERR_PTR(-EINVAL);
606 }
607 }
608 larbdev = data->larb_imu[larbid].dev;
609 if (!larbdev)
610 return ERR_PTR(-EINVAL);
611
612 link = device_link_add(dev, larbdev,
613 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
614 if (!link)
615 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
616 return &data->iommu;
617 }
618
mtk_iommu_release_device(struct device * dev)619 static void mtk_iommu_release_device(struct device *dev)
620 {
621 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
622 struct mtk_iommu_data *data;
623 struct device *larbdev;
624 unsigned int larbid;
625
626 if (!fwspec || fwspec->ops != &mtk_iommu_ops)
627 return;
628
629 data = dev_iommu_priv_get(dev);
630 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
631 larbdev = data->larb_imu[larbid].dev;
632 device_link_remove(dev, larbdev);
633
634 iommu_fwspec_free(dev);
635 }
636
mtk_iommu_device_group(struct device * dev)637 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
638 {
639 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
640 struct iommu_group *group;
641 int domid;
642
643 if (!data)
644 return ERR_PTR(-ENODEV);
645
646 domid = mtk_iommu_get_domain_id(dev, data->plat_data);
647 if (domid < 0)
648 return ERR_PTR(domid);
649
650 mutex_lock(&data->mutex);
651 group = data->m4u_group[domid];
652 if (!group) {
653 group = iommu_group_alloc();
654 if (!IS_ERR(group))
655 data->m4u_group[domid] = group;
656 } else {
657 iommu_group_ref_get(group);
658 }
659 mutex_unlock(&data->mutex);
660 return group;
661 }
662
mtk_iommu_of_xlate(struct device * dev,struct of_phandle_args * args)663 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
664 {
665 struct platform_device *m4updev;
666
667 if (args->args_count != 1) {
668 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
669 args->args_count);
670 return -EINVAL;
671 }
672
673 if (!dev_iommu_priv_get(dev)) {
674 /* Get the m4u device */
675 m4updev = of_find_device_by_node(args->np);
676 if (WARN_ON(!m4updev))
677 return -EINVAL;
678
679 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
680 }
681
682 return iommu_fwspec_add_ids(dev, args->args, 1);
683 }
684
mtk_iommu_get_resv_regions(struct device * dev,struct list_head * head)685 static void mtk_iommu_get_resv_regions(struct device *dev,
686 struct list_head *head)
687 {
688 struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
689 unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i;
690 const struct mtk_iommu_iova_region *resv, *curdom;
691 struct iommu_resv_region *region;
692 int prot = IOMMU_WRITE | IOMMU_READ;
693
694 if ((int)domid < 0)
695 return;
696 curdom = data->plat_data->iova_region + domid;
697 for (i = 0; i < data->plat_data->iova_region_nr; i++) {
698 resv = data->plat_data->iova_region + i;
699
700 /* Only reserve when the region is inside the current domain */
701 if (resv->iova_base <= curdom->iova_base ||
702 resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
703 continue;
704
705 region = iommu_alloc_resv_region(resv->iova_base, resv->size,
706 prot, IOMMU_RESV_RESERVED);
707 if (!region)
708 return;
709
710 list_add_tail(®ion->list, head);
711 }
712 }
713
714 static const struct iommu_ops mtk_iommu_ops = {
715 .domain_alloc = mtk_iommu_domain_alloc,
716 .domain_free = mtk_iommu_domain_free,
717 .attach_dev = mtk_iommu_attach_device,
718 .detach_dev = mtk_iommu_detach_device,
719 .map = mtk_iommu_map,
720 .unmap = mtk_iommu_unmap,
721 .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
722 .iotlb_sync = mtk_iommu_iotlb_sync,
723 .iotlb_sync_map = mtk_iommu_sync_map,
724 .iova_to_phys = mtk_iommu_iova_to_phys,
725 .probe_device = mtk_iommu_probe_device,
726 .release_device = mtk_iommu_release_device,
727 .device_group = mtk_iommu_device_group,
728 .of_xlate = mtk_iommu_of_xlate,
729 .get_resv_regions = mtk_iommu_get_resv_regions,
730 .put_resv_regions = generic_iommu_put_resv_regions,
731 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
732 .owner = THIS_MODULE,
733 };
734
mtk_iommu_hw_init(const struct mtk_iommu_data * data)735 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
736 {
737 u32 regval;
738
739 if (data->plat_data->m4u_plat == M4U_MT8173) {
740 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
741 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
742 } else {
743 regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
744 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
745 }
746 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
747
748 regval = F_L2_MULIT_HIT_EN |
749 F_TABLE_WALK_FAULT_INT_EN |
750 F_PREETCH_FIFO_OVERFLOW_INT_EN |
751 F_MISS_FIFO_OVERFLOW_INT_EN |
752 F_PREFETCH_FIFO_ERR_INT_EN |
753 F_MISS_FIFO_ERR_INT_EN;
754 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
755
756 regval = F_INT_TRANSLATION_FAULT |
757 F_INT_MAIN_MULTI_HIT_FAULT |
758 F_INT_INVALID_PA_FAULT |
759 F_INT_ENTRY_REPLACEMENT_FAULT |
760 F_INT_TLB_MISS_FAULT |
761 F_INT_MISS_TRANSACTION_FIFO_FAULT |
762 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
763 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
764
765 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
766 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
767 else
768 regval = lower_32_bits(data->protect_base) |
769 upper_32_bits(data->protect_base);
770 writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
771
772 if (data->enable_4GB &&
773 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
774 /*
775 * If 4GB mode is enabled, the validate PA range is from
776 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
777 */
778 regval = F_MMU_VLD_PA_RNG(7, 4);
779 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
780 }
781 writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
782 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
783 /* write command throttling mode */
784 regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL);
785 regval &= ~F_MMU_WR_THROT_DIS_MASK;
786 writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL);
787 }
788
789 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
790 /* The register is called STANDARD_AXI_MODE in this case */
791 regval = 0;
792 } else {
793 regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
794 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
795 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
796 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
797 }
798 writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
799
800 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
801 dev_name(data->dev), (void *)data)) {
802 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
803 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
804 return -ENODEV;
805 }
806
807 return 0;
808 }
809
810 static const struct component_master_ops mtk_iommu_com_ops = {
811 .bind = mtk_iommu_bind,
812 .unbind = mtk_iommu_unbind,
813 };
814
mtk_iommu_probe(struct platform_device * pdev)815 static int mtk_iommu_probe(struct platform_device *pdev)
816 {
817 struct mtk_iommu_data *data;
818 struct device *dev = &pdev->dev;
819 struct device_node *larbnode, *smicomm_node;
820 struct platform_device *plarbdev;
821 struct device_link *link;
822 struct resource *res;
823 resource_size_t ioaddr;
824 struct component_match *match = NULL;
825 struct regmap *infracfg;
826 void *protect;
827 int i, larb_nr, ret;
828 u32 val;
829 char *p;
830
831 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
832 if (!data)
833 return -ENOMEM;
834 data->dev = dev;
835 data->plat_data = of_device_get_match_data(dev);
836
837 /* Protect memory. HW will access here while translation fault.*/
838 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
839 if (!protect)
840 return -ENOMEM;
841 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
842
843 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
844 switch (data->plat_data->m4u_plat) {
845 case M4U_MT2712:
846 p = "mediatek,mt2712-infracfg";
847 break;
848 case M4U_MT8173:
849 p = "mediatek,mt8173-infracfg";
850 break;
851 default:
852 p = NULL;
853 }
854
855 infracfg = syscon_regmap_lookup_by_compatible(p);
856
857 if (IS_ERR(infracfg))
858 return PTR_ERR(infracfg);
859
860 ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
861 if (ret)
862 return ret;
863 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
864 }
865
866 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
867 data->base = devm_ioremap_resource(dev, res);
868 if (IS_ERR(data->base))
869 return PTR_ERR(data->base);
870 ioaddr = res->start;
871
872 data->irq = platform_get_irq(pdev, 0);
873 if (data->irq < 0)
874 return data->irq;
875
876 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
877 data->bclk = devm_clk_get(dev, "bclk");
878 if (IS_ERR(data->bclk))
879 return PTR_ERR(data->bclk);
880 }
881
882 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) {
883 ret = dma_set_mask(dev, DMA_BIT_MASK(35));
884 if (ret) {
885 dev_err(dev, "Failed to set dma_mask 35.\n");
886 return ret;
887 }
888 }
889
890 larb_nr = of_count_phandle_with_args(dev->of_node,
891 "mediatek,larbs", NULL);
892 if (larb_nr < 0)
893 return larb_nr;
894
895 for (i = 0; i < larb_nr; i++) {
896 u32 id;
897
898 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
899 if (!larbnode)
900 return -EINVAL;
901
902 if (!of_device_is_available(larbnode)) {
903 of_node_put(larbnode);
904 continue;
905 }
906
907 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
908 if (ret)/* The id is consecutive if there is no this property */
909 id = i;
910
911 plarbdev = of_find_device_by_node(larbnode);
912 if (!plarbdev) {
913 of_node_put(larbnode);
914 return -ENODEV;
915 }
916 data->larb_imu[id].dev = &plarbdev->dev;
917
918 component_match_add_release(dev, &match, release_of,
919 compare_of, larbnode);
920 }
921
922 /* Get smi-common dev from the last larb. */
923 smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
924 if (!smicomm_node)
925 return -EINVAL;
926
927 plarbdev = of_find_device_by_node(smicomm_node);
928 of_node_put(smicomm_node);
929 data->smicomm_dev = &plarbdev->dev;
930
931 pm_runtime_enable(dev);
932
933 link = device_link_add(data->smicomm_dev, dev,
934 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
935 if (!link) {
936 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
937 ret = -EINVAL;
938 goto out_runtime_disable;
939 }
940
941 platform_set_drvdata(pdev, data);
942 mutex_init(&data->mutex);
943
944 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
945 "mtk-iommu.%pa", &ioaddr);
946 if (ret)
947 goto out_link_remove;
948
949 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
950 if (ret)
951 goto out_sysfs_remove;
952
953 spin_lock_init(&data->tlb_lock);
954 list_add_tail(&data->list, &m4ulist);
955
956 if (!iommu_present(&platform_bus_type)) {
957 ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
958 if (ret)
959 goto out_list_del;
960 }
961
962 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
963 if (ret)
964 goto out_bus_set_null;
965 return ret;
966
967 out_bus_set_null:
968 bus_set_iommu(&platform_bus_type, NULL);
969 out_list_del:
970 list_del(&data->list);
971 iommu_device_unregister(&data->iommu);
972 out_sysfs_remove:
973 iommu_device_sysfs_remove(&data->iommu);
974 out_link_remove:
975 device_link_remove(data->smicomm_dev, dev);
976 out_runtime_disable:
977 pm_runtime_disable(dev);
978 return ret;
979 }
980
mtk_iommu_remove(struct platform_device * pdev)981 static int mtk_iommu_remove(struct platform_device *pdev)
982 {
983 struct mtk_iommu_data *data = platform_get_drvdata(pdev);
984
985 iommu_device_sysfs_remove(&data->iommu);
986 iommu_device_unregister(&data->iommu);
987
988 list_del(&data->list);
989
990 device_link_remove(data->smicomm_dev, &pdev->dev);
991 pm_runtime_disable(&pdev->dev);
992 devm_free_irq(&pdev->dev, data->irq, data);
993 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
994 return 0;
995 }
996
mtk_iommu_runtime_suspend(struct device * dev)997 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
998 {
999 struct mtk_iommu_data *data = dev_get_drvdata(dev);
1000 struct mtk_iommu_suspend_reg *reg = &data->reg;
1001 void __iomem *base = data->base;
1002
1003 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
1004 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
1005 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
1006 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
1007 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
1008 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
1009 reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
1010 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
1011 clk_disable_unprepare(data->bclk);
1012 return 0;
1013 }
1014
mtk_iommu_runtime_resume(struct device * dev)1015 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
1016 {
1017 struct mtk_iommu_data *data = dev_get_drvdata(dev);
1018 struct mtk_iommu_suspend_reg *reg = &data->reg;
1019 struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
1020 void __iomem *base = data->base;
1021 int ret;
1022
1023 ret = clk_prepare_enable(data->bclk);
1024 if (ret) {
1025 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
1026 return ret;
1027 }
1028
1029 /*
1030 * Uppon first resume, only enable the clk and return, since the values of the
1031 * registers are not yet set.
1032 */
1033 if (!m4u_dom)
1034 return 0;
1035
1036 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
1037 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
1038 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
1039 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
1040 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
1041 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
1042 writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
1043 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
1044 writel(m4u_dom->ttbr, base + REG_MMU_PT_BASE_ADDR);
1045 return 0;
1046 }
1047
1048 static const struct dev_pm_ops mtk_iommu_pm_ops = {
1049 SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
1050 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1051 pm_runtime_force_resume)
1052 };
1053
1054 static const struct mtk_iommu_plat_data mt2712_data = {
1055 .m4u_plat = M4U_MT2712,
1056 .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
1057 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1058 .iova_region = single_domain,
1059 .iova_region_nr = ARRAY_SIZE(single_domain),
1060 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1061 };
1062
1063 static const struct mtk_iommu_plat_data mt6779_data = {
1064 .m4u_plat = M4U_MT6779,
1065 .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN |
1066 PGTABLE_PA_35_EN,
1067 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1068 .iova_region = single_domain,
1069 .iova_region_nr = ARRAY_SIZE(single_domain),
1070 .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
1071 };
1072
1073 static const struct mtk_iommu_plat_data mt8167_data = {
1074 .m4u_plat = M4U_MT8167,
1075 .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR,
1076 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1077 .iova_region = single_domain,
1078 .iova_region_nr = ARRAY_SIZE(single_domain),
1079 .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
1080 };
1081
1082 static const struct mtk_iommu_plat_data mt8173_data = {
1083 .m4u_plat = M4U_MT8173,
1084 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1085 HAS_LEGACY_IVRP_PADDR,
1086 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1087 .iova_region = single_domain,
1088 .iova_region_nr = ARRAY_SIZE(single_domain),
1089 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1090 };
1091
1092 static const struct mtk_iommu_plat_data mt8183_data = {
1093 .m4u_plat = M4U_MT8183,
1094 .flags = RESET_AXI,
1095 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1096 .iova_region = single_domain,
1097 .iova_region_nr = ARRAY_SIZE(single_domain),
1098 .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1099 };
1100
1101 static const struct mtk_iommu_plat_data mt8192_data = {
1102 .m4u_plat = M4U_MT8192,
1103 .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
1104 WR_THROT_EN | IOVA_34_EN,
1105 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1106 .iova_region = mt8192_multi_dom,
1107 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1108 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
1109 {0, 14, 16}, {0, 13, 18, 17}},
1110 };
1111
1112 static const struct of_device_id mtk_iommu_of_ids[] = {
1113 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1114 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1115 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1116 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1117 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1118 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1119 {}
1120 };
1121
1122 static struct platform_driver mtk_iommu_driver = {
1123 .probe = mtk_iommu_probe,
1124 .remove = mtk_iommu_remove,
1125 .driver = {
1126 .name = "mtk-iommu",
1127 .of_match_table = mtk_iommu_of_ids,
1128 .pm = &mtk_iommu_pm_ops,
1129 }
1130 };
1131 module_platform_driver(mtk_iommu_driver);
1132
1133 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
1134 MODULE_LICENSE("GPL v2");
1135