1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 *
5 * Interrupt architecture for the GIC:
6 *
7 * o There is one Interrupt Distributor, which receives interrupts
8 * from system devices and sends them to the Interrupt Controllers.
9 *
10 * o There is one CPU Interface per CPU, which sends interrupts sent
11 * by the Distributor, and interrupts generated locally, to the
12 * associated CPU. The base address of the CPU interface is usually
13 * aliased so that the same address points to different chips depending
14 * on the CPU it is accessed from.
15 *
16 * Note that IRQs 0-31 are special - they are local to each CPU.
17 * As such, the enable set/clear, pending set/clear and active bit
18 * registers are banked per-cpu for these sources.
19 */
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/smp.h>
26 #include <linux/cpu.h>
27 #include <linux/cpu_pm.h>
28 #include <linux/cpumask.h>
29 #include <linux/io.h>
30 #include <linux/of.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/acpi.h>
34 #include <linux/irqdomain.h>
35 #include <linux/interrupt.h>
36 #include <linux/percpu.h>
37 #include <linux/slab.h>
38 #include <linux/syscore_ops.h>
39 #include <linux/irqchip.h>
40 #include <linux/irqchip/chained_irq.h>
41 #include <linux/irqchip/arm-gic.h>
42 #include <trace/hooks/gic.h>
43
44 #include <asm/cputype.h>
45 #include <asm/irq.h>
46 #include <asm/exception.h>
47 #include <asm/smp_plat.h>
48 #include <asm/virt.h>
49
50 #include "irq-gic-common.h"
51
52 #ifdef CONFIG_ARM64
53 #include <asm/cpufeature.h>
54
gic_check_cpu_features(void)55 static void gic_check_cpu_features(void)
56 {
57 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
58 TAINT_CPU_OUT_OF_SPEC,
59 "GICv3 system registers enabled, broken firmware!\n");
60 }
61 #else
62 #define gic_check_cpu_features() do { } while(0)
63 #endif
64
65 union gic_base {
66 void __iomem *common_base;
67 void __percpu * __iomem *percpu_base;
68 };
69
70 struct gic_chip_data {
71 struct irq_chip chip;
72 union gic_base dist_base;
73 union gic_base cpu_base;
74 void __iomem *raw_dist_base;
75 void __iomem *raw_cpu_base;
76 u32 percpu_offset;
77 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
78 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
79 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
80 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
81 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
82 u32 __percpu *saved_ppi_enable;
83 u32 __percpu *saved_ppi_active;
84 u32 __percpu *saved_ppi_conf;
85 #endif
86 struct irq_domain *domain;
87 unsigned int gic_irqs;
88 };
89
90 #ifdef CONFIG_BL_SWITCHER
91
92 static DEFINE_RAW_SPINLOCK(cpu_map_lock);
93
94 #define gic_lock_irqsave(f) \
95 raw_spin_lock_irqsave(&cpu_map_lock, (f))
96 #define gic_unlock_irqrestore(f) \
97 raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
98
99 #define gic_lock() raw_spin_lock(&cpu_map_lock)
100 #define gic_unlock() raw_spin_unlock(&cpu_map_lock)
101
102 #else
103
104 #define gic_lock_irqsave(f) do { (void)(f); } while(0)
105 #define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
106
107 #define gic_lock() do { } while(0)
108 #define gic_unlock() do { } while(0)
109
110 #endif
111
112 static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
113
114 /*
115 * The GIC mapping of CPU interfaces does not necessarily match
116 * the logical CPU numbering. Let's use a mapping as returned
117 * by the GIC itself.
118 */
119 #define NR_GIC_CPU_IF 8
120 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
121
122 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
123
124 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
125
126 static struct gic_kvm_info gic_v2_kvm_info __initdata;
127
128 static DEFINE_PER_CPU(u32, sgi_intid);
129
130 #ifdef CONFIG_GIC_NON_BANKED
131 static DEFINE_STATIC_KEY_FALSE(frankengic_key);
132
enable_frankengic(void)133 static void enable_frankengic(void)
134 {
135 static_branch_enable(&frankengic_key);
136 }
137
__get_base(union gic_base * base)138 static inline void __iomem *__get_base(union gic_base *base)
139 {
140 if (static_branch_unlikely(&frankengic_key))
141 return raw_cpu_read(*base->percpu_base);
142
143 return base->common_base;
144 }
145
146 #define gic_data_dist_base(d) __get_base(&(d)->dist_base)
147 #define gic_data_cpu_base(d) __get_base(&(d)->cpu_base)
148 #else
149 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
150 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
151 #define enable_frankengic() do { } while(0)
152 #endif
153
gic_dist_base(struct irq_data * d)154 static inline void __iomem *gic_dist_base(struct irq_data *d)
155 {
156 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
157 return gic_data_dist_base(gic_data);
158 }
159
gic_cpu_base(struct irq_data * d)160 static inline void __iomem *gic_cpu_base(struct irq_data *d)
161 {
162 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
163 return gic_data_cpu_base(gic_data);
164 }
165
gic_irq(struct irq_data * d)166 static inline unsigned int gic_irq(struct irq_data *d)
167 {
168 return d->hwirq;
169 }
170
cascading_gic_irq(struct irq_data * d)171 static inline bool cascading_gic_irq(struct irq_data *d)
172 {
173 void *data = irq_data_get_irq_handler_data(d);
174
175 /*
176 * If handler_data is set, this is a cascading interrupt, and
177 * it cannot possibly be forwarded.
178 */
179 return data != NULL;
180 }
181
182 /*
183 * Routines to acknowledge, disable and enable interrupts
184 */
gic_poke_irq(struct irq_data * d,u32 offset)185 static void gic_poke_irq(struct irq_data *d, u32 offset)
186 {
187 u32 mask = 1 << (gic_irq(d) % 32);
188 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
189 }
190
gic_peek_irq(struct irq_data * d,u32 offset)191 static int gic_peek_irq(struct irq_data *d, u32 offset)
192 {
193 u32 mask = 1 << (gic_irq(d) % 32);
194 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
195 }
196
gic_mask_irq(struct irq_data * d)197 static void gic_mask_irq(struct irq_data *d)
198 {
199 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
200 }
201
gic_eoimode1_mask_irq(struct irq_data * d)202 static void gic_eoimode1_mask_irq(struct irq_data *d)
203 {
204 gic_mask_irq(d);
205 /*
206 * When masking a forwarded interrupt, make sure it is
207 * deactivated as well.
208 *
209 * This ensures that an interrupt that is getting
210 * disabled/masked will not get "stuck", because there is
211 * noone to deactivate it (guest is being terminated).
212 */
213 if (irqd_is_forwarded_to_vcpu(d))
214 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
215 }
216
gic_unmask_irq(struct irq_data * d)217 static void gic_unmask_irq(struct irq_data *d)
218 {
219 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
220 }
221
gic_eoi_irq(struct irq_data * d)222 static void gic_eoi_irq(struct irq_data *d)
223 {
224 u32 hwirq = gic_irq(d);
225
226 if (hwirq < 16)
227 hwirq = this_cpu_read(sgi_intid);
228
229 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
230 }
231
gic_eoimode1_eoi_irq(struct irq_data * d)232 static void gic_eoimode1_eoi_irq(struct irq_data *d)
233 {
234 u32 hwirq = gic_irq(d);
235
236 /* Do not deactivate an IRQ forwarded to a vcpu. */
237 if (irqd_is_forwarded_to_vcpu(d))
238 return;
239
240 if (hwirq < 16)
241 hwirq = this_cpu_read(sgi_intid);
242
243 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
244 }
245
gic_irq_set_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool val)246 static int gic_irq_set_irqchip_state(struct irq_data *d,
247 enum irqchip_irq_state which, bool val)
248 {
249 u32 reg;
250
251 switch (which) {
252 case IRQCHIP_STATE_PENDING:
253 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
254 break;
255
256 case IRQCHIP_STATE_ACTIVE:
257 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
258 break;
259
260 case IRQCHIP_STATE_MASKED:
261 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
262 break;
263
264 default:
265 return -EINVAL;
266 }
267
268 gic_poke_irq(d, reg);
269 return 0;
270 }
271
gic_irq_get_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool * val)272 static int gic_irq_get_irqchip_state(struct irq_data *d,
273 enum irqchip_irq_state which, bool *val)
274 {
275 switch (which) {
276 case IRQCHIP_STATE_PENDING:
277 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
278 break;
279
280 case IRQCHIP_STATE_ACTIVE:
281 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
282 break;
283
284 case IRQCHIP_STATE_MASKED:
285 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
286 break;
287
288 default:
289 return -EINVAL;
290 }
291
292 return 0;
293 }
294
gic_set_type(struct irq_data * d,unsigned int type)295 static int gic_set_type(struct irq_data *d, unsigned int type)
296 {
297 void __iomem *base = gic_dist_base(d);
298 unsigned int gicirq = gic_irq(d);
299 int ret;
300
301 /* Interrupt configuration for SGIs can't be changed */
302 if (gicirq < 16)
303 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
304
305 /* SPIs have restrictions on the supported types */
306 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
307 type != IRQ_TYPE_EDGE_RISING)
308 return -EINVAL;
309
310 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
311 if (ret && gicirq < 32) {
312 /* Misconfigured PPIs are usually not fatal */
313 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
314 ret = 0;
315 }
316
317 return ret;
318 }
319
gic_irq_set_vcpu_affinity(struct irq_data * d,void * vcpu)320 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
321 {
322 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
323 if (cascading_gic_irq(d) || gic_irq(d) < 16)
324 return -EINVAL;
325
326 if (vcpu)
327 irqd_set_forwarded_to_vcpu(d);
328 else
329 irqd_clr_forwarded_to_vcpu(d);
330 return 0;
331 }
332
gic_retrigger(struct irq_data * data)333 static int gic_retrigger(struct irq_data *data)
334 {
335 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
336 }
337
gic_handle_irq(struct pt_regs * regs)338 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
339 {
340 u32 irqstat, irqnr;
341 struct gic_chip_data *gic = &gic_data[0];
342 void __iomem *cpu_base = gic_data_cpu_base(gic);
343
344 do {
345 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
346 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
347
348 if (unlikely(irqnr >= 1020))
349 break;
350
351 if (static_branch_likely(&supports_deactivate_key))
352 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
353 isb();
354
355 /*
356 * Ensure any shared data written by the CPU sending the IPI
357 * is read after we've read the ACK register on the GIC.
358 *
359 * Pairs with the write barrier in gic_ipi_send_mask
360 */
361 if (irqnr <= 15) {
362 smp_rmb();
363
364 /*
365 * The GIC encodes the source CPU in GICC_IAR,
366 * leading to the deactivation to fail if not
367 * written back as is to GICC_EOI. Stash the INTID
368 * away for gic_eoi_irq() to write back. This only
369 * works because we don't nest SGIs...
370 */
371 this_cpu_write(sgi_intid, irqstat);
372 }
373
374 handle_domain_irq(gic->domain, irqnr, regs);
375 } while (1);
376 }
377
gic_handle_cascade_irq(struct irq_desc * desc)378 static void gic_handle_cascade_irq(struct irq_desc *desc)
379 {
380 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
381 struct irq_chip *chip = irq_desc_get_chip(desc);
382 unsigned int gic_irq;
383 unsigned long status;
384 int ret;
385
386 chained_irq_enter(chip, desc);
387
388 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
389
390 gic_irq = (status & GICC_IAR_INT_ID_MASK);
391 if (gic_irq == GICC_INT_SPURIOUS)
392 goto out;
393
394 isb();
395 ret = generic_handle_domain_irq(chip_data->domain, gic_irq);
396 if (unlikely(ret))
397 handle_bad_irq(desc);
398 out:
399 chained_irq_exit(chip, desc);
400 }
401
402 #ifdef CONFIG_PM
gic_v2_resume(void)403 void gic_v2_resume(void)
404 {
405 trace_android_vh_gic_v2_resume(gic_data[0].domain, gic_data_dist_base(&gic_data[0]));
406 }
407 EXPORT_SYMBOL_GPL(gic_v2_resume);
408
409 static struct syscore_ops gic_v2_syscore_ops = {
410 .resume = gic_v2_resume,
411 };
412
gic_v2_syscore_init(void)413 static void gic_v2_syscore_init(void)
414 {
415 register_syscore_ops(&gic_v2_syscore_ops);
416 }
417
418 #else
gic_v2_syscore_init(void)419 static inline void gic_v2_syscore_init(void) { }
gic_v2_resume(void)420 void gic_v2_resume(void) { }
421 #endif
422
423 static const struct irq_chip gic_chip = {
424 .irq_mask = gic_mask_irq,
425 .irq_unmask = gic_unmask_irq,
426 .irq_eoi = gic_eoi_irq,
427 .irq_set_type = gic_set_type,
428 .irq_retrigger = gic_retrigger,
429 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
430 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
431 .flags = IRQCHIP_SET_TYPE_MASKED |
432 IRQCHIP_SKIP_SET_WAKE |
433 IRQCHIP_MASK_ON_SUSPEND,
434 };
435
gic_cascade_irq(unsigned int gic_nr,unsigned int irq)436 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
437 {
438 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
439 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
440 &gic_data[gic_nr]);
441 }
442
gic_get_cpumask(struct gic_chip_data * gic)443 static u8 gic_get_cpumask(struct gic_chip_data *gic)
444 {
445 void __iomem *base = gic_data_dist_base(gic);
446 u32 mask, i;
447
448 for (i = mask = 0; i < 32; i += 4) {
449 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
450 mask |= mask >> 16;
451 mask |= mask >> 8;
452 if (mask)
453 break;
454 }
455
456 if (!mask && num_possible_cpus() > 1)
457 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
458
459 return mask;
460 }
461
gic_check_gicv2(void __iomem * base)462 static bool gic_check_gicv2(void __iomem *base)
463 {
464 u32 val = readl_relaxed(base + GIC_CPU_IDENT);
465 return (val & 0xff0fff) == 0x02043B;
466 }
467
gic_cpu_if_up(struct gic_chip_data * gic)468 static void gic_cpu_if_up(struct gic_chip_data *gic)
469 {
470 void __iomem *cpu_base = gic_data_cpu_base(gic);
471 u32 bypass = 0;
472 u32 mode = 0;
473 int i;
474
475 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
476 mode = GIC_CPU_CTRL_EOImodeNS;
477
478 if (gic_check_gicv2(cpu_base))
479 for (i = 0; i < 4; i++)
480 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
481
482 /*
483 * Preserve bypass disable bits to be written back later
484 */
485 bypass = readl(cpu_base + GIC_CPU_CTRL);
486 bypass &= GICC_DIS_BYPASS_MASK;
487
488 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
489 }
490
491
gic_dist_init(struct gic_chip_data * gic)492 static void gic_dist_init(struct gic_chip_data *gic)
493 {
494 unsigned int i;
495 u32 cpumask;
496 unsigned int gic_irqs = gic->gic_irqs;
497 void __iomem *base = gic_data_dist_base(gic);
498
499 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
500
501 /*
502 * Set all global interrupts to this CPU only.
503 */
504 cpumask = gic_get_cpumask(gic);
505 cpumask |= cpumask << 8;
506 cpumask |= cpumask << 16;
507 for (i = 32; i < gic_irqs; i += 4)
508 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
509
510 gic_dist_config(base, gic_irqs, NULL);
511
512 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
513 }
514
gic_cpu_init(struct gic_chip_data * gic)515 static int gic_cpu_init(struct gic_chip_data *gic)
516 {
517 void __iomem *dist_base = gic_data_dist_base(gic);
518 void __iomem *base = gic_data_cpu_base(gic);
519 unsigned int cpu_mask, cpu = smp_processor_id();
520 int i;
521
522 /*
523 * Setting up the CPU map is only relevant for the primary GIC
524 * because any nested/secondary GICs do not directly interface
525 * with the CPU(s).
526 */
527 if (gic == &gic_data[0]) {
528 /*
529 * Get what the GIC says our CPU mask is.
530 */
531 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
532 return -EINVAL;
533
534 gic_check_cpu_features();
535 cpu_mask = gic_get_cpumask(gic);
536 gic_cpu_map[cpu] = cpu_mask;
537
538 /*
539 * Clear our mask from the other map entries in case they're
540 * still undefined.
541 */
542 for (i = 0; i < NR_GIC_CPU_IF; i++)
543 if (i != cpu)
544 gic_cpu_map[i] &= ~cpu_mask;
545 }
546
547 gic_cpu_config(dist_base, 32, NULL);
548
549 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
550 gic_cpu_if_up(gic);
551
552 return 0;
553 }
554
gic_cpu_if_down(unsigned int gic_nr)555 int gic_cpu_if_down(unsigned int gic_nr)
556 {
557 void __iomem *cpu_base;
558 u32 val = 0;
559
560 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
561 return -EINVAL;
562
563 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
564 val = readl(cpu_base + GIC_CPU_CTRL);
565 val &= ~GICC_ENABLE;
566 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
567
568 return 0;
569 }
570
571 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
572 /*
573 * Saves the GIC distributor registers during suspend or idle. Must be called
574 * with interrupts disabled but before powering down the GIC. After calling
575 * this function, no interrupts will be delivered by the GIC, and another
576 * platform-specific wakeup source must be enabled.
577 */
gic_dist_save(struct gic_chip_data * gic)578 void gic_dist_save(struct gic_chip_data *gic)
579 {
580 unsigned int gic_irqs;
581 void __iomem *dist_base;
582 int i;
583
584 if (WARN_ON(!gic))
585 return;
586
587 gic_irqs = gic->gic_irqs;
588 dist_base = gic_data_dist_base(gic);
589
590 if (!dist_base)
591 return;
592
593 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
594 gic->saved_spi_conf[i] =
595 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
596
597 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
598 gic->saved_spi_target[i] =
599 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
600
601 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
602 gic->saved_spi_enable[i] =
603 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
604
605 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
606 gic->saved_spi_active[i] =
607 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
608 }
609
610 /*
611 * Restores the GIC distributor registers during resume or when coming out of
612 * idle. Must be called before enabling interrupts. If a level interrupt
613 * that occurred while the GIC was suspended is still present, it will be
614 * handled normally, but any edge interrupts that occurred will not be seen by
615 * the GIC and need to be handled by the platform-specific wakeup source.
616 */
gic_dist_restore(struct gic_chip_data * gic)617 void gic_dist_restore(struct gic_chip_data *gic)
618 {
619 unsigned int gic_irqs;
620 unsigned int i;
621 void __iomem *dist_base;
622
623 if (WARN_ON(!gic))
624 return;
625
626 gic_irqs = gic->gic_irqs;
627 dist_base = gic_data_dist_base(gic);
628
629 if (!dist_base)
630 return;
631
632 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
633
634 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
635 writel_relaxed(gic->saved_spi_conf[i],
636 dist_base + GIC_DIST_CONFIG + i * 4);
637
638 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
639 writel_relaxed(GICD_INT_DEF_PRI_X4,
640 dist_base + GIC_DIST_PRI + i * 4);
641
642 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
643 writel_relaxed(gic->saved_spi_target[i],
644 dist_base + GIC_DIST_TARGET + i * 4);
645
646 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
647 writel_relaxed(GICD_INT_EN_CLR_X32,
648 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
649 writel_relaxed(gic->saved_spi_enable[i],
650 dist_base + GIC_DIST_ENABLE_SET + i * 4);
651 }
652
653 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
654 writel_relaxed(GICD_INT_EN_CLR_X32,
655 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
656 writel_relaxed(gic->saved_spi_active[i],
657 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
658 }
659
660 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
661 }
662
gic_cpu_save(struct gic_chip_data * gic)663 void gic_cpu_save(struct gic_chip_data *gic)
664 {
665 int i;
666 u32 *ptr;
667 void __iomem *dist_base;
668 void __iomem *cpu_base;
669
670 if (WARN_ON(!gic))
671 return;
672
673 dist_base = gic_data_dist_base(gic);
674 cpu_base = gic_data_cpu_base(gic);
675
676 if (!dist_base || !cpu_base)
677 return;
678
679 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
680 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
681 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
682
683 ptr = raw_cpu_ptr(gic->saved_ppi_active);
684 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
685 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
686
687 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
688 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
689 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
690
691 }
692
gic_cpu_restore(struct gic_chip_data * gic)693 void gic_cpu_restore(struct gic_chip_data *gic)
694 {
695 int i;
696 u32 *ptr;
697 void __iomem *dist_base;
698 void __iomem *cpu_base;
699
700 if (WARN_ON(!gic))
701 return;
702
703 dist_base = gic_data_dist_base(gic);
704 cpu_base = gic_data_cpu_base(gic);
705
706 if (!dist_base || !cpu_base)
707 return;
708
709 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
710 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
711 writel_relaxed(GICD_INT_EN_CLR_X32,
712 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
713 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
714 }
715
716 ptr = raw_cpu_ptr(gic->saved_ppi_active);
717 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
718 writel_relaxed(GICD_INT_EN_CLR_X32,
719 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
720 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
721 }
722
723 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
724 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
725 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
726
727 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
728 writel_relaxed(GICD_INT_DEF_PRI_X4,
729 dist_base + GIC_DIST_PRI + i * 4);
730
731 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
732 gic_cpu_if_up(gic);
733 }
734
gic_notifier(struct notifier_block * self,unsigned long cmd,void * v)735 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
736 {
737 int i;
738
739 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
740 switch (cmd) {
741 case CPU_PM_ENTER:
742 gic_cpu_save(&gic_data[i]);
743 break;
744 case CPU_PM_ENTER_FAILED:
745 case CPU_PM_EXIT:
746 gic_cpu_restore(&gic_data[i]);
747 break;
748 case CPU_CLUSTER_PM_ENTER:
749 gic_dist_save(&gic_data[i]);
750 break;
751 case CPU_CLUSTER_PM_ENTER_FAILED:
752 case CPU_CLUSTER_PM_EXIT:
753 gic_dist_restore(&gic_data[i]);
754 break;
755 }
756 }
757
758 return NOTIFY_OK;
759 }
760
761 static struct notifier_block gic_notifier_block = {
762 .notifier_call = gic_notifier,
763 };
764
gic_pm_init(struct gic_chip_data * gic)765 static int gic_pm_init(struct gic_chip_data *gic)
766 {
767 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
768 sizeof(u32));
769 if (WARN_ON(!gic->saved_ppi_enable))
770 return -ENOMEM;
771
772 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
773 sizeof(u32));
774 if (WARN_ON(!gic->saved_ppi_active))
775 goto free_ppi_enable;
776
777 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
778 sizeof(u32));
779 if (WARN_ON(!gic->saved_ppi_conf))
780 goto free_ppi_active;
781
782 if (gic == &gic_data[0])
783 cpu_pm_register_notifier(&gic_notifier_block);
784
785 return 0;
786
787 free_ppi_active:
788 free_percpu(gic->saved_ppi_active);
789 free_ppi_enable:
790 free_percpu(gic->saved_ppi_enable);
791
792 return -ENOMEM;
793 }
794 #else
gic_pm_init(struct gic_chip_data * gic)795 static int gic_pm_init(struct gic_chip_data *gic)
796 {
797 return 0;
798 }
799 #endif
800
801 #ifdef CONFIG_SMP
rmw_writeb(u8 bval,void __iomem * addr)802 static void rmw_writeb(u8 bval, void __iomem *addr)
803 {
804 static DEFINE_RAW_SPINLOCK(rmw_lock);
805 unsigned long offset = (unsigned long)addr & 3UL;
806 unsigned long shift = offset * 8;
807 unsigned long flags;
808 u32 val;
809
810 raw_spin_lock_irqsave(&rmw_lock, flags);
811
812 addr -= offset;
813 val = readl_relaxed(addr);
814 val &= ~GENMASK(shift + 7, shift);
815 val |= bval << shift;
816 writel_relaxed(val, addr);
817
818 raw_spin_unlock_irqrestore(&rmw_lock, flags);
819 }
820
gic_set_affinity(struct irq_data * d,const struct cpumask * mask_val,bool force)821 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
822 bool force)
823 {
824 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
825 unsigned int cpu;
826
827 if (!force)
828 cpu = cpumask_any_and(mask_val, cpu_online_mask);
829 else
830 cpu = cpumask_first(mask_val);
831
832 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
833 return -EINVAL;
834
835 if (static_branch_unlikely(&needs_rmw_access))
836 rmw_writeb(gic_cpu_map[cpu], reg);
837 else
838 writeb_relaxed(gic_cpu_map[cpu], reg);
839 irq_data_update_effective_affinity(d, cpumask_of(cpu));
840
841 trace_android_vh_gic_set_affinity(d, mask_val, force, gic_cpu_map, reg);
842
843 return IRQ_SET_MASK_OK_DONE;
844 }
845
gic_ipi_send_mask(struct irq_data * d,const struct cpumask * mask)846 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
847 {
848 int cpu;
849 unsigned long flags, map = 0;
850
851 if (unlikely(nr_cpu_ids == 1)) {
852 /* Only one CPU? let's do a self-IPI... */
853 writel_relaxed(2 << 24 | d->hwirq,
854 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
855 return;
856 }
857
858 gic_lock_irqsave(flags);
859
860 /* Convert our logical CPU mask into a physical one. */
861 for_each_cpu(cpu, mask)
862 map |= gic_cpu_map[cpu];
863
864 /*
865 * Ensure that stores to Normal memory are visible to the
866 * other CPUs before they observe us issuing the IPI.
867 */
868 dmb(ishst);
869
870 /* this always happens on GIC0 */
871 writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
872
873 gic_unlock_irqrestore(flags);
874 }
875
gic_starting_cpu(unsigned int cpu)876 static int gic_starting_cpu(unsigned int cpu)
877 {
878 gic_cpu_init(&gic_data[0]);
879 return 0;
880 }
881
gic_smp_init(void)882 static __init void gic_smp_init(void)
883 {
884 struct irq_fwspec sgi_fwspec = {
885 .fwnode = gic_data[0].domain->fwnode,
886 .param_count = 1,
887 };
888 int base_sgi;
889
890 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
891 "irqchip/arm/gic:starting",
892 gic_starting_cpu, NULL);
893
894 base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8,
895 NUMA_NO_NODE, &sgi_fwspec,
896 false, NULL);
897 if (WARN_ON(base_sgi <= 0))
898 return;
899
900 set_smp_ipi_range(base_sgi, 8);
901 }
902 #else
903 #define gic_smp_init() do { } while(0)
904 #define gic_set_affinity NULL
905 #define gic_ipi_send_mask NULL
906 #endif
907
908 #ifdef CONFIG_BL_SWITCHER
909 /*
910 * gic_send_sgi - send a SGI directly to given CPU interface number
911 *
912 * cpu_id: the ID for the destination CPU interface
913 * irq: the IPI number to send a SGI for
914 */
gic_send_sgi(unsigned int cpu_id,unsigned int irq)915 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
916 {
917 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
918 cpu_id = 1 << cpu_id;
919 /* this always happens on GIC0 */
920 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
921 }
922
923 /*
924 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
925 *
926 * @cpu: the logical CPU number to get the GIC ID for.
927 *
928 * Return the CPU interface ID for the given logical CPU number,
929 * or -1 if the CPU number is too large or the interface ID is
930 * unknown (more than one bit set).
931 */
gic_get_cpu_id(unsigned int cpu)932 int gic_get_cpu_id(unsigned int cpu)
933 {
934 unsigned int cpu_bit;
935
936 if (cpu >= NR_GIC_CPU_IF)
937 return -1;
938 cpu_bit = gic_cpu_map[cpu];
939 if (cpu_bit & (cpu_bit - 1))
940 return -1;
941 return __ffs(cpu_bit);
942 }
943
944 /*
945 * gic_migrate_target - migrate IRQs to another CPU interface
946 *
947 * @new_cpu_id: the CPU target ID to migrate IRQs to
948 *
949 * Migrate all peripheral interrupts with a target matching the current CPU
950 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
951 * is also updated. Targets to other CPU interfaces are unchanged.
952 * This must be called with IRQs locally disabled.
953 */
gic_migrate_target(unsigned int new_cpu_id)954 void gic_migrate_target(unsigned int new_cpu_id)
955 {
956 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
957 void __iomem *dist_base;
958 int i, ror_val, cpu = smp_processor_id();
959 u32 val, cur_target_mask, active_mask;
960
961 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
962
963 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
964 if (!dist_base)
965 return;
966 gic_irqs = gic_data[gic_nr].gic_irqs;
967
968 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
969 cur_target_mask = 0x01010101 << cur_cpu_id;
970 ror_val = (cur_cpu_id - new_cpu_id) & 31;
971
972 gic_lock();
973
974 /* Update the target interface for this logical CPU */
975 gic_cpu_map[cpu] = 1 << new_cpu_id;
976
977 /*
978 * Find all the peripheral interrupts targeting the current
979 * CPU interface and migrate them to the new CPU interface.
980 * We skip DIST_TARGET 0 to 7 as they are read-only.
981 */
982 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
983 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
984 active_mask = val & cur_target_mask;
985 if (active_mask) {
986 val &= ~active_mask;
987 val |= ror32(active_mask, ror_val);
988 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
989 }
990 }
991
992 gic_unlock();
993
994 /*
995 * Now let's migrate and clear any potential SGIs that might be
996 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
997 * is a banked register, we can only forward the SGI using
998 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
999 * doesn't use that information anyway.
1000 *
1001 * For the same reason we do not adjust SGI source information
1002 * for previously sent SGIs by us to other CPUs either.
1003 */
1004 for (i = 0; i < 16; i += 4) {
1005 int j;
1006 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
1007 if (!val)
1008 continue;
1009 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
1010 for (j = i; j < i + 4; j++) {
1011 if (val & 0xff)
1012 writel_relaxed((1 << (new_cpu_id + 16)) | j,
1013 dist_base + GIC_DIST_SOFTINT);
1014 val >>= 8;
1015 }
1016 }
1017 }
1018
1019 /*
1020 * gic_get_sgir_physaddr - get the physical address for the SGI register
1021 *
1022 * Return the physical address of the SGI register to be used
1023 * by some early assembly code when the kernel is not yet available.
1024 */
1025 static unsigned long gic_dist_physaddr;
1026
gic_get_sgir_physaddr(void)1027 unsigned long gic_get_sgir_physaddr(void)
1028 {
1029 if (!gic_dist_physaddr)
1030 return 0;
1031 return gic_dist_physaddr + GIC_DIST_SOFTINT;
1032 }
1033
gic_init_physaddr(struct device_node * node)1034 static void __init gic_init_physaddr(struct device_node *node)
1035 {
1036 struct resource res;
1037 if (of_address_to_resource(node, 0, &res) == 0) {
1038 gic_dist_physaddr = res.start;
1039 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
1040 }
1041 }
1042
1043 #else
1044 #define gic_init_physaddr(node) do { } while (0)
1045 #endif
1046
gic_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)1047 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1048 irq_hw_number_t hw)
1049 {
1050 struct gic_chip_data *gic = d->host_data;
1051 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1052
1053 switch (hw) {
1054 case 0 ... 31:
1055 irq_set_percpu_devid(irq);
1056 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1057 handle_percpu_devid_irq, NULL, NULL);
1058 break;
1059 default:
1060 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1061 handle_fasteoi_irq, NULL, NULL);
1062 irq_set_probe(irq);
1063 irqd_set_single_target(irqd);
1064 break;
1065 }
1066
1067 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1068 irqd_set_handle_enforce_irqctx(irqd);
1069 return 0;
1070 }
1071
gic_irq_domain_unmap(struct irq_domain * d,unsigned int irq)1072 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
1073 {
1074 }
1075
gic_irq_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1076 static int gic_irq_domain_translate(struct irq_domain *d,
1077 struct irq_fwspec *fwspec,
1078 unsigned long *hwirq,
1079 unsigned int *type)
1080 {
1081 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1082 *hwirq = fwspec->param[0];
1083 *type = IRQ_TYPE_EDGE_RISING;
1084 return 0;
1085 }
1086
1087 if (is_of_node(fwspec->fwnode)) {
1088 if (fwspec->param_count < 3)
1089 return -EINVAL;
1090
1091 switch (fwspec->param[0]) {
1092 case 0: /* SPI */
1093 *hwirq = fwspec->param[1] + 32;
1094 break;
1095 case 1: /* PPI */
1096 *hwirq = fwspec->param[1] + 16;
1097 break;
1098 default:
1099 return -EINVAL;
1100 }
1101
1102 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1103
1104 /* Make it clear that broken DTs are... broken */
1105 WARN_ON(*type == IRQ_TYPE_NONE);
1106 return 0;
1107 }
1108
1109 if (is_fwnode_irqchip(fwspec->fwnode)) {
1110 if(fwspec->param_count != 2)
1111 return -EINVAL;
1112
1113 if (fwspec->param[0] < 16) {
1114 pr_err(FW_BUG "Illegal GSI%d translation request\n",
1115 fwspec->param[0]);
1116 return -EINVAL;
1117 }
1118
1119 *hwirq = fwspec->param[0];
1120 *type = fwspec->param[1];
1121
1122 WARN_ON(*type == IRQ_TYPE_NONE);
1123 return 0;
1124 }
1125
1126 return -EINVAL;
1127 }
1128
gic_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)1129 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1130 unsigned int nr_irqs, void *arg)
1131 {
1132 int i, ret;
1133 irq_hw_number_t hwirq;
1134 unsigned int type = IRQ_TYPE_NONE;
1135 struct irq_fwspec *fwspec = arg;
1136
1137 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1138 if (ret)
1139 return ret;
1140
1141 for (i = 0; i < nr_irqs; i++) {
1142 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1143 if (ret)
1144 return ret;
1145 }
1146
1147 return 0;
1148 }
1149
1150 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1151 .translate = gic_irq_domain_translate,
1152 .alloc = gic_irq_domain_alloc,
1153 .free = irq_domain_free_irqs_top,
1154 };
1155
1156 static const struct irq_domain_ops gic_irq_domain_ops = {
1157 .map = gic_irq_domain_map,
1158 .unmap = gic_irq_domain_unmap,
1159 };
1160
gic_init_chip(struct gic_chip_data * gic,struct device * dev,const char * name,bool use_eoimode1)1161 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1162 const char *name, bool use_eoimode1)
1163 {
1164 /* Initialize irq_chip */
1165 gic->chip = gic_chip;
1166 gic->chip.name = name;
1167 gic->chip.parent_device = dev;
1168
1169 if (use_eoimode1) {
1170 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1171 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1172 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1173 }
1174
1175 if (gic == &gic_data[0]) {
1176 gic->chip.irq_set_affinity = gic_set_affinity;
1177 gic->chip.ipi_send_mask = gic_ipi_send_mask;
1178 }
1179 }
1180
gic_init_bases(struct gic_chip_data * gic,struct fwnode_handle * handle)1181 static int gic_init_bases(struct gic_chip_data *gic,
1182 struct fwnode_handle *handle)
1183 {
1184 int gic_irqs, ret;
1185
1186 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1187 /* Frankein-GIC without banked registers... */
1188 unsigned int cpu;
1189
1190 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1191 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1192 if (WARN_ON(!gic->dist_base.percpu_base ||
1193 !gic->cpu_base.percpu_base)) {
1194 ret = -ENOMEM;
1195 goto error;
1196 }
1197
1198 for_each_possible_cpu(cpu) {
1199 u32 mpidr = cpu_logical_map(cpu);
1200 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1201 unsigned long offset = gic->percpu_offset * core_id;
1202 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1203 gic->raw_dist_base + offset;
1204 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1205 gic->raw_cpu_base + offset;
1206 }
1207
1208 enable_frankengic();
1209 } else {
1210 /* Normal, sane GIC... */
1211 WARN(gic->percpu_offset,
1212 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1213 gic->percpu_offset);
1214 gic->dist_base.common_base = gic->raw_dist_base;
1215 gic->cpu_base.common_base = gic->raw_cpu_base;
1216 }
1217
1218 /*
1219 * Find out how many interrupts are supported.
1220 * The GIC only supports up to 1020 interrupt sources.
1221 */
1222 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1223 gic_irqs = (gic_irqs + 1) * 32;
1224 if (gic_irqs > 1020)
1225 gic_irqs = 1020;
1226 gic->gic_irqs = gic_irqs;
1227
1228 if (handle) { /* DT/ACPI */
1229 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1230 &gic_irq_domain_hierarchy_ops,
1231 gic);
1232 } else { /* Legacy support */
1233 /*
1234 * For primary GICs, skip over SGIs.
1235 * No secondary GIC support whatsoever.
1236 */
1237 int irq_base;
1238
1239 gic_irqs -= 16; /* calculate # of irqs to allocate */
1240
1241 irq_base = irq_alloc_descs(16, 16, gic_irqs,
1242 numa_node_id());
1243 if (irq_base < 0) {
1244 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
1245 irq_base = 16;
1246 }
1247
1248 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1249 16, &gic_irq_domain_ops, gic);
1250 }
1251
1252 if (WARN_ON(!gic->domain)) {
1253 ret = -ENODEV;
1254 goto error;
1255 }
1256
1257 gic_dist_init(gic);
1258 ret = gic_cpu_init(gic);
1259 if (ret)
1260 goto error;
1261
1262 ret = gic_pm_init(gic);
1263 if (ret)
1264 goto error;
1265
1266 gic_v2_syscore_init();
1267
1268 return 0;
1269
1270 error:
1271 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1272 free_percpu(gic->dist_base.percpu_base);
1273 free_percpu(gic->cpu_base.percpu_base);
1274 }
1275
1276 return ret;
1277 }
1278
__gic_init_bases(struct gic_chip_data * gic,struct fwnode_handle * handle)1279 static int __init __gic_init_bases(struct gic_chip_data *gic,
1280 struct fwnode_handle *handle)
1281 {
1282 char *name;
1283 int i, ret;
1284
1285 if (WARN_ON(!gic || gic->domain))
1286 return -EINVAL;
1287
1288 if (gic == &gic_data[0]) {
1289 /*
1290 * Initialize the CPU interface map to all CPUs.
1291 * It will be refined as each CPU probes its ID.
1292 * This is only necessary for the primary GIC.
1293 */
1294 for (i = 0; i < NR_GIC_CPU_IF; i++)
1295 gic_cpu_map[i] = 0xff;
1296
1297 set_handle_irq(gic_handle_irq);
1298 if (static_branch_likely(&supports_deactivate_key))
1299 pr_info("GIC: Using split EOI/Deactivate mode\n");
1300 }
1301
1302 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
1303 name = kasprintf(GFP_KERNEL, "GICv2");
1304 gic_init_chip(gic, NULL, name, true);
1305 } else {
1306 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1307 gic_init_chip(gic, NULL, name, false);
1308 }
1309
1310 ret = gic_init_bases(gic, handle);
1311 if (ret)
1312 kfree(name);
1313 else if (gic == &gic_data[0])
1314 gic_smp_init();
1315
1316 return ret;
1317 }
1318
gic_init(void __iomem * dist_base,void __iomem * cpu_base)1319 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
1320 {
1321 struct gic_chip_data *gic;
1322
1323 /*
1324 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1325 * bother with these...
1326 */
1327 static_branch_disable(&supports_deactivate_key);
1328
1329 gic = &gic_data[0];
1330 gic->raw_dist_base = dist_base;
1331 gic->raw_cpu_base = cpu_base;
1332
1333 __gic_init_bases(gic, NULL);
1334 }
1335
gic_teardown(struct gic_chip_data * gic)1336 static void gic_teardown(struct gic_chip_data *gic)
1337 {
1338 if (WARN_ON(!gic))
1339 return;
1340
1341 if (gic->raw_dist_base)
1342 iounmap(gic->raw_dist_base);
1343 if (gic->raw_cpu_base)
1344 iounmap(gic->raw_cpu_base);
1345 }
1346
1347 #ifdef CONFIG_OF
1348 static int gic_cnt __initdata;
1349 static bool gicv2_force_probe;
1350
gicv2_force_probe_cfg(char * buf)1351 static int __init gicv2_force_probe_cfg(char *buf)
1352 {
1353 return strtobool(buf, &gicv2_force_probe);
1354 }
1355 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
1356
gic_check_eoimode(struct device_node * node,void __iomem ** base)1357 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1358 {
1359 struct resource cpuif_res;
1360
1361 of_address_to_resource(node, 1, &cpuif_res);
1362
1363 if (!is_hyp_mode_available())
1364 return false;
1365 if (resource_size(&cpuif_res) < SZ_8K) {
1366 void __iomem *alt;
1367 /*
1368 * Check for a stupid firmware that only exposes the
1369 * first page of a GICv2.
1370 */
1371 if (!gic_check_gicv2(*base))
1372 return false;
1373
1374 if (!gicv2_force_probe) {
1375 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
1376 return false;
1377 }
1378
1379 alt = ioremap(cpuif_res.start, SZ_8K);
1380 if (!alt)
1381 return false;
1382 if (!gic_check_gicv2(alt + SZ_4K)) {
1383 /*
1384 * The first page was that of a GICv2, and
1385 * the second was *something*. Let's trust it
1386 * to be a GICv2, and update the mapping.
1387 */
1388 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
1389 &cpuif_res.start);
1390 iounmap(*base);
1391 *base = alt;
1392 return true;
1393 }
1394
1395 /*
1396 * We detected *two* initial GICv2 pages in a
1397 * row. Could be a GICv2 aliased over two 64kB
1398 * pages. Update the resource, map the iospace, and
1399 * pray.
1400 */
1401 iounmap(alt);
1402 alt = ioremap(cpuif_res.start, SZ_128K);
1403 if (!alt)
1404 return false;
1405 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
1406 &cpuif_res.start);
1407 cpuif_res.end = cpuif_res.start + SZ_128K -1;
1408 iounmap(*base);
1409 *base = alt;
1410 }
1411 if (resource_size(&cpuif_res) == SZ_128K) {
1412 /*
1413 * Verify that we have the first 4kB of a GICv2
1414 * aliased over the first 64kB by checking the
1415 * GICC_IIDR register on both ends.
1416 */
1417 if (!gic_check_gicv2(*base) ||
1418 !gic_check_gicv2(*base + 0xf000))
1419 return false;
1420
1421 /*
1422 * Move the base up by 60kB, so that we have a 8kB
1423 * contiguous region, which allows us to use GICC_DIR
1424 * at its normal offset. Please pass me that bucket.
1425 */
1426 *base += 0xf000;
1427 cpuif_res.start += 0xf000;
1428 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1429 &cpuif_res.start);
1430 }
1431
1432 return true;
1433 }
1434
gic_enable_rmw_access(void * data)1435 static bool gic_enable_rmw_access(void *data)
1436 {
1437 /*
1438 * The EMEV2 class of machines has a broken interconnect, and
1439 * locks up on accesses that are less than 32bit. So far, only
1440 * the affinity setting requires it.
1441 */
1442 if (of_machine_is_compatible("renesas,emev2")) {
1443 static_branch_enable(&needs_rmw_access);
1444 return true;
1445 }
1446
1447 return false;
1448 }
1449
1450 static const struct gic_quirk gic_quirks[] = {
1451 {
1452 .desc = "broken byte access",
1453 .compatible = "arm,pl390",
1454 .init = gic_enable_rmw_access,
1455 },
1456 { },
1457 };
1458
gic_of_setup(struct gic_chip_data * gic,struct device_node * node)1459 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1460 {
1461 if (!gic || !node)
1462 return -EINVAL;
1463
1464 gic->raw_dist_base = of_iomap(node, 0);
1465 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1466 goto error;
1467
1468 gic->raw_cpu_base = of_iomap(node, 1);
1469 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1470 goto error;
1471
1472 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1473 gic->percpu_offset = 0;
1474
1475 gic_enable_of_quirks(node, gic_quirks, gic);
1476
1477 return 0;
1478
1479 error:
1480 gic_teardown(gic);
1481
1482 return -ENOMEM;
1483 }
1484
gic_of_init_child(struct device * dev,struct gic_chip_data ** gic,int irq)1485 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1486 {
1487 int ret;
1488
1489 if (!dev || !dev->of_node || !gic || !irq)
1490 return -EINVAL;
1491
1492 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1493 if (!*gic)
1494 return -ENOMEM;
1495
1496 gic_init_chip(*gic, dev, dev->of_node->name, false);
1497
1498 ret = gic_of_setup(*gic, dev->of_node);
1499 if (ret)
1500 return ret;
1501
1502 ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1503 if (ret) {
1504 gic_teardown(*gic);
1505 return ret;
1506 }
1507
1508 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1509
1510 return 0;
1511 }
1512
gic_of_setup_kvm_info(struct device_node * node)1513 static void __init gic_of_setup_kvm_info(struct device_node *node)
1514 {
1515 int ret;
1516 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1517 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1518
1519 gic_v2_kvm_info.type = GIC_V2;
1520
1521 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1522 if (!gic_v2_kvm_info.maint_irq)
1523 return;
1524
1525 ret = of_address_to_resource(node, 2, vctrl_res);
1526 if (ret)
1527 return;
1528
1529 ret = of_address_to_resource(node, 3, vcpu_res);
1530 if (ret)
1531 return;
1532
1533 if (static_branch_likely(&supports_deactivate_key))
1534 vgic_set_kvm_info(&gic_v2_kvm_info);
1535 }
1536
1537 int __init
gic_of_init(struct device_node * node,struct device_node * parent)1538 gic_of_init(struct device_node *node, struct device_node *parent)
1539 {
1540 struct gic_chip_data *gic;
1541 int irq, ret;
1542
1543 if (WARN_ON(!node))
1544 return -ENODEV;
1545
1546 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1547 return -EINVAL;
1548
1549 gic = &gic_data[gic_cnt];
1550
1551 ret = gic_of_setup(gic, node);
1552 if (ret)
1553 return ret;
1554
1555 /*
1556 * Disable split EOI/Deactivate if either HYP is not available
1557 * or the CPU interface is too small.
1558 */
1559 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1560 static_branch_disable(&supports_deactivate_key);
1561
1562 ret = __gic_init_bases(gic, &node->fwnode);
1563 if (ret) {
1564 gic_teardown(gic);
1565 return ret;
1566 }
1567
1568 if (!gic_cnt) {
1569 gic_init_physaddr(node);
1570 gic_of_setup_kvm_info(node);
1571 }
1572
1573 if (parent) {
1574 irq = irq_of_parse_and_map(node, 0);
1575 gic_cascade_irq(gic_cnt, irq);
1576 }
1577
1578 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1579 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1580
1581 gic_cnt++;
1582 return 0;
1583 }
1584 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1585 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1586 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1587 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1588 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1589 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1590 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1591 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1592 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1593 #else
gic_of_init_child(struct device * dev,struct gic_chip_data ** gic,int irq)1594 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1595 {
1596 return -ENOTSUPP;
1597 }
1598 #endif
1599
1600 #ifdef CONFIG_ACPI
1601 static struct
1602 {
1603 phys_addr_t cpu_phys_base;
1604 u32 maint_irq;
1605 int maint_irq_mode;
1606 phys_addr_t vctrl_base;
1607 phys_addr_t vcpu_base;
1608 } acpi_data __initdata;
1609
1610 static int __init
gic_acpi_parse_madt_cpu(union acpi_subtable_headers * header,const unsigned long end)1611 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
1612 const unsigned long end)
1613 {
1614 struct acpi_madt_generic_interrupt *processor;
1615 phys_addr_t gic_cpu_base;
1616 static int cpu_base_assigned;
1617
1618 processor = (struct acpi_madt_generic_interrupt *)header;
1619
1620 if (BAD_MADT_GICC_ENTRY(processor, end))
1621 return -EINVAL;
1622
1623 /*
1624 * There is no support for non-banked GICv1/2 register in ACPI spec.
1625 * All CPU interface addresses have to be the same.
1626 */
1627 gic_cpu_base = processor->base_address;
1628 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1629 return -EINVAL;
1630
1631 acpi_data.cpu_phys_base = gic_cpu_base;
1632 acpi_data.maint_irq = processor->vgic_interrupt;
1633 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1634 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1635 acpi_data.vctrl_base = processor->gich_base_address;
1636 acpi_data.vcpu_base = processor->gicv_base_address;
1637
1638 cpu_base_assigned = 1;
1639 return 0;
1640 }
1641
1642 /* The things you have to do to just *count* something... */
acpi_dummy_func(union acpi_subtable_headers * header,const unsigned long end)1643 static int __init acpi_dummy_func(union acpi_subtable_headers *header,
1644 const unsigned long end)
1645 {
1646 return 0;
1647 }
1648
acpi_gic_redist_is_present(void)1649 static bool __init acpi_gic_redist_is_present(void)
1650 {
1651 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1652 acpi_dummy_func, 0) > 0;
1653 }
1654
gic_validate_dist(struct acpi_subtable_header * header,struct acpi_probe_entry * ape)1655 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1656 struct acpi_probe_entry *ape)
1657 {
1658 struct acpi_madt_generic_distributor *dist;
1659 dist = (struct acpi_madt_generic_distributor *)header;
1660
1661 return (dist->version == ape->driver_data &&
1662 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1663 !acpi_gic_redist_is_present()));
1664 }
1665
1666 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1667 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1668 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1669 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1670
gic_acpi_setup_kvm_info(void)1671 static void __init gic_acpi_setup_kvm_info(void)
1672 {
1673 int irq;
1674 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1675 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1676
1677 gic_v2_kvm_info.type = GIC_V2;
1678
1679 if (!acpi_data.vctrl_base)
1680 return;
1681
1682 vctrl_res->flags = IORESOURCE_MEM;
1683 vctrl_res->start = acpi_data.vctrl_base;
1684 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1685
1686 if (!acpi_data.vcpu_base)
1687 return;
1688
1689 vcpu_res->flags = IORESOURCE_MEM;
1690 vcpu_res->start = acpi_data.vcpu_base;
1691 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1692
1693 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1694 acpi_data.maint_irq_mode,
1695 ACPI_ACTIVE_HIGH);
1696 if (irq <= 0)
1697 return;
1698
1699 gic_v2_kvm_info.maint_irq = irq;
1700
1701 vgic_set_kvm_info(&gic_v2_kvm_info);
1702 }
1703
gic_v2_acpi_init(union acpi_subtable_headers * header,const unsigned long end)1704 static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
1705 const unsigned long end)
1706 {
1707 struct acpi_madt_generic_distributor *dist;
1708 struct fwnode_handle *domain_handle;
1709 struct gic_chip_data *gic = &gic_data[0];
1710 int count, ret;
1711
1712 /* Collect CPU base addresses */
1713 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1714 gic_acpi_parse_madt_cpu, 0);
1715 if (count <= 0) {
1716 pr_err("No valid GICC entries exist\n");
1717 return -EINVAL;
1718 }
1719
1720 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1721 if (!gic->raw_cpu_base) {
1722 pr_err("Unable to map GICC registers\n");
1723 return -ENOMEM;
1724 }
1725
1726 dist = (struct acpi_madt_generic_distributor *)header;
1727 gic->raw_dist_base = ioremap(dist->base_address,
1728 ACPI_GICV2_DIST_MEM_SIZE);
1729 if (!gic->raw_dist_base) {
1730 pr_err("Unable to map GICD registers\n");
1731 gic_teardown(gic);
1732 return -ENOMEM;
1733 }
1734
1735 /*
1736 * Disable split EOI/Deactivate if HYP is not available. ACPI
1737 * guarantees that we'll always have a GICv2, so the CPU
1738 * interface will always be the right size.
1739 */
1740 if (!is_hyp_mode_available())
1741 static_branch_disable(&supports_deactivate_key);
1742
1743 /*
1744 * Initialize GIC instance zero (no multi-GIC support).
1745 */
1746 domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
1747 if (!domain_handle) {
1748 pr_err("Unable to allocate domain handle\n");
1749 gic_teardown(gic);
1750 return -ENOMEM;
1751 }
1752
1753 ret = __gic_init_bases(gic, domain_handle);
1754 if (ret) {
1755 pr_err("Failed to initialise GIC\n");
1756 irq_domain_free_fwnode(domain_handle);
1757 gic_teardown(gic);
1758 return ret;
1759 }
1760
1761 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1762
1763 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1764 gicv2m_init(NULL, gic_data[0].domain);
1765
1766 if (static_branch_likely(&supports_deactivate_key))
1767 gic_acpi_setup_kvm_info();
1768
1769 return 0;
1770 }
1771 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1772 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1773 gic_v2_acpi_init);
1774 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1775 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1776 gic_v2_acpi_init);
1777 #endif
1778