1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
4 * Loongson Local IO Interrupt Controller support
5 */
6
7 #include <linux/errno.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/ioport.h>
12 #include <linux/irqchip.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/io.h>
16 #include <linux/smp.h>
17 #include <linux/irqchip/chained_irq.h>
18
19 #include <loongson.h>
20
21 #define LIOINTC_CHIP_IRQ 32
22 #define LIOINTC_NUM_PARENT 4
23 #define LIOINTC_NUM_CORES 4
24
25 #define LIOINTC_INTC_CHIP_START 0x20
26
27 #define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
28 #define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
29 #define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
30 #define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
31 #define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
32 #define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
33
34 #define LIOINTC_SHIFT_INTx 4
35
36 #define LIOINTC_ERRATA_IRQ 10
37
38 struct liointc_handler_data {
39 struct liointc_priv *priv;
40 u32 parent_int_map;
41 };
42
43 struct liointc_priv {
44 struct irq_chip_generic *gc;
45 struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
46 void __iomem *core_isr[LIOINTC_NUM_CORES];
47 u8 map_cache[LIOINTC_CHIP_IRQ];
48 bool has_lpc_irq_errata;
49 };
50
liointc_chained_handle_irq(struct irq_desc * desc)51 static void liointc_chained_handle_irq(struct irq_desc *desc)
52 {
53 struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
54 struct irq_chip *chip = irq_desc_get_chip(desc);
55 struct irq_chip_generic *gc = handler->priv->gc;
56 int core = get_ebase_cpunum() % LIOINTC_NUM_CORES;
57 u32 pending;
58
59 chained_irq_enter(chip, desc);
60
61 pending = readl(handler->priv->core_isr[core]);
62
63 if (!pending) {
64 /* Always blame LPC IRQ if we have that bug */
65 if (handler->priv->has_lpc_irq_errata &&
66 (handler->parent_int_map & gc->mask_cache &
67 BIT(LIOINTC_ERRATA_IRQ)))
68 pending = BIT(LIOINTC_ERRATA_IRQ);
69 else
70 spurious_interrupt();
71 }
72
73 while (pending) {
74 int bit = __ffs(pending);
75
76 generic_handle_domain_irq(gc->domain, bit);
77 pending &= ~BIT(bit);
78 }
79
80 chained_irq_exit(chip, desc);
81 }
82
liointc_set_bit(struct irq_chip_generic * gc,unsigned int offset,u32 mask,bool set)83 static void liointc_set_bit(struct irq_chip_generic *gc,
84 unsigned int offset,
85 u32 mask, bool set)
86 {
87 if (set)
88 writel(readl(gc->reg_base + offset) | mask,
89 gc->reg_base + offset);
90 else
91 writel(readl(gc->reg_base + offset) & ~mask,
92 gc->reg_base + offset);
93 }
94
liointc_set_type(struct irq_data * data,unsigned int type)95 static int liointc_set_type(struct irq_data *data, unsigned int type)
96 {
97 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
98 u32 mask = data->mask;
99 unsigned long flags;
100
101 irq_gc_lock_irqsave(gc, flags);
102 switch (type) {
103 case IRQ_TYPE_LEVEL_HIGH:
104 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
105 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
106 break;
107 case IRQ_TYPE_LEVEL_LOW:
108 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
109 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
110 break;
111 case IRQ_TYPE_EDGE_RISING:
112 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
113 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
114 break;
115 case IRQ_TYPE_EDGE_FALLING:
116 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
117 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
118 break;
119 default:
120 irq_gc_unlock_irqrestore(gc, flags);
121 return -EINVAL;
122 }
123 irq_gc_unlock_irqrestore(gc, flags);
124
125 irqd_set_trigger_type(data, type);
126 return 0;
127 }
128
liointc_resume(struct irq_chip_generic * gc)129 static void liointc_resume(struct irq_chip_generic *gc)
130 {
131 struct liointc_priv *priv = gc->private;
132 unsigned long flags;
133 int i;
134
135 irq_gc_lock_irqsave(gc, flags);
136 /* Disable all at first */
137 writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
138 /* Restore map cache */
139 for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
140 writeb(priv->map_cache[i], gc->reg_base + i);
141 /* Restore mask cache */
142 writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
143 irq_gc_unlock_irqrestore(gc, flags);
144 }
145
146 static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
147 static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
148
liointc_get_reg_byname(struct device_node * node,const char * name)149 static void __iomem *liointc_get_reg_byname(struct device_node *node,
150 const char *name)
151 {
152 int index = of_property_match_string(node, "reg-names", name);
153
154 if (index < 0)
155 return NULL;
156
157 return of_iomap(node, index);
158 }
159
liointc_of_init(struct device_node * node,struct device_node * parent)160 static int __init liointc_of_init(struct device_node *node,
161 struct device_node *parent)
162 {
163 struct irq_chip_generic *gc;
164 struct irq_domain *domain;
165 struct irq_chip_type *ct;
166 struct liointc_priv *priv;
167 void __iomem *base;
168 u32 of_parent_int_map[LIOINTC_NUM_PARENT];
169 int parent_irq[LIOINTC_NUM_PARENT];
170 bool have_parent = FALSE;
171 int sz, i, err = 0;
172
173 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
174 if (!priv)
175 return -ENOMEM;
176
177 if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
178 base = liointc_get_reg_byname(node, "main");
179 if (!base) {
180 err = -ENODEV;
181 goto out_free_priv;
182 }
183
184 for (i = 0; i < LIOINTC_NUM_CORES; i++)
185 priv->core_isr[i] = liointc_get_reg_byname(node, core_reg_names[i]);
186 if (!priv->core_isr[0]) {
187 err = -ENODEV;
188 goto out_iounmap_base;
189 }
190 } else {
191 base = of_iomap(node, 0);
192 if (!base) {
193 err = -ENODEV;
194 goto out_free_priv;
195 }
196
197 for (i = 0; i < LIOINTC_NUM_CORES; i++)
198 priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
199 }
200
201 for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
202 parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
203 if (parent_irq[i] > 0)
204 have_parent = TRUE;
205 }
206 if (!have_parent) {
207 err = -ENODEV;
208 goto out_iounmap_isr;
209 }
210
211 sz = of_property_read_variable_u32_array(node,
212 "loongson,parent_int_map",
213 &of_parent_int_map[0],
214 LIOINTC_NUM_PARENT,
215 LIOINTC_NUM_PARENT);
216 if (sz < 4) {
217 pr_err("loongson-liointc: No parent_int_map\n");
218 err = -ENODEV;
219 goto out_iounmap_isr;
220 }
221
222 for (i = 0; i < LIOINTC_NUM_PARENT; i++)
223 priv->handler[i].parent_int_map = of_parent_int_map[i];
224
225 /* Setup IRQ domain */
226 domain = irq_domain_add_linear(node, 32,
227 &irq_generic_chip_ops, priv);
228 if (!domain) {
229 pr_err("loongson-liointc: cannot add IRQ domain\n");
230 err = -EINVAL;
231 goto out_iounmap_isr;
232 }
233
234 err = irq_alloc_domain_generic_chips(domain, 32, 1,
235 node->full_name, handle_level_irq,
236 IRQ_NOPROBE, 0, 0);
237 if (err) {
238 pr_err("loongson-liointc: unable to register IRQ domain\n");
239 goto out_free_domain;
240 }
241
242
243 /* Disable all IRQs */
244 writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
245 /* Set to level triggered */
246 writel(0x0, base + LIOINTC_REG_INTC_EDGE);
247
248 /* Generate parent INT part of map cache */
249 for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
250 u32 pending = priv->handler[i].parent_int_map;
251
252 while (pending) {
253 int bit = __ffs(pending);
254
255 priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
256 pending &= ~BIT(bit);
257 }
258 }
259
260 for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
261 /* Generate core part of map cache */
262 priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
263 writeb(priv->map_cache[i], base + i);
264 }
265
266 gc = irq_get_domain_generic_chip(domain, 0);
267 gc->private = priv;
268 gc->reg_base = base;
269 gc->domain = domain;
270 gc->resume = liointc_resume;
271
272 ct = gc->chip_types;
273 ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
274 ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
275 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
276 ct->chip.irq_mask = irq_gc_mask_disable_reg;
277 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
278 ct->chip.irq_set_type = liointc_set_type;
279
280 gc->mask_cache = 0;
281 priv->gc = gc;
282
283 for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
284 if (parent_irq[i] <= 0)
285 continue;
286
287 priv->handler[i].priv = priv;
288 irq_set_chained_handler_and_data(parent_irq[i],
289 liointc_chained_handle_irq, &priv->handler[i]);
290 }
291
292 return 0;
293
294 out_free_domain:
295 irq_domain_remove(domain);
296 out_iounmap_isr:
297 for (i = 0; i < LIOINTC_NUM_CORES; i++) {
298 if (!priv->core_isr[i])
299 continue;
300 iounmap(priv->core_isr[i]);
301 }
302 out_iounmap_base:
303 iounmap(base);
304 out_free_priv:
305 kfree(priv);
306
307 return err;
308 }
309
310 IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
311 IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
312 IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
313