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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Driver for SiliconFile SR030PC30 VGA (1/10-Inch) Image Sensor with ISP
4  *
5  * Copyright (C) 2010 Samsung Electronics Co., Ltd
6  * Author: Sylwester Nawrocki, s.nawrocki@samsung.com
7  *
8  * Based on original driver authored by Dongsoo Nathaniel Kim
9  * and HeungJun Kim <riverful.kim@samsung.com>.
10  *
11  * Based on mt9v011 Micron Digital Image Sensor driver
12  * Copyright (c) 2009 Mauro Carvalho Chehab
13  */
14 
15 #include <linux/i2c.h>
16 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-subdev.h>
21 #include <media/v4l2-mediabus.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/i2c/sr030pc30.h>
24 
25 static int debug;
26 module_param(debug, int, 0644);
27 
28 #define MODULE_NAME	"SR030PC30"
29 
30 /*
31  * Register offsets within a page
32  * b15..b8 - page id, b7..b0 - register address
33  */
34 #define POWER_CTRL_REG		0x0001
35 #define PAGEMODE_REG		0x03
36 #define DEVICE_ID_REG		0x0004
37 #define NOON010PC30_ID		0x86
38 #define SR030PC30_ID		0x8C
39 #define VDO_CTL1_REG		0x0010
40 #define SUBSAMPL_NONE_VGA	0
41 #define SUBSAMPL_QVGA		0x10
42 #define SUBSAMPL_QQVGA		0x20
43 #define VDO_CTL2_REG		0x0011
44 #define SYNC_CTL_REG		0x0012
45 #define WIN_ROWH_REG		0x0020
46 #define WIN_ROWL_REG		0x0021
47 #define WIN_COLH_REG		0x0022
48 #define WIN_COLL_REG		0x0023
49 #define WIN_HEIGHTH_REG		0x0024
50 #define WIN_HEIGHTL_REG		0x0025
51 #define WIN_WIDTHH_REG		0x0026
52 #define WIN_WIDTHL_REG		0x0027
53 #define HBLANKH_REG		0x0040
54 #define HBLANKL_REG		0x0041
55 #define VSYNCH_REG		0x0042
56 #define VSYNCL_REG		0x0043
57 /* page 10 */
58 #define ISP_CTL_REG(n)		(0x1010 + (n))
59 #define YOFS_REG		0x1040
60 #define DARK_YOFS_REG		0x1041
61 #define AG_ABRTH_REG		0x1050
62 #define SAT_CTL_REG		0x1060
63 #define BSAT_REG		0x1061
64 #define RSAT_REG		0x1062
65 #define AG_SAT_TH_REG		0x1063
66 /* page 11 */
67 #define ZLPF_CTRL_REG		0x1110
68 #define ZLPF_CTRL2_REG		0x1112
69 #define ZLPF_AGH_THR_REG	0x1121
70 #define ZLPF_THR_REG		0x1160
71 #define ZLPF_DYN_THR_REG	0x1160
72 /* page 12 */
73 #define YCLPF_CTL1_REG		0x1240
74 #define YCLPF_CTL2_REG		0x1241
75 #define YCLPF_THR_REG		0x1250
76 #define BLPF_CTL_REG		0x1270
77 #define BLPF_THR1_REG		0x1274
78 #define BLPF_THR2_REG		0x1275
79 /* page 14 - Lens Shading Compensation */
80 #define LENS_CTRL_REG		0x1410
81 #define LENS_XCEN_REG		0x1420
82 #define LENS_YCEN_REG		0x1421
83 #define LENS_R_COMP_REG		0x1422
84 #define LENS_G_COMP_REG		0x1423
85 #define LENS_B_COMP_REG		0x1424
86 /* page 15 - Color correction */
87 #define CMC_CTL_REG		0x1510
88 #define CMC_OFSGH_REG		0x1514
89 #define CMC_OFSGL_REG		0x1516
90 #define CMC_SIGN_REG		0x1517
91 /* Color correction coefficients */
92 #define CMC_COEF_REG(n)		(0x1530 + (n))
93 /* Color correction offset coefficients */
94 #define CMC_OFS_REG(n)		(0x1540 + (n))
95 /* page 16 - Gamma correction */
96 #define GMA_CTL_REG		0x1610
97 /* Gamma correction coefficients 0.14 */
98 #define GMA_COEF_REG(n)		(0x1630 + (n))
99 /* page 20 - Auto Exposure */
100 #define AE_CTL1_REG		0x2010
101 #define AE_CTL2_REG		0x2011
102 #define AE_FRM_CTL_REG		0x2020
103 #define AE_FINE_CTL_REG(n)	(0x2028 + (n))
104 #define EXP_TIMEH_REG		0x2083
105 #define EXP_TIMEM_REG		0x2084
106 #define EXP_TIMEL_REG		0x2085
107 #define EXP_MMINH_REG		0x2086
108 #define EXP_MMINL_REG		0x2087
109 #define EXP_MMAXH_REG		0x2088
110 #define EXP_MMAXM_REG		0x2089
111 #define EXP_MMAXL_REG		0x208A
112 /* page 22 - Auto White Balance */
113 #define AWB_CTL1_REG		0x2210
114 #define AWB_ENABLE		0x80
115 #define AWB_CTL2_REG		0x2211
116 #define MWB_ENABLE		0x01
117 /* RGB gain control (manual WB) when AWB_CTL1[7]=0 */
118 #define AWB_RGAIN_REG		0x2280
119 #define AWB_GGAIN_REG		0x2281
120 #define AWB_BGAIN_REG		0x2282
121 #define AWB_RMAX_REG		0x2283
122 #define AWB_RMIN_REG		0x2284
123 #define AWB_BMAX_REG		0x2285
124 #define AWB_BMIN_REG		0x2286
125 /* R, B gain range in bright light conditions */
126 #define AWB_RMAXB_REG		0x2287
127 #define AWB_RMINB_REG		0x2288
128 #define AWB_BMAXB_REG		0x2289
129 #define AWB_BMINB_REG		0x228A
130 /* manual white balance, when AWB_CTL2[0]=1 */
131 #define MWB_RGAIN_REG		0x22B2
132 #define MWB_BGAIN_REG		0x22B3
133 /* the token to mark an array end */
134 #define REG_TERM		0xFFFF
135 
136 /* Minimum and maximum exposure time in ms */
137 #define EXPOS_MIN_MS		1
138 #define EXPOS_MAX_MS		125
139 
140 struct sr030pc30_info {
141 	struct v4l2_subdev sd;
142 	struct v4l2_ctrl_handler hdl;
143 	const struct sr030pc30_platform_data *pdata;
144 	const struct sr030pc30_format *curr_fmt;
145 	const struct sr030pc30_frmsize *curr_win;
146 	unsigned int hflip:1;
147 	unsigned int vflip:1;
148 	unsigned int sleep:1;
149 	struct {
150 		/* auto whitebalance control cluster */
151 		struct v4l2_ctrl *awb;
152 		struct v4l2_ctrl *red;
153 		struct v4l2_ctrl *blue;
154 	};
155 	struct {
156 		/* auto exposure control cluster */
157 		struct v4l2_ctrl *autoexp;
158 		struct v4l2_ctrl *exp;
159 	};
160 	u8 i2c_reg_page;
161 };
162 
163 struct sr030pc30_format {
164 	u32 code;
165 	enum v4l2_colorspace colorspace;
166 	u16 ispctl1_reg;
167 };
168 
169 struct sr030pc30_frmsize {
170 	u16 width;
171 	u16 height;
172 	int vid_ctl1;
173 };
174 
175 struct i2c_regval {
176 	u16 addr;
177 	u16 val;
178 };
179 
180 /* supported resolutions */
181 static const struct sr030pc30_frmsize sr030pc30_sizes[] = {
182 	{
183 		.width		= 640,
184 		.height		= 480,
185 		.vid_ctl1	= SUBSAMPL_NONE_VGA,
186 	}, {
187 		.width		= 320,
188 		.height		= 240,
189 		.vid_ctl1	= SUBSAMPL_QVGA,
190 	}, {
191 		.width		= 160,
192 		.height		= 120,
193 		.vid_ctl1	= SUBSAMPL_QQVGA,
194 	},
195 };
196 
197 /* supported pixel formats */
198 static const struct sr030pc30_format sr030pc30_formats[] = {
199 	{
200 		.code		= MEDIA_BUS_FMT_YUYV8_2X8,
201 		.colorspace	= V4L2_COLORSPACE_JPEG,
202 		.ispctl1_reg	= 0x03,
203 	}, {
204 		.code		= MEDIA_BUS_FMT_YVYU8_2X8,
205 		.colorspace	= V4L2_COLORSPACE_JPEG,
206 		.ispctl1_reg	= 0x02,
207 	}, {
208 		.code		= MEDIA_BUS_FMT_VYUY8_2X8,
209 		.colorspace	= V4L2_COLORSPACE_JPEG,
210 		.ispctl1_reg	= 0,
211 	}, {
212 		.code		= MEDIA_BUS_FMT_UYVY8_2X8,
213 		.colorspace	= V4L2_COLORSPACE_JPEG,
214 		.ispctl1_reg	= 0x01,
215 	}, {
216 		.code		= MEDIA_BUS_FMT_RGB565_2X8_BE,
217 		.colorspace	= V4L2_COLORSPACE_JPEG,
218 		.ispctl1_reg	= 0x40,
219 	},
220 };
221 
222 static const struct i2c_regval sr030pc30_base_regs[] = {
223 	/* Window size and position within pixel matrix */
224 	{ WIN_ROWH_REG,		0x00 }, { WIN_ROWL_REG,		0x06 },
225 	{ WIN_COLH_REG,		0x00 },	{ WIN_COLL_REG,		0x06 },
226 	{ WIN_HEIGHTH_REG,	0x01 }, { WIN_HEIGHTL_REG,	0xE0 },
227 	{ WIN_WIDTHH_REG,	0x02 }, { WIN_WIDTHL_REG,	0x80 },
228 	{ HBLANKH_REG,		0x01 }, { HBLANKL_REG,		0x50 },
229 	{ VSYNCH_REG,		0x00 }, { VSYNCL_REG,		0x14 },
230 	{ SYNC_CTL_REG,		0 },
231 	/* Color corection and saturation */
232 	{ ISP_CTL_REG(0),	0x30 }, { YOFS_REG,		0x80 },
233 	{ DARK_YOFS_REG,	0x04 }, { AG_ABRTH_REG,		0x78 },
234 	{ SAT_CTL_REG,		0x1F }, { BSAT_REG,		0x90 },
235 	{ AG_SAT_TH_REG,	0xF0 }, { 0x1064,		0x80 },
236 	{ CMC_CTL_REG,		0x03 }, { CMC_OFSGH_REG,	0x3C },
237 	{ CMC_OFSGL_REG,	0x2C }, { CMC_SIGN_REG,		0x2F },
238 	{ CMC_COEF_REG(0),	0xCB }, { CMC_OFS_REG(0),	0x87 },
239 	{ CMC_COEF_REG(1),	0x61 }, { CMC_OFS_REG(1),	0x18 },
240 	{ CMC_COEF_REG(2),	0x16 }, { CMC_OFS_REG(2),	0x91 },
241 	{ CMC_COEF_REG(3),	0x23 }, { CMC_OFS_REG(3),	0x94 },
242 	{ CMC_COEF_REG(4),	0xCE }, { CMC_OFS_REG(4),	0x9f },
243 	{ CMC_COEF_REG(5),	0x2B }, { CMC_OFS_REG(5),	0x33 },
244 	{ CMC_COEF_REG(6),	0x01 }, { CMC_OFS_REG(6),	0x00 },
245 	{ CMC_COEF_REG(7),	0x34 }, { CMC_OFS_REG(7),	0x94 },
246 	{ CMC_COEF_REG(8),	0x75 }, { CMC_OFS_REG(8),	0x14 },
247 	/* Color corection coefficients */
248 	{ GMA_CTL_REG,		0x03 },	{ GMA_COEF_REG(0),	0x00 },
249 	{ GMA_COEF_REG(1),	0x19 },	{ GMA_COEF_REG(2),	0x26 },
250 	{ GMA_COEF_REG(3),	0x3B },	{ GMA_COEF_REG(4),	0x5D },
251 	{ GMA_COEF_REG(5),	0x79 }, { GMA_COEF_REG(6),	0x8E },
252 	{ GMA_COEF_REG(7),	0x9F },	{ GMA_COEF_REG(8),	0xAF },
253 	{ GMA_COEF_REG(9),	0xBD },	{ GMA_COEF_REG(10),	0xCA },
254 	{ GMA_COEF_REG(11),	0xDD }, { GMA_COEF_REG(12),	0xEC },
255 	{ GMA_COEF_REG(13),	0xF7 },	{ GMA_COEF_REG(14),	0xFF },
256 	/* Noise reduction, Z-LPF, YC-LPF and BLPF filters setup */
257 	{ ZLPF_CTRL_REG,	0x99 }, { ZLPF_CTRL2_REG,	0x0E },
258 	{ ZLPF_AGH_THR_REG,	0x29 }, { ZLPF_THR_REG,		0x0F },
259 	{ ZLPF_DYN_THR_REG,	0x63 }, { YCLPF_CTL1_REG,	0x23 },
260 	{ YCLPF_CTL2_REG,	0x3B }, { YCLPF_THR_REG,	0x05 },
261 	{ BLPF_CTL_REG,		0x1D }, { BLPF_THR1_REG,	0x05 },
262 	{ BLPF_THR2_REG,	0x04 },
263 	/* Automatic white balance */
264 	{ AWB_CTL1_REG,		0xFB }, { AWB_CTL2_REG,		0x26 },
265 	{ AWB_RMAX_REG,		0x54 }, { AWB_RMIN_REG,		0x2B },
266 	{ AWB_BMAX_REG,		0x57 }, { AWB_BMIN_REG,		0x29 },
267 	{ AWB_RMAXB_REG,	0x50 }, { AWB_RMINB_REG,	0x43 },
268 	{ AWB_BMAXB_REG,	0x30 }, { AWB_BMINB_REG,	0x22 },
269 	/* Auto exposure */
270 	{ AE_CTL1_REG,		0x8C }, { AE_CTL2_REG,		0x04 },
271 	{ AE_FRM_CTL_REG,	0x01 }, { AE_FINE_CTL_REG(0),	0x3F },
272 	{ AE_FINE_CTL_REG(1),	0xA3 }, { AE_FINE_CTL_REG(3),	0x34 },
273 	/* Lens shading compensation */
274 	{ LENS_CTRL_REG,	0x01 }, { LENS_XCEN_REG,	0x80 },
275 	{ LENS_YCEN_REG,	0x70 }, { LENS_R_COMP_REG,	0x53 },
276 	{ LENS_G_COMP_REG,	0x40 }, { LENS_B_COMP_REG,	0x3e },
277 	{ REG_TERM,		0 },
278 };
279 
to_sr030pc30(struct v4l2_subdev * sd)280 static inline struct sr030pc30_info *to_sr030pc30(struct v4l2_subdev *sd)
281 {
282 	return container_of(sd, struct sr030pc30_info, sd);
283 }
284 
set_i2c_page(struct sr030pc30_info * info,struct i2c_client * client,unsigned int reg)285 static inline int set_i2c_page(struct sr030pc30_info *info,
286 			       struct i2c_client *client, unsigned int reg)
287 {
288 	int ret = 0;
289 	u32 page = reg >> 8 & 0xFF;
290 
291 	if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
292 		ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
293 		if (!ret)
294 			info->i2c_reg_page = page;
295 	}
296 	return ret;
297 }
298 
cam_i2c_read(struct v4l2_subdev * sd,u32 reg_addr)299 static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
300 {
301 	struct i2c_client *client = v4l2_get_subdevdata(sd);
302 	struct sr030pc30_info *info = to_sr030pc30(sd);
303 
304 	int ret = set_i2c_page(info, client, reg_addr);
305 	if (!ret)
306 		ret = i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
307 	return ret;
308 }
309 
cam_i2c_write(struct v4l2_subdev * sd,u32 reg_addr,u32 val)310 static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
311 {
312 	struct i2c_client *client = v4l2_get_subdevdata(sd);
313 	struct sr030pc30_info *info = to_sr030pc30(sd);
314 
315 	int ret = set_i2c_page(info, client, reg_addr);
316 	if (!ret)
317 		ret = i2c_smbus_write_byte_data(
318 			client, reg_addr & 0xFF, val);
319 	return ret;
320 }
321 
sr030pc30_bulk_write_reg(struct v4l2_subdev * sd,const struct i2c_regval * msg)322 static inline int sr030pc30_bulk_write_reg(struct v4l2_subdev *sd,
323 				const struct i2c_regval *msg)
324 {
325 	while (msg->addr != REG_TERM) {
326 		int ret = cam_i2c_write(sd, msg->addr, msg->val);
327 		if (ret)
328 			return ret;
329 		msg++;
330 	}
331 	return 0;
332 }
333 
334 /* Device reset and sleep mode control */
sr030pc30_pwr_ctrl(struct v4l2_subdev * sd,bool reset,bool sleep)335 static int sr030pc30_pwr_ctrl(struct v4l2_subdev *sd,
336 				     bool reset, bool sleep)
337 {
338 	struct sr030pc30_info *info = to_sr030pc30(sd);
339 	u8 reg = sleep ? 0xF1 : 0xF0;
340 	int ret = 0;
341 
342 	if (reset)
343 		ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
344 	if (!ret) {
345 		ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
346 		if (!ret) {
347 			info->sleep = sleep;
348 			if (reset)
349 				info->i2c_reg_page = -1;
350 		}
351 	}
352 	return ret;
353 }
354 
sr030pc30_set_flip(struct v4l2_subdev * sd)355 static int sr030pc30_set_flip(struct v4l2_subdev *sd)
356 {
357 	struct sr030pc30_info *info = to_sr030pc30(sd);
358 
359 	s32 reg = cam_i2c_read(sd, VDO_CTL2_REG);
360 	if (reg < 0)
361 		return reg;
362 
363 	reg &= 0x7C;
364 	if (info->hflip)
365 		reg |= 0x01;
366 	if (info->vflip)
367 		reg |= 0x02;
368 	return cam_i2c_write(sd, VDO_CTL2_REG, reg | 0x80);
369 }
370 
371 /* Configure resolution, color format and image flip */
sr030pc30_set_params(struct v4l2_subdev * sd)372 static int sr030pc30_set_params(struct v4l2_subdev *sd)
373 {
374 	struct sr030pc30_info *info = to_sr030pc30(sd);
375 	int ret;
376 
377 	if (!info->curr_win)
378 		return -EINVAL;
379 
380 	/* Configure the resolution through subsampling */
381 	ret = cam_i2c_write(sd, VDO_CTL1_REG,
382 			    info->curr_win->vid_ctl1);
383 
384 	if (!ret && info->curr_fmt)
385 		ret = cam_i2c_write(sd, ISP_CTL_REG(0),
386 				info->curr_fmt->ispctl1_reg);
387 	if (!ret)
388 		ret = sr030pc30_set_flip(sd);
389 
390 	return ret;
391 }
392 
393 /* Find nearest matching image pixel size. */
sr030pc30_try_frame_size(struct v4l2_mbus_framefmt * mf)394 static int sr030pc30_try_frame_size(struct v4l2_mbus_framefmt *mf)
395 {
396 	unsigned int min_err = ~0;
397 	int i = ARRAY_SIZE(sr030pc30_sizes);
398 	const struct sr030pc30_frmsize *fsize = &sr030pc30_sizes[0],
399 					*match = NULL;
400 	while (i--) {
401 		int err = abs(fsize->width - mf->width)
402 				+ abs(fsize->height - mf->height);
403 		if (err < min_err) {
404 			min_err = err;
405 			match = fsize;
406 		}
407 		fsize++;
408 	}
409 	if (match) {
410 		mf->width  = match->width;
411 		mf->height = match->height;
412 		return 0;
413 	}
414 	return -EINVAL;
415 }
416 
sr030pc30_s_ctrl(struct v4l2_ctrl * ctrl)417 static int sr030pc30_s_ctrl(struct v4l2_ctrl *ctrl)
418 {
419 	struct sr030pc30_info *info =
420 		container_of(ctrl->handler, struct sr030pc30_info, hdl);
421 	struct v4l2_subdev *sd = &info->sd;
422 	int ret = 0;
423 
424 	v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
425 			 __func__, ctrl->id, ctrl->val);
426 
427 	switch (ctrl->id) {
428 	case V4L2_CID_AUTO_WHITE_BALANCE:
429 		if (ctrl->is_new) {
430 			ret = cam_i2c_write(sd, AWB_CTL2_REG,
431 					ctrl->val ? 0x2E : 0x2F);
432 			if (!ret)
433 				ret = cam_i2c_write(sd, AWB_CTL1_REG,
434 						ctrl->val ? 0xFB : 0x7B);
435 		}
436 		if (!ret && info->blue->is_new)
437 			ret = cam_i2c_write(sd, MWB_BGAIN_REG, info->blue->val);
438 		if (!ret && info->red->is_new)
439 			ret = cam_i2c_write(sd, MWB_RGAIN_REG, info->red->val);
440 		return ret;
441 
442 	case V4L2_CID_EXPOSURE_AUTO:
443 		/* auto anti-flicker is also enabled here */
444 		if (ctrl->is_new)
445 			ret = cam_i2c_write(sd, AE_CTL1_REG,
446 				ctrl->val == V4L2_EXPOSURE_AUTO ? 0xDC : 0x0C);
447 		if (info->exp->is_new) {
448 			unsigned long expos = info->exp->val;
449 
450 			expos = expos * info->pdata->clk_rate / (8 * 1000);
451 
452 			if (!ret)
453 				ret = cam_i2c_write(sd, EXP_TIMEH_REG,
454 						expos >> 16 & 0xFF);
455 			if (!ret)
456 				ret = cam_i2c_write(sd, EXP_TIMEM_REG,
457 						expos >> 8 & 0xFF);
458 			if (!ret)
459 				ret = cam_i2c_write(sd, EXP_TIMEL_REG,
460 						expos & 0xFF);
461 		}
462 		return ret;
463 	default:
464 		return -EINVAL;
465 	}
466 
467 	return 0;
468 }
469 
sr030pc30_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)470 static int sr030pc30_enum_mbus_code(struct v4l2_subdev *sd,
471 		struct v4l2_subdev_state *sd_state,
472 		struct v4l2_subdev_mbus_code_enum *code)
473 {
474 	if (!code || code->pad ||
475 	    code->index >= ARRAY_SIZE(sr030pc30_formats))
476 		return -EINVAL;
477 
478 	code->code = sr030pc30_formats[code->index].code;
479 	return 0;
480 }
481 
sr030pc30_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)482 static int sr030pc30_get_fmt(struct v4l2_subdev *sd,
483 		struct v4l2_subdev_state *sd_state,
484 		struct v4l2_subdev_format *format)
485 {
486 	struct v4l2_mbus_framefmt *mf;
487 	struct sr030pc30_info *info = to_sr030pc30(sd);
488 
489 	if (!format || format->pad)
490 		return -EINVAL;
491 
492 	mf = &format->format;
493 
494 	if (!info->curr_win || !info->curr_fmt)
495 		return -EINVAL;
496 
497 	mf->width	= info->curr_win->width;
498 	mf->height	= info->curr_win->height;
499 	mf->code	= info->curr_fmt->code;
500 	mf->colorspace	= info->curr_fmt->colorspace;
501 	mf->field	= V4L2_FIELD_NONE;
502 
503 	return 0;
504 }
505 
506 /* Return nearest media bus frame format. */
try_fmt(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * mf)507 static const struct sr030pc30_format *try_fmt(struct v4l2_subdev *sd,
508 					      struct v4l2_mbus_framefmt *mf)
509 {
510 	int i;
511 
512 	sr030pc30_try_frame_size(mf);
513 
514 	for (i = 0; i < ARRAY_SIZE(sr030pc30_formats); i++) {
515 		if (mf->code == sr030pc30_formats[i].code)
516 			break;
517 	}
518 	if (i == ARRAY_SIZE(sr030pc30_formats))
519 		i = 0;
520 
521 	mf->code = sr030pc30_formats[i].code;
522 
523 	return &sr030pc30_formats[i];
524 }
525 
526 /* Return nearest media bus frame format. */
sr030pc30_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)527 static int sr030pc30_set_fmt(struct v4l2_subdev *sd,
528 		struct v4l2_subdev_state *sd_state,
529 		struct v4l2_subdev_format *format)
530 {
531 	struct sr030pc30_info *info = sd ? to_sr030pc30(sd) : NULL;
532 	const struct sr030pc30_format *fmt;
533 	struct v4l2_mbus_framefmt *mf;
534 
535 	if (!sd || !format)
536 		return -EINVAL;
537 
538 	mf = &format->format;
539 	if (format->pad)
540 		return -EINVAL;
541 
542 	fmt = try_fmt(sd, mf);
543 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
544 		sd_state->pads->try_fmt = *mf;
545 		return 0;
546 	}
547 
548 	info->curr_fmt = fmt;
549 
550 	return sr030pc30_set_params(sd);
551 }
552 
sr030pc30_base_config(struct v4l2_subdev * sd)553 static int sr030pc30_base_config(struct v4l2_subdev *sd)
554 {
555 	struct sr030pc30_info *info = to_sr030pc30(sd);
556 	int ret;
557 	unsigned long expmin, expmax;
558 
559 	ret = sr030pc30_bulk_write_reg(sd, sr030pc30_base_regs);
560 	if (!ret) {
561 		info->curr_fmt = &sr030pc30_formats[0];
562 		info->curr_win = &sr030pc30_sizes[0];
563 		ret = sr030pc30_set_params(sd);
564 	}
565 	if (!ret)
566 		ret = sr030pc30_pwr_ctrl(sd, false, false);
567 
568 	if (ret)
569 		return ret;
570 
571 	expmin = EXPOS_MIN_MS * info->pdata->clk_rate / (8 * 1000);
572 	expmax = EXPOS_MAX_MS * info->pdata->clk_rate / (8 * 1000);
573 
574 	v4l2_dbg(1, debug, sd, "%s: expmin= %lx, expmax= %lx", __func__,
575 		 expmin, expmax);
576 
577 	/* Setting up manual exposure time range */
578 	ret = cam_i2c_write(sd, EXP_MMINH_REG, expmin >> 8 & 0xFF);
579 	if (!ret)
580 		ret = cam_i2c_write(sd, EXP_MMINL_REG, expmin & 0xFF);
581 	if (!ret)
582 		ret = cam_i2c_write(sd, EXP_MMAXH_REG, expmax >> 16 & 0xFF);
583 	if (!ret)
584 		ret = cam_i2c_write(sd, EXP_MMAXM_REG, expmax >> 8 & 0xFF);
585 	if (!ret)
586 		ret = cam_i2c_write(sd, EXP_MMAXL_REG, expmax & 0xFF);
587 
588 	return ret;
589 }
590 
sr030pc30_s_power(struct v4l2_subdev * sd,int on)591 static int sr030pc30_s_power(struct v4l2_subdev *sd, int on)
592 {
593 	struct i2c_client *client = v4l2_get_subdevdata(sd);
594 	struct sr030pc30_info *info = to_sr030pc30(sd);
595 	const struct sr030pc30_platform_data *pdata = info->pdata;
596 	int ret;
597 
598 	if (pdata == NULL) {
599 		WARN(1, "No platform data!\n");
600 		return -EINVAL;
601 	}
602 
603 	/*
604 	 * Put sensor into power sleep mode before switching off
605 	 * power and disabling MCLK.
606 	 */
607 	if (!on)
608 		sr030pc30_pwr_ctrl(sd, false, true);
609 
610 	/* set_power controls sensor's power and clock */
611 	if (pdata->set_power) {
612 		ret = pdata->set_power(&client->dev, on);
613 		if (ret)
614 			return ret;
615 	}
616 
617 	if (on) {
618 		ret = sr030pc30_base_config(sd);
619 	} else {
620 		ret = 0;
621 		info->curr_win = NULL;
622 		info->curr_fmt = NULL;
623 	}
624 
625 	return ret;
626 }
627 
628 static const struct v4l2_ctrl_ops sr030pc30_ctrl_ops = {
629 	.s_ctrl = sr030pc30_s_ctrl,
630 };
631 
632 static const struct v4l2_subdev_core_ops sr030pc30_core_ops = {
633 	.s_power	= sr030pc30_s_power,
634 };
635 
636 static const struct v4l2_subdev_pad_ops sr030pc30_pad_ops = {
637 	.enum_mbus_code = sr030pc30_enum_mbus_code,
638 	.get_fmt	= sr030pc30_get_fmt,
639 	.set_fmt	= sr030pc30_set_fmt,
640 };
641 
642 static const struct v4l2_subdev_ops sr030pc30_ops = {
643 	.core	= &sr030pc30_core_ops,
644 	.pad	= &sr030pc30_pad_ops,
645 };
646 
647 /*
648  * Detect sensor type. Return 0 if SR030PC30 was detected
649  * or -ENODEV otherwise.
650  */
sr030pc30_detect(struct i2c_client * client)651 static int sr030pc30_detect(struct i2c_client *client)
652 {
653 	const struct sr030pc30_platform_data *pdata
654 		= client->dev.platform_data;
655 	int ret;
656 
657 	/* Enable sensor's power and clock */
658 	if (pdata->set_power) {
659 		ret = pdata->set_power(&client->dev, 1);
660 		if (ret)
661 			return ret;
662 	}
663 
664 	ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
665 
666 	if (pdata->set_power)
667 		pdata->set_power(&client->dev, 0);
668 
669 	if (ret < 0) {
670 		dev_err(&client->dev, "%s: I2C read failed\n", __func__);
671 		return ret;
672 	}
673 
674 	return ret == SR030PC30_ID ? 0 : -ENODEV;
675 }
676 
677 
sr030pc30_probe(struct i2c_client * client,const struct i2c_device_id * id)678 static int sr030pc30_probe(struct i2c_client *client,
679 			   const struct i2c_device_id *id)
680 {
681 	struct sr030pc30_info *info;
682 	struct v4l2_subdev *sd;
683 	struct v4l2_ctrl_handler *hdl;
684 	const struct sr030pc30_platform_data *pdata
685 		= client->dev.platform_data;
686 	int ret;
687 
688 	if (!pdata) {
689 		dev_err(&client->dev, "No platform data!");
690 		return -EIO;
691 	}
692 
693 	ret = sr030pc30_detect(client);
694 	if (ret)
695 		return ret;
696 
697 	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
698 	if (!info)
699 		return -ENOMEM;
700 
701 	sd = &info->sd;
702 	info->pdata = client->dev.platform_data;
703 
704 	v4l2_i2c_subdev_init(sd, client, &sr030pc30_ops);
705 
706 	hdl = &info->hdl;
707 	v4l2_ctrl_handler_init(hdl, 6);
708 	info->awb = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
709 			V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
710 	info->red = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
711 			V4L2_CID_RED_BALANCE, 0, 127, 1, 64);
712 	info->blue = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
713 			V4L2_CID_BLUE_BALANCE, 0, 127, 1, 64);
714 	info->autoexp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
715 			V4L2_CID_EXPOSURE_AUTO, 0, 1, 1, 1);
716 	info->exp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
717 			V4L2_CID_EXPOSURE, EXPOS_MIN_MS, EXPOS_MAX_MS, 1, 30);
718 	sd->ctrl_handler = hdl;
719 	if (hdl->error) {
720 		int err = hdl->error;
721 
722 		v4l2_ctrl_handler_free(hdl);
723 		return err;
724 	}
725 	v4l2_ctrl_auto_cluster(3, &info->awb, 0, false);
726 	v4l2_ctrl_auto_cluster(2, &info->autoexp, V4L2_EXPOSURE_MANUAL, false);
727 	v4l2_ctrl_handler_setup(hdl);
728 
729 	info->i2c_reg_page	= -1;
730 	info->hflip		= 1;
731 
732 	return 0;
733 }
734 
sr030pc30_remove(struct i2c_client * client)735 static int sr030pc30_remove(struct i2c_client *client)
736 {
737 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
738 
739 	v4l2_device_unregister_subdev(sd);
740 	v4l2_ctrl_handler_free(sd->ctrl_handler);
741 	return 0;
742 }
743 
744 static const struct i2c_device_id sr030pc30_id[] = {
745 	{ MODULE_NAME, 0 },
746 	{ },
747 };
748 MODULE_DEVICE_TABLE(i2c, sr030pc30_id);
749 
750 
751 static struct i2c_driver sr030pc30_i2c_driver = {
752 	.driver = {
753 		.name = MODULE_NAME
754 	},
755 	.probe		= sr030pc30_probe,
756 	.remove		= sr030pc30_remove,
757 	.id_table	= sr030pc30_id,
758 };
759 
760 module_i2c_driver(sr030pc30_i2c_driver);
761 
762 MODULE_DESCRIPTION("Siliconfile SR030PC30 camera driver");
763 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
764 MODULE_LICENSE("GPL");
765