1 /*
2 * vpif - Video Port Interface driver
3 * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
4 * that receiving video byte stream and two channels(2, 3) for video output.
5 * The hardware supports SDTV, HDTV formats, raw data capture.
6 * Currently, the driver supports NTSC and PAL standards.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation version 2.
13 *
14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
15 * kind, whether express or implied; without even the implied warranty
16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/spinlock.h>
28 #include <linux/v4l2-dv-timings.h>
29 #include <linux/of_graph.h>
30
31 #include "vpif.h"
32
33 MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
34 MODULE_LICENSE("GPL");
35
36 #define VPIF_DRIVER_NAME "vpif"
37 MODULE_ALIAS("platform:" VPIF_DRIVER_NAME);
38
39 #define VPIF_CH0_MAX_MODES 22
40 #define VPIF_CH1_MAX_MODES 2
41 #define VPIF_CH2_MAX_MODES 15
42 #define VPIF_CH3_MAX_MODES 2
43
44 struct vpif_data {
45 struct platform_device *capture;
46 struct platform_device *display;
47 };
48
49 DEFINE_SPINLOCK(vpif_lock);
50 EXPORT_SYMBOL_GPL(vpif_lock);
51
52 void __iomem *vpif_base;
53 EXPORT_SYMBOL_GPL(vpif_base);
54
55 /*
56 * vpif_ch_params: video standard configuration parameters for vpif
57 *
58 * The table must include all presets from supported subdevices.
59 */
60 const struct vpif_channel_config_params vpif_ch_params[] = {
61 /* HDTV formats */
62 {
63 .name = "480p59_94",
64 .width = 720,
65 .height = 480,
66 .frm_fmt = 1,
67 .ycmux_mode = 0,
68 .eav2sav = 138-8,
69 .sav2eav = 720,
70 .l1 = 1,
71 .l3 = 43,
72 .l5 = 523,
73 .vsize = 525,
74 .capture_format = 0,
75 .vbi_supported = 0,
76 .hd_sd = 1,
77 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
78 },
79 {
80 .name = "576p50",
81 .width = 720,
82 .height = 576,
83 .frm_fmt = 1,
84 .ycmux_mode = 0,
85 .eav2sav = 144-8,
86 .sav2eav = 720,
87 .l1 = 1,
88 .l3 = 45,
89 .l5 = 621,
90 .vsize = 625,
91 .capture_format = 0,
92 .vbi_supported = 0,
93 .hd_sd = 1,
94 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
95 },
96 {
97 .name = "720p50",
98 .width = 1280,
99 .height = 720,
100 .frm_fmt = 1,
101 .ycmux_mode = 0,
102 .eav2sav = 700-8,
103 .sav2eav = 1280,
104 .l1 = 1,
105 .l3 = 26,
106 .l5 = 746,
107 .vsize = 750,
108 .capture_format = 0,
109 .vbi_supported = 0,
110 .hd_sd = 1,
111 .dv_timings = V4L2_DV_BT_CEA_1280X720P50,
112 },
113 {
114 .name = "720p60",
115 .width = 1280,
116 .height = 720,
117 .frm_fmt = 1,
118 .ycmux_mode = 0,
119 .eav2sav = 370 - 8,
120 .sav2eav = 1280,
121 .l1 = 1,
122 .l3 = 26,
123 .l5 = 746,
124 .vsize = 750,
125 .capture_format = 0,
126 .vbi_supported = 0,
127 .hd_sd = 1,
128 .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
129 },
130 {
131 .name = "1080I50",
132 .width = 1920,
133 .height = 1080,
134 .frm_fmt = 0,
135 .ycmux_mode = 0,
136 .eav2sav = 720 - 8,
137 .sav2eav = 1920,
138 .l1 = 1,
139 .l3 = 21,
140 .l5 = 561,
141 .l7 = 563,
142 .l9 = 584,
143 .l11 = 1124,
144 .vsize = 1125,
145 .capture_format = 0,
146 .vbi_supported = 0,
147 .hd_sd = 1,
148 .dv_timings = V4L2_DV_BT_CEA_1920X1080I50,
149 },
150 {
151 .name = "1080I60",
152 .width = 1920,
153 .height = 1080,
154 .frm_fmt = 0,
155 .ycmux_mode = 0,
156 .eav2sav = 280 - 8,
157 .sav2eav = 1920,
158 .l1 = 1,
159 .l3 = 21,
160 .l5 = 561,
161 .l7 = 563,
162 .l9 = 584,
163 .l11 = 1124,
164 .vsize = 1125,
165 .capture_format = 0,
166 .vbi_supported = 0,
167 .hd_sd = 1,
168 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
169 },
170 {
171 .name = "1080p60",
172 .width = 1920,
173 .height = 1080,
174 .frm_fmt = 1,
175 .ycmux_mode = 0,
176 .eav2sav = 280 - 8,
177 .sav2eav = 1920,
178 .l1 = 1,
179 .l3 = 42,
180 .l5 = 1122,
181 .vsize = 1125,
182 .capture_format = 0,
183 .vbi_supported = 0,
184 .hd_sd = 1,
185 .dv_timings = V4L2_DV_BT_CEA_1920X1080P60,
186 },
187
188 /* SDTV formats */
189 {
190 .name = "NTSC_M",
191 .width = 720,
192 .height = 480,
193 .frm_fmt = 0,
194 .ycmux_mode = 1,
195 .eav2sav = 268,
196 .sav2eav = 1440,
197 .l1 = 1,
198 .l3 = 23,
199 .l5 = 263,
200 .l7 = 266,
201 .l9 = 286,
202 .l11 = 525,
203 .vsize = 525,
204 .capture_format = 0,
205 .vbi_supported = 1,
206 .hd_sd = 0,
207 .stdid = V4L2_STD_525_60,
208 },
209 {
210 .name = "PAL_BDGHIK",
211 .width = 720,
212 .height = 576,
213 .frm_fmt = 0,
214 .ycmux_mode = 1,
215 .eav2sav = 280,
216 .sav2eav = 1440,
217 .l1 = 1,
218 .l3 = 23,
219 .l5 = 311,
220 .l7 = 313,
221 .l9 = 336,
222 .l11 = 624,
223 .vsize = 625,
224 .capture_format = 0,
225 .vbi_supported = 1,
226 .hd_sd = 0,
227 .stdid = V4L2_STD_625_50,
228 },
229 };
230 EXPORT_SYMBOL_GPL(vpif_ch_params);
231
232 const unsigned int vpif_ch_params_count = ARRAY_SIZE(vpif_ch_params);
233 EXPORT_SYMBOL_GPL(vpif_ch_params_count);
234
vpif_wr_bit(u32 reg,u32 bit,u32 val)235 static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
236 {
237 if (val)
238 vpif_set_bit(reg, bit);
239 else
240 vpif_clr_bit(reg, bit);
241 }
242
243 /* This structure is used to keep track of VPIF size register's offsets */
244 struct vpif_registers {
245 u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
246 u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
247 u32 vanc1_size, width_mask, len_mask;
248 u8 max_modes;
249 };
250
251 static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
252 /* Channel0 */
253 {
254 VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
255 VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
256 VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
257 VPIF_CH0_MAX_MODES,
258 },
259 /* Channel1 */
260 {
261 VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
262 VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
263 VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
264 VPIF_CH1_MAX_MODES,
265 },
266 /* Channel2 */
267 {
268 VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
269 VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
270 VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
271 VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
272 VPIF_CH2_MAX_MODES
273 },
274 /* Channel3 */
275 {
276 VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
277 VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
278 VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
279 VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
280 VPIF_CH3_MAX_MODES
281 },
282 };
283
284 /* vpif_set_mode_info:
285 * This function is used to set horizontal and vertical config parameters
286 * As per the standard in the channel, configure the values of L1, L3,
287 * L5, L7 L9, L11 in VPIF Register , also write width and height
288 */
vpif_set_mode_info(const struct vpif_channel_config_params * config,u8 channel_id,u8 config_channel_id)289 static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
290 u8 channel_id, u8 config_channel_id)
291 {
292 u32 value;
293
294 value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
295 value <<= VPIF_CH_LEN_SHIFT;
296 value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
297 regw(value, vpifregs[channel_id].h_cfg);
298
299 value = (config->l1 & vpifregs[config_channel_id].len_mask);
300 value <<= VPIF_CH_LEN_SHIFT;
301 value |= (config->l3 & vpifregs[config_channel_id].len_mask);
302 regw(value, vpifregs[channel_id].v_cfg_00);
303
304 value = (config->l5 & vpifregs[config_channel_id].len_mask);
305 value <<= VPIF_CH_LEN_SHIFT;
306 value |= (config->l7 & vpifregs[config_channel_id].len_mask);
307 regw(value, vpifregs[channel_id].v_cfg_01);
308
309 value = (config->l9 & vpifregs[config_channel_id].len_mask);
310 value <<= VPIF_CH_LEN_SHIFT;
311 value |= (config->l11 & vpifregs[config_channel_id].len_mask);
312 regw(value, vpifregs[channel_id].v_cfg_02);
313
314 value = (config->vsize & vpifregs[config_channel_id].len_mask);
315 regw(value, vpifregs[channel_id].v_cfg);
316 }
317
318 /* config_vpif_params
319 * Function to set the parameters of a channel
320 * Mainly modifies the channel ciontrol register
321 * It sets frame format, yc mux mode
322 */
config_vpif_params(struct vpif_params * vpifparams,u8 channel_id,u8 found)323 static void config_vpif_params(struct vpif_params *vpifparams,
324 u8 channel_id, u8 found)
325 {
326 const struct vpif_channel_config_params *config = &vpifparams->std_info;
327 u32 value, ch_nip, reg;
328 u8 start, end;
329 int i;
330
331 start = channel_id;
332 end = channel_id + found;
333
334 for (i = start; i < end; i++) {
335 reg = vpifregs[i].ch_ctrl;
336 if (channel_id < 2)
337 ch_nip = VPIF_CAPTURE_CH_NIP;
338 else
339 ch_nip = VPIF_DISPLAY_CH_NIP;
340
341 vpif_wr_bit(reg, ch_nip, config->frm_fmt);
342 vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
343 vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
344 vpifparams->video_params.storage_mode);
345
346 /* Set raster scanning SDR Format */
347 vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
348 vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
349
350 if (channel_id > 1) /* Set the Pixel enable bit */
351 vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
352 else if (config->capture_format) {
353 /* Set the polarity of various pins */
354 vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
355 vpifparams->iface.fid_pol);
356 vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
357 vpifparams->iface.vd_pol);
358 vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
359 vpifparams->iface.hd_pol);
360
361 value = regr(reg);
362 /* Set data width */
363 value &= ~(0x3u <<
364 VPIF_CH_DATA_WIDTH_BIT);
365 value |= ((vpifparams->params.data_sz) <<
366 VPIF_CH_DATA_WIDTH_BIT);
367 regw(value, reg);
368 }
369
370 /* Write the pitch in the driver */
371 regw((vpifparams->video_params.hpitch),
372 vpifregs[i].line_offset);
373 }
374 }
375
376 /* vpif_set_video_params
377 * This function is used to set video parameters in VPIF register
378 */
vpif_set_video_params(struct vpif_params * vpifparams,u8 channel_id)379 int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
380 {
381 const struct vpif_channel_config_params *config = &vpifparams->std_info;
382 int found = 1;
383
384 vpif_set_mode_info(config, channel_id, channel_id);
385 if (!config->ycmux_mode) {
386 /* YC are on separate channels (HDTV formats) */
387 vpif_set_mode_info(config, channel_id + 1, channel_id);
388 found = 2;
389 }
390
391 config_vpif_params(vpifparams, channel_id, found);
392
393 regw(0x80, VPIF_REQ_SIZE);
394 regw(0x01, VPIF_EMULATION_CTRL);
395
396 return found;
397 }
398 EXPORT_SYMBOL(vpif_set_video_params);
399
vpif_set_vbi_display_params(struct vpif_vbi_params * vbiparams,u8 channel_id)400 void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
401 u8 channel_id)
402 {
403 u32 value;
404
405 value = 0x3F8 & (vbiparams->hstart0);
406 value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
407 regw(value, vpifregs[channel_id].vanc0_strt);
408
409 value = 0x3F8 & (vbiparams->hstart1);
410 value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
411 regw(value, vpifregs[channel_id].vanc1_strt);
412
413 value = 0x3F8 & (vbiparams->hsize0);
414 value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
415 regw(value, vpifregs[channel_id].vanc0_size);
416
417 value = 0x3F8 & (vbiparams->hsize1);
418 value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
419 regw(value, vpifregs[channel_id].vanc1_size);
420
421 }
422 EXPORT_SYMBOL(vpif_set_vbi_display_params);
423
vpif_channel_getfid(u8 channel_id)424 int vpif_channel_getfid(u8 channel_id)
425 {
426 return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
427 >> VPIF_CH_FID_SHIFT;
428 }
429 EXPORT_SYMBOL(vpif_channel_getfid);
430
vpif_pdev_release(struct device * dev)431 static void vpif_pdev_release(struct device *dev)
432 {
433 struct platform_device *pdev = to_platform_device(dev);
434
435 kfree(pdev);
436 }
437
vpif_probe(struct platform_device * pdev)438 static int vpif_probe(struct platform_device *pdev)
439 {
440 static struct resource *res, *res_irq;
441 struct platform_device *pdev_capture, *pdev_display;
442 struct device_node *endpoint = NULL;
443 struct vpif_data *data;
444 int ret;
445
446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
447 vpif_base = devm_ioremap_resource(&pdev->dev, res);
448 if (IS_ERR(vpif_base))
449 return PTR_ERR(vpif_base);
450
451 data = kzalloc(sizeof(*data), GFP_KERNEL);
452 if (!data)
453 return -ENOMEM;
454
455 platform_set_drvdata(pdev, data);
456
457 pm_runtime_enable(&pdev->dev);
458 pm_runtime_get(&pdev->dev);
459
460 dev_info(&pdev->dev, "vpif probe success\n");
461
462 /*
463 * If VPIF Node has endpoints, assume "new" DT support,
464 * where capture and display drivers don't have DT nodes
465 * so their devices need to be registered manually here
466 * for their legacy platform_drivers to work.
467 */
468 endpoint = of_graph_get_next_endpoint(pdev->dev.of_node,
469 endpoint);
470 if (!endpoint)
471 return 0;
472
473 /*
474 * For DT platforms, manually create platform_devices for
475 * capture/display drivers.
476 */
477 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
478 if (!res_irq) {
479 dev_warn(&pdev->dev, "Missing IRQ resource.\n");
480 ret = -EINVAL;
481 goto err_put_rpm;
482 }
483
484 pdev_capture = kzalloc(sizeof(*pdev_capture), GFP_KERNEL);
485 if (!pdev_capture) {
486 ret = -ENOMEM;
487 goto err_put_rpm;
488 }
489
490 pdev_capture->name = "vpif_capture";
491 pdev_capture->id = -1;
492 pdev_capture->resource = res_irq;
493 pdev_capture->num_resources = 1;
494 pdev_capture->dev.dma_mask = pdev->dev.dma_mask;
495 pdev_capture->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
496 pdev_capture->dev.parent = &pdev->dev;
497 pdev_capture->dev.release = vpif_pdev_release;
498
499 ret = platform_device_register(pdev_capture);
500 if (ret)
501 goto err_put_pdev_capture;
502
503 pdev_display = kzalloc(sizeof(*pdev_display), GFP_KERNEL);
504 if (!pdev_display) {
505 ret = -ENOMEM;
506 goto err_put_pdev_capture;
507 }
508
509 pdev_display->name = "vpif_display";
510 pdev_display->id = -1;
511 pdev_display->resource = res_irq;
512 pdev_display->num_resources = 1;
513 pdev_display->dev.dma_mask = pdev->dev.dma_mask;
514 pdev_display->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
515 pdev_display->dev.parent = &pdev->dev;
516 pdev_display->dev.release = vpif_pdev_release;
517
518 ret = platform_device_register(pdev_display);
519 if (ret)
520 goto err_put_pdev_display;
521
522 data->capture = pdev_capture;
523 data->display = pdev_display;
524
525 return 0;
526
527 err_put_pdev_display:
528 platform_device_put(pdev_display);
529 err_put_pdev_capture:
530 platform_device_put(pdev_capture);
531 err_put_rpm:
532 pm_runtime_put(&pdev->dev);
533 pm_runtime_disable(&pdev->dev);
534 kfree(data);
535
536 return ret;
537 }
538
vpif_remove(struct platform_device * pdev)539 static int vpif_remove(struct platform_device *pdev)
540 {
541 struct vpif_data *data = platform_get_drvdata(pdev);
542
543 if (data->capture)
544 platform_device_unregister(data->capture);
545 if (data->display)
546 platform_device_unregister(data->display);
547
548 pm_runtime_put(&pdev->dev);
549 pm_runtime_disable(&pdev->dev);
550
551 kfree(data);
552
553 return 0;
554 }
555
556 #ifdef CONFIG_PM
vpif_suspend(struct device * dev)557 static int vpif_suspend(struct device *dev)
558 {
559 pm_runtime_put(dev);
560 return 0;
561 }
562
vpif_resume(struct device * dev)563 static int vpif_resume(struct device *dev)
564 {
565 pm_runtime_get(dev);
566 return 0;
567 }
568
569 static const struct dev_pm_ops vpif_pm = {
570 .suspend = vpif_suspend,
571 .resume = vpif_resume,
572 };
573
574 #define vpif_pm_ops (&vpif_pm)
575 #else
576 #define vpif_pm_ops NULL
577 #endif
578
579 #if IS_ENABLED(CONFIG_OF)
580 static const struct of_device_id vpif_of_match[] = {
581 { .compatible = "ti,da850-vpif", },
582 { /* sentinel */ },
583 };
584 MODULE_DEVICE_TABLE(of, vpif_of_match);
585 #endif
586
587 static struct platform_driver vpif_driver = {
588 .driver = {
589 .of_match_table = of_match_ptr(vpif_of_match),
590 .name = VPIF_DRIVER_NAME,
591 .pm = vpif_pm_ops,
592 },
593 .remove = vpif_remove,
594 .probe = vpif_probe,
595 };
596
vpif_exit(void)597 static void vpif_exit(void)
598 {
599 platform_driver_unregister(&vpif_driver);
600 }
601
vpif_init(void)602 static int __init vpif_init(void)
603 {
604 return platform_driver_register(&vpif_driver);
605 }
606 subsys_initcall(vpif_init);
607 module_exit(vpif_exit);
608
609