1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author: Jacob Chen <jacob-chen@iotwrt.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/fs.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/timer.h>
19
20 #include <linux/platform_device.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-dma-sg.h>
26 #include <media/videobuf2-v4l2.h>
27
28 #include "rga-hw.h"
29 #include "rga.h"
30
31 static int debug;
32 module_param(debug, int, 0644);
33
device_run(void * prv)34 static void device_run(void *prv)
35 {
36 struct rga_ctx *ctx = prv;
37 struct rockchip_rga *rga = ctx->rga;
38 struct vb2_v4l2_buffer *src, *dst;
39 unsigned long flags;
40
41 spin_lock_irqsave(&rga->ctrl_lock, flags);
42
43 rga->curr = ctx;
44
45 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
46 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
47
48 rga_buf_map(&src->vb2_buf);
49 rga_buf_map(&dst->vb2_buf);
50
51 rga_hw_start(rga);
52
53 spin_unlock_irqrestore(&rga->ctrl_lock, flags);
54 }
55
rga_isr(int irq,void * prv)56 static irqreturn_t rga_isr(int irq, void *prv)
57 {
58 struct rockchip_rga *rga = prv;
59 int intr;
60
61 intr = rga_read(rga, RGA_INT) & 0xf;
62
63 rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
64
65 if (intr & 0x04) {
66 struct vb2_v4l2_buffer *src, *dst;
67 struct rga_ctx *ctx = rga->curr;
68
69 WARN_ON(!ctx);
70
71 rga->curr = NULL;
72
73 src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
74 dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
75
76 WARN_ON(!src);
77 WARN_ON(!dst);
78
79 dst->timecode = src->timecode;
80 dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
81 dst->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
82 dst->flags |= src->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
83
84 v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
85 v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
86 v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
87 }
88
89 return IRQ_HANDLED;
90 }
91
92 static const struct v4l2_m2m_ops rga_m2m_ops = {
93 .device_run = device_run,
94 };
95
96 static int
queue_init(void * priv,struct vb2_queue * src_vq,struct vb2_queue * dst_vq)97 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
98 {
99 struct rga_ctx *ctx = priv;
100 int ret;
101
102 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
103 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
104 src_vq->drv_priv = ctx;
105 src_vq->ops = &rga_qops;
106 src_vq->mem_ops = &vb2_dma_sg_memops;
107 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
108 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
109 src_vq->lock = &ctx->rga->mutex;
110 src_vq->dev = ctx->rga->v4l2_dev.dev;
111
112 ret = vb2_queue_init(src_vq);
113 if (ret)
114 return ret;
115
116 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
117 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
118 dst_vq->drv_priv = ctx;
119 dst_vq->ops = &rga_qops;
120 dst_vq->mem_ops = &vb2_dma_sg_memops;
121 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
122 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
123 dst_vq->lock = &ctx->rga->mutex;
124 dst_vq->dev = ctx->rga->v4l2_dev.dev;
125
126 return vb2_queue_init(dst_vq);
127 }
128
rga_s_ctrl(struct v4l2_ctrl * ctrl)129 static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
130 {
131 struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
132 ctrl_handler);
133 unsigned long flags;
134
135 spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
136 switch (ctrl->id) {
137 case V4L2_CID_HFLIP:
138 ctx->hflip = ctrl->val;
139 break;
140 case V4L2_CID_VFLIP:
141 ctx->vflip = ctrl->val;
142 break;
143 case V4L2_CID_ROTATE:
144 ctx->rotate = ctrl->val;
145 break;
146 case V4L2_CID_BG_COLOR:
147 ctx->fill_color = ctrl->val;
148 break;
149 }
150 spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
151 return 0;
152 }
153
154 static const struct v4l2_ctrl_ops rga_ctrl_ops = {
155 .s_ctrl = rga_s_ctrl,
156 };
157
rga_setup_ctrls(struct rga_ctx * ctx)158 static int rga_setup_ctrls(struct rga_ctx *ctx)
159 {
160 struct rockchip_rga *rga = ctx->rga;
161
162 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
163
164 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
165 V4L2_CID_HFLIP, 0, 1, 1, 0);
166
167 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
168 V4L2_CID_VFLIP, 0, 1, 1, 0);
169
170 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
171 V4L2_CID_ROTATE, 0, 270, 90, 0);
172
173 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
174 V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
175
176 if (ctx->ctrl_handler.error) {
177 int err = ctx->ctrl_handler.error;
178
179 v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
180 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
181 return err;
182 }
183
184 return 0;
185 }
186
187 static struct rga_fmt formats[] = {
188 {
189 .fourcc = V4L2_PIX_FMT_ARGB32,
190 .color_swap = RGA_COLOR_ALPHA_SWAP,
191 .hw_format = RGA_COLOR_FMT_ABGR8888,
192 .depth = 32,
193 .uv_factor = 1,
194 .y_div = 1,
195 .x_div = 1,
196 },
197 {
198 .fourcc = V4L2_PIX_FMT_ABGR32,
199 .color_swap = RGA_COLOR_RB_SWAP,
200 .hw_format = RGA_COLOR_FMT_ABGR8888,
201 .depth = 32,
202 .uv_factor = 1,
203 .y_div = 1,
204 .x_div = 1,
205 },
206 {
207 .fourcc = V4L2_PIX_FMT_XBGR32,
208 .color_swap = RGA_COLOR_RB_SWAP,
209 .hw_format = RGA_COLOR_FMT_XBGR8888,
210 .depth = 32,
211 .uv_factor = 1,
212 .y_div = 1,
213 .x_div = 1,
214 },
215 {
216 .fourcc = V4L2_PIX_FMT_RGB24,
217 .color_swap = RGA_COLOR_NONE_SWAP,
218 .hw_format = RGA_COLOR_FMT_RGB888,
219 .depth = 24,
220 .uv_factor = 1,
221 .y_div = 1,
222 .x_div = 1,
223 },
224 {
225 .fourcc = V4L2_PIX_FMT_BGR24,
226 .color_swap = RGA_COLOR_RB_SWAP,
227 .hw_format = RGA_COLOR_FMT_RGB888,
228 .depth = 24,
229 .uv_factor = 1,
230 .y_div = 1,
231 .x_div = 1,
232 },
233 {
234 .fourcc = V4L2_PIX_FMT_ARGB444,
235 .color_swap = RGA_COLOR_RB_SWAP,
236 .hw_format = RGA_COLOR_FMT_ABGR4444,
237 .depth = 16,
238 .uv_factor = 1,
239 .y_div = 1,
240 .x_div = 1,
241 },
242 {
243 .fourcc = V4L2_PIX_FMT_ARGB555,
244 .color_swap = RGA_COLOR_RB_SWAP,
245 .hw_format = RGA_COLOR_FMT_ABGR1555,
246 .depth = 16,
247 .uv_factor = 1,
248 .y_div = 1,
249 .x_div = 1,
250 },
251 {
252 .fourcc = V4L2_PIX_FMT_RGB565,
253 .color_swap = RGA_COLOR_RB_SWAP,
254 .hw_format = RGA_COLOR_FMT_BGR565,
255 .depth = 16,
256 .uv_factor = 1,
257 .y_div = 1,
258 .x_div = 1,
259 },
260 {
261 .fourcc = V4L2_PIX_FMT_NV21,
262 .color_swap = RGA_COLOR_UV_SWAP,
263 .hw_format = RGA_COLOR_FMT_YUV420SP,
264 .depth = 12,
265 .uv_factor = 4,
266 .y_div = 2,
267 .x_div = 1,
268 },
269 {
270 .fourcc = V4L2_PIX_FMT_NV61,
271 .color_swap = RGA_COLOR_UV_SWAP,
272 .hw_format = RGA_COLOR_FMT_YUV422SP,
273 .depth = 16,
274 .uv_factor = 2,
275 .y_div = 1,
276 .x_div = 1,
277 },
278 {
279 .fourcc = V4L2_PIX_FMT_NV12,
280 .color_swap = RGA_COLOR_NONE_SWAP,
281 .hw_format = RGA_COLOR_FMT_YUV420SP,
282 .depth = 12,
283 .uv_factor = 4,
284 .y_div = 2,
285 .x_div = 1,
286 },
287 {
288 .fourcc = V4L2_PIX_FMT_NV16,
289 .color_swap = RGA_COLOR_NONE_SWAP,
290 .hw_format = RGA_COLOR_FMT_YUV422SP,
291 .depth = 16,
292 .uv_factor = 2,
293 .y_div = 1,
294 .x_div = 1,
295 },
296 {
297 .fourcc = V4L2_PIX_FMT_YUV420,
298 .color_swap = RGA_COLOR_NONE_SWAP,
299 .hw_format = RGA_COLOR_FMT_YUV420P,
300 .depth = 12,
301 .uv_factor = 4,
302 .y_div = 2,
303 .x_div = 2,
304 },
305 {
306 .fourcc = V4L2_PIX_FMT_YUV422P,
307 .color_swap = RGA_COLOR_NONE_SWAP,
308 .hw_format = RGA_COLOR_FMT_YUV422P,
309 .depth = 16,
310 .uv_factor = 2,
311 .y_div = 1,
312 .x_div = 2,
313 },
314 {
315 .fourcc = V4L2_PIX_FMT_YVU420,
316 .color_swap = RGA_COLOR_UV_SWAP,
317 .hw_format = RGA_COLOR_FMT_YUV420P,
318 .depth = 12,
319 .uv_factor = 4,
320 .y_div = 2,
321 .x_div = 2,
322 },
323 };
324
325 #define NUM_FORMATS ARRAY_SIZE(formats)
326
rga_fmt_find(struct v4l2_format * f)327 static struct rga_fmt *rga_fmt_find(struct v4l2_format *f)
328 {
329 unsigned int i;
330
331 for (i = 0; i < NUM_FORMATS; i++) {
332 if (formats[i].fourcc == f->fmt.pix.pixelformat)
333 return &formats[i];
334 }
335 return NULL;
336 }
337
338 static struct rga_frame def_frame = {
339 .width = DEFAULT_WIDTH,
340 .height = DEFAULT_HEIGHT,
341 .colorspace = V4L2_COLORSPACE_DEFAULT,
342 .crop.left = 0,
343 .crop.top = 0,
344 .crop.width = DEFAULT_WIDTH,
345 .crop.height = DEFAULT_HEIGHT,
346 .fmt = &formats[0],
347 };
348
rga_get_frame(struct rga_ctx * ctx,enum v4l2_buf_type type)349 struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
350 {
351 switch (type) {
352 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
353 return &ctx->in;
354 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
355 return &ctx->out;
356 default:
357 return ERR_PTR(-EINVAL);
358 }
359 }
360
rga_open(struct file * file)361 static int rga_open(struct file *file)
362 {
363 struct rockchip_rga *rga = video_drvdata(file);
364 struct rga_ctx *ctx = NULL;
365 int ret = 0;
366
367 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
368 if (!ctx)
369 return -ENOMEM;
370 ctx->rga = rga;
371 /* Set default formats */
372 ctx->in = def_frame;
373 ctx->out = def_frame;
374
375 if (mutex_lock_interruptible(&rga->mutex)) {
376 kfree(ctx);
377 return -ERESTARTSYS;
378 }
379 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
380 if (IS_ERR(ctx->fh.m2m_ctx)) {
381 ret = PTR_ERR(ctx->fh.m2m_ctx);
382 mutex_unlock(&rga->mutex);
383 kfree(ctx);
384 return ret;
385 }
386 v4l2_fh_init(&ctx->fh, video_devdata(file));
387 file->private_data = &ctx->fh;
388 v4l2_fh_add(&ctx->fh);
389
390 rga_setup_ctrls(ctx);
391
392 /* Write the default values to the ctx struct */
393 v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
394
395 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
396 mutex_unlock(&rga->mutex);
397
398 return 0;
399 }
400
rga_release(struct file * file)401 static int rga_release(struct file *file)
402 {
403 struct rga_ctx *ctx =
404 container_of(file->private_data, struct rga_ctx, fh);
405 struct rockchip_rga *rga = ctx->rga;
406
407 mutex_lock(&rga->mutex);
408
409 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
410
411 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
412 v4l2_fh_del(&ctx->fh);
413 v4l2_fh_exit(&ctx->fh);
414 kfree(ctx);
415
416 mutex_unlock(&rga->mutex);
417
418 return 0;
419 }
420
421 static const struct v4l2_file_operations rga_fops = {
422 .owner = THIS_MODULE,
423 .open = rga_open,
424 .release = rga_release,
425 .poll = v4l2_m2m_fop_poll,
426 .unlocked_ioctl = video_ioctl2,
427 .mmap = v4l2_m2m_fop_mmap,
428 };
429
430 static int
vidioc_querycap(struct file * file,void * priv,struct v4l2_capability * cap)431 vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
432 {
433 strscpy(cap->driver, RGA_NAME, sizeof(cap->driver));
434 strscpy(cap->card, "rockchip-rga", sizeof(cap->card));
435 strscpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
436
437 return 0;
438 }
439
vidioc_enum_fmt(struct file * file,void * prv,struct v4l2_fmtdesc * f)440 static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
441 {
442 struct rga_fmt *fmt;
443
444 if (f->index >= NUM_FORMATS)
445 return -EINVAL;
446
447 fmt = &formats[f->index];
448 f->pixelformat = fmt->fourcc;
449
450 return 0;
451 }
452
vidioc_g_fmt(struct file * file,void * prv,struct v4l2_format * f)453 static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
454 {
455 struct rga_ctx *ctx = prv;
456 struct vb2_queue *vq;
457 struct rga_frame *frm;
458
459 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
460 if (!vq)
461 return -EINVAL;
462 frm = rga_get_frame(ctx, f->type);
463 if (IS_ERR(frm))
464 return PTR_ERR(frm);
465
466 f->fmt.pix.width = frm->width;
467 f->fmt.pix.height = frm->height;
468 f->fmt.pix.field = V4L2_FIELD_NONE;
469 f->fmt.pix.pixelformat = frm->fmt->fourcc;
470 f->fmt.pix.bytesperline = frm->stride;
471 f->fmt.pix.sizeimage = frm->size;
472 f->fmt.pix.colorspace = frm->colorspace;
473
474 return 0;
475 }
476
vidioc_try_fmt(struct file * file,void * prv,struct v4l2_format * f)477 static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
478 {
479 struct rga_fmt *fmt;
480
481 fmt = rga_fmt_find(f);
482 if (!fmt) {
483 fmt = &formats[0];
484 f->fmt.pix.pixelformat = fmt->fourcc;
485 }
486
487 f->fmt.pix.field = V4L2_FIELD_NONE;
488
489 if (f->fmt.pix.width > MAX_WIDTH)
490 f->fmt.pix.width = MAX_WIDTH;
491 if (f->fmt.pix.height > MAX_HEIGHT)
492 f->fmt.pix.height = MAX_HEIGHT;
493
494 if (f->fmt.pix.width < MIN_WIDTH)
495 f->fmt.pix.width = MIN_WIDTH;
496 if (f->fmt.pix.height < MIN_HEIGHT)
497 f->fmt.pix.height = MIN_HEIGHT;
498
499 if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP)
500 f->fmt.pix.bytesperline = f->fmt.pix.width;
501 else
502 f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
503
504 f->fmt.pix.sizeimage =
505 f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3;
506
507 return 0;
508 }
509
vidioc_s_fmt(struct file * file,void * prv,struct v4l2_format * f)510 static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
511 {
512 struct rga_ctx *ctx = prv;
513 struct rockchip_rga *rga = ctx->rga;
514 struct vb2_queue *vq;
515 struct rga_frame *frm;
516 struct rga_fmt *fmt;
517 int ret = 0;
518
519 /* Adjust all values accordingly to the hardware capabilities
520 * and chosen format.
521 */
522 ret = vidioc_try_fmt(file, prv, f);
523 if (ret)
524 return ret;
525 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
526 if (vb2_is_busy(vq)) {
527 v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
528 return -EBUSY;
529 }
530 frm = rga_get_frame(ctx, f->type);
531 if (IS_ERR(frm))
532 return PTR_ERR(frm);
533 fmt = rga_fmt_find(f);
534 if (!fmt)
535 return -EINVAL;
536 frm->width = f->fmt.pix.width;
537 frm->height = f->fmt.pix.height;
538 frm->size = f->fmt.pix.sizeimage;
539 frm->fmt = fmt;
540 frm->stride = f->fmt.pix.bytesperline;
541 frm->colorspace = f->fmt.pix.colorspace;
542
543 /* Reset crop settings */
544 frm->crop.left = 0;
545 frm->crop.top = 0;
546 frm->crop.width = frm->width;
547 frm->crop.height = frm->height;
548
549 return 0;
550 }
551
vidioc_g_selection(struct file * file,void * prv,struct v4l2_selection * s)552 static int vidioc_g_selection(struct file *file, void *prv,
553 struct v4l2_selection *s)
554 {
555 struct rga_ctx *ctx = prv;
556 struct rga_frame *f;
557 bool use_frame = false;
558
559 f = rga_get_frame(ctx, s->type);
560 if (IS_ERR(f))
561 return PTR_ERR(f);
562
563 switch (s->target) {
564 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
565 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
566 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
567 return -EINVAL;
568 break;
569 case V4L2_SEL_TGT_CROP_DEFAULT:
570 case V4L2_SEL_TGT_CROP_BOUNDS:
571 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
572 return -EINVAL;
573 break;
574 case V4L2_SEL_TGT_COMPOSE:
575 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
576 return -EINVAL;
577 use_frame = true;
578 break;
579 case V4L2_SEL_TGT_CROP:
580 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
581 return -EINVAL;
582 use_frame = true;
583 break;
584 default:
585 return -EINVAL;
586 }
587
588 if (use_frame) {
589 s->r = f->crop;
590 } else {
591 s->r.left = 0;
592 s->r.top = 0;
593 s->r.width = f->width;
594 s->r.height = f->height;
595 }
596
597 return 0;
598 }
599
vidioc_s_selection(struct file * file,void * prv,struct v4l2_selection * s)600 static int vidioc_s_selection(struct file *file, void *prv,
601 struct v4l2_selection *s)
602 {
603 struct rga_ctx *ctx = prv;
604 struct rockchip_rga *rga = ctx->rga;
605 struct rga_frame *f;
606 int ret = 0;
607
608 f = rga_get_frame(ctx, s->type);
609 if (IS_ERR(f))
610 return PTR_ERR(f);
611
612 switch (s->target) {
613 case V4L2_SEL_TGT_COMPOSE:
614 /*
615 * COMPOSE target is only valid for capture buffer type, return
616 * error for output buffer type
617 */
618 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
619 return -EINVAL;
620 break;
621 case V4L2_SEL_TGT_CROP:
622 /*
623 * CROP target is only valid for output buffer type, return
624 * error for capture buffer type
625 */
626 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
627 return -EINVAL;
628 break;
629 /*
630 * bound and default crop/compose targets are invalid targets to
631 * try/set
632 */
633 default:
634 return -EINVAL;
635 }
636
637 if (s->r.top < 0 || s->r.left < 0) {
638 v4l2_dbg(debug, 1, &rga->v4l2_dev,
639 "doesn't support negative values for top & left.\n");
640 return -EINVAL;
641 }
642
643 if (s->r.left + s->r.width > f->width ||
644 s->r.top + s->r.height > f->height ||
645 s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
646 v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n");
647 return -EINVAL;
648 }
649
650 f->crop = s->r;
651
652 return ret;
653 }
654
655 static const struct v4l2_ioctl_ops rga_ioctl_ops = {
656 .vidioc_querycap = vidioc_querycap,
657
658 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
659 .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
660 .vidioc_try_fmt_vid_cap = vidioc_try_fmt,
661 .vidioc_s_fmt_vid_cap = vidioc_s_fmt,
662
663 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
664 .vidioc_g_fmt_vid_out = vidioc_g_fmt,
665 .vidioc_try_fmt_vid_out = vidioc_try_fmt,
666 .vidioc_s_fmt_vid_out = vidioc_s_fmt,
667
668 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
669 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
670 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
671 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
672 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
673 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
674 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
675
676 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
677 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
678
679 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
680 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
681
682 .vidioc_g_selection = vidioc_g_selection,
683 .vidioc_s_selection = vidioc_s_selection,
684 };
685
686 static const struct video_device rga_videodev = {
687 .name = "rockchip-rga",
688 .fops = &rga_fops,
689 .ioctl_ops = &rga_ioctl_ops,
690 .minor = -1,
691 .release = video_device_release,
692 .vfl_dir = VFL_DIR_M2M,
693 .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
694 };
695
rga_enable_clocks(struct rockchip_rga * rga)696 static int rga_enable_clocks(struct rockchip_rga *rga)
697 {
698 int ret;
699
700 ret = clk_prepare_enable(rga->sclk);
701 if (ret) {
702 dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
703 return ret;
704 }
705
706 ret = clk_prepare_enable(rga->aclk);
707 if (ret) {
708 dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
709 goto err_disable_sclk;
710 }
711
712 ret = clk_prepare_enable(rga->hclk);
713 if (ret) {
714 dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
715 goto err_disable_aclk;
716 }
717
718 return 0;
719
720 err_disable_sclk:
721 clk_disable_unprepare(rga->sclk);
722 err_disable_aclk:
723 clk_disable_unprepare(rga->aclk);
724
725 return ret;
726 }
727
rga_disable_clocks(struct rockchip_rga * rga)728 static void rga_disable_clocks(struct rockchip_rga *rga)
729 {
730 clk_disable_unprepare(rga->sclk);
731 clk_disable_unprepare(rga->hclk);
732 clk_disable_unprepare(rga->aclk);
733 }
734
rga_parse_dt(struct rockchip_rga * rga)735 static int rga_parse_dt(struct rockchip_rga *rga)
736 {
737 struct reset_control *core_rst, *axi_rst, *ahb_rst;
738
739 core_rst = devm_reset_control_get(rga->dev, "core");
740 if (IS_ERR(core_rst)) {
741 dev_err(rga->dev, "failed to get core reset controller\n");
742 return PTR_ERR(core_rst);
743 }
744
745 axi_rst = devm_reset_control_get(rga->dev, "axi");
746 if (IS_ERR(axi_rst)) {
747 dev_err(rga->dev, "failed to get axi reset controller\n");
748 return PTR_ERR(axi_rst);
749 }
750
751 ahb_rst = devm_reset_control_get(rga->dev, "ahb");
752 if (IS_ERR(ahb_rst)) {
753 dev_err(rga->dev, "failed to get ahb reset controller\n");
754 return PTR_ERR(ahb_rst);
755 }
756
757 reset_control_assert(core_rst);
758 udelay(1);
759 reset_control_deassert(core_rst);
760
761 reset_control_assert(axi_rst);
762 udelay(1);
763 reset_control_deassert(axi_rst);
764
765 reset_control_assert(ahb_rst);
766 udelay(1);
767 reset_control_deassert(ahb_rst);
768
769 rga->sclk = devm_clk_get(rga->dev, "sclk");
770 if (IS_ERR(rga->sclk)) {
771 dev_err(rga->dev, "failed to get sclk clock\n");
772 return PTR_ERR(rga->sclk);
773 }
774
775 rga->aclk = devm_clk_get(rga->dev, "aclk");
776 if (IS_ERR(rga->aclk)) {
777 dev_err(rga->dev, "failed to get aclk clock\n");
778 return PTR_ERR(rga->aclk);
779 }
780
781 rga->hclk = devm_clk_get(rga->dev, "hclk");
782 if (IS_ERR(rga->hclk)) {
783 dev_err(rga->dev, "failed to get hclk clock\n");
784 return PTR_ERR(rga->hclk);
785 }
786
787 return 0;
788 }
789
rga_probe(struct platform_device * pdev)790 static int rga_probe(struct platform_device *pdev)
791 {
792 struct rockchip_rga *rga;
793 struct video_device *vfd;
794 struct resource *res;
795 int ret = 0;
796 int irq;
797
798 if (!pdev->dev.of_node)
799 return -ENODEV;
800
801 rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
802 if (!rga)
803 return -ENOMEM;
804
805 rga->dev = &pdev->dev;
806 spin_lock_init(&rga->ctrl_lock);
807 mutex_init(&rga->mutex);
808
809 ret = rga_parse_dt(rga);
810 if (ret)
811 dev_err(&pdev->dev, "Unable to parse OF data\n");
812
813 pm_runtime_enable(rga->dev);
814
815 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
816
817 rga->regs = devm_ioremap_resource(rga->dev, res);
818 if (IS_ERR(rga->regs)) {
819 ret = PTR_ERR(rga->regs);
820 goto err_put_clk;
821 }
822
823 irq = platform_get_irq(pdev, 0);
824 if (irq < 0) {
825 ret = irq;
826 goto err_put_clk;
827 }
828
829 ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
830 dev_name(rga->dev), rga);
831 if (ret < 0) {
832 dev_err(rga->dev, "failed to request irq\n");
833 goto err_put_clk;
834 }
835
836 ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
837 if (ret)
838 goto err_put_clk;
839 vfd = video_device_alloc();
840 if (!vfd) {
841 v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
842 ret = -ENOMEM;
843 goto unreg_v4l2_dev;
844 }
845 *vfd = rga_videodev;
846 vfd->lock = &rga->mutex;
847 vfd->v4l2_dev = &rga->v4l2_dev;
848
849 video_set_drvdata(vfd, rga);
850 rga->vfd = vfd;
851
852 platform_set_drvdata(pdev, rga);
853 rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
854 if (IS_ERR(rga->m2m_dev)) {
855 v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
856 ret = PTR_ERR(rga->m2m_dev);
857 goto rel_vdev;
858 }
859
860 ret = pm_runtime_resume_and_get(rga->dev);
861 if (ret < 0)
862 goto rel_m2m;
863
864 rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
865 rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
866
867 v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
868 rga->version.major, rga->version.minor);
869
870 pm_runtime_put(rga->dev);
871
872 /* Create CMD buffer */
873 rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
874 &rga->cmdbuf_phy, GFP_KERNEL,
875 DMA_ATTR_WRITE_COMBINE);
876 if (!rga->cmdbuf_virt) {
877 ret = -ENOMEM;
878 goto rel_m2m;
879 }
880
881 rga->src_mmu_pages =
882 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
883 if (!rga->src_mmu_pages) {
884 ret = -ENOMEM;
885 goto free_dma;
886 }
887 rga->dst_mmu_pages =
888 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
889 if (!rga->dst_mmu_pages) {
890 ret = -ENOMEM;
891 goto free_src_pages;
892 }
893
894 def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
895 def_frame.size = def_frame.stride * def_frame.height;
896
897 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
898 if (ret) {
899 v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
900 goto free_dst_pages;
901 }
902
903 v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
904 vfd->name, video_device_node_name(vfd));
905
906 return 0;
907
908 free_dst_pages:
909 free_pages((unsigned long)rga->dst_mmu_pages, 3);
910 free_src_pages:
911 free_pages((unsigned long)rga->src_mmu_pages, 3);
912 free_dma:
913 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
914 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
915 rel_m2m:
916 v4l2_m2m_release(rga->m2m_dev);
917 rel_vdev:
918 video_device_release(vfd);
919 unreg_v4l2_dev:
920 v4l2_device_unregister(&rga->v4l2_dev);
921 err_put_clk:
922 pm_runtime_disable(rga->dev);
923
924 return ret;
925 }
926
rga_remove(struct platform_device * pdev)927 static int rga_remove(struct platform_device *pdev)
928 {
929 struct rockchip_rga *rga = platform_get_drvdata(pdev);
930
931 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
932 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
933
934 free_pages((unsigned long)rga->src_mmu_pages, 3);
935 free_pages((unsigned long)rga->dst_mmu_pages, 3);
936
937 v4l2_info(&rga->v4l2_dev, "Removing\n");
938
939 v4l2_m2m_release(rga->m2m_dev);
940 video_unregister_device(rga->vfd);
941 v4l2_device_unregister(&rga->v4l2_dev);
942
943 pm_runtime_disable(rga->dev);
944
945 return 0;
946 }
947
rga_runtime_suspend(struct device * dev)948 static int __maybe_unused rga_runtime_suspend(struct device *dev)
949 {
950 struct rockchip_rga *rga = dev_get_drvdata(dev);
951
952 rga_disable_clocks(rga);
953
954 return 0;
955 }
956
rga_runtime_resume(struct device * dev)957 static int __maybe_unused rga_runtime_resume(struct device *dev)
958 {
959 struct rockchip_rga *rga = dev_get_drvdata(dev);
960
961 return rga_enable_clocks(rga);
962 }
963
964 static const struct dev_pm_ops rga_pm = {
965 SET_RUNTIME_PM_OPS(rga_runtime_suspend,
966 rga_runtime_resume, NULL)
967 };
968
969 static const struct of_device_id rockchip_rga_match[] = {
970 {
971 .compatible = "rockchip,rk3288-rga",
972 },
973 {
974 .compatible = "rockchip,rk3399-rga",
975 },
976 {},
977 };
978
979 MODULE_DEVICE_TABLE(of, rockchip_rga_match);
980
981 static struct platform_driver rga_pdrv = {
982 .probe = rga_probe,
983 .remove = rga_remove,
984 .driver = {
985 .name = RGA_NAME,
986 .pm = &rga_pm,
987 .of_match_table = rockchip_rga_match,
988 },
989 };
990
991 module_platform_driver(rga_pdrv);
992
993 MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
994 MODULE_DESCRIPTION("Rockchip Raster 2d Graphic Acceleration Unit");
995 MODULE_LICENSE("GPL");
996