1 /*
2 * tps80031.c -- TI TPS80031/TPS80032 mfd core driver.
3 *
4 * MFD core driver for TI TPS80031/TPS80032 Fully Integrated
5 * Power Management with Power Path and Battery Charger
6 *
7 * Copyright (c) 2012, NVIDIA Corporation.
8 *
9 * Author: Laxman Dewangan <ldewangan@nvidia.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
16 * whether express or implied; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
23 * 02111-1307, USA
24 */
25
26 #include <linux/err.h>
27 #include <linux/i2c.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/mfd/core.h>
32 #include <linux/mfd/tps80031.h>
33 #include <linux/pm.h>
34 #include <linux/regmap.h>
35 #include <linux/slab.h>
36
37 static const struct resource tps80031_rtc_resources[] = {
38 DEFINE_RES_IRQ(TPS80031_INT_RTC_ALARM),
39 };
40
41 /* TPS80031 sub mfd devices */
42 static const struct mfd_cell tps80031_cell[] = {
43 {
44 .name = "tps80031-pmic",
45 },
46 {
47 .name = "tps80031-clock",
48 },
49 {
50 .name = "tps80031-rtc",
51 .num_resources = ARRAY_SIZE(tps80031_rtc_resources),
52 .resources = tps80031_rtc_resources,
53 },
54 {
55 .name = "tps80031-gpadc",
56 },
57 {
58 .name = "tps80031-fuel-gauge",
59 },
60 {
61 .name = "tps80031-charger",
62 },
63 };
64
65 static int tps80031_slave_address[TPS80031_NUM_SLAVES] = {
66 TPS80031_I2C_ID0_ADDR,
67 TPS80031_I2C_ID1_ADDR,
68 TPS80031_I2C_ID2_ADDR,
69 TPS80031_I2C_ID3_ADDR,
70 };
71
72 struct tps80031_pupd_data {
73 u8 reg;
74 u8 pullup_bit;
75 u8 pulldown_bit;
76 };
77
78 #define TPS80031_IRQ(_reg, _mask) \
79 { \
80 .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \
81 TPS80031_INT_MSK_LINE_A, \
82 .mask = BIT(_mask), \
83 }
84
85 static const struct regmap_irq tps80031_main_irqs[] = {
86 [TPS80031_INT_PWRON] = TPS80031_IRQ(A, 0),
87 [TPS80031_INT_RPWRON] = TPS80031_IRQ(A, 1),
88 [TPS80031_INT_SYS_VLOW] = TPS80031_IRQ(A, 2),
89 [TPS80031_INT_RTC_ALARM] = TPS80031_IRQ(A, 3),
90 [TPS80031_INT_RTC_PERIOD] = TPS80031_IRQ(A, 4),
91 [TPS80031_INT_HOT_DIE] = TPS80031_IRQ(A, 5),
92 [TPS80031_INT_VXX_SHORT] = TPS80031_IRQ(A, 6),
93 [TPS80031_INT_SPDURATION] = TPS80031_IRQ(A, 7),
94 [TPS80031_INT_WATCHDOG] = TPS80031_IRQ(B, 0),
95 [TPS80031_INT_BAT] = TPS80031_IRQ(B, 1),
96 [TPS80031_INT_SIM] = TPS80031_IRQ(B, 2),
97 [TPS80031_INT_MMC] = TPS80031_IRQ(B, 3),
98 [TPS80031_INT_RES] = TPS80031_IRQ(B, 4),
99 [TPS80031_INT_GPADC_RT] = TPS80031_IRQ(B, 5),
100 [TPS80031_INT_GPADC_SW2_EOC] = TPS80031_IRQ(B, 6),
101 [TPS80031_INT_CC_AUTOCAL] = TPS80031_IRQ(B, 7),
102 [TPS80031_INT_ID_WKUP] = TPS80031_IRQ(C, 0),
103 [TPS80031_INT_VBUSS_WKUP] = TPS80031_IRQ(C, 1),
104 [TPS80031_INT_ID] = TPS80031_IRQ(C, 2),
105 [TPS80031_INT_VBUS] = TPS80031_IRQ(C, 3),
106 [TPS80031_INT_CHRG_CTRL] = TPS80031_IRQ(C, 4),
107 [TPS80031_INT_EXT_CHRG] = TPS80031_IRQ(C, 5),
108 [TPS80031_INT_INT_CHRG] = TPS80031_IRQ(C, 6),
109 [TPS80031_INT_RES2] = TPS80031_IRQ(C, 7),
110 };
111
112 static struct regmap_irq_chip tps80031_irq_chip = {
113 .name = "tps80031",
114 .irqs = tps80031_main_irqs,
115 .num_irqs = ARRAY_SIZE(tps80031_main_irqs),
116 .num_regs = 3,
117 .status_base = TPS80031_INT_STS_A,
118 .mask_base = TPS80031_INT_MSK_LINE_A,
119 };
120
121 #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit) \
122 { \
123 .reg = TPS80031_CFG_INPUT_PUPD##_reg, \
124 .pulldown_bit = _pulldown_bit, \
125 .pullup_bit = _pullup_bit, \
126 }
127
128 static const struct tps80031_pupd_data tps80031_pupds[] = {
129 [TPS80031_PREQ1] = PUPD_DATA(1, BIT(0), BIT(1)),
130 [TPS80031_PREQ2A] = PUPD_DATA(1, BIT(2), BIT(3)),
131 [TPS80031_PREQ2B] = PUPD_DATA(1, BIT(4), BIT(5)),
132 [TPS80031_PREQ2C] = PUPD_DATA(1, BIT(6), BIT(7)),
133 [TPS80031_PREQ3] = PUPD_DATA(2, BIT(0), BIT(1)),
134 [TPS80031_NRES_WARM] = PUPD_DATA(2, 0, BIT(2)),
135 [TPS80031_PWM_FORCE] = PUPD_DATA(2, BIT(5), 0),
136 [TPS80031_CHRG_EXT_CHRG_STATZ] = PUPD_DATA(2, 0, BIT(6)),
137 [TPS80031_SIM] = PUPD_DATA(3, BIT(0), BIT(1)),
138 [TPS80031_MMC] = PUPD_DATA(3, BIT(2), BIT(3)),
139 [TPS80031_GPADC_START] = PUPD_DATA(3, BIT(4), 0),
140 [TPS80031_DVSI2C_SCL] = PUPD_DATA(4, 0, BIT(0)),
141 [TPS80031_DVSI2C_SDA] = PUPD_DATA(4, 0, BIT(1)),
142 [TPS80031_CTLI2C_SCL] = PUPD_DATA(4, 0, BIT(2)),
143 [TPS80031_CTLI2C_SDA] = PUPD_DATA(4, 0, BIT(3)),
144 };
145 static struct tps80031 *tps80031_power_off_dev;
146
tps80031_ext_power_req_config(struct device * dev,unsigned long ext_ctrl_flag,int preq_bit,int state_reg_add,int trans_reg_add)147 int tps80031_ext_power_req_config(struct device *dev,
148 unsigned long ext_ctrl_flag, int preq_bit,
149 int state_reg_add, int trans_reg_add)
150 {
151 u8 res_ass_reg = 0;
152 int preq_mask_bit = 0;
153 int ret;
154
155 if (!(ext_ctrl_flag & TPS80031_EXT_PWR_REQ))
156 return 0;
157
158 if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ1) {
159 res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3);
160 preq_mask_bit = 5;
161 } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ2) {
162 res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3);
163 preq_mask_bit = 6;
164 } else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ3) {
165 res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3);
166 preq_mask_bit = 7;
167 }
168
169 /* Configure REQ_ASS registers */
170 ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1, res_ass_reg,
171 BIT(preq_bit & 0x7));
172 if (ret < 0) {
173 dev_err(dev, "reg 0x%02x setbit failed, err = %d\n",
174 res_ass_reg, ret);
175 return ret;
176 }
177
178 /* Unmask the PREQ */
179 ret = tps80031_clr_bits(dev, TPS80031_SLAVE_ID1,
180 TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit));
181 if (ret < 0) {
182 dev_err(dev, "reg 0x%02x clrbit failed, err = %d\n",
183 TPS80031_PHOENIX_MSK_TRANSITION, ret);
184 return ret;
185 }
186
187 /* Switch regulator control to resource now */
188 if (ext_ctrl_flag & (TPS80031_PWR_REQ_INPUT_PREQ2 |
189 TPS80031_PWR_REQ_INPUT_PREQ3)) {
190 ret = tps80031_update(dev, TPS80031_SLAVE_ID1, state_reg_add,
191 0x0, TPS80031_STATE_MASK);
192 if (ret < 0)
193 dev_err(dev, "reg 0x%02x update failed, err = %d\n",
194 state_reg_add, ret);
195 } else {
196 ret = tps80031_update(dev, TPS80031_SLAVE_ID1, trans_reg_add,
197 TPS80031_TRANS_SLEEP_OFF,
198 TPS80031_TRANS_SLEEP_MASK);
199 if (ret < 0)
200 dev_err(dev, "reg 0x%02x update failed, err = %d\n",
201 trans_reg_add, ret);
202 }
203 return ret;
204 }
205 EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config);
206
tps80031_power_off(void)207 static void tps80031_power_off(void)
208 {
209 dev_info(tps80031_power_off_dev->dev, "switching off PMU\n");
210 tps80031_write(tps80031_power_off_dev->dev, TPS80031_SLAVE_ID1,
211 TPS80031_PHOENIX_DEV_ON, TPS80031_DEVOFF);
212 }
213
tps80031_pupd_init(struct tps80031 * tps80031,struct tps80031_platform_data * pdata)214 static void tps80031_pupd_init(struct tps80031 *tps80031,
215 struct tps80031_platform_data *pdata)
216 {
217 struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data;
218 int data_size = pdata->pupd_init_data_size;
219 int i;
220
221 for (i = 0; i < data_size; ++i) {
222 struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i];
223 const struct tps80031_pupd_data *pupd =
224 &tps80031_pupds[pupd_init->input_pin];
225 u8 update_value = 0;
226 u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit;
227
228 if (pupd_init->setting == TPS80031_PUPD_PULLDOWN)
229 update_value = pupd->pulldown_bit;
230 else if (pupd_init->setting == TPS80031_PUPD_PULLUP)
231 update_value = pupd->pullup_bit;
232
233 tps80031_update(tps80031->dev, TPS80031_SLAVE_ID1, pupd->reg,
234 update_value, update_mask);
235 }
236 }
237
tps80031_init_ext_control(struct tps80031 * tps80031,struct tps80031_platform_data * pdata)238 static int tps80031_init_ext_control(struct tps80031 *tps80031,
239 struct tps80031_platform_data *pdata)
240 {
241 struct device *dev = tps80031->dev;
242 int ret;
243 int i;
244
245 /* Clear all external control for this rail */
246 for (i = 0; i < 9; ++i) {
247 ret = tps80031_write(dev, TPS80031_SLAVE_ID1,
248 TPS80031_PREQ1_RES_ASS_A + i, 0);
249 if (ret < 0) {
250 dev_err(dev, "reg 0x%02x write failed, err = %d\n",
251 TPS80031_PREQ1_RES_ASS_A + i, ret);
252 return ret;
253 }
254 }
255
256 /* Mask the PREQ */
257 ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1,
258 TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5);
259 if (ret < 0) {
260 dev_err(dev, "reg 0x%02x set_bits failed, err = %d\n",
261 TPS80031_PHOENIX_MSK_TRANSITION, ret);
262 return ret;
263 }
264 return ret;
265 }
266
tps80031_irq_init(struct tps80031 * tps80031,int irq,int irq_base)267 static int tps80031_irq_init(struct tps80031 *tps80031, int irq, int irq_base)
268 {
269 struct device *dev = tps80031->dev;
270 int i, ret;
271
272 /*
273 * The MASK register used for updating status register when
274 * interrupt occurs and LINE register used to pass the status
275 * to actual interrupt line. As per datasheet:
276 * When INT_MSK_LINE [i] is set to 1, the associated interrupt
277 * number i is INT line masked, which means that no interrupt is
278 * generated on the INT line.
279 * When INT_MSK_LINE [i] is set to 0, the associated interrupt
280 * number i is line enabled: An interrupt is generated on the
281 * INT line.
282 * In any case, the INT_STS [i] status bit may or may not be updated,
283 * only linked to the INT_MSK_STS [i] configuration register bit.
284 *
285 * When INT_MSK_STS [i] is set to 1, the associated interrupt number
286 * i is status masked, which means that no interrupt is stored in
287 * the INT_STS[i] status bit. Note that no interrupt number i is
288 * generated on the INT line, even if the INT_MSK_LINE [i] register
289 * bit is set to 0.
290 * When INT_MSK_STS [i] is set to 0, the associated interrupt number i
291 * is status enabled: An interrupt status is updated in the INT_STS [i]
292 * register. The interrupt may or may not be generated on the INT line,
293 * depending on the INT_MSK_LINE [i] configuration register bit.
294 */
295 for (i = 0; i < 3; i++)
296 tps80031_write(dev, TPS80031_SLAVE_ID2,
297 TPS80031_INT_MSK_STS_A + i, 0x00);
298
299 ret = regmap_add_irq_chip(tps80031->regmap[TPS80031_SLAVE_ID2], irq,
300 IRQF_ONESHOT, irq_base,
301 &tps80031_irq_chip, &tps80031->irq_data);
302 if (ret < 0) {
303 dev_err(dev, "add irq failed, err = %d\n", ret);
304 return ret;
305 }
306 return ret;
307 }
308
rd_wr_reg_id0(struct device * dev,unsigned int reg)309 static bool rd_wr_reg_id0(struct device *dev, unsigned int reg)
310 {
311 switch (reg) {
312 case TPS80031_SMPS1_CFG_FORCE ... TPS80031_SMPS2_CFG_VOLTAGE:
313 return true;
314 default:
315 return false;
316 }
317 }
318
rd_wr_reg_id1(struct device * dev,unsigned int reg)319 static bool rd_wr_reg_id1(struct device *dev, unsigned int reg)
320 {
321 switch (reg) {
322 case TPS80031_SECONDS_REG ... TPS80031_RTC_RESET_STATUS_REG:
323 case TPS80031_VALIDITY0 ... TPS80031_VALIDITY7:
324 case TPS80031_PHOENIX_START_CONDITION ... TPS80031_KEY_PRESS_DUR_CFG:
325 case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
326 case TPS80031_BROADCAST_ADDR_ALL ... TPS80031_BROADCAST_ADDR_CLK_RST:
327 case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
328 case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
329 case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
330 case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
331 case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
332 case TPS80031_BACKUP_REG:
333 return true;
334 default:
335 return false;
336 }
337 }
338
is_volatile_reg_id1(struct device * dev,unsigned int reg)339 static bool is_volatile_reg_id1(struct device *dev, unsigned int reg)
340 {
341 switch (reg) {
342 case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE:
343 case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE:
344 case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE:
345 case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C:
346 case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING:
347 case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD:
348 return true;
349 default:
350 return false;
351 }
352 }
353
rd_wr_reg_id2(struct device * dev,unsigned int reg)354 static bool rd_wr_reg_id2(struct device *dev, unsigned int reg)
355 {
356 switch (reg) {
357 case TPS80031_USB_VENDOR_ID_LSB ... TPS80031_USB_OTG_REVISION:
358 case TPS80031_GPADC_CTRL ... TPS80031_CTRL_P1:
359 case TPS80031_RTCH0_LSB ... TPS80031_GPCH0_MSB:
360 case TPS80031_TOGGLE1 ... TPS80031_VIBMODE:
361 case TPS80031_PWM1ON ... TPS80031_PWM2OFF:
362 case TPS80031_FG_REG_00 ... TPS80031_FG_REG_11:
363 case TPS80031_INT_STS_A ... TPS80031_INT_MSK_STS_C:
364 case TPS80031_CONTROLLER_CTRL2 ... TPS80031_LED_PWM_CTRL2:
365 return true;
366 default:
367 return false;
368 }
369 }
370
rd_wr_reg_id3(struct device * dev,unsigned int reg)371 static bool rd_wr_reg_id3(struct device *dev, unsigned int reg)
372 {
373 switch (reg) {
374 case TPS80031_GPADC_TRIM0 ... TPS80031_GPADC_TRIM18:
375 return true;
376 default:
377 return false;
378 }
379 }
380
381 static const struct regmap_config tps80031_regmap_configs[] = {
382 {
383 .reg_bits = 8,
384 .val_bits = 8,
385 .writeable_reg = rd_wr_reg_id0,
386 .readable_reg = rd_wr_reg_id0,
387 .max_register = TPS80031_MAX_REGISTER,
388 },
389 {
390 .reg_bits = 8,
391 .val_bits = 8,
392 .writeable_reg = rd_wr_reg_id1,
393 .readable_reg = rd_wr_reg_id1,
394 .volatile_reg = is_volatile_reg_id1,
395 .max_register = TPS80031_MAX_REGISTER,
396 },
397 {
398 .reg_bits = 8,
399 .val_bits = 8,
400 .writeable_reg = rd_wr_reg_id2,
401 .readable_reg = rd_wr_reg_id2,
402 .max_register = TPS80031_MAX_REGISTER,
403 },
404 {
405 .reg_bits = 8,
406 .val_bits = 8,
407 .writeable_reg = rd_wr_reg_id3,
408 .readable_reg = rd_wr_reg_id3,
409 .max_register = TPS80031_MAX_REGISTER,
410 },
411 };
412
tps80031_probe(struct i2c_client * client,const struct i2c_device_id * id)413 static int tps80031_probe(struct i2c_client *client,
414 const struct i2c_device_id *id)
415 {
416 struct tps80031_platform_data *pdata = dev_get_platdata(&client->dev);
417 struct tps80031 *tps80031;
418 int ret;
419 uint8_t es_version;
420 uint8_t ep_ver;
421 int i;
422
423 if (!pdata) {
424 dev_err(&client->dev, "tps80031 requires platform data\n");
425 return -EINVAL;
426 }
427
428 tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL);
429 if (!tps80031)
430 return -ENOMEM;
431
432 for (i = 0; i < TPS80031_NUM_SLAVES; i++) {
433 if (tps80031_slave_address[i] == client->addr)
434 tps80031->clients[i] = client;
435 else
436 tps80031->clients[i] = devm_i2c_new_dummy_device(&client->dev,
437 client->adapter, tps80031_slave_address[i]);
438 if (IS_ERR(tps80031->clients[i])) {
439 dev_err(&client->dev, "can't attach client %d\n", i);
440 return PTR_ERR(tps80031->clients[i]);
441 }
442
443 i2c_set_clientdata(tps80031->clients[i], tps80031);
444 tps80031->regmap[i] = devm_regmap_init_i2c(tps80031->clients[i],
445 &tps80031_regmap_configs[i]);
446 if (IS_ERR(tps80031->regmap[i])) {
447 ret = PTR_ERR(tps80031->regmap[i]);
448 dev_err(&client->dev,
449 "regmap %d init failed, err %d\n", i, ret);
450 return ret;
451 }
452 }
453
454 ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
455 TPS80031_JTAGVERNUM, &es_version);
456 if (ret < 0) {
457 dev_err(&client->dev,
458 "Silicon version number read failed: %d\n", ret);
459 return ret;
460 }
461
462 ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3,
463 TPS80031_EPROM_REV, &ep_ver);
464 if (ret < 0) {
465 dev_err(&client->dev,
466 "Silicon eeprom version read failed: %d\n", ret);
467 return ret;
468 }
469
470 dev_info(&client->dev, "ES version 0x%02x and EPROM version 0x%02x\n",
471 es_version, ep_ver);
472 tps80031->es_version = es_version;
473 tps80031->dev = &client->dev;
474 i2c_set_clientdata(client, tps80031);
475 tps80031->chip_info = id->driver_data;
476
477 ret = tps80031_irq_init(tps80031, client->irq, pdata->irq_base);
478 if (ret) {
479 dev_err(&client->dev, "IRQ init failed: %d\n", ret);
480 return ret;
481 }
482
483 tps80031_pupd_init(tps80031, pdata);
484
485 tps80031_init_ext_control(tps80031, pdata);
486
487 ret = mfd_add_devices(tps80031->dev, -1,
488 tps80031_cell, ARRAY_SIZE(tps80031_cell),
489 NULL, 0,
490 regmap_irq_get_domain(tps80031->irq_data));
491 if (ret < 0) {
492 dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
493 goto fail_mfd_add;
494 }
495
496 if (pdata->use_power_off && !pm_power_off) {
497 tps80031_power_off_dev = tps80031;
498 pm_power_off = tps80031_power_off;
499 }
500 return 0;
501
502 fail_mfd_add:
503 regmap_del_irq_chip(client->irq, tps80031->irq_data);
504 return ret;
505 }
506
507 static const struct i2c_device_id tps80031_id_table[] = {
508 { "tps80031", TPS80031 },
509 { "tps80032", TPS80032 },
510 { }
511 };
512
513 static struct i2c_driver tps80031_driver = {
514 .driver = {
515 .name = "tps80031",
516 .suppress_bind_attrs = true,
517 },
518 .probe = tps80031_probe,
519 .id_table = tps80031_id_table,
520 };
521
tps80031_init(void)522 static int __init tps80031_init(void)
523 {
524 return i2c_add_driver(&tps80031_driver);
525 }
526 subsys_initcall(tps80031_init);
527