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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
3  *
4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5  *
6  * Author:
7  *   Wei WANG <wei_wang@realsil.com.cn>
8  */
9 
10 #include <linux/module.h>
11 #include <linux/delay.h>
12 #include <linux/rtsx_pci.h>
13 
14 #include "rtsx_pcr.h"
15 
rts5249_get_ic_version(struct rtsx_pcr * pcr)16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
17 {
18 	u8 val;
19 
20 	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
21 	return val & 0x0F;
22 }
23 
rts5249_fill_driving(struct rtsx_pcr * pcr,u8 voltage)24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
25 {
26 	u8 driving_3v3[4][3] = {
27 		{0x11, 0x11, 0x18},
28 		{0x55, 0x55, 0x5C},
29 		{0xFF, 0xFF, 0xFF},
30 		{0x96, 0x96, 0x96},
31 	};
32 	u8 driving_1v8[4][3] = {
33 		{0xC4, 0xC4, 0xC4},
34 		{0x3C, 0x3C, 0x3C},
35 		{0xFE, 0xFE, 0xFE},
36 		{0xB3, 0xB3, 0xB3},
37 	};
38 	u8 (*driving)[3], drive_sel;
39 
40 	if (voltage == OUTPUT_3V3) {
41 		driving = driving_3v3;
42 		drive_sel = pcr->sd30_drive_sel_3v3;
43 	} else {
44 		driving = driving_1v8;
45 		drive_sel = pcr->sd30_drive_sel_1v8;
46 	}
47 
48 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
49 			0xFF, driving[drive_sel][0]);
50 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
51 			0xFF, driving[drive_sel][1]);
52 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
53 			0xFF, driving[drive_sel][2]);
54 }
55 
rtsx_base_fetch_vendor_settings(struct rtsx_pcr * pcr)56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
57 {
58 	struct pci_dev *pdev = pcr->pci;
59 	u32 reg;
60 
61 	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
62 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
63 
64 	if (!rtsx_vendor_setting_valid(reg)) {
65 		pcr_dbg(pcr, "skip fetch vendor setting\n");
66 		return;
67 	}
68 
69 	pcr->aspm_en = rtsx_reg_to_aspm(reg);
70 	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
71 	pcr->card_drive_sel &= 0x3F;
72 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
73 
74 	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
75 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
76 
77 	pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg);
78 
79 	if (rtsx_check_mmc_support(reg))
80 		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
81 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
82 	if (rtsx_reg_check_reverse_socket(reg))
83 		pcr->flags |= PCR_REVERSE_SOCKET;
84 }
85 
rts5249_init_from_cfg(struct rtsx_pcr * pcr)86 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
87 {
88 	struct rtsx_cr_option *option = &(pcr->option);
89 
90 	if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
91 		if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
92 				| PM_L1_1_EN | PM_L1_2_EN))
93 			rtsx_pci_disable_oobs_polling(pcr);
94 		else
95 			rtsx_pci_enable_oobs_polling(pcr);
96 	}
97 
98 	if (option->ltr_en) {
99 		if (option->ltr_enabled)
100 			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
101 	}
102 }
103 
rts52xa_save_content_from_efuse(struct rtsx_pcr * pcr)104 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
105 {
106 	u8 cnt, sv;
107 	u16 j = 0;
108 	u8 tmp;
109 	u8 val;
110 	int i;
111 
112 	rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
113 				REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
114 	udelay(1);
115 
116 	pcr_dbg(pcr, "Enable efuse por!");
117 	pcr_dbg(pcr, "save efuse to autoload");
118 
119 	rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
120 	rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
121 				REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
122 	/* Wait transfer end */
123 	for (j = 0; j < 1024; j++) {
124 		rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
125 		if ((tmp & 0x80) == 0)
126 			break;
127 	}
128 	rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
129 	cnt = val & 0x0F;
130 	sv = val & 0x10;
131 
132 	if (sv) {
133 		for (i = 0; i < 4; i++) {
134 			rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
135 				REG_EFUSE_ADD_MASK, 0x04 + i);
136 			rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
137 				REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
138 			/* Wait transfer end */
139 			for (j = 0; j < 1024; j++) {
140 				rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
141 				if ((tmp & 0x80) == 0)
142 					break;
143 			}
144 			rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
145 			rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
146 		}
147 	} else {
148 		rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
149 		rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
150 		rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
151 		rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
152 	}
153 
154 	for (i = 0; i < cnt * 4; i++) {
155 		if (sv)
156 			rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
157 				REG_EFUSE_ADD_MASK, 0x08 + i);
158 		else
159 			rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
160 				REG_EFUSE_ADD_MASK, 0x04 + i);
161 		rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
162 				REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
163 		/* Wait transfer end */
164 		for (j = 0; j < 1024; j++) {
165 			rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
166 			if ((tmp & 0x80) == 0)
167 				break;
168 		}
169 		rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
170 		rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
171 	}
172 	rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
173 	rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
174 		REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
175 	pcr_dbg(pcr, "Disable efuse por!");
176 }
177 
rts52xa_save_content_to_autoload_space(struct rtsx_pcr * pcr)178 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
179 {
180 	u8 val;
181 
182 	rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
183 	if (val & 0x02) {
184 		rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
185 		if (val & RTS525A_LOAD_BIOS_FLAG) {
186 			rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
187 				RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
188 
189 			rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
190 				REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
191 
192 			pcr_dbg(pcr, "Power ON efuse!");
193 			mdelay(1);
194 			rts52xa_save_content_from_efuse(pcr);
195 		} else {
196 			rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
197 			if (!(val & 0x08))
198 				rts52xa_save_content_from_efuse(pcr);
199 		}
200 	} else {
201 		pcr_dbg(pcr, "Load from autoload");
202 		rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
203 		rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
204 		rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
205 		rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
206 		rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
207 	}
208 }
209 
rts5249_extra_init_hw(struct rtsx_pcr * pcr)210 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
211 {
212 	struct rtsx_cr_option *option = &(pcr->option);
213 
214 	rts5249_init_from_cfg(pcr);
215 
216 	rtsx_pci_init_cmd(pcr);
217 
218 	if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
219 		rts52xa_save_content_to_autoload_space(pcr);
220 
221 	/* Rest L1SUB Config */
222 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
223 	/* Configure GPIO as output */
224 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
225 	/* Reset ASPM state to default value */
226 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
227 	/* Switch LDO3318 source from DV33 to card_3v3 */
228 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
229 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
230 	/* LED shine disabled, set initial shine cycle period */
231 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
232 	/* Configure driving */
233 	rts5249_fill_driving(pcr, OUTPUT_3V3);
234 	if (pcr->flags & PCR_REVERSE_SOCKET)
235 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
236 	else
237 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
238 
239 	rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
240 
241 	if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
242 		rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
243 
244 	if (pcr->rtd3_en) {
245 		if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
246 			rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01);
247 			rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30);
248 		} else {
249 			rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01);
250 			rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33);
251 		}
252 	} else {
253 		if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
254 			rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
255 			rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
256 		} else {
257 			rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
258 			rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
259 		}
260 	}
261 
262 
263 	/*
264 	 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
265 	 * to drive low, and we forcibly request clock.
266 	 */
267 	if (option->force_clkreq_0)
268 		rtsx_pci_write_register(pcr, PETXCFG,
269 			FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
270 	else
271 		rtsx_pci_write_register(pcr, PETXCFG,
272 			FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
273 
274 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
275 	if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
276 		rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
277 				REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
278 		pcr_dbg(pcr, "Power OFF efuse!");
279 	}
280 
281 	return 0;
282 }
283 
rts5249_optimize_phy(struct rtsx_pcr * pcr)284 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
285 {
286 	int err;
287 
288 	err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
289 	if (err < 0)
290 		return err;
291 
292 	err = rtsx_pci_write_phy_register(pcr, PHY_REV,
293 			PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
294 			PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
295 			PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
296 			PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
297 			PHY_REV_STOP_CLKWR);
298 	if (err < 0)
299 		return err;
300 
301 	msleep(1);
302 
303 	err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
304 			PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
305 			PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
306 	if (err < 0)
307 		return err;
308 
309 	err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
310 			PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
311 			PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
312 			PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
313 	if (err < 0)
314 		return err;
315 
316 	err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
317 			PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
318 			PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
319 			PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
320 	if (err < 0)
321 		return err;
322 
323 	err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
324 			PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
325 			PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
326 			PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
327 			PHY_FLD4_BER_CHK_EN);
328 	if (err < 0)
329 		return err;
330 	err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
331 			PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
332 	if (err < 0)
333 		return err;
334 	err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
335 			PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
336 	if (err < 0)
337 		return err;
338 	err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
339 			PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
340 			PHY_FLD3_RXDELINK);
341 	if (err < 0)
342 		return err;
343 
344 	return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
345 			PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
346 			PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
347 			PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
348 }
349 
rtsx_base_turn_on_led(struct rtsx_pcr * pcr)350 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
351 {
352 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
353 }
354 
rtsx_base_turn_off_led(struct rtsx_pcr * pcr)355 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
356 {
357 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
358 }
359 
rtsx_base_enable_auto_blink(struct rtsx_pcr * pcr)360 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
361 {
362 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
363 }
364 
rtsx_base_disable_auto_blink(struct rtsx_pcr * pcr)365 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
366 {
367 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
368 }
369 
rtsx_base_card_power_on(struct rtsx_pcr * pcr,int card)370 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
371 {
372 	int err;
373 	struct rtsx_cr_option *option = &pcr->option;
374 
375 	if (option->ocp_en)
376 		rtsx_pci_enable_ocp(pcr);
377 
378 	rtsx_pci_init_cmd(pcr);
379 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
380 			SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
381 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
382 			LDO3318_PWR_MASK, 0x02);
383 	err = rtsx_pci_send_cmd(pcr, 100);
384 	if (err < 0)
385 		return err;
386 
387 	msleep(5);
388 
389 	rtsx_pci_init_cmd(pcr);
390 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
391 			SD_POWER_MASK, SD_VCC_POWER_ON);
392 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
393 			LDO3318_PWR_MASK, 0x06);
394 	return rtsx_pci_send_cmd(pcr, 100);
395 }
396 
rtsx_base_card_power_off(struct rtsx_pcr * pcr,int card)397 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
398 {
399 	struct rtsx_cr_option *option = &pcr->option;
400 
401 	if (option->ocp_en)
402 		rtsx_pci_disable_ocp(pcr);
403 
404 	rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
405 
406 	rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
407 	return 0;
408 }
409 
rtsx_base_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)410 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
411 {
412 	int err;
413 	u16 append;
414 
415 	switch (voltage) {
416 	case OUTPUT_3V3:
417 		err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
418 			PHY_TUNE_VOLTAGE_3V3);
419 		if (err < 0)
420 			return err;
421 		break;
422 	case OUTPUT_1V8:
423 		append = PHY_TUNE_D18_1V8;
424 		if (CHK_PCI_PID(pcr, 0x5249)) {
425 			err = rtsx_pci_update_phy(pcr, PHY_BACR,
426 				PHY_BACR_BASIC_MASK, 0);
427 			if (err < 0)
428 				return err;
429 			append = PHY_TUNE_D18_1V7;
430 		}
431 
432 		err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
433 			append);
434 		if (err < 0)
435 			return err;
436 		break;
437 	default:
438 		pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
439 		return -EINVAL;
440 	}
441 
442 	/* set pad drive */
443 	rtsx_pci_init_cmd(pcr);
444 	rts5249_fill_driving(pcr, voltage);
445 	return rtsx_pci_send_cmd(pcr, 100);
446 }
447 
448 static const struct pcr_ops rts5249_pcr_ops = {
449 	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
450 	.extra_init_hw = rts5249_extra_init_hw,
451 	.optimize_phy = rts5249_optimize_phy,
452 	.turn_on_led = rtsx_base_turn_on_led,
453 	.turn_off_led = rtsx_base_turn_off_led,
454 	.enable_auto_blink = rtsx_base_enable_auto_blink,
455 	.disable_auto_blink = rtsx_base_disable_auto_blink,
456 	.card_power_on = rtsx_base_card_power_on,
457 	.card_power_off = rtsx_base_card_power_off,
458 	.switch_output_voltage = rtsx_base_switch_output_voltage,
459 };
460 
461 /* SD Pull Control Enable:
462  *     SD_DAT[3:0] ==> pull up
463  *     SD_CD       ==> pull up
464  *     SD_WP       ==> pull up
465  *     SD_CMD      ==> pull up
466  *     SD_CLK      ==> pull down
467  */
468 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
469 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
470 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
471 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
472 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
473 	0,
474 };
475 
476 /* SD Pull Control Disable:
477  *     SD_DAT[3:0] ==> pull down
478  *     SD_CD       ==> pull up
479  *     SD_WP       ==> pull down
480  *     SD_CMD      ==> pull down
481  *     SD_CLK      ==> pull down
482  */
483 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
484 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
485 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
486 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
487 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
488 	0,
489 };
490 
491 /* MS Pull Control Enable:
492  *     MS CD       ==> pull up
493  *     others      ==> pull down
494  */
495 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
496 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
497 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
498 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
499 	0,
500 };
501 
502 /* MS Pull Control Disable:
503  *     MS CD       ==> pull up
504  *     others      ==> pull down
505  */
506 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
507 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
508 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
509 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
510 	0,
511 };
512 
rts5249_init_params(struct rtsx_pcr * pcr)513 void rts5249_init_params(struct rtsx_pcr *pcr)
514 {
515 	struct rtsx_cr_option *option = &(pcr->option);
516 
517 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
518 	pcr->num_slots = 2;
519 	pcr->ops = &rts5249_pcr_ops;
520 
521 	pcr->flags = 0;
522 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
523 	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
524 	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
525 	pcr->aspm_en = ASPM_L1_EN;
526 	pcr->aspm_mode = ASPM_MODE_CFG;
527 	pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
528 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
529 
530 	pcr->ic_version = rts5249_get_ic_version(pcr);
531 	pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
532 	pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
533 	pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
534 	pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
535 
536 	pcr->reg_pm_ctrl3 = PM_CTRL3;
537 
538 	option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
539 				| LTR_L1SS_PWR_GATE_EN);
540 	option->ltr_en = true;
541 
542 	/* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
543 	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
544 	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
545 	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
546 	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
547 	option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
548 	option->ltr_l1off_snooze_sspwrgate =
549 		LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
550 }
551 
rts524a_write_phy(struct rtsx_pcr * pcr,u8 addr,u16 val)552 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
553 {
554 	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
555 
556 	return __rtsx_pci_write_phy_register(pcr, addr, val);
557 }
558 
rts524a_read_phy(struct rtsx_pcr * pcr,u8 addr,u16 * val)559 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
560 {
561 	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
562 
563 	return __rtsx_pci_read_phy_register(pcr, addr, val);
564 }
565 
rts524a_optimize_phy(struct rtsx_pcr * pcr)566 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
567 {
568 	int err;
569 
570 	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
571 		D3_DELINK_MODE_EN, 0x00);
572 	if (err < 0)
573 		return err;
574 
575 	rtsx_pci_write_phy_register(pcr, PHY_PCR,
576 		PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
577 		PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
578 	rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
579 		PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
580 
581 	if (is_version(pcr, 0x524A, IC_VER_A)) {
582 		rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
583 			PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
584 		rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
585 			PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
586 			PHY_SSCCR2_TIME2_WIDTH);
587 		rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
588 			PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
589 			PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
590 		rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
591 			PHY_ANA1D_DEBUG_ADDR);
592 		rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
593 			PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
594 			PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
595 			PHY_DIG1E_RCLK_TX_EN_KEEP |
596 			PHY_DIG1E_RCLK_TX_TERM_KEEP |
597 			PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
598 			PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
599 			PHY_DIG1E_RX_EN_KEEP);
600 	}
601 
602 	rtsx_pci_write_phy_register(pcr, PHY_ANA08,
603 		PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
604 		PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
605 
606 	return 0;
607 }
608 
rts524a_extra_init_hw(struct rtsx_pcr * pcr)609 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
610 {
611 	rts5249_extra_init_hw(pcr);
612 
613 	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
614 		FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
615 	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
616 	rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
617 		LDO_VCC_LMT_EN);
618 	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
619 	if (is_version(pcr, 0x524A, IC_VER_A)) {
620 		rtsx_pci_write_register(pcr, LDO_DV18_CFG,
621 			LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
622 		rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
623 			LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
624 		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
625 			LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
626 		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
627 			LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
628 		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
629 			LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
630 		rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
631 			SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
632 	}
633 
634 	return 0;
635 }
636 
rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr * pcr,int active)637 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
638 {
639 	struct rtsx_cr_option *option = &(pcr->option);
640 
641 	u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
642 	int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
643 	int aspm_L1_1, aspm_L1_2;
644 	u8 val = 0;
645 
646 	aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
647 	aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
648 
649 	if (active) {
650 		/* Run, latency: 60us */
651 		if (aspm_L1_1)
652 			val = option->ltr_l1off_snooze_sspwrgate;
653 	} else {
654 		/* L1off, latency: 300us */
655 		if (aspm_L1_2)
656 			val = option->ltr_l1off_sspwrgate;
657 	}
658 
659 	if (aspm_L1_1 || aspm_L1_2) {
660 		if (rtsx_check_dev_flag(pcr,
661 					LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
662 			if (card_exist)
663 				val &= ~L1OFF_MBIAS2_EN_5250;
664 			else
665 				val |= L1OFF_MBIAS2_EN_5250;
666 		}
667 	}
668 	rtsx_set_l1off_sub(pcr, val);
669 }
670 
671 static const struct pcr_ops rts524a_pcr_ops = {
672 	.write_phy = rts524a_write_phy,
673 	.read_phy = rts524a_read_phy,
674 	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
675 	.extra_init_hw = rts524a_extra_init_hw,
676 	.optimize_phy = rts524a_optimize_phy,
677 	.turn_on_led = rtsx_base_turn_on_led,
678 	.turn_off_led = rtsx_base_turn_off_led,
679 	.enable_auto_blink = rtsx_base_enable_auto_blink,
680 	.disable_auto_blink = rtsx_base_disable_auto_blink,
681 	.card_power_on = rtsx_base_card_power_on,
682 	.card_power_off = rtsx_base_card_power_off,
683 	.switch_output_voltage = rtsx_base_switch_output_voltage,
684 	.set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
685 };
686 
rts524a_init_params(struct rtsx_pcr * pcr)687 void rts524a_init_params(struct rtsx_pcr *pcr)
688 {
689 	rts5249_init_params(pcr);
690 	pcr->aspm_mode = ASPM_MODE_REG;
691 	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
692 	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
693 	pcr->option.ltr_l1off_snooze_sspwrgate =
694 		LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
695 
696 	pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
697 	pcr->ops = &rts524a_pcr_ops;
698 
699 	pcr->option.ocp_en = 1;
700 	if (pcr->option.ocp_en)
701 		pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
702 	pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
703 	pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
704 
705 }
706 
rts525a_card_power_on(struct rtsx_pcr * pcr,int card)707 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
708 {
709 	rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
710 		LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
711 	return rtsx_base_card_power_on(pcr, card);
712 }
713 
rts525a_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)714 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
715 {
716 	switch (voltage) {
717 	case OUTPUT_3V3:
718 		rtsx_pci_write_register(pcr, LDO_CONFIG2,
719 			LDO_D3318_MASK, LDO_D3318_33V);
720 		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
721 		break;
722 	case OUTPUT_1V8:
723 		rtsx_pci_write_register(pcr, LDO_CONFIG2,
724 			LDO_D3318_MASK, LDO_D3318_18V);
725 		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
726 			SD_IO_USING_1V8);
727 		break;
728 	default:
729 		return -EINVAL;
730 	}
731 
732 	rtsx_pci_init_cmd(pcr);
733 	rts5249_fill_driving(pcr, voltage);
734 	return rtsx_pci_send_cmd(pcr, 100);
735 }
736 
rts525a_optimize_phy(struct rtsx_pcr * pcr)737 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
738 {
739 	int err;
740 
741 	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
742 		D3_DELINK_MODE_EN, 0x00);
743 	if (err < 0)
744 		return err;
745 
746 	rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
747 		_PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
748 		_PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
749 		_PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
750 
751 	rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
752 		_PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
753 		_PHY_CMU_DEBUG_EN);
754 
755 	if (is_version(pcr, 0x525A, IC_VER_A))
756 		rtsx_pci_write_phy_register(pcr, _PHY_REV0,
757 			_PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
758 			_PHY_REV0_CDR_RX_IDLE_BYPASS);
759 
760 	return 0;
761 }
762 
rts525a_extra_init_hw(struct rtsx_pcr * pcr)763 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
764 {
765 	rts5249_extra_init_hw(pcr);
766 
767 	rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
768 
769 	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
770 	if (is_version(pcr, 0x525A, IC_VER_A)) {
771 		rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
772 			L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
773 		rtsx_pci_write_register(pcr, RREF_CFG,
774 			RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
775 		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
776 			LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
777 		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
778 			LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
779 		rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
780 			LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
781 		rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
782 			LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
783 		rtsx_pci_write_register(pcr, OOBS_CONFIG,
784 			OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
785 	}
786 
787 	return 0;
788 }
789 
790 static const struct pcr_ops rts525a_pcr_ops = {
791 	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
792 	.extra_init_hw = rts525a_extra_init_hw,
793 	.optimize_phy = rts525a_optimize_phy,
794 	.turn_on_led = rtsx_base_turn_on_led,
795 	.turn_off_led = rtsx_base_turn_off_led,
796 	.enable_auto_blink = rtsx_base_enable_auto_blink,
797 	.disable_auto_blink = rtsx_base_disable_auto_blink,
798 	.card_power_on = rts525a_card_power_on,
799 	.card_power_off = rtsx_base_card_power_off,
800 	.switch_output_voltage = rts525a_switch_output_voltage,
801 	.set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
802 };
803 
rts525a_init_params(struct rtsx_pcr * pcr)804 void rts525a_init_params(struct rtsx_pcr *pcr)
805 {
806 	rts5249_init_params(pcr);
807 	pcr->aspm_mode = ASPM_MODE_REG;
808 	pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
809 	pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
810 	pcr->option.ltr_l1off_snooze_sspwrgate =
811 		LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
812 
813 	pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
814 	pcr->ops = &rts525a_pcr_ops;
815 
816 	pcr->option.ocp_en = 1;
817 	if (pcr->option.ocp_en)
818 		pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
819 	pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
820 	pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
821 }
822