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1 // SPDX-License-Identifier: GPL-2.0-only
2 /**
3  * Host side test driver to test endpoint functionality
4  *
5  * Copyright (C) 2017 Texas Instruments
6  * Author: Kishon Vijay Abraham I <kishon@ti.com>
7  */
8 
9 #include <linux/crc32.h>
10 #include <linux/delay.h>
11 #include <linux/fs.h>
12 #include <linux/io.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/miscdevice.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/random.h>
19 #include <linux/slab.h>
20 #include <linux/uaccess.h>
21 #include <linux/pci.h>
22 #include <linux/pci_ids.h>
23 
24 #include <linux/pci_regs.h>
25 
26 #include <uapi/linux/pcitest.h>
27 
28 #define DRV_MODULE_NAME				"pci-endpoint-test"
29 
30 #define IRQ_TYPE_UNDEFINED			-1
31 #define IRQ_TYPE_LEGACY				0
32 #define IRQ_TYPE_MSI				1
33 #define IRQ_TYPE_MSIX				2
34 
35 #define PCI_ENDPOINT_TEST_MAGIC			0x0
36 
37 #define PCI_ENDPOINT_TEST_COMMAND		0x4
38 #define COMMAND_RAISE_LEGACY_IRQ		BIT(0)
39 #define COMMAND_RAISE_MSI_IRQ			BIT(1)
40 #define COMMAND_RAISE_MSIX_IRQ			BIT(2)
41 #define COMMAND_READ				BIT(3)
42 #define COMMAND_WRITE				BIT(4)
43 #define COMMAND_COPY				BIT(5)
44 
45 #define PCI_ENDPOINT_TEST_STATUS		0x8
46 #define STATUS_READ_SUCCESS			BIT(0)
47 #define STATUS_READ_FAIL			BIT(1)
48 #define STATUS_WRITE_SUCCESS			BIT(2)
49 #define STATUS_WRITE_FAIL			BIT(3)
50 #define STATUS_COPY_SUCCESS			BIT(4)
51 #define STATUS_COPY_FAIL			BIT(5)
52 #define STATUS_IRQ_RAISED			BIT(6)
53 #define STATUS_SRC_ADDR_INVALID			BIT(7)
54 #define STATUS_DST_ADDR_INVALID			BIT(8)
55 
56 #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR	0x0c
57 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR	0x10
58 
59 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR	0x14
60 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR	0x18
61 
62 #define PCI_ENDPOINT_TEST_SIZE			0x1c
63 #define PCI_ENDPOINT_TEST_CHECKSUM		0x20
64 
65 #define PCI_ENDPOINT_TEST_IRQ_TYPE		0x24
66 #define PCI_ENDPOINT_TEST_IRQ_NUMBER		0x28
67 
68 #define PCI_ENDPOINT_TEST_FLAGS			0x2c
69 #define FLAG_USE_DMA				BIT(0)
70 
71 #define PCI_DEVICE_ID_TI_AM654			0xb00c
72 #define PCI_DEVICE_ID_TI_J7200			0xb00f
73 #define PCI_DEVICE_ID_TI_AM64			0xb010
74 #define PCI_DEVICE_ID_TI_J721S2		0xb013
75 #define PCI_DEVICE_ID_LS1088A			0x80c0
76 
77 #define is_am654_pci_dev(pdev)		\
78 		((pdev)->device == PCI_DEVICE_ID_TI_AM654)
79 
80 #define PCI_DEVICE_ID_RENESAS_R8A774A1		0x0028
81 #define PCI_DEVICE_ID_RENESAS_R8A774B1		0x002b
82 #define PCI_DEVICE_ID_RENESAS_R8A774C0		0x002d
83 #define PCI_DEVICE_ID_RENESAS_R8A774E1		0x0025
84 #define PCI_DEVICE_ID_RENESAS_R8A779F0		0x0031
85 
86 static DEFINE_IDA(pci_endpoint_test_ida);
87 
88 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
89 					    miscdev)
90 
91 static bool no_msi;
92 module_param(no_msi, bool, 0444);
93 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
94 
95 static int irq_type = IRQ_TYPE_MSI;
96 module_param(irq_type, int, 0444);
97 MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
98 
99 enum pci_barno {
100 	BAR_0,
101 	BAR_1,
102 	BAR_2,
103 	BAR_3,
104 	BAR_4,
105 	BAR_5,
106 };
107 
108 struct pci_endpoint_test {
109 	struct pci_dev	*pdev;
110 	void __iomem	*base;
111 	void __iomem	*bar[PCI_STD_NUM_BARS];
112 	struct completion irq_raised;
113 	int		last_irq;
114 	int		num_irqs;
115 	int		irq_type;
116 	/* mutex to protect the ioctls */
117 	struct mutex	mutex;
118 	struct miscdevice miscdev;
119 	enum pci_barno test_reg_bar;
120 	size_t alignment;
121 	const char *name;
122 };
123 
124 struct pci_endpoint_test_data {
125 	enum pci_barno test_reg_bar;
126 	size_t alignment;
127 	int irq_type;
128 };
129 
pci_endpoint_test_readl(struct pci_endpoint_test * test,u32 offset)130 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
131 					  u32 offset)
132 {
133 	return readl(test->base + offset);
134 }
135 
pci_endpoint_test_writel(struct pci_endpoint_test * test,u32 offset,u32 value)136 static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
137 					    u32 offset, u32 value)
138 {
139 	writel(value, test->base + offset);
140 }
141 
pci_endpoint_test_bar_readl(struct pci_endpoint_test * test,int bar,int offset)142 static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
143 					      int bar, int offset)
144 {
145 	return readl(test->bar[bar] + offset);
146 }
147 
pci_endpoint_test_bar_writel(struct pci_endpoint_test * test,int bar,u32 offset,u32 value)148 static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
149 						int bar, u32 offset, u32 value)
150 {
151 	writel(value, test->bar[bar] + offset);
152 }
153 
pci_endpoint_test_irqhandler(int irq,void * dev_id)154 static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
155 {
156 	struct pci_endpoint_test *test = dev_id;
157 	u32 reg;
158 
159 	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
160 	if (reg & STATUS_IRQ_RAISED) {
161 		test->last_irq = irq;
162 		complete(&test->irq_raised);
163 		reg &= ~STATUS_IRQ_RAISED;
164 	}
165 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
166 				 reg);
167 
168 	return IRQ_HANDLED;
169 }
170 
pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test * test)171 static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
172 {
173 	struct pci_dev *pdev = test->pdev;
174 
175 	pci_free_irq_vectors(pdev);
176 	test->irq_type = IRQ_TYPE_UNDEFINED;
177 }
178 
pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test * test,int type)179 static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
180 						int type)
181 {
182 	int irq = -1;
183 	struct pci_dev *pdev = test->pdev;
184 	struct device *dev = &pdev->dev;
185 	bool res = true;
186 
187 	switch (type) {
188 	case IRQ_TYPE_LEGACY:
189 		irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
190 		if (irq < 0)
191 			dev_err(dev, "Failed to get Legacy interrupt\n");
192 		break;
193 	case IRQ_TYPE_MSI:
194 		irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
195 		if (irq < 0)
196 			dev_err(dev, "Failed to get MSI interrupts\n");
197 		break;
198 	case IRQ_TYPE_MSIX:
199 		irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
200 		if (irq < 0)
201 			dev_err(dev, "Failed to get MSI-X interrupts\n");
202 		break;
203 	default:
204 		dev_err(dev, "Invalid IRQ type selected\n");
205 	}
206 
207 	if (irq < 0) {
208 		irq = 0;
209 		res = false;
210 	}
211 
212 	test->irq_type = type;
213 	test->num_irqs = irq;
214 
215 	return res;
216 }
217 
pci_endpoint_test_release_irq(struct pci_endpoint_test * test)218 static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
219 {
220 	int i;
221 	struct pci_dev *pdev = test->pdev;
222 	struct device *dev = &pdev->dev;
223 
224 	for (i = 0; i < test->num_irqs; i++)
225 		devm_free_irq(dev, pci_irq_vector(pdev, i), test);
226 
227 	test->num_irqs = 0;
228 }
229 
pci_endpoint_test_request_irq(struct pci_endpoint_test * test)230 static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
231 {
232 	int i;
233 	int err;
234 	struct pci_dev *pdev = test->pdev;
235 	struct device *dev = &pdev->dev;
236 
237 	for (i = 0; i < test->num_irqs; i++) {
238 		err = devm_request_irq(dev, pci_irq_vector(pdev, i),
239 				       pci_endpoint_test_irqhandler,
240 				       IRQF_SHARED, test->name, test);
241 		if (err)
242 			goto fail;
243 	}
244 
245 	return true;
246 
247 fail:
248 	switch (irq_type) {
249 	case IRQ_TYPE_LEGACY:
250 		dev_err(dev, "Failed to request IRQ %d for Legacy\n",
251 			pci_irq_vector(pdev, i));
252 		break;
253 	case IRQ_TYPE_MSI:
254 		dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
255 			pci_irq_vector(pdev, i),
256 			i + 1);
257 		break;
258 	case IRQ_TYPE_MSIX:
259 		dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
260 			pci_irq_vector(pdev, i),
261 			i + 1);
262 		break;
263 	}
264 
265 	return false;
266 }
267 
pci_endpoint_test_bar(struct pci_endpoint_test * test,enum pci_barno barno)268 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
269 				  enum pci_barno barno)
270 {
271 	int j;
272 	u32 val;
273 	int size;
274 	struct pci_dev *pdev = test->pdev;
275 
276 	if (!test->bar[barno])
277 		return false;
278 
279 	size = pci_resource_len(pdev, barno);
280 
281 	if (barno == test->test_reg_bar)
282 		size = 0x4;
283 
284 	for (j = 0; j < size; j += 4)
285 		pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
286 
287 	for (j = 0; j < size; j += 4) {
288 		val = pci_endpoint_test_bar_readl(test, barno, j);
289 		if (val != 0xA0A0A0A0)
290 			return false;
291 	}
292 
293 	return true;
294 }
295 
pci_endpoint_test_legacy_irq(struct pci_endpoint_test * test)296 static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
297 {
298 	u32 val;
299 
300 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
301 				 IRQ_TYPE_LEGACY);
302 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
303 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
304 				 COMMAND_RAISE_LEGACY_IRQ);
305 	val = wait_for_completion_timeout(&test->irq_raised,
306 					  msecs_to_jiffies(1000));
307 	if (!val)
308 		return false;
309 
310 	return true;
311 }
312 
pci_endpoint_test_msi_irq(struct pci_endpoint_test * test,u16 msi_num,bool msix)313 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
314 				       u16 msi_num, bool msix)
315 {
316 	u32 val;
317 	struct pci_dev *pdev = test->pdev;
318 
319 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
320 				 msix == false ? IRQ_TYPE_MSI :
321 				 IRQ_TYPE_MSIX);
322 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
323 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
324 				 msix == false ? COMMAND_RAISE_MSI_IRQ :
325 				 COMMAND_RAISE_MSIX_IRQ);
326 	val = wait_for_completion_timeout(&test->irq_raised,
327 					  msecs_to_jiffies(1000));
328 	if (!val)
329 		return false;
330 
331 	if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
332 		return true;
333 
334 	return false;
335 }
336 
pci_endpoint_test_validate_xfer_params(struct device * dev,struct pci_endpoint_test_xfer_param * param,size_t alignment)337 static int pci_endpoint_test_validate_xfer_params(struct device *dev,
338 		struct pci_endpoint_test_xfer_param *param, size_t alignment)
339 {
340 	if (!param->size) {
341 		dev_dbg(dev, "Data size is zero\n");
342 		return -EINVAL;
343 	}
344 
345 	if (param->size > SIZE_MAX - alignment) {
346 		dev_dbg(dev, "Maximum transfer data size exceeded\n");
347 		return -EINVAL;
348 	}
349 
350 	return 0;
351 }
352 
pci_endpoint_test_copy(struct pci_endpoint_test * test,unsigned long arg)353 static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,
354 				   unsigned long arg)
355 {
356 	struct pci_endpoint_test_xfer_param param;
357 	bool ret = false;
358 	void *src_addr;
359 	void *dst_addr;
360 	u32 flags = 0;
361 	bool use_dma;
362 	size_t size;
363 	dma_addr_t src_phys_addr;
364 	dma_addr_t dst_phys_addr;
365 	struct pci_dev *pdev = test->pdev;
366 	struct device *dev = &pdev->dev;
367 	void *orig_src_addr;
368 	dma_addr_t orig_src_phys_addr;
369 	void *orig_dst_addr;
370 	dma_addr_t orig_dst_phys_addr;
371 	size_t offset;
372 	size_t alignment = test->alignment;
373 	int irq_type = test->irq_type;
374 	u32 src_crc32;
375 	u32 dst_crc32;
376 	int err;
377 
378 	err = copy_from_user(&param, (void __user *)arg, sizeof(param));
379 	if (err) {
380 		dev_err(dev, "Failed to get transfer param\n");
381 		return false;
382 	}
383 
384 	err = pci_endpoint_test_validate_xfer_params(dev, &param, alignment);
385 	if (err)
386 		return false;
387 
388 	size = param.size;
389 
390 	use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
391 	if (use_dma)
392 		flags |= FLAG_USE_DMA;
393 
394 	if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
395 		dev_err(dev, "Invalid IRQ type option\n");
396 		goto err;
397 	}
398 
399 	orig_src_addr = kzalloc(size + alignment, GFP_KERNEL);
400 	if (!orig_src_addr) {
401 		dev_err(dev, "Failed to allocate source buffer\n");
402 		ret = false;
403 		goto err;
404 	}
405 
406 	get_random_bytes(orig_src_addr, size + alignment);
407 	orig_src_phys_addr = dma_map_single(dev, orig_src_addr,
408 					    size + alignment, DMA_TO_DEVICE);
409 	if (dma_mapping_error(dev, orig_src_phys_addr)) {
410 		dev_err(dev, "failed to map source buffer address\n");
411 		ret = false;
412 		goto err_src_phys_addr;
413 	}
414 
415 	if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
416 		src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
417 		offset = src_phys_addr - orig_src_phys_addr;
418 		src_addr = orig_src_addr + offset;
419 	} else {
420 		src_phys_addr = orig_src_phys_addr;
421 		src_addr = orig_src_addr;
422 	}
423 
424 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
425 				 lower_32_bits(src_phys_addr));
426 
427 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
428 				 upper_32_bits(src_phys_addr));
429 
430 	src_crc32 = crc32_le(~0, src_addr, size);
431 
432 	orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL);
433 	if (!orig_dst_addr) {
434 		dev_err(dev, "Failed to allocate destination address\n");
435 		ret = false;
436 		goto err_dst_addr;
437 	}
438 
439 	orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr,
440 					    size + alignment, DMA_FROM_DEVICE);
441 	if (dma_mapping_error(dev, orig_dst_phys_addr)) {
442 		dev_err(dev, "failed to map destination buffer address\n");
443 		ret = false;
444 		goto err_dst_phys_addr;
445 	}
446 
447 	if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
448 		dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
449 		offset = dst_phys_addr - orig_dst_phys_addr;
450 		dst_addr = orig_dst_addr + offset;
451 	} else {
452 		dst_phys_addr = orig_dst_phys_addr;
453 		dst_addr = orig_dst_addr;
454 	}
455 
456 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
457 				 lower_32_bits(dst_phys_addr));
458 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
459 				 upper_32_bits(dst_phys_addr));
460 
461 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
462 				 size);
463 
464 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
465 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
466 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
467 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
468 				 COMMAND_COPY);
469 
470 	wait_for_completion(&test->irq_raised);
471 
472 	dma_unmap_single(dev, orig_dst_phys_addr, size + alignment,
473 			 DMA_FROM_DEVICE);
474 
475 	dst_crc32 = crc32_le(~0, dst_addr, size);
476 	if (dst_crc32 == src_crc32)
477 		ret = true;
478 
479 err_dst_phys_addr:
480 	kfree(orig_dst_addr);
481 
482 err_dst_addr:
483 	dma_unmap_single(dev, orig_src_phys_addr, size + alignment,
484 			 DMA_TO_DEVICE);
485 
486 err_src_phys_addr:
487 	kfree(orig_src_addr);
488 
489 err:
490 	return ret;
491 }
492 
pci_endpoint_test_write(struct pci_endpoint_test * test,unsigned long arg)493 static bool pci_endpoint_test_write(struct pci_endpoint_test *test,
494 				    unsigned long arg)
495 {
496 	struct pci_endpoint_test_xfer_param param;
497 	bool ret = false;
498 	u32 flags = 0;
499 	bool use_dma;
500 	u32 reg;
501 	void *addr;
502 	dma_addr_t phys_addr;
503 	struct pci_dev *pdev = test->pdev;
504 	struct device *dev = &pdev->dev;
505 	void *orig_addr;
506 	dma_addr_t orig_phys_addr;
507 	size_t offset;
508 	size_t alignment = test->alignment;
509 	int irq_type = test->irq_type;
510 	size_t size;
511 	u32 crc32;
512 	int err;
513 
514 	err = copy_from_user(&param, (void __user *)arg, sizeof(param));
515 	if (err != 0) {
516 		dev_err(dev, "Failed to get transfer param\n");
517 		return false;
518 	}
519 
520 	err = pci_endpoint_test_validate_xfer_params(dev, &param, alignment);
521 	if (err)
522 		return false;
523 
524 	size = param.size;
525 
526 	use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
527 	if (use_dma)
528 		flags |= FLAG_USE_DMA;
529 
530 	if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
531 		dev_err(dev, "Invalid IRQ type option\n");
532 		goto err;
533 	}
534 
535 	orig_addr = kzalloc(size + alignment, GFP_KERNEL);
536 	if (!orig_addr) {
537 		dev_err(dev, "Failed to allocate address\n");
538 		ret = false;
539 		goto err;
540 	}
541 
542 	get_random_bytes(orig_addr, size + alignment);
543 
544 	orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
545 					DMA_TO_DEVICE);
546 	if (dma_mapping_error(dev, orig_phys_addr)) {
547 		dev_err(dev, "failed to map source buffer address\n");
548 		ret = false;
549 		goto err_phys_addr;
550 	}
551 
552 	if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
553 		phys_addr =  PTR_ALIGN(orig_phys_addr, alignment);
554 		offset = phys_addr - orig_phys_addr;
555 		addr = orig_addr + offset;
556 	} else {
557 		phys_addr = orig_phys_addr;
558 		addr = orig_addr;
559 	}
560 
561 	crc32 = crc32_le(~0, addr, size);
562 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
563 				 crc32);
564 
565 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
566 				 lower_32_bits(phys_addr));
567 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
568 				 upper_32_bits(phys_addr));
569 
570 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
571 
572 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
573 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
574 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
575 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
576 				 COMMAND_READ);
577 
578 	wait_for_completion(&test->irq_raised);
579 
580 	reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
581 	if (reg & STATUS_READ_SUCCESS)
582 		ret = true;
583 
584 	dma_unmap_single(dev, orig_phys_addr, size + alignment,
585 			 DMA_TO_DEVICE);
586 
587 err_phys_addr:
588 	kfree(orig_addr);
589 
590 err:
591 	return ret;
592 }
593 
pci_endpoint_test_read(struct pci_endpoint_test * test,unsigned long arg)594 static bool pci_endpoint_test_read(struct pci_endpoint_test *test,
595 				   unsigned long arg)
596 {
597 	struct pci_endpoint_test_xfer_param param;
598 	bool ret = false;
599 	u32 flags = 0;
600 	bool use_dma;
601 	size_t size;
602 	void *addr;
603 	dma_addr_t phys_addr;
604 	struct pci_dev *pdev = test->pdev;
605 	struct device *dev = &pdev->dev;
606 	void *orig_addr;
607 	dma_addr_t orig_phys_addr;
608 	size_t offset;
609 	size_t alignment = test->alignment;
610 	int irq_type = test->irq_type;
611 	u32 crc32;
612 	int err;
613 
614 	err = copy_from_user(&param, (void __user *)arg, sizeof(param));
615 	if (err) {
616 		dev_err(dev, "Failed to get transfer param\n");
617 		return false;
618 	}
619 
620 	err = pci_endpoint_test_validate_xfer_params(dev, &param, alignment);
621 	if (err)
622 		return false;
623 
624 	size = param.size;
625 
626 	use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
627 	if (use_dma)
628 		flags |= FLAG_USE_DMA;
629 
630 	if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
631 		dev_err(dev, "Invalid IRQ type option\n");
632 		goto err;
633 	}
634 
635 	orig_addr = kzalloc(size + alignment, GFP_KERNEL);
636 	if (!orig_addr) {
637 		dev_err(dev, "Failed to allocate destination address\n");
638 		ret = false;
639 		goto err;
640 	}
641 
642 	orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
643 					DMA_FROM_DEVICE);
644 	if (dma_mapping_error(dev, orig_phys_addr)) {
645 		dev_err(dev, "failed to map source buffer address\n");
646 		ret = false;
647 		goto err_phys_addr;
648 	}
649 
650 	if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
651 		phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
652 		offset = phys_addr - orig_phys_addr;
653 		addr = orig_addr + offset;
654 	} else {
655 		phys_addr = orig_phys_addr;
656 		addr = orig_addr;
657 	}
658 
659 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
660 				 lower_32_bits(phys_addr));
661 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
662 				 upper_32_bits(phys_addr));
663 
664 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
665 
666 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
667 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
668 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
669 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
670 				 COMMAND_WRITE);
671 
672 	wait_for_completion(&test->irq_raised);
673 
674 	dma_unmap_single(dev, orig_phys_addr, size + alignment,
675 			 DMA_FROM_DEVICE);
676 
677 	crc32 = crc32_le(~0, addr, size);
678 	if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
679 		ret = true;
680 
681 err_phys_addr:
682 	kfree(orig_addr);
683 err:
684 	return ret;
685 }
686 
pci_endpoint_test_clear_irq(struct pci_endpoint_test * test)687 static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test)
688 {
689 	pci_endpoint_test_release_irq(test);
690 	pci_endpoint_test_free_irq_vectors(test);
691 	return true;
692 }
693 
pci_endpoint_test_set_irq(struct pci_endpoint_test * test,int req_irq_type)694 static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
695 				      int req_irq_type)
696 {
697 	struct pci_dev *pdev = test->pdev;
698 	struct device *dev = &pdev->dev;
699 
700 	if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
701 		dev_err(dev, "Invalid IRQ type option\n");
702 		return false;
703 	}
704 
705 	if (test->irq_type == req_irq_type)
706 		return true;
707 
708 	pci_endpoint_test_release_irq(test);
709 	pci_endpoint_test_free_irq_vectors(test);
710 
711 	if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
712 		goto err;
713 
714 	if (!pci_endpoint_test_request_irq(test))
715 		goto err;
716 
717 	return true;
718 
719 err:
720 	pci_endpoint_test_free_irq_vectors(test);
721 	return false;
722 }
723 
pci_endpoint_test_ioctl(struct file * file,unsigned int cmd,unsigned long arg)724 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
725 				    unsigned long arg)
726 {
727 	int ret = -EINVAL;
728 	enum pci_barno bar;
729 	struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
730 	struct pci_dev *pdev = test->pdev;
731 
732 	mutex_lock(&test->mutex);
733 
734 	reinit_completion(&test->irq_raised);
735 	test->last_irq = -ENODATA;
736 
737 	switch (cmd) {
738 	case PCITEST_BAR:
739 		bar = arg;
740 		if (bar > BAR_5)
741 			goto ret;
742 		if (is_am654_pci_dev(pdev) && bar == BAR_0)
743 			goto ret;
744 		ret = pci_endpoint_test_bar(test, bar);
745 		break;
746 	case PCITEST_LEGACY_IRQ:
747 		ret = pci_endpoint_test_legacy_irq(test);
748 		break;
749 	case PCITEST_MSI:
750 	case PCITEST_MSIX:
751 		ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
752 		break;
753 	case PCITEST_WRITE:
754 		ret = pci_endpoint_test_write(test, arg);
755 		break;
756 	case PCITEST_READ:
757 		ret = pci_endpoint_test_read(test, arg);
758 		break;
759 	case PCITEST_COPY:
760 		ret = pci_endpoint_test_copy(test, arg);
761 		break;
762 	case PCITEST_SET_IRQTYPE:
763 		ret = pci_endpoint_test_set_irq(test, arg);
764 		break;
765 	case PCITEST_GET_IRQTYPE:
766 		ret = irq_type;
767 		break;
768 	case PCITEST_CLEAR_IRQ:
769 		ret = pci_endpoint_test_clear_irq(test);
770 		break;
771 	}
772 
773 ret:
774 	mutex_unlock(&test->mutex);
775 	return ret;
776 }
777 
778 static const struct file_operations pci_endpoint_test_fops = {
779 	.owner = THIS_MODULE,
780 	.unlocked_ioctl = pci_endpoint_test_ioctl,
781 };
782 
pci_endpoint_test_probe(struct pci_dev * pdev,const struct pci_device_id * ent)783 static int pci_endpoint_test_probe(struct pci_dev *pdev,
784 				   const struct pci_device_id *ent)
785 {
786 	int err;
787 	int id;
788 	char name[24];
789 	enum pci_barno bar;
790 	void __iomem *base;
791 	struct device *dev = &pdev->dev;
792 	struct pci_endpoint_test *test;
793 	struct pci_endpoint_test_data *data;
794 	enum pci_barno test_reg_bar = BAR_0;
795 	struct miscdevice *misc_device;
796 
797 	if (pci_is_bridge(pdev))
798 		return -ENODEV;
799 
800 	test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
801 	if (!test)
802 		return -ENOMEM;
803 
804 	test->test_reg_bar = 0;
805 	test->alignment = 0;
806 	test->pdev = pdev;
807 	test->irq_type = IRQ_TYPE_UNDEFINED;
808 
809 	if (no_msi)
810 		irq_type = IRQ_TYPE_LEGACY;
811 
812 	data = (struct pci_endpoint_test_data *)ent->driver_data;
813 	if (data) {
814 		test_reg_bar = data->test_reg_bar;
815 		test->test_reg_bar = test_reg_bar;
816 		test->alignment = data->alignment;
817 		irq_type = data->irq_type;
818 	}
819 
820 	init_completion(&test->irq_raised);
821 	mutex_init(&test->mutex);
822 
823 	if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) &&
824 	    dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
825 		dev_err(dev, "Cannot set DMA mask\n");
826 		return -EINVAL;
827 	}
828 
829 	err = pci_enable_device(pdev);
830 	if (err) {
831 		dev_err(dev, "Cannot enable PCI device\n");
832 		return err;
833 	}
834 
835 	err = pci_request_regions(pdev, DRV_MODULE_NAME);
836 	if (err) {
837 		dev_err(dev, "Cannot obtain PCI resources\n");
838 		goto err_disable_pdev;
839 	}
840 
841 	pci_set_master(pdev);
842 
843 	if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) {
844 		err = -EINVAL;
845 		goto err_disable_irq;
846 	}
847 
848 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
849 		if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
850 			base = pci_ioremap_bar(pdev, bar);
851 			if (!base) {
852 				dev_err(dev, "Failed to read BAR%d\n", bar);
853 				WARN_ON(bar == test_reg_bar);
854 			}
855 			test->bar[bar] = base;
856 		}
857 	}
858 
859 	test->base = test->bar[test_reg_bar];
860 	if (!test->base) {
861 		err = -ENOMEM;
862 		dev_err(dev, "Cannot perform PCI test without BAR%d\n",
863 			test_reg_bar);
864 		goto err_iounmap;
865 	}
866 
867 	pci_set_drvdata(pdev, test);
868 
869 	id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
870 	if (id < 0) {
871 		err = id;
872 		dev_err(dev, "Unable to get id\n");
873 		goto err_iounmap;
874 	}
875 
876 	snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
877 	test->name = kstrdup(name, GFP_KERNEL);
878 	if (!test->name) {
879 		err = -ENOMEM;
880 		goto err_ida_remove;
881 	}
882 
883 	if (!pci_endpoint_test_request_irq(test)) {
884 		err = -EINVAL;
885 		goto err_kfree_test_name;
886 	}
887 
888 	misc_device = &test->miscdev;
889 	misc_device->minor = MISC_DYNAMIC_MINOR;
890 	misc_device->name = kstrdup(name, GFP_KERNEL);
891 	if (!misc_device->name) {
892 		err = -ENOMEM;
893 		goto err_release_irq;
894 	}
895 	misc_device->parent = &pdev->dev;
896 	misc_device->fops = &pci_endpoint_test_fops,
897 
898 	err = misc_register(misc_device);
899 	if (err) {
900 		dev_err(dev, "Failed to register device\n");
901 		goto err_kfree_name;
902 	}
903 
904 	return 0;
905 
906 err_kfree_name:
907 	kfree(misc_device->name);
908 
909 err_release_irq:
910 	pci_endpoint_test_release_irq(test);
911 
912 err_kfree_test_name:
913 	kfree(test->name);
914 
915 err_ida_remove:
916 	ida_simple_remove(&pci_endpoint_test_ida, id);
917 
918 err_iounmap:
919 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
920 		if (test->bar[bar])
921 			pci_iounmap(pdev, test->bar[bar]);
922 	}
923 
924 err_disable_irq:
925 	pci_endpoint_test_free_irq_vectors(test);
926 	pci_release_regions(pdev);
927 
928 err_disable_pdev:
929 	pci_disable_device(pdev);
930 
931 	return err;
932 }
933 
pci_endpoint_test_remove(struct pci_dev * pdev)934 static void pci_endpoint_test_remove(struct pci_dev *pdev)
935 {
936 	int id;
937 	enum pci_barno bar;
938 	struct pci_endpoint_test *test = pci_get_drvdata(pdev);
939 	struct miscdevice *misc_device = &test->miscdev;
940 
941 	if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
942 		return;
943 	if (id < 0)
944 		return;
945 
946 	pci_endpoint_test_release_irq(test);
947 	pci_endpoint_test_free_irq_vectors(test);
948 
949 	misc_deregister(&test->miscdev);
950 	kfree(misc_device->name);
951 	kfree(test->name);
952 	ida_simple_remove(&pci_endpoint_test_ida, id);
953 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
954 		if (test->bar[bar])
955 			pci_iounmap(pdev, test->bar[bar]);
956 	}
957 
958 	pci_release_regions(pdev);
959 	pci_disable_device(pdev);
960 }
961 
962 static const struct pci_endpoint_test_data default_data = {
963 	.test_reg_bar = BAR_0,
964 	.alignment = SZ_4K,
965 	.irq_type = IRQ_TYPE_MSI,
966 };
967 
968 static const struct pci_endpoint_test_data am654_data = {
969 	.test_reg_bar = BAR_2,
970 	.alignment = SZ_64K,
971 	.irq_type = IRQ_TYPE_MSI,
972 };
973 
974 static const struct pci_endpoint_test_data j721e_data = {
975 	.alignment = 256,
976 	.irq_type = IRQ_TYPE_MSI,
977 };
978 
979 static const struct pci_device_id pci_endpoint_test_tbl[] = {
980 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
981 	  .driver_data = (kernel_ulong_t)&default_data,
982 	},
983 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),
984 	  .driver_data = (kernel_ulong_t)&default_data,
985 	},
986 	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),
987 	  .driver_data = (kernel_ulong_t)&default_data,
988 	},
989 	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),
990 	  .driver_data = (kernel_ulong_t)&default_data,
991 	},
992 	{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
993 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
994 	  .driver_data = (kernel_ulong_t)&am654_data
995 	},
996 	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
997 	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
998 	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
999 	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
1000 	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),
1001 	  .driver_data = (kernel_ulong_t)&default_data,
1002 	},
1003 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
1004 	  .driver_data = (kernel_ulong_t)&j721e_data,
1005 	},
1006 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200),
1007 	  .driver_data = (kernel_ulong_t)&j721e_data,
1008 	},
1009 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64),
1010 	  .driver_data = (kernel_ulong_t)&j721e_data,
1011 	},
1012 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721S2),
1013 	  .driver_data = (kernel_ulong_t)&j721e_data,
1014 	},
1015 	{ }
1016 };
1017 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
1018 
1019 static struct pci_driver pci_endpoint_test_driver = {
1020 	.name		= DRV_MODULE_NAME,
1021 	.id_table	= pci_endpoint_test_tbl,
1022 	.probe		= pci_endpoint_test_probe,
1023 	.remove		= pci_endpoint_test_remove,
1024 	.sriov_configure = pci_sriov_configure_simple,
1025 };
1026 module_pci_driver(pci_endpoint_test_driver);
1027 
1028 MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
1029 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
1030 MODULE_LICENSE("GPL v2");
1031