1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
4 *
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Kevin Hilman <khilman@baylibre.com>
7 */
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/iopoll.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/ioport.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/mmc/host.h>
19 #include <linux/mmc/mmc.h>
20 #include <linux/mmc/sdio.h>
21 #include <linux/mmc/slot-gpio.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24 #include <linux/clk-provider.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/reset.h>
27 #include <linux/interrupt.h>
28 #include <linux/bitfield.h>
29 #include <linux/pinctrl/consumer.h>
30
31 #define DRIVER_NAME "meson-gx-mmc"
32
33 #define SD_EMMC_CLOCK 0x0
34 #define CLK_DIV_MASK GENMASK(5, 0)
35 #define CLK_SRC_MASK GENMASK(7, 6)
36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
37 #define CLK_TX_PHASE_MASK GENMASK(11, 10)
38 #define CLK_RX_PHASE_MASK GENMASK(13, 12)
39 #define CLK_PHASE_0 0
40 #define CLK_PHASE_180 2
41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
43 #define CLK_V2_ALWAYS_ON BIT(24)
44
45 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
46 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
47 #define CLK_V3_ALWAYS_ON BIT(28)
48
49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
51 #define CLK_ALWAYS_ON(h) (h->data->always_on)
52
53 #define SD_EMMC_DELAY 0x4
54 #define SD_EMMC_ADJUST 0x8
55 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
56 #define ADJUST_DS_EN BIT(15)
57 #define ADJUST_ADJ_EN BIT(13)
58
59 #define SD_EMMC_DELAY1 0x4
60 #define SD_EMMC_DELAY2 0x8
61 #define SD_EMMC_V3_ADJUST 0xc
62
63 #define SD_EMMC_CALOUT 0x10
64 #define SD_EMMC_START 0x40
65 #define START_DESC_INIT BIT(0)
66 #define START_DESC_BUSY BIT(1)
67 #define START_DESC_ADDR_MASK GENMASK(31, 2)
68
69 #define SD_EMMC_CFG 0x44
70 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
71 #define CFG_BUS_WIDTH_1 0x0
72 #define CFG_BUS_WIDTH_4 0x1
73 #define CFG_BUS_WIDTH_8 0x2
74 #define CFG_DDR BIT(2)
75 #define CFG_BLK_LEN_MASK GENMASK(7, 4)
76 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
77 #define CFG_RC_CC_MASK GENMASK(15, 12)
78 #define CFG_STOP_CLOCK BIT(22)
79 #define CFG_CLK_ALWAYS_ON BIT(18)
80 #define CFG_CHK_DS BIT(20)
81 #define CFG_AUTO_CLK BIT(23)
82 #define CFG_ERR_ABORT BIT(27)
83
84 #define SD_EMMC_STATUS 0x48
85 #define STATUS_BUSY BIT(31)
86 #define STATUS_DESC_BUSY BIT(30)
87 #define STATUS_DATI GENMASK(23, 16)
88
89 #define SD_EMMC_IRQ_EN 0x4c
90 #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
91 #define IRQ_TXD_ERR BIT(8)
92 #define IRQ_DESC_ERR BIT(9)
93 #define IRQ_RESP_ERR BIT(10)
94 #define IRQ_CRC_ERR \
95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
96 #define IRQ_RESP_TIMEOUT BIT(11)
97 #define IRQ_DESC_TIMEOUT BIT(12)
98 #define IRQ_TIMEOUTS \
99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
100 #define IRQ_END_OF_CHAIN BIT(13)
101 #define IRQ_RESP_STATUS BIT(14)
102 #define IRQ_SDIO BIT(15)
103 #define IRQ_EN_MASK \
104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
105 IRQ_SDIO)
106
107 #define SD_EMMC_CMD_CFG 0x50
108 #define SD_EMMC_CMD_ARG 0x54
109 #define SD_EMMC_CMD_DAT 0x58
110 #define SD_EMMC_CMD_RSP 0x5c
111 #define SD_EMMC_CMD_RSP1 0x60
112 #define SD_EMMC_CMD_RSP2 0x64
113 #define SD_EMMC_CMD_RSP3 0x68
114
115 #define SD_EMMC_RXD 0x94
116 #define SD_EMMC_TXD 0x94
117 #define SD_EMMC_LAST_REG SD_EMMC_TXD
118
119 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536
120 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
121
122 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
123 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
124 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
125 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
126 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
127 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
128
129 #define SD_EMMC_PRE_REQ_DONE BIT(0)
130 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
131
132 #define MUX_CLK_NUM_PARENTS 2
133
134 struct meson_mmc_data {
135 unsigned int tx_delay_mask;
136 unsigned int rx_delay_mask;
137 unsigned int always_on;
138 unsigned int adjust;
139 };
140
141 struct sd_emmc_desc {
142 u32 cmd_cfg;
143 u32 cmd_arg;
144 u32 cmd_data;
145 u32 cmd_resp;
146 };
147
148 struct meson_host {
149 struct device *dev;
150 struct meson_mmc_data *data;
151 struct mmc_host *mmc;
152 struct mmc_command *cmd;
153
154 void __iomem *regs;
155 struct clk *core_clk;
156 struct clk *mux_clk;
157 struct clk *mmc_clk;
158 unsigned long req_rate;
159 bool ddr;
160
161 bool dram_access_quirk;
162
163 struct pinctrl *pinctrl;
164 struct pinctrl_state *pins_clk_gate;
165
166 unsigned int bounce_buf_size;
167 void *bounce_buf;
168 void __iomem *bounce_iomem_buf;
169 dma_addr_t bounce_dma_addr;
170 struct sd_emmc_desc *descs;
171 dma_addr_t descs_dma_addr;
172
173 int irq;
174
175 bool vqmmc_enabled;
176 bool needs_pre_post_req;
177
178 };
179
180 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
181 #define CMD_CFG_BLOCK_MODE BIT(9)
182 #define CMD_CFG_R1B BIT(10)
183 #define CMD_CFG_END_OF_CHAIN BIT(11)
184 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
185 #define CMD_CFG_NO_RESP BIT(16)
186 #define CMD_CFG_NO_CMD BIT(17)
187 #define CMD_CFG_DATA_IO BIT(18)
188 #define CMD_CFG_DATA_WR BIT(19)
189 #define CMD_CFG_RESP_NOCRC BIT(20)
190 #define CMD_CFG_RESP_128 BIT(21)
191 #define CMD_CFG_RESP_NUM BIT(22)
192 #define CMD_CFG_DATA_NUM BIT(23)
193 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
194 #define CMD_CFG_ERROR BIT(30)
195 #define CMD_CFG_OWNER BIT(31)
196
197 #define CMD_DATA_MASK GENMASK(31, 2)
198 #define CMD_DATA_BIG_ENDIAN BIT(1)
199 #define CMD_DATA_SRAM BIT(0)
200 #define CMD_RESP_MASK GENMASK(31, 1)
201 #define CMD_RESP_SRAM BIT(0)
202
meson_mmc_get_timeout_msecs(struct mmc_data * data)203 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
204 {
205 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
206
207 if (!timeout)
208 return SD_EMMC_CMD_TIMEOUT_DATA;
209
210 timeout = roundup_pow_of_two(timeout);
211
212 return min(timeout, 32768U); /* max. 2^15 ms */
213 }
214
meson_mmc_get_next_command(struct mmc_command * cmd)215 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
216 {
217 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
218 return cmd->mrq->cmd;
219 else if (mmc_op_multi(cmd->opcode) &&
220 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
221 return cmd->mrq->stop;
222 else
223 return NULL;
224 }
225
meson_mmc_get_transfer_mode(struct mmc_host * mmc,struct mmc_request * mrq)226 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
227 struct mmc_request *mrq)
228 {
229 struct meson_host *host = mmc_priv(mmc);
230 struct mmc_data *data = mrq->data;
231 struct scatterlist *sg;
232 int i;
233
234 /*
235 * When Controller DMA cannot directly access DDR memory, disable
236 * support for Chain Mode to directly use the internal SRAM using
237 * the bounce buffer mode.
238 */
239 if (host->dram_access_quirk)
240 return;
241
242 /* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */
243 if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) {
244 /*
245 * In block mode DMA descriptor format, "length" field indicates
246 * number of blocks and there is no way to pass DMA size that
247 * is not multiple of SDIO block size, making it impossible to
248 * tie more than one memory buffer with single SDIO block.
249 * Block mode sg buffer size should be aligned with SDIO block
250 * size, otherwise chain mode could not be used.
251 */
252 for_each_sg(data->sg, sg, data->sg_len, i) {
253 if (sg->length % data->blksz) {
254 dev_warn_once(mmc_dev(mmc),
255 "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n",
256 sg->length, data->blksz);
257 return;
258 }
259 }
260 }
261
262 for_each_sg(data->sg, sg, data->sg_len, i) {
263 /* check for 8 byte alignment */
264 if (sg->offset % 8) {
265 dev_warn_once(mmc_dev(mmc),
266 "unaligned sg offset %u, disabling descriptor DMA for transfer\n",
267 sg->offset);
268 return;
269 }
270 }
271
272 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
273 }
274
meson_mmc_desc_chain_mode(const struct mmc_data * data)275 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
276 {
277 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
278 }
279
meson_mmc_bounce_buf_read(const struct mmc_data * data)280 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
281 {
282 return data && data->flags & MMC_DATA_READ &&
283 !meson_mmc_desc_chain_mode(data);
284 }
285
meson_mmc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)286 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
287 {
288 struct mmc_data *data = mrq->data;
289
290 if (!data)
291 return;
292
293 meson_mmc_get_transfer_mode(mmc, mrq);
294 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
295
296 if (!meson_mmc_desc_chain_mode(data))
297 return;
298
299 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
300 mmc_get_dma_dir(data));
301 if (!data->sg_count)
302 dev_err(mmc_dev(mmc), "dma_map_sg failed");
303 }
304
meson_mmc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)305 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
306 int err)
307 {
308 struct mmc_data *data = mrq->data;
309
310 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
311 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
312 mmc_get_dma_dir(data));
313 }
314
315 /*
316 * Gating the clock on this controller is tricky. It seems the mmc clock
317 * is also used by the controller. It may crash during some operation if the
318 * clock is stopped. The safest thing to do, whenever possible, is to keep
319 * clock running at stop it at the pad using the pinmux.
320 */
meson_mmc_clk_gate(struct meson_host * host)321 static void meson_mmc_clk_gate(struct meson_host *host)
322 {
323 u32 cfg;
324
325 if (host->pins_clk_gate) {
326 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
327 } else {
328 /*
329 * If the pinmux is not provided - default to the classic and
330 * unsafe method
331 */
332 cfg = readl(host->regs + SD_EMMC_CFG);
333 cfg |= CFG_STOP_CLOCK;
334 writel(cfg, host->regs + SD_EMMC_CFG);
335 }
336 }
337
meson_mmc_clk_ungate(struct meson_host * host)338 static void meson_mmc_clk_ungate(struct meson_host *host)
339 {
340 u32 cfg;
341
342 if (host->pins_clk_gate)
343 pinctrl_select_default_state(host->dev);
344
345 /* Make sure the clock is not stopped in the controller */
346 cfg = readl(host->regs + SD_EMMC_CFG);
347 cfg &= ~CFG_STOP_CLOCK;
348 writel(cfg, host->regs + SD_EMMC_CFG);
349 }
350
meson_mmc_clk_set(struct meson_host * host,unsigned long rate,bool ddr)351 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
352 bool ddr)
353 {
354 struct mmc_host *mmc = host->mmc;
355 int ret;
356 u32 cfg;
357
358 /* Same request - bail-out */
359 if (host->ddr == ddr && host->req_rate == rate)
360 return 0;
361
362 /* stop clock */
363 meson_mmc_clk_gate(host);
364 host->req_rate = 0;
365 mmc->actual_clock = 0;
366
367 /* return with clock being stopped */
368 if (!rate)
369 return 0;
370
371 /* Stop the clock during rate change to avoid glitches */
372 cfg = readl(host->regs + SD_EMMC_CFG);
373 cfg |= CFG_STOP_CLOCK;
374 writel(cfg, host->regs + SD_EMMC_CFG);
375
376 if (ddr) {
377 /* DDR modes require higher module clock */
378 rate <<= 1;
379 cfg |= CFG_DDR;
380 } else {
381 cfg &= ~CFG_DDR;
382 }
383 writel(cfg, host->regs + SD_EMMC_CFG);
384 host->ddr = ddr;
385
386 ret = clk_set_rate(host->mmc_clk, rate);
387 if (ret) {
388 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
389 rate, ret);
390 return ret;
391 }
392
393 host->req_rate = rate;
394 mmc->actual_clock = clk_get_rate(host->mmc_clk);
395
396 /* We should report the real output frequency of the controller */
397 if (ddr) {
398 host->req_rate >>= 1;
399 mmc->actual_clock >>= 1;
400 }
401
402 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
403 if (rate != mmc->actual_clock)
404 dev_dbg(host->dev, "requested rate was %lu\n", rate);
405
406 /* (re)start clock */
407 meson_mmc_clk_ungate(host);
408
409 return 0;
410 }
411
412 /*
413 * The SD/eMMC IP block has an internal mux and divider used for
414 * generating the MMC clock. Use the clock framework to create and
415 * manage these clocks.
416 */
meson_mmc_clk_init(struct meson_host * host)417 static int meson_mmc_clk_init(struct meson_host *host)
418 {
419 struct clk_init_data init;
420 struct clk_mux *mux;
421 struct clk_divider *div;
422 char clk_name[32];
423 int i, ret = 0;
424 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
425 const char *clk_parent[1];
426 u32 clk_reg;
427
428 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
429 clk_reg = CLK_ALWAYS_ON(host);
430 clk_reg |= CLK_DIV_MASK;
431 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
432 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
433 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
434 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
435
436 /* get the mux parents */
437 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
438 struct clk *clk;
439 char name[16];
440
441 snprintf(name, sizeof(name), "clkin%d", i);
442 clk = devm_clk_get(host->dev, name);
443 if (IS_ERR(clk))
444 return dev_err_probe(host->dev, PTR_ERR(clk),
445 "Missing clock %s\n", name);
446
447 mux_parent_names[i] = __clk_get_name(clk);
448 }
449
450 /* create the mux */
451 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
452 if (!mux)
453 return -ENOMEM;
454
455 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
456 init.name = clk_name;
457 init.ops = &clk_mux_ops;
458 init.flags = 0;
459 init.parent_names = mux_parent_names;
460 init.num_parents = MUX_CLK_NUM_PARENTS;
461
462 mux->reg = host->regs + SD_EMMC_CLOCK;
463 mux->shift = __ffs(CLK_SRC_MASK);
464 mux->mask = CLK_SRC_MASK >> mux->shift;
465 mux->hw.init = &init;
466
467 host->mux_clk = devm_clk_register(host->dev, &mux->hw);
468 if (WARN_ON(IS_ERR(host->mux_clk)))
469 return PTR_ERR(host->mux_clk);
470
471 /* create the divider */
472 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
473 if (!div)
474 return -ENOMEM;
475
476 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
477 init.name = clk_name;
478 init.ops = &clk_divider_ops;
479 init.flags = CLK_SET_RATE_PARENT;
480 clk_parent[0] = __clk_get_name(host->mux_clk);
481 init.parent_names = clk_parent;
482 init.num_parents = 1;
483
484 div->reg = host->regs + SD_EMMC_CLOCK;
485 div->shift = __ffs(CLK_DIV_MASK);
486 div->width = __builtin_popcountl(CLK_DIV_MASK);
487 div->hw.init = &init;
488 div->flags = CLK_DIVIDER_ONE_BASED;
489
490 host->mmc_clk = devm_clk_register(host->dev, &div->hw);
491 if (WARN_ON(IS_ERR(host->mmc_clk)))
492 return PTR_ERR(host->mmc_clk);
493
494 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
495 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
496 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
497 if (ret)
498 return ret;
499
500 return clk_prepare_enable(host->mmc_clk);
501 }
502
meson_mmc_disable_resampling(struct meson_host * host)503 static void meson_mmc_disable_resampling(struct meson_host *host)
504 {
505 unsigned int val = readl(host->regs + host->data->adjust);
506
507 val &= ~ADJUST_ADJ_EN;
508 writel(val, host->regs + host->data->adjust);
509 }
510
meson_mmc_reset_resampling(struct meson_host * host)511 static void meson_mmc_reset_resampling(struct meson_host *host)
512 {
513 unsigned int val;
514
515 meson_mmc_disable_resampling(host);
516
517 val = readl(host->regs + host->data->adjust);
518 val &= ~ADJUST_ADJ_DELAY_MASK;
519 writel(val, host->regs + host->data->adjust);
520 }
521
meson_mmc_resampling_tuning(struct mmc_host * mmc,u32 opcode)522 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
523 {
524 struct meson_host *host = mmc_priv(mmc);
525 unsigned int val, dly, max_dly, i;
526 int ret;
527
528 /* Resampling is done using the source clock */
529 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
530 clk_get_rate(host->mmc_clk));
531
532 val = readl(host->regs + host->data->adjust);
533 val |= ADJUST_ADJ_EN;
534 writel(val, host->regs + host->data->adjust);
535
536 if (mmc_doing_retune(mmc))
537 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
538 else
539 dly = 0;
540
541 for (i = 0; i < max_dly; i++) {
542 val &= ~ADJUST_ADJ_DELAY_MASK;
543 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
544 writel(val, host->regs + host->data->adjust);
545
546 ret = mmc_send_tuning(mmc, opcode, NULL);
547 if (!ret) {
548 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
549 (dly + i) % max_dly);
550 return 0;
551 }
552 }
553
554 meson_mmc_reset_resampling(host);
555 return -EIO;
556 }
557
meson_mmc_prepare_ios_clock(struct meson_host * host,struct mmc_ios * ios)558 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
559 struct mmc_ios *ios)
560 {
561 bool ddr;
562
563 switch (ios->timing) {
564 case MMC_TIMING_MMC_DDR52:
565 case MMC_TIMING_UHS_DDR50:
566 ddr = true;
567 break;
568
569 default:
570 ddr = false;
571 break;
572 }
573
574 return meson_mmc_clk_set(host, ios->clock, ddr);
575 }
576
meson_mmc_check_resampling(struct meson_host * host,struct mmc_ios * ios)577 static void meson_mmc_check_resampling(struct meson_host *host,
578 struct mmc_ios *ios)
579 {
580 switch (ios->timing) {
581 case MMC_TIMING_LEGACY:
582 case MMC_TIMING_MMC_HS:
583 case MMC_TIMING_SD_HS:
584 case MMC_TIMING_MMC_DDR52:
585 meson_mmc_disable_resampling(host);
586 break;
587 }
588 }
589
meson_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)590 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
591 {
592 struct meson_host *host = mmc_priv(mmc);
593 u32 bus_width, val;
594 int err;
595
596 /*
597 * GPIO regulator, only controls switching between 1v8 and
598 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
599 */
600 switch (ios->power_mode) {
601 case MMC_POWER_OFF:
602 if (!IS_ERR(mmc->supply.vmmc))
603 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
604
605 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
606 regulator_disable(mmc->supply.vqmmc);
607 host->vqmmc_enabled = false;
608 }
609
610 break;
611
612 case MMC_POWER_UP:
613 if (!IS_ERR(mmc->supply.vmmc))
614 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
615
616 break;
617
618 case MMC_POWER_ON:
619 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
620 int ret = regulator_enable(mmc->supply.vqmmc);
621
622 if (ret < 0)
623 dev_err(host->dev,
624 "failed to enable vqmmc regulator\n");
625 else
626 host->vqmmc_enabled = true;
627 }
628
629 break;
630 }
631
632 /* Bus width */
633 switch (ios->bus_width) {
634 case MMC_BUS_WIDTH_1:
635 bus_width = CFG_BUS_WIDTH_1;
636 break;
637 case MMC_BUS_WIDTH_4:
638 bus_width = CFG_BUS_WIDTH_4;
639 break;
640 case MMC_BUS_WIDTH_8:
641 bus_width = CFG_BUS_WIDTH_8;
642 break;
643 default:
644 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
645 ios->bus_width);
646 bus_width = CFG_BUS_WIDTH_4;
647 }
648
649 val = readl(host->regs + SD_EMMC_CFG);
650 val &= ~CFG_BUS_WIDTH_MASK;
651 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
652 writel(val, host->regs + SD_EMMC_CFG);
653
654 meson_mmc_check_resampling(host, ios);
655 err = meson_mmc_prepare_ios_clock(host, ios);
656 if (err)
657 dev_err(host->dev, "Failed to set clock: %d\n,", err);
658
659 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
660 }
661
meson_mmc_request_done(struct mmc_host * mmc,struct mmc_request * mrq)662 static void meson_mmc_request_done(struct mmc_host *mmc,
663 struct mmc_request *mrq)
664 {
665 struct meson_host *host = mmc_priv(mmc);
666
667 host->cmd = NULL;
668 if (host->needs_pre_post_req)
669 meson_mmc_post_req(mmc, mrq, 0);
670 mmc_request_done(host->mmc, mrq);
671 }
672
meson_mmc_set_blksz(struct mmc_host * mmc,unsigned int blksz)673 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
674 {
675 struct meson_host *host = mmc_priv(mmc);
676 u32 cfg, blksz_old;
677
678 cfg = readl(host->regs + SD_EMMC_CFG);
679 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
680
681 if (!is_power_of_2(blksz))
682 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
683
684 blksz = ilog2(blksz);
685
686 /* check if block-size matches, if not update */
687 if (blksz == blksz_old)
688 return;
689
690 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
691 blksz_old, blksz);
692
693 cfg &= ~CFG_BLK_LEN_MASK;
694 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
695 writel(cfg, host->regs + SD_EMMC_CFG);
696 }
697
meson_mmc_set_response_bits(struct mmc_command * cmd,u32 * cmd_cfg)698 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
699 {
700 if (cmd->flags & MMC_RSP_PRESENT) {
701 if (cmd->flags & MMC_RSP_136)
702 *cmd_cfg |= CMD_CFG_RESP_128;
703 *cmd_cfg |= CMD_CFG_RESP_NUM;
704
705 if (!(cmd->flags & MMC_RSP_CRC))
706 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
707
708 if (cmd->flags & MMC_RSP_BUSY)
709 *cmd_cfg |= CMD_CFG_R1B;
710 } else {
711 *cmd_cfg |= CMD_CFG_NO_RESP;
712 }
713 }
714
meson_mmc_desc_chain_transfer(struct mmc_host * mmc,u32 cmd_cfg)715 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
716 {
717 struct meson_host *host = mmc_priv(mmc);
718 struct sd_emmc_desc *desc = host->descs;
719 struct mmc_data *data = host->cmd->data;
720 struct scatterlist *sg;
721 u32 start;
722 int i;
723
724 if (data->flags & MMC_DATA_WRITE)
725 cmd_cfg |= CMD_CFG_DATA_WR;
726
727 if (data->blocks > 1) {
728 cmd_cfg |= CMD_CFG_BLOCK_MODE;
729 meson_mmc_set_blksz(mmc, data->blksz);
730 }
731
732 for_each_sg(data->sg, sg, data->sg_count, i) {
733 unsigned int len = sg_dma_len(sg);
734
735 if (data->blocks > 1)
736 len /= data->blksz;
737
738 desc[i].cmd_cfg = cmd_cfg;
739 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
740 if (i > 0)
741 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
742 desc[i].cmd_arg = host->cmd->arg;
743 desc[i].cmd_resp = 0;
744 desc[i].cmd_data = sg_dma_address(sg);
745 }
746 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
747
748 dma_wmb(); /* ensure descriptor is written before kicked */
749 start = host->descs_dma_addr | START_DESC_BUSY;
750 writel(start, host->regs + SD_EMMC_START);
751 }
752
753 /* local sg copy for dram_access_quirk */
meson_mmc_copy_buffer(struct meson_host * host,struct mmc_data * data,size_t buflen,bool to_buffer)754 static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
755 size_t buflen, bool to_buffer)
756 {
757 unsigned int sg_flags = SG_MITER_ATOMIC;
758 struct scatterlist *sgl = data->sg;
759 unsigned int nents = data->sg_len;
760 struct sg_mapping_iter miter;
761 unsigned int offset = 0;
762
763 if (to_buffer)
764 sg_flags |= SG_MITER_FROM_SG;
765 else
766 sg_flags |= SG_MITER_TO_SG;
767
768 sg_miter_start(&miter, sgl, nents, sg_flags);
769
770 while ((offset < buflen) && sg_miter_next(&miter)) {
771 unsigned int buf_offset = 0;
772 unsigned int len, left;
773 u32 *buf = miter.addr;
774
775 len = min(miter.length, buflen - offset);
776 left = len;
777
778 if (to_buffer) {
779 do {
780 writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
781
782 buf_offset += 4;
783 left -= 4;
784 } while (left);
785 } else {
786 do {
787 *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
788
789 buf_offset += 4;
790 left -= 4;
791 } while (left);
792 }
793
794 offset += len;
795 }
796
797 sg_miter_stop(&miter);
798 }
799
meson_mmc_start_cmd(struct mmc_host * mmc,struct mmc_command * cmd)800 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
801 {
802 struct meson_host *host = mmc_priv(mmc);
803 struct mmc_data *data = cmd->data;
804 u32 cmd_cfg = 0, cmd_data = 0;
805 unsigned int xfer_bytes = 0;
806
807 /* Setup descriptors */
808 dma_rmb();
809
810 host->cmd = cmd;
811
812 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
813 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
814
815 meson_mmc_set_response_bits(cmd, &cmd_cfg);
816
817 /* data? */
818 if (data) {
819 data->bytes_xfered = 0;
820 cmd_cfg |= CMD_CFG_DATA_IO;
821 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
822 ilog2(meson_mmc_get_timeout_msecs(data)));
823
824 if (meson_mmc_desc_chain_mode(data)) {
825 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
826 return;
827 }
828
829 if (data->blocks > 1) {
830 cmd_cfg |= CMD_CFG_BLOCK_MODE;
831 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
832 data->blocks);
833 meson_mmc_set_blksz(mmc, data->blksz);
834 } else {
835 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
836 }
837
838 xfer_bytes = data->blksz * data->blocks;
839 if (data->flags & MMC_DATA_WRITE) {
840 cmd_cfg |= CMD_CFG_DATA_WR;
841 WARN_ON(xfer_bytes > host->bounce_buf_size);
842 if (host->dram_access_quirk)
843 meson_mmc_copy_buffer(host, data, xfer_bytes, true);
844 else
845 sg_copy_to_buffer(data->sg, data->sg_len,
846 host->bounce_buf, xfer_bytes);
847 dma_wmb();
848 }
849
850 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
851 } else {
852 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
853 ilog2(SD_EMMC_CMD_TIMEOUT));
854 }
855
856 /* Last descriptor */
857 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
858 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
859 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
860 writel(0, host->regs + SD_EMMC_CMD_RSP);
861 wmb(); /* ensure descriptor is written before kicked */
862 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
863 }
864
meson_mmc_validate_dram_access(struct mmc_host * mmc,struct mmc_data * data)865 static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data)
866 {
867 struct scatterlist *sg;
868 int i;
869
870 /* Reject request if any element offset or size is not 32bit aligned */
871 for_each_sg(data->sg, sg, data->sg_len, i) {
872 if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
873 !IS_ALIGNED(sg->length, sizeof(u32))) {
874 dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",
875 data->sg->offset, data->sg->length);
876 return -EINVAL;
877 }
878 }
879
880 return 0;
881 }
882
meson_mmc_request(struct mmc_host * mmc,struct mmc_request * mrq)883 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
884 {
885 struct meson_host *host = mmc_priv(mmc);
886 host->needs_pre_post_req = mrq->data &&
887 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
888
889 /*
890 * The memory at the end of the controller used as bounce buffer for
891 * the dram_access_quirk only accepts 32bit read/write access,
892 * check the aligment and length of the data before starting the request.
893 */
894 if (host->dram_access_quirk && mrq->data) {
895 mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
896 if (mrq->cmd->error) {
897 mmc_request_done(mmc, mrq);
898 return;
899 }
900 }
901
902 if (host->needs_pre_post_req) {
903 meson_mmc_get_transfer_mode(mmc, mrq);
904 if (!meson_mmc_desc_chain_mode(mrq->data))
905 host->needs_pre_post_req = false;
906 }
907
908 if (host->needs_pre_post_req)
909 meson_mmc_pre_req(mmc, mrq);
910
911 /* Stop execution */
912 writel(0, host->regs + SD_EMMC_START);
913
914 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
915 }
916
meson_mmc_read_resp(struct mmc_host * mmc,struct mmc_command * cmd)917 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
918 {
919 struct meson_host *host = mmc_priv(mmc);
920
921 if (cmd->flags & MMC_RSP_136) {
922 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
923 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
924 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
925 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
926 } else if (cmd->flags & MMC_RSP_PRESENT) {
927 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
928 }
929 }
930
meson_mmc_irq(int irq,void * dev_id)931 static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
932 {
933 struct meson_host *host = dev_id;
934 struct mmc_command *cmd;
935 struct mmc_data *data;
936 u32 irq_en, status, raw_status;
937 irqreturn_t ret = IRQ_NONE;
938
939 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
940 raw_status = readl(host->regs + SD_EMMC_STATUS);
941 status = raw_status & irq_en;
942
943 if (!status) {
944 dev_dbg(host->dev,
945 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
946 irq_en, raw_status);
947 return IRQ_NONE;
948 }
949
950 if (WARN_ON(!host) || WARN_ON(!host->cmd))
951 return IRQ_NONE;
952
953 /* ack all raised interrupts */
954 writel(status, host->regs + SD_EMMC_STATUS);
955
956 cmd = host->cmd;
957 data = cmd->data;
958 cmd->error = 0;
959 if (status & IRQ_CRC_ERR) {
960 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
961 cmd->error = -EILSEQ;
962 ret = IRQ_WAKE_THREAD;
963 goto out;
964 }
965
966 if (status & IRQ_TIMEOUTS) {
967 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
968 cmd->error = -ETIMEDOUT;
969 ret = IRQ_WAKE_THREAD;
970 goto out;
971 }
972
973 meson_mmc_read_resp(host->mmc, cmd);
974
975 if (status & IRQ_SDIO) {
976 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
977 ret = IRQ_HANDLED;
978 }
979
980 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
981 if (data && !cmd->error)
982 data->bytes_xfered = data->blksz * data->blocks;
983
984 return IRQ_WAKE_THREAD;
985 }
986
987 out:
988 if (cmd->error) {
989 /* Stop desc in case of errors */
990 u32 start = readl(host->regs + SD_EMMC_START);
991
992 start &= ~START_DESC_BUSY;
993 writel(start, host->regs + SD_EMMC_START);
994 }
995
996 return ret;
997 }
998
meson_mmc_wait_desc_stop(struct meson_host * host)999 static int meson_mmc_wait_desc_stop(struct meson_host *host)
1000 {
1001 u32 status;
1002
1003 /*
1004 * It may sometimes take a while for it to actually halt. Here, we
1005 * are giving it 5ms to comply
1006 *
1007 * If we don't confirm the descriptor is stopped, it might raise new
1008 * IRQs after we have called mmc_request_done() which is bad.
1009 */
1010
1011 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
1012 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
1013 100, 5000);
1014 }
1015
meson_mmc_irq_thread(int irq,void * dev_id)1016 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1017 {
1018 struct meson_host *host = dev_id;
1019 struct mmc_command *next_cmd, *cmd = host->cmd;
1020 struct mmc_data *data;
1021 unsigned int xfer_bytes;
1022
1023 if (WARN_ON(!cmd))
1024 return IRQ_NONE;
1025
1026 if (cmd->error) {
1027 meson_mmc_wait_desc_stop(host);
1028 meson_mmc_request_done(host->mmc, cmd->mrq);
1029
1030 return IRQ_HANDLED;
1031 }
1032
1033 data = cmd->data;
1034 if (meson_mmc_bounce_buf_read(data)) {
1035 xfer_bytes = data->blksz * data->blocks;
1036 WARN_ON(xfer_bytes > host->bounce_buf_size);
1037 if (host->dram_access_quirk)
1038 meson_mmc_copy_buffer(host, data, xfer_bytes, false);
1039 else
1040 sg_copy_from_buffer(data->sg, data->sg_len,
1041 host->bounce_buf, xfer_bytes);
1042 }
1043
1044 next_cmd = meson_mmc_get_next_command(cmd);
1045 if (next_cmd)
1046 meson_mmc_start_cmd(host->mmc, next_cmd);
1047 else
1048 meson_mmc_request_done(host->mmc, cmd->mrq);
1049
1050 return IRQ_HANDLED;
1051 }
1052
1053 /*
1054 * NOTE: we only need this until the GPIO/pinctrl driver can handle
1055 * interrupts. For now, the MMC core will use this for polling.
1056 */
meson_mmc_get_cd(struct mmc_host * mmc)1057 static int meson_mmc_get_cd(struct mmc_host *mmc)
1058 {
1059 int status = mmc_gpio_get_cd(mmc);
1060
1061 if (status == -ENOSYS)
1062 return 1; /* assume present */
1063
1064 return status;
1065 }
1066
meson_mmc_cfg_init(struct meson_host * host)1067 static void meson_mmc_cfg_init(struct meson_host *host)
1068 {
1069 u32 cfg = 0;
1070
1071 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1072 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1073 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1074 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1075
1076 /* abort chain on R/W errors */
1077 cfg |= CFG_ERR_ABORT;
1078
1079 writel(cfg, host->regs + SD_EMMC_CFG);
1080 }
1081
meson_mmc_card_busy(struct mmc_host * mmc)1082 static int meson_mmc_card_busy(struct mmc_host *mmc)
1083 {
1084 struct meson_host *host = mmc_priv(mmc);
1085 u32 regval;
1086
1087 regval = readl(host->regs + SD_EMMC_STATUS);
1088
1089 /* We are only interrested in lines 0 to 3, so mask the other ones */
1090 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1091 }
1092
meson_mmc_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)1093 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1094 {
1095 int ret;
1096
1097 /* vqmmc regulator is available */
1098 if (!IS_ERR(mmc->supply.vqmmc)) {
1099 /*
1100 * The usual amlogic setup uses a GPIO to switch from one
1101 * regulator to the other. While the voltage ramp up is
1102 * pretty fast, care must be taken when switching from 3.3v
1103 * to 1.8v. Please make sure the regulator framework is aware
1104 * of your own regulator constraints
1105 */
1106 ret = mmc_regulator_set_vqmmc(mmc, ios);
1107 return ret < 0 ? ret : 0;
1108 }
1109
1110 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1111 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1112 return 0;
1113
1114 return -EINVAL;
1115 }
1116
1117 static const struct mmc_host_ops meson_mmc_ops = {
1118 .request = meson_mmc_request,
1119 .set_ios = meson_mmc_set_ios,
1120 .get_cd = meson_mmc_get_cd,
1121 .pre_req = meson_mmc_pre_req,
1122 .post_req = meson_mmc_post_req,
1123 .execute_tuning = meson_mmc_resampling_tuning,
1124 .card_busy = meson_mmc_card_busy,
1125 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1126 };
1127
meson_mmc_probe(struct platform_device * pdev)1128 static int meson_mmc_probe(struct platform_device *pdev)
1129 {
1130 struct resource *res;
1131 struct meson_host *host;
1132 struct mmc_host *mmc;
1133 int ret;
1134
1135 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1136 if (!mmc)
1137 return -ENOMEM;
1138 host = mmc_priv(mmc);
1139 host->mmc = mmc;
1140 host->dev = &pdev->dev;
1141 dev_set_drvdata(&pdev->dev, host);
1142
1143 /* The G12A SDIO Controller needs an SRAM bounce buffer */
1144 host->dram_access_quirk = device_property_read_bool(&pdev->dev,
1145 "amlogic,dram-access-quirk");
1146
1147 /* Get regulators and the supported OCR mask */
1148 host->vqmmc_enabled = false;
1149 ret = mmc_regulator_get_supply(mmc);
1150 if (ret)
1151 goto free_host;
1152
1153 ret = mmc_of_parse(mmc);
1154 if (ret) {
1155 if (ret != -EPROBE_DEFER)
1156 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1157 goto free_host;
1158 }
1159
1160 host->data = (struct meson_mmc_data *)
1161 of_device_get_match_data(&pdev->dev);
1162 if (!host->data) {
1163 ret = -EINVAL;
1164 goto free_host;
1165 }
1166
1167 ret = device_reset_optional(&pdev->dev);
1168 if (ret) {
1169 dev_err_probe(&pdev->dev, ret, "device reset failed\n");
1170 goto free_host;
1171 }
1172
1173 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1174 host->regs = devm_ioremap_resource(&pdev->dev, res);
1175 if (IS_ERR(host->regs)) {
1176 ret = PTR_ERR(host->regs);
1177 goto free_host;
1178 }
1179
1180 host->irq = platform_get_irq(pdev, 0);
1181 if (host->irq < 0) {
1182 ret = host->irq;
1183 goto free_host;
1184 }
1185
1186 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1187 if (IS_ERR(host->pinctrl)) {
1188 ret = PTR_ERR(host->pinctrl);
1189 goto free_host;
1190 }
1191
1192 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1193 "clk-gate");
1194 if (IS_ERR(host->pins_clk_gate)) {
1195 dev_warn(&pdev->dev,
1196 "can't get clk-gate pinctrl, using clk_stop bit\n");
1197 host->pins_clk_gate = NULL;
1198 }
1199
1200 host->core_clk = devm_clk_get(&pdev->dev, "core");
1201 if (IS_ERR(host->core_clk)) {
1202 ret = PTR_ERR(host->core_clk);
1203 goto free_host;
1204 }
1205
1206 ret = clk_prepare_enable(host->core_clk);
1207 if (ret)
1208 goto free_host;
1209
1210 ret = meson_mmc_clk_init(host);
1211 if (ret)
1212 goto err_core_clk;
1213
1214 /* set config to sane default */
1215 meson_mmc_cfg_init(host);
1216
1217 /* Stop execution */
1218 writel(0, host->regs + SD_EMMC_START);
1219
1220 /* clear, ack and enable interrupts */
1221 writel(0, host->regs + SD_EMMC_IRQ_EN);
1222 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1223 host->regs + SD_EMMC_STATUS);
1224 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1225 host->regs + SD_EMMC_IRQ_EN);
1226
1227 ret = request_threaded_irq(host->irq, meson_mmc_irq,
1228 meson_mmc_irq_thread, IRQF_ONESHOT,
1229 dev_name(&pdev->dev), host);
1230 if (ret)
1231 goto err_init_clk;
1232
1233 mmc->caps |= MMC_CAP_CMD23;
1234 if (host->dram_access_quirk) {
1235 /* Limit segments to 1 due to low available sram memory */
1236 mmc->max_segs = 1;
1237 /* Limit to the available sram memory */
1238 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
1239 mmc->max_blk_size;
1240 } else {
1241 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1242 mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
1243 sizeof(struct sd_emmc_desc);
1244 }
1245 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1246 mmc->max_seg_size = mmc->max_req_size;
1247
1248 /*
1249 * At the moment, we don't know how to reliably enable HS400.
1250 * From the different datasheets, it is not even clear if this mode
1251 * is officially supported by any of the SoCs
1252 */
1253 mmc->caps2 &= ~MMC_CAP2_HS400;
1254
1255 if (host->dram_access_quirk) {
1256 /*
1257 * The MMC Controller embeds 1,5KiB of internal SRAM
1258 * that can be used to be used as bounce buffer.
1259 * In the case of the G12A SDIO controller, use these
1260 * instead of the DDR memory
1261 */
1262 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
1263 host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
1264 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
1265 } else {
1266 /* data bounce buffer */
1267 host->bounce_buf_size = mmc->max_req_size;
1268 host->bounce_buf =
1269 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1270 &host->bounce_dma_addr, GFP_KERNEL);
1271 if (host->bounce_buf == NULL) {
1272 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1273 ret = -ENOMEM;
1274 goto err_free_irq;
1275 }
1276 }
1277
1278 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1279 &host->descs_dma_addr, GFP_KERNEL);
1280 if (!host->descs) {
1281 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1282 ret = -ENOMEM;
1283 goto err_bounce_buf;
1284 }
1285
1286 mmc->ops = &meson_mmc_ops;
1287 ret = mmc_add_host(mmc);
1288 if (ret)
1289 goto err_free_irq;
1290
1291 return 0;
1292
1293 err_bounce_buf:
1294 if (!host->dram_access_quirk)
1295 dma_free_coherent(host->dev, host->bounce_buf_size,
1296 host->bounce_buf, host->bounce_dma_addr);
1297 err_free_irq:
1298 free_irq(host->irq, host);
1299 err_init_clk:
1300 clk_disable_unprepare(host->mmc_clk);
1301 err_core_clk:
1302 clk_disable_unprepare(host->core_clk);
1303 free_host:
1304 mmc_free_host(mmc);
1305 return ret;
1306 }
1307
meson_mmc_remove(struct platform_device * pdev)1308 static int meson_mmc_remove(struct platform_device *pdev)
1309 {
1310 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1311
1312 mmc_remove_host(host->mmc);
1313
1314 /* disable interrupts */
1315 writel(0, host->regs + SD_EMMC_IRQ_EN);
1316 free_irq(host->irq, host);
1317
1318 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1319 host->descs, host->descs_dma_addr);
1320
1321 if (!host->dram_access_quirk)
1322 dma_free_coherent(host->dev, host->bounce_buf_size,
1323 host->bounce_buf, host->bounce_dma_addr);
1324
1325 clk_disable_unprepare(host->mmc_clk);
1326 clk_disable_unprepare(host->core_clk);
1327
1328 mmc_free_host(host->mmc);
1329 return 0;
1330 }
1331
1332 static const struct meson_mmc_data meson_gx_data = {
1333 .tx_delay_mask = CLK_V2_TX_DELAY_MASK,
1334 .rx_delay_mask = CLK_V2_RX_DELAY_MASK,
1335 .always_on = CLK_V2_ALWAYS_ON,
1336 .adjust = SD_EMMC_ADJUST,
1337 };
1338
1339 static const struct meson_mmc_data meson_axg_data = {
1340 .tx_delay_mask = CLK_V3_TX_DELAY_MASK,
1341 .rx_delay_mask = CLK_V3_RX_DELAY_MASK,
1342 .always_on = CLK_V3_ALWAYS_ON,
1343 .adjust = SD_EMMC_V3_ADJUST,
1344 };
1345
1346 static const struct of_device_id meson_mmc_of_match[] = {
1347 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
1348 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
1349 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
1350 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
1351 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
1352 {}
1353 };
1354 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1355
1356 static struct platform_driver meson_mmc_driver = {
1357 .probe = meson_mmc_probe,
1358 .remove = meson_mmc_remove,
1359 .driver = {
1360 .name = DRIVER_NAME,
1361 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1362 .of_match_table = meson_mmc_of_match,
1363 },
1364 };
1365
1366 module_platform_driver(meson_mmc_driver);
1367
1368 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1369 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1370 MODULE_LICENSE("GPL v2");
1371