1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2004 Richard Purdie
4 * Copyright (C) 2008 Dmitry Baryshkov
5 *
6 * Based on Sharp's NAND driver sharp_sl.c
7 */
8
9 #include <linux/genhd.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/nand-ecc-sw-hamming.h>
15 #include <linux/mtd/rawnand.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/mtd/sharpsl.h>
18 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/io.h>
21
22 struct sharpsl_nand {
23 struct nand_controller controller;
24 struct nand_chip chip;
25
26 void __iomem *io;
27 };
28
mtd_to_sharpsl(struct mtd_info * mtd)29 static inline struct sharpsl_nand *mtd_to_sharpsl(struct mtd_info *mtd)
30 {
31 return container_of(mtd_to_nand(mtd), struct sharpsl_nand, chip);
32 }
33
34 /* register offset */
35 #define ECCLPLB 0x00 /* line parity 7 - 0 bit */
36 #define ECCLPUB 0x04 /* line parity 15 - 8 bit */
37 #define ECCCP 0x08 /* column parity 5 - 0 bit */
38 #define ECCCNTR 0x0C /* ECC byte counter */
39 #define ECCCLRR 0x10 /* cleare ECC */
40 #define FLASHIO 0x14 /* Flash I/O */
41 #define FLASHCTL 0x18 /* Flash Control */
42
43 /* Flash control bit */
44 #define FLRYBY (1 << 5)
45 #define FLCE1 (1 << 4)
46 #define FLWP (1 << 3)
47 #define FLALE (1 << 2)
48 #define FLCLE (1 << 1)
49 #define FLCE0 (1 << 0)
50
51 /*
52 * hardware specific access to control-lines
53 * ctrl:
54 * NAND_CNE: bit 0 -> ! bit 0 & 4
55 * NAND_CLE: bit 1 -> bit 1
56 * NAND_ALE: bit 2 -> bit 2
57 *
58 */
sharpsl_nand_hwcontrol(struct nand_chip * chip,int cmd,unsigned int ctrl)59 static void sharpsl_nand_hwcontrol(struct nand_chip *chip, int cmd,
60 unsigned int ctrl)
61 {
62 struct sharpsl_nand *sharpsl = mtd_to_sharpsl(nand_to_mtd(chip));
63
64 if (ctrl & NAND_CTRL_CHANGE) {
65 unsigned char bits = ctrl & 0x07;
66
67 bits |= (ctrl & 0x01) << 4;
68
69 bits ^= 0x11;
70
71 writeb((readb(sharpsl->io + FLASHCTL) & ~0x17) | bits, sharpsl->io + FLASHCTL);
72 }
73
74 if (cmd != NAND_CMD_NONE)
75 writeb(cmd, chip->legacy.IO_ADDR_W);
76 }
77
sharpsl_nand_dev_ready(struct nand_chip * chip)78 static int sharpsl_nand_dev_ready(struct nand_chip *chip)
79 {
80 struct sharpsl_nand *sharpsl = mtd_to_sharpsl(nand_to_mtd(chip));
81 return !((readb(sharpsl->io + FLASHCTL) & FLRYBY) == 0);
82 }
83
sharpsl_nand_enable_hwecc(struct nand_chip * chip,int mode)84 static void sharpsl_nand_enable_hwecc(struct nand_chip *chip, int mode)
85 {
86 struct sharpsl_nand *sharpsl = mtd_to_sharpsl(nand_to_mtd(chip));
87 writeb(0, sharpsl->io + ECCCLRR);
88 }
89
sharpsl_nand_calculate_ecc(struct nand_chip * chip,const u_char * dat,u_char * ecc_code)90 static int sharpsl_nand_calculate_ecc(struct nand_chip *chip,
91 const u_char * dat, u_char * ecc_code)
92 {
93 struct sharpsl_nand *sharpsl = mtd_to_sharpsl(nand_to_mtd(chip));
94 ecc_code[0] = ~readb(sharpsl->io + ECCLPUB);
95 ecc_code[1] = ~readb(sharpsl->io + ECCLPLB);
96 ecc_code[2] = (~readb(sharpsl->io + ECCCP) << 2) | 0x03;
97 return readb(sharpsl->io + ECCCNTR) != 0;
98 }
99
sharpsl_nand_correct_ecc(struct nand_chip * chip,unsigned char * buf,unsigned char * read_ecc,unsigned char * calc_ecc)100 static int sharpsl_nand_correct_ecc(struct nand_chip *chip,
101 unsigned char *buf,
102 unsigned char *read_ecc,
103 unsigned char *calc_ecc)
104 {
105 return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
106 chip->ecc.size, false);
107 }
108
sharpsl_attach_chip(struct nand_chip * chip)109 static int sharpsl_attach_chip(struct nand_chip *chip)
110 {
111 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
112 return 0;
113
114 chip->ecc.size = 256;
115 chip->ecc.bytes = 3;
116 chip->ecc.strength = 1;
117 chip->ecc.hwctl = sharpsl_nand_enable_hwecc;
118 chip->ecc.calculate = sharpsl_nand_calculate_ecc;
119 chip->ecc.correct = sharpsl_nand_correct_ecc;
120
121 return 0;
122 }
123
124 static const struct nand_controller_ops sharpsl_ops = {
125 .attach_chip = sharpsl_attach_chip,
126 };
127
128 /*
129 * Main initialization routine
130 */
sharpsl_nand_probe(struct platform_device * pdev)131 static int sharpsl_nand_probe(struct platform_device *pdev)
132 {
133 struct nand_chip *this;
134 struct mtd_info *mtd;
135 struct resource *r;
136 int err = 0;
137 struct sharpsl_nand *sharpsl;
138 struct sharpsl_nand_platform_data *data = dev_get_platdata(&pdev->dev);
139
140 if (!data) {
141 dev_err(&pdev->dev, "no platform data!\n");
142 return -EINVAL;
143 }
144
145 /* Allocate memory for MTD device structure and private data */
146 sharpsl = kzalloc(sizeof(struct sharpsl_nand), GFP_KERNEL);
147 if (!sharpsl)
148 return -ENOMEM;
149
150 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
151 if (!r) {
152 dev_err(&pdev->dev, "no io memory resource defined!\n");
153 err = -ENODEV;
154 goto err_get_res;
155 }
156
157 /* map physical address */
158 sharpsl->io = ioremap(r->start, resource_size(r));
159 if (!sharpsl->io) {
160 dev_err(&pdev->dev, "ioremap to access Sharp SL NAND chip failed\n");
161 err = -EIO;
162 goto err_ioremap;
163 }
164
165 /* Get pointer to private data */
166 this = (struct nand_chip *)(&sharpsl->chip);
167
168 nand_controller_init(&sharpsl->controller);
169 sharpsl->controller.ops = &sharpsl_ops;
170 this->controller = &sharpsl->controller;
171
172 /* Link the private data with the MTD structure */
173 mtd = nand_to_mtd(this);
174 mtd->dev.parent = &pdev->dev;
175 mtd_set_ooblayout(mtd, data->ecc_layout);
176
177 platform_set_drvdata(pdev, sharpsl);
178
179 /*
180 * PXA initialize
181 */
182 writeb(readb(sharpsl->io + FLASHCTL) | FLWP, sharpsl->io + FLASHCTL);
183
184 /* Set address of NAND IO lines */
185 this->legacy.IO_ADDR_R = sharpsl->io + FLASHIO;
186 this->legacy.IO_ADDR_W = sharpsl->io + FLASHIO;
187 /* Set address of hardware control function */
188 this->legacy.cmd_ctrl = sharpsl_nand_hwcontrol;
189 this->legacy.dev_ready = sharpsl_nand_dev_ready;
190 /* 15 us command delay time */
191 this->legacy.chip_delay = 15;
192 this->badblock_pattern = data->badblock_pattern;
193
194 /* Scan to find existence of the device */
195 err = nand_scan(this, 1);
196 if (err)
197 goto err_scan;
198
199 /* Register the partitions */
200 mtd->name = "sharpsl-nand";
201
202 err = mtd_device_parse_register(mtd, data->part_parsers, NULL,
203 data->partitions, data->nr_partitions);
204 if (err)
205 goto err_add;
206
207 /* Return happy */
208 return 0;
209
210 err_add:
211 nand_cleanup(this);
212
213 err_scan:
214 iounmap(sharpsl->io);
215 err_ioremap:
216 err_get_res:
217 kfree(sharpsl);
218 return err;
219 }
220
221 /*
222 * Clean up routine
223 */
sharpsl_nand_remove(struct platform_device * pdev)224 static int sharpsl_nand_remove(struct platform_device *pdev)
225 {
226 struct sharpsl_nand *sharpsl = platform_get_drvdata(pdev);
227 struct nand_chip *chip = &sharpsl->chip;
228 int ret;
229
230 /* Unregister device */
231 ret = mtd_device_unregister(nand_to_mtd(chip));
232 WARN_ON(ret);
233
234 /* Release resources */
235 nand_cleanup(chip);
236
237 iounmap(sharpsl->io);
238
239 /* Free the driver's structure */
240 kfree(sharpsl);
241
242 return 0;
243 }
244
245 static struct platform_driver sharpsl_nand_driver = {
246 .driver = {
247 .name = "sharpsl-nand",
248 },
249 .probe = sharpsl_nand_probe,
250 .remove = sharpsl_nand_remove,
251 };
252
253 module_platform_driver(sharpsl_nand_driver);
254
255 MODULE_LICENSE("GPL");
256 MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
257 MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series");
258