1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel PCH/PCU SPI flash driver.
4 *
5 * Copyright (C) 2016, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 */
8
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/sizes.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/mtd/spi-nor.h>
18
19 #include "intel-spi.h"
20
21 /* Offsets are from @ispi->base */
22 #define BFPREG 0x00
23
24 #define HSFSTS_CTL 0x04
25 #define HSFSTS_CTL_FSMIE BIT(31)
26 #define HSFSTS_CTL_FDBC_SHIFT 24
27 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
28
29 #define HSFSTS_CTL_FCYCLE_SHIFT 17
30 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
31 /* HW sequencer opcodes */
32 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
33 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
34 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
35 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
36 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
37 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
38 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
39
40 #define HSFSTS_CTL_FGO BIT(16)
41 #define HSFSTS_CTL_FLOCKDN BIT(15)
42 #define HSFSTS_CTL_FDV BIT(14)
43 #define HSFSTS_CTL_SCIP BIT(5)
44 #define HSFSTS_CTL_AEL BIT(2)
45 #define HSFSTS_CTL_FCERR BIT(1)
46 #define HSFSTS_CTL_FDONE BIT(0)
47
48 #define FADDR 0x08
49 #define DLOCK 0x0c
50 #define FDATA(n) (0x10 + ((n) * 4))
51
52 #define FRACC 0x50
53
54 #define FREG(n) (0x54 + ((n) * 4))
55 #define FREG_BASE_MASK GENMASK(14, 0)
56 #define FREG_LIMIT_SHIFT 16
57 #define FREG_LIMIT_MASK GENMASK(30, 16)
58
59 /* Offset is from @ispi->pregs */
60 #define PR(n) ((n) * 4)
61 #define PR_WPE BIT(31)
62 #define PR_LIMIT_SHIFT 16
63 #define PR_LIMIT_MASK GENMASK(30, 16)
64 #define PR_RPE BIT(15)
65 #define PR_BASE_MASK GENMASK(14, 0)
66
67 /* Offsets are from @ispi->sregs */
68 #define SSFSTS_CTL 0x00
69 #define SSFSTS_CTL_FSMIE BIT(23)
70 #define SSFSTS_CTL_DS BIT(22)
71 #define SSFSTS_CTL_DBC_SHIFT 16
72 #define SSFSTS_CTL_SPOP BIT(11)
73 #define SSFSTS_CTL_ACS BIT(10)
74 #define SSFSTS_CTL_SCGO BIT(9)
75 #define SSFSTS_CTL_COP_SHIFT 12
76 #define SSFSTS_CTL_FRS BIT(7)
77 #define SSFSTS_CTL_DOFRS BIT(6)
78 #define SSFSTS_CTL_AEL BIT(4)
79 #define SSFSTS_CTL_FCERR BIT(3)
80 #define SSFSTS_CTL_FDONE BIT(2)
81 #define SSFSTS_CTL_SCIP BIT(0)
82
83 #define PREOP_OPTYPE 0x04
84 #define OPMENU0 0x08
85 #define OPMENU1 0x0c
86
87 #define OPTYPE_READ_NO_ADDR 0
88 #define OPTYPE_WRITE_NO_ADDR 1
89 #define OPTYPE_READ_WITH_ADDR 2
90 #define OPTYPE_WRITE_WITH_ADDR 3
91
92 /* CPU specifics */
93 #define BYT_PR 0x74
94 #define BYT_SSFSTS_CTL 0x90
95 #define BYT_BCR 0xfc
96 #define BYT_BCR_WPD BIT(0)
97 #define BYT_FREG_NUM 5
98 #define BYT_PR_NUM 5
99
100 #define LPT_PR 0x74
101 #define LPT_SSFSTS_CTL 0x90
102 #define LPT_FREG_NUM 5
103 #define LPT_PR_NUM 5
104
105 #define BXT_PR 0x84
106 #define BXT_SSFSTS_CTL 0xa0
107 #define BXT_FREG_NUM 12
108 #define BXT_PR_NUM 6
109
110 #define CNL_PR 0x84
111 #define CNL_FREG_NUM 6
112 #define CNL_PR_NUM 5
113
114 #define LVSCC 0xc4
115 #define UVSCC 0xc8
116 #define ERASE_OPCODE_SHIFT 8
117 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
118 #define ERASE_64K_OPCODE_SHIFT 16
119 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT)
120
121 #define INTEL_SPI_TIMEOUT 5000 /* ms */
122 #define INTEL_SPI_FIFO_SZ 64
123
124 /**
125 * struct intel_spi - Driver private data
126 * @dev: Device pointer
127 * @info: Pointer to board specific info
128 * @nor: SPI NOR layer structure
129 * @base: Beginning of MMIO space
130 * @pregs: Start of protection registers
131 * @sregs: Start of software sequencer registers
132 * @nregions: Maximum number of regions
133 * @pr_num: Maximum number of protected range registers
134 * @locked: Is SPI setting locked
135 * @swseq_reg: Use SW sequencer in register reads/writes
136 * @swseq_erase: Use SW sequencer in erase operation
137 * @erase_64k: 64k erase supported
138 * @atomic_preopcode: Holds preopcode when atomic sequence is requested
139 * @opcodes: Opcodes which are supported. This are programmed by BIOS
140 * before it locks down the controller.
141 */
142 struct intel_spi {
143 struct device *dev;
144 const struct intel_spi_boardinfo *info;
145 struct spi_nor nor;
146 void __iomem *base;
147 void __iomem *pregs;
148 void __iomem *sregs;
149 size_t nregions;
150 size_t pr_num;
151 bool locked;
152 bool swseq_reg;
153 bool swseq_erase;
154 bool erase_64k;
155 u8 atomic_preopcode;
156 u8 opcodes[8];
157 };
158
159 static bool writeable;
160 module_param(writeable, bool, 0);
161 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
162
intel_spi_dump_regs(struct intel_spi * ispi)163 static void intel_spi_dump_regs(struct intel_spi *ispi)
164 {
165 u32 value;
166 int i;
167
168 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
169
170 value = readl(ispi->base + HSFSTS_CTL);
171 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
172 if (value & HSFSTS_CTL_FLOCKDN)
173 dev_dbg(ispi->dev, "-> Locked\n");
174
175 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
176 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
177
178 for (i = 0; i < 16; i++)
179 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
180 i, readl(ispi->base + FDATA(i)));
181
182 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
183
184 for (i = 0; i < ispi->nregions; i++)
185 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
186 readl(ispi->base + FREG(i)));
187 for (i = 0; i < ispi->pr_num; i++)
188 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
189 readl(ispi->pregs + PR(i)));
190
191 if (ispi->sregs) {
192 value = readl(ispi->sregs + SSFSTS_CTL);
193 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
194 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
195 readl(ispi->sregs + PREOP_OPTYPE));
196 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",
197 readl(ispi->sregs + OPMENU0));
198 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",
199 readl(ispi->sregs + OPMENU1));
200 }
201
202 if (ispi->info->type == INTEL_SPI_BYT)
203 dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
204
205 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));
206 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));
207
208 dev_dbg(ispi->dev, "Protected regions:\n");
209 for (i = 0; i < ispi->pr_num; i++) {
210 u32 base, limit;
211
212 value = readl(ispi->pregs + PR(i));
213 if (!(value & (PR_WPE | PR_RPE)))
214 continue;
215
216 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
217 base = value & PR_BASE_MASK;
218
219 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
220 i, base << 12, (limit << 12) | 0xfff,
221 value & PR_WPE ? 'W' : '.',
222 value & PR_RPE ? 'R' : '.');
223 }
224
225 dev_dbg(ispi->dev, "Flash regions:\n");
226 for (i = 0; i < ispi->nregions; i++) {
227 u32 region, base, limit;
228
229 region = readl(ispi->base + FREG(i));
230 base = region & FREG_BASE_MASK;
231 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
232
233 if (base >= limit || (i > 0 && limit == 0))
234 dev_dbg(ispi->dev, " %02d disabled\n", i);
235 else
236 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
237 i, base << 12, (limit << 12) | 0xfff);
238 }
239
240 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
241 ispi->swseq_reg ? 'S' : 'H');
242 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",
243 ispi->swseq_erase ? 'S' : 'H');
244 }
245
246 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
intel_spi_read_block(struct intel_spi * ispi,void * buf,size_t size)247 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
248 {
249 size_t bytes;
250 int i = 0;
251
252 if (size > INTEL_SPI_FIFO_SZ)
253 return -EINVAL;
254
255 while (size > 0) {
256 bytes = min_t(size_t, size, 4);
257 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
258 size -= bytes;
259 buf += bytes;
260 i++;
261 }
262
263 return 0;
264 }
265
266 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
intel_spi_write_block(struct intel_spi * ispi,const void * buf,size_t size)267 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
268 size_t size)
269 {
270 size_t bytes;
271 int i = 0;
272
273 if (size > INTEL_SPI_FIFO_SZ)
274 return -EINVAL;
275
276 while (size > 0) {
277 bytes = min_t(size_t, size, 4);
278 memcpy_toio(ispi->base + FDATA(i), buf, bytes);
279 size -= bytes;
280 buf += bytes;
281 i++;
282 }
283
284 return 0;
285 }
286
intel_spi_wait_hw_busy(struct intel_spi * ispi)287 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
288 {
289 u32 val;
290
291 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
292 !(val & HSFSTS_CTL_SCIP), 0,
293 INTEL_SPI_TIMEOUT * 1000);
294 }
295
intel_spi_wait_sw_busy(struct intel_spi * ispi)296 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
297 {
298 u32 val;
299
300 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
301 !(val & SSFSTS_CTL_SCIP), 0,
302 INTEL_SPI_TIMEOUT * 1000);
303 }
304
intel_spi_set_writeable(struct intel_spi * ispi)305 static bool intel_spi_set_writeable(struct intel_spi *ispi)
306 {
307 if (!ispi->info->set_writeable)
308 return false;
309
310 return ispi->info->set_writeable(ispi->base, ispi->info->data);
311 }
312
intel_spi_init(struct intel_spi * ispi)313 static int intel_spi_init(struct intel_spi *ispi)
314 {
315 u32 opmenu0, opmenu1, lvscc, uvscc, val;
316 int i;
317
318 switch (ispi->info->type) {
319 case INTEL_SPI_BYT:
320 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
321 ispi->pregs = ispi->base + BYT_PR;
322 ispi->nregions = BYT_FREG_NUM;
323 ispi->pr_num = BYT_PR_NUM;
324 ispi->swseq_reg = true;
325 break;
326
327 case INTEL_SPI_LPT:
328 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
329 ispi->pregs = ispi->base + LPT_PR;
330 ispi->nregions = LPT_FREG_NUM;
331 ispi->pr_num = LPT_PR_NUM;
332 ispi->swseq_reg = true;
333 break;
334
335 case INTEL_SPI_BXT:
336 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
337 ispi->pregs = ispi->base + BXT_PR;
338 ispi->nregions = BXT_FREG_NUM;
339 ispi->pr_num = BXT_PR_NUM;
340 ispi->erase_64k = true;
341 break;
342
343 case INTEL_SPI_CNL:
344 ispi->sregs = NULL;
345 ispi->pregs = ispi->base + CNL_PR;
346 ispi->nregions = CNL_FREG_NUM;
347 ispi->pr_num = CNL_PR_NUM;
348 break;
349
350 default:
351 return -EINVAL;
352 }
353
354 /* Try to disable write protection if user asked to do so */
355 if (writeable && !intel_spi_set_writeable(ispi)) {
356 dev_warn(ispi->dev, "can't disable chip write protection\n");
357 writeable = false;
358 }
359
360 /* Disable #SMI generation from HW sequencer */
361 val = readl(ispi->base + HSFSTS_CTL);
362 val &= ~HSFSTS_CTL_FSMIE;
363 writel(val, ispi->base + HSFSTS_CTL);
364
365 /*
366 * Determine whether erase operation should use HW or SW sequencer.
367 *
368 * The HW sequencer has a predefined list of opcodes, with only the
369 * erase opcode being programmable in LVSCC and UVSCC registers.
370 * If these registers don't contain a valid erase opcode, erase
371 * cannot be done using HW sequencer.
372 */
373 lvscc = readl(ispi->base + LVSCC);
374 uvscc = readl(ispi->base + UVSCC);
375 if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK))
376 ispi->swseq_erase = true;
377 /* SPI controller on Intel BXT supports 64K erase opcode */
378 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)
379 if (!(lvscc & ERASE_64K_OPCODE_MASK) ||
380 !(uvscc & ERASE_64K_OPCODE_MASK))
381 ispi->erase_64k = false;
382
383 if (ispi->sregs == NULL && (ispi->swseq_reg || ispi->swseq_erase)) {
384 dev_err(ispi->dev, "software sequencer not supported, but required\n");
385 return -EINVAL;
386 }
387
388 /*
389 * Some controllers can only do basic operations using hardware
390 * sequencer. All other operations are supposed to be carried out
391 * using software sequencer.
392 */
393 if (ispi->swseq_reg) {
394 /* Disable #SMI generation from SW sequencer */
395 val = readl(ispi->sregs + SSFSTS_CTL);
396 val &= ~SSFSTS_CTL_FSMIE;
397 writel(val, ispi->sregs + SSFSTS_CTL);
398 }
399
400 /* Check controller's lock status */
401 val = readl(ispi->base + HSFSTS_CTL);
402 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
403
404 if (ispi->locked && ispi->sregs) {
405 /*
406 * BIOS programs allowed opcodes and then locks down the
407 * register. So read back what opcodes it decided to support.
408 * That's the set we are going to support as well.
409 */
410 opmenu0 = readl(ispi->sregs + OPMENU0);
411 opmenu1 = readl(ispi->sregs + OPMENU1);
412
413 if (opmenu0 && opmenu1) {
414 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
415 ispi->opcodes[i] = opmenu0 >> i * 8;
416 ispi->opcodes[i + 4] = opmenu1 >> i * 8;
417 }
418 }
419 }
420
421 intel_spi_dump_regs(ispi);
422
423 return 0;
424 }
425
intel_spi_opcode_index(struct intel_spi * ispi,u8 opcode,int optype)426 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
427 {
428 int i;
429 int preop;
430
431 if (ispi->locked) {
432 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
433 if (ispi->opcodes[i] == opcode)
434 return i;
435
436 return -EINVAL;
437 }
438
439 /* The lock is off, so just use index 0 */
440 writel(opcode, ispi->sregs + OPMENU0);
441 preop = readw(ispi->sregs + PREOP_OPTYPE);
442 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
443
444 return 0;
445 }
446
intel_spi_hw_cycle(struct intel_spi * ispi,u8 opcode,size_t len)447 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)
448 {
449 u32 val, status;
450 int ret;
451
452 val = readl(ispi->base + HSFSTS_CTL);
453 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
454
455 switch (opcode) {
456 case SPINOR_OP_RDID:
457 val |= HSFSTS_CTL_FCYCLE_RDID;
458 break;
459 case SPINOR_OP_WRSR:
460 val |= HSFSTS_CTL_FCYCLE_WRSR;
461 break;
462 case SPINOR_OP_RDSR:
463 val |= HSFSTS_CTL_FCYCLE_RDSR;
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 if (len > INTEL_SPI_FIFO_SZ)
470 return -EINVAL;
471
472 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
473 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
474 val |= HSFSTS_CTL_FGO;
475 writel(val, ispi->base + HSFSTS_CTL);
476
477 ret = intel_spi_wait_hw_busy(ispi);
478 if (ret)
479 return ret;
480
481 status = readl(ispi->base + HSFSTS_CTL);
482 if (status & HSFSTS_CTL_FCERR)
483 return -EIO;
484 else if (status & HSFSTS_CTL_AEL)
485 return -EACCES;
486
487 return 0;
488 }
489
intel_spi_sw_cycle(struct intel_spi * ispi,u8 opcode,size_t len,int optype)490 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,
491 int optype)
492 {
493 u32 val = 0, status;
494 u8 atomic_preopcode;
495 int ret;
496
497 ret = intel_spi_opcode_index(ispi, opcode, optype);
498 if (ret < 0)
499 return ret;
500
501 if (len > INTEL_SPI_FIFO_SZ)
502 return -EINVAL;
503
504 /*
505 * Always clear it after each SW sequencer operation regardless
506 * of whether it is successful or not.
507 */
508 atomic_preopcode = ispi->atomic_preopcode;
509 ispi->atomic_preopcode = 0;
510
511 /* Only mark 'Data Cycle' bit when there is data to be transferred */
512 if (len > 0)
513 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
514 val |= ret << SSFSTS_CTL_COP_SHIFT;
515 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
516 val |= SSFSTS_CTL_SCGO;
517 if (atomic_preopcode) {
518 u16 preop;
519
520 switch (optype) {
521 case OPTYPE_WRITE_NO_ADDR:
522 case OPTYPE_WRITE_WITH_ADDR:
523 /* Pick matching preopcode for the atomic sequence */
524 preop = readw(ispi->sregs + PREOP_OPTYPE);
525 if ((preop & 0xff) == atomic_preopcode)
526 ; /* Do nothing */
527 else if ((preop >> 8) == atomic_preopcode)
528 val |= SSFSTS_CTL_SPOP;
529 else
530 return -EINVAL;
531
532 /* Enable atomic sequence */
533 val |= SSFSTS_CTL_ACS;
534 break;
535
536 default:
537 return -EINVAL;
538 }
539
540 }
541 writel(val, ispi->sregs + SSFSTS_CTL);
542
543 ret = intel_spi_wait_sw_busy(ispi);
544 if (ret)
545 return ret;
546
547 status = readl(ispi->sregs + SSFSTS_CTL);
548 if (status & SSFSTS_CTL_FCERR)
549 return -EIO;
550 else if (status & SSFSTS_CTL_AEL)
551 return -EACCES;
552
553 return 0;
554 }
555
intel_spi_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,size_t len)556 static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
557 size_t len)
558 {
559 struct intel_spi *ispi = nor->priv;
560 int ret;
561
562 /* Address of the first chip */
563 writel(0, ispi->base + FADDR);
564
565 if (ispi->swseq_reg)
566 ret = intel_spi_sw_cycle(ispi, opcode, len,
567 OPTYPE_READ_NO_ADDR);
568 else
569 ret = intel_spi_hw_cycle(ispi, opcode, len);
570
571 if (ret)
572 return ret;
573
574 return intel_spi_read_block(ispi, buf, len);
575 }
576
intel_spi_write_reg(struct spi_nor * nor,u8 opcode,const u8 * buf,size_t len)577 static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
578 size_t len)
579 {
580 struct intel_spi *ispi = nor->priv;
581 int ret;
582
583 /*
584 * This is handled with atomic operation and preop code in Intel
585 * controller so we only verify that it is available. If the
586 * controller is not locked, program the opcode to the PREOP
587 * register for later use.
588 *
589 * When hardware sequencer is used there is no need to program
590 * any opcodes (it handles them automatically as part of a command).
591 */
592 if (opcode == SPINOR_OP_WREN) {
593 u16 preop;
594
595 if (!ispi->swseq_reg)
596 return 0;
597
598 preop = readw(ispi->sregs + PREOP_OPTYPE);
599 if ((preop & 0xff) != opcode && (preop >> 8) != opcode) {
600 if (ispi->locked)
601 return -EINVAL;
602 writel(opcode, ispi->sregs + PREOP_OPTYPE);
603 }
604
605 /*
606 * This enables atomic sequence on next SW sycle. Will
607 * be cleared after next operation.
608 */
609 ispi->atomic_preopcode = opcode;
610 return 0;
611 }
612
613 /*
614 * We hope that HW sequencer will do the right thing automatically and
615 * with the SW sequencer we cannot use preopcode anyway, so just ignore
616 * the Write Disable operation and pretend it was completed
617 * successfully.
618 */
619 if (opcode == SPINOR_OP_WRDI)
620 return 0;
621
622 writel(0, ispi->base + FADDR);
623
624 /* Write the value beforehand */
625 ret = intel_spi_write_block(ispi, buf, len);
626 if (ret)
627 return ret;
628
629 if (ispi->swseq_reg)
630 return intel_spi_sw_cycle(ispi, opcode, len,
631 OPTYPE_WRITE_NO_ADDR);
632 return intel_spi_hw_cycle(ispi, opcode, len);
633 }
634
intel_spi_read(struct spi_nor * nor,loff_t from,size_t len,u_char * read_buf)635 static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
636 u_char *read_buf)
637 {
638 struct intel_spi *ispi = nor->priv;
639 size_t block_size, retlen = 0;
640 u32 val, status;
641 ssize_t ret;
642
643 /*
644 * Atomic sequence is not expected with HW sequencer reads. Make
645 * sure it is cleared regardless.
646 */
647 if (WARN_ON_ONCE(ispi->atomic_preopcode))
648 ispi->atomic_preopcode = 0;
649
650 switch (nor->read_opcode) {
651 case SPINOR_OP_READ:
652 case SPINOR_OP_READ_FAST:
653 case SPINOR_OP_READ_4B:
654 case SPINOR_OP_READ_FAST_4B:
655 break;
656 default:
657 return -EINVAL;
658 }
659
660 while (len > 0) {
661 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
662
663 /* Read cannot cross 4K boundary */
664 block_size = min_t(loff_t, from + block_size,
665 round_up(from + 1, SZ_4K)) - from;
666
667 writel(from, ispi->base + FADDR);
668
669 val = readl(ispi->base + HSFSTS_CTL);
670 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
671 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
672 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
673 val |= HSFSTS_CTL_FCYCLE_READ;
674 val |= HSFSTS_CTL_FGO;
675 writel(val, ispi->base + HSFSTS_CTL);
676
677 ret = intel_spi_wait_hw_busy(ispi);
678 if (ret)
679 return ret;
680
681 status = readl(ispi->base + HSFSTS_CTL);
682 if (status & HSFSTS_CTL_FCERR)
683 ret = -EIO;
684 else if (status & HSFSTS_CTL_AEL)
685 ret = -EACCES;
686
687 if (ret < 0) {
688 dev_err(ispi->dev, "read error: %llx: %#x\n", from,
689 status);
690 return ret;
691 }
692
693 ret = intel_spi_read_block(ispi, read_buf, block_size);
694 if (ret)
695 return ret;
696
697 len -= block_size;
698 from += block_size;
699 retlen += block_size;
700 read_buf += block_size;
701 }
702
703 return retlen;
704 }
705
intel_spi_write(struct spi_nor * nor,loff_t to,size_t len,const u_char * write_buf)706 static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len,
707 const u_char *write_buf)
708 {
709 struct intel_spi *ispi = nor->priv;
710 size_t block_size, retlen = 0;
711 u32 val, status;
712 ssize_t ret;
713
714 /* Not needed with HW sequencer write, make sure it is cleared */
715 ispi->atomic_preopcode = 0;
716
717 while (len > 0) {
718 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
719
720 /* Write cannot cross 4K boundary */
721 block_size = min_t(loff_t, to + block_size,
722 round_up(to + 1, SZ_4K)) - to;
723
724 writel(to, ispi->base + FADDR);
725
726 val = readl(ispi->base + HSFSTS_CTL);
727 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
728 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
729 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
730 val |= HSFSTS_CTL_FCYCLE_WRITE;
731
732 ret = intel_spi_write_block(ispi, write_buf, block_size);
733 if (ret) {
734 dev_err(ispi->dev, "failed to write block\n");
735 return ret;
736 }
737
738 /* Start the write now */
739 val |= HSFSTS_CTL_FGO;
740 writel(val, ispi->base + HSFSTS_CTL);
741
742 ret = intel_spi_wait_hw_busy(ispi);
743 if (ret) {
744 dev_err(ispi->dev, "timeout\n");
745 return ret;
746 }
747
748 status = readl(ispi->base + HSFSTS_CTL);
749 if (status & HSFSTS_CTL_FCERR)
750 ret = -EIO;
751 else if (status & HSFSTS_CTL_AEL)
752 ret = -EACCES;
753
754 if (ret < 0) {
755 dev_err(ispi->dev, "write error: %llx: %#x\n", to,
756 status);
757 return ret;
758 }
759
760 len -= block_size;
761 to += block_size;
762 retlen += block_size;
763 write_buf += block_size;
764 }
765
766 return retlen;
767 }
768
intel_spi_erase(struct spi_nor * nor,loff_t offs)769 static int intel_spi_erase(struct spi_nor *nor, loff_t offs)
770 {
771 size_t erase_size, len = nor->mtd.erasesize;
772 struct intel_spi *ispi = nor->priv;
773 u32 val, status, cmd;
774 int ret;
775
776 /* If the hardware can do 64k erase use that when possible */
777 if (len >= SZ_64K && ispi->erase_64k) {
778 cmd = HSFSTS_CTL_FCYCLE_ERASE_64K;
779 erase_size = SZ_64K;
780 } else {
781 cmd = HSFSTS_CTL_FCYCLE_ERASE;
782 erase_size = SZ_4K;
783 }
784
785 if (ispi->swseq_erase) {
786 while (len > 0) {
787 writel(offs, ispi->base + FADDR);
788
789 ret = intel_spi_sw_cycle(ispi, nor->erase_opcode,
790 0, OPTYPE_WRITE_WITH_ADDR);
791 if (ret)
792 return ret;
793
794 offs += erase_size;
795 len -= erase_size;
796 }
797
798 return 0;
799 }
800
801 /* Not needed with HW sequencer erase, make sure it is cleared */
802 ispi->atomic_preopcode = 0;
803
804 while (len > 0) {
805 writel(offs, ispi->base + FADDR);
806
807 val = readl(ispi->base + HSFSTS_CTL);
808 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
809 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
810 val |= cmd;
811 val |= HSFSTS_CTL_FGO;
812 writel(val, ispi->base + HSFSTS_CTL);
813
814 ret = intel_spi_wait_hw_busy(ispi);
815 if (ret)
816 return ret;
817
818 status = readl(ispi->base + HSFSTS_CTL);
819 if (status & HSFSTS_CTL_FCERR)
820 return -EIO;
821 else if (status & HSFSTS_CTL_AEL)
822 return -EACCES;
823
824 offs += erase_size;
825 len -= erase_size;
826 }
827
828 return 0;
829 }
830
intel_spi_is_protected(const struct intel_spi * ispi,unsigned int base,unsigned int limit)831 static bool intel_spi_is_protected(const struct intel_spi *ispi,
832 unsigned int base, unsigned int limit)
833 {
834 int i;
835
836 for (i = 0; i < ispi->pr_num; i++) {
837 u32 pr_base, pr_limit, pr_value;
838
839 pr_value = readl(ispi->pregs + PR(i));
840 if (!(pr_value & (PR_WPE | PR_RPE)))
841 continue;
842
843 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
844 pr_base = pr_value & PR_BASE_MASK;
845
846 if (pr_base >= base && pr_limit <= limit)
847 return true;
848 }
849
850 return false;
851 }
852
853 /*
854 * There will be a single partition holding all enabled flash regions. We
855 * call this "BIOS".
856 */
intel_spi_fill_partition(struct intel_spi * ispi,struct mtd_partition * part)857 static void intel_spi_fill_partition(struct intel_spi *ispi,
858 struct mtd_partition *part)
859 {
860 u64 end;
861 int i;
862
863 memset(part, 0, sizeof(*part));
864
865 /* Start from the mandatory descriptor region */
866 part->size = 4096;
867 part->name = "BIOS";
868
869 /*
870 * Now try to find where this partition ends based on the flash
871 * region registers.
872 */
873 for (i = 1; i < ispi->nregions; i++) {
874 u32 region, base, limit;
875
876 region = readl(ispi->base + FREG(i));
877 base = region & FREG_BASE_MASK;
878 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
879
880 if (base >= limit || limit == 0)
881 continue;
882
883 /*
884 * If any of the regions have protection bits set, make the
885 * whole partition read-only to be on the safe side.
886 *
887 * Also if the user did not ask the chip to be writeable
888 * mask the bit too.
889 */
890 if (!writeable || intel_spi_is_protected(ispi, base, limit))
891 part->mask_flags |= MTD_WRITEABLE;
892
893 end = (limit << 12) + 4096;
894 if (end > part->size)
895 part->size = end;
896 }
897 }
898
899 static const struct spi_nor_controller_ops intel_spi_controller_ops = {
900 .read_reg = intel_spi_read_reg,
901 .write_reg = intel_spi_write_reg,
902 .read = intel_spi_read,
903 .write = intel_spi_write,
904 .erase = intel_spi_erase,
905 };
906
intel_spi_probe(struct device * dev,struct resource * mem,const struct intel_spi_boardinfo * info)907 struct intel_spi *intel_spi_probe(struct device *dev,
908 struct resource *mem, const struct intel_spi_boardinfo *info)
909 {
910 const struct spi_nor_hwcaps hwcaps = {
911 .mask = SNOR_HWCAPS_READ |
912 SNOR_HWCAPS_READ_FAST |
913 SNOR_HWCAPS_PP,
914 };
915 struct mtd_partition part;
916 struct intel_spi *ispi;
917 int ret;
918
919 if (!info || !mem)
920 return ERR_PTR(-EINVAL);
921
922 ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL);
923 if (!ispi)
924 return ERR_PTR(-ENOMEM);
925
926 ispi->base = devm_ioremap_resource(dev, mem);
927 if (IS_ERR(ispi->base))
928 return ERR_CAST(ispi->base);
929
930 ispi->dev = dev;
931 ispi->info = info;
932
933 ret = intel_spi_init(ispi);
934 if (ret)
935 return ERR_PTR(ret);
936
937 ispi->nor.dev = ispi->dev;
938 ispi->nor.priv = ispi;
939 ispi->nor.controller_ops = &intel_spi_controller_ops;
940
941 ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps);
942 if (ret) {
943 dev_info(dev, "failed to locate the chip\n");
944 return ERR_PTR(ret);
945 }
946
947 intel_spi_fill_partition(ispi, &part);
948
949 ret = mtd_device_register(&ispi->nor.mtd, &part, 1);
950 if (ret)
951 return ERR_PTR(ret);
952
953 return ispi;
954 }
955 EXPORT_SYMBOL_GPL(intel_spi_probe);
956
intel_spi_remove(struct intel_spi * ispi)957 int intel_spi_remove(struct intel_spi *ispi)
958 {
959 return mtd_device_unregister(&ispi->nor.mtd);
960 }
961 EXPORT_SYMBOL_GPL(intel_spi_remove);
962
963 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
964 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
965 MODULE_LICENSE("GPL v2");
966