1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
5 */
6
7 #include <linux/mtd/spi-nor.h>
8
9 #include "core.h"
10
11 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
12 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
13 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003
14 #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb
15 #define SPINOR_REG_CYPRESS_CFR3V 0x00800004
16 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */
17 #define SPINOR_REG_CYPRESS_CFR5V 0x00800006
18 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6)
19 #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1)
20 #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0)
21 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \
22 (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \
23 SPINOR_REG_CYPRESS_CFR5_OPI)
24 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6
25 #define SPINOR_OP_CYPRESS_RD_FAST 0xee
26
27 /**
28 * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
29 * @nor: pointer to a 'struct spi_nor'
30 * @enable: whether to enable or disable Octal DTR
31 *
32 * This also sets the memory access latency cycles to 24 to allow the flash to
33 * run at up to 200MHz.
34 *
35 * Return: 0 on success, -errno otherwise.
36 */
spi_nor_cypress_octal_dtr_enable(struct spi_nor * nor,bool enable)37 static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
38 {
39 struct spi_mem_op op;
40 u8 *buf = nor->bouncebuf;
41 int ret;
42
43 if (enable) {
44 /* Use 24 dummy cycles for memory array reads. */
45 ret = spi_nor_write_enable(nor);
46 if (ret)
47 return ret;
48
49 *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
50 op = (struct spi_mem_op)
51 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
52 SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V,
53 1),
54 SPI_MEM_OP_NO_DUMMY,
55 SPI_MEM_OP_DATA_OUT(1, buf, 1));
56
57 ret = spi_mem_exec_op(nor->spimem, &op);
58 if (ret)
59 return ret;
60
61 ret = spi_nor_wait_till_ready(nor);
62 if (ret)
63 return ret;
64
65 nor->read_dummy = 24;
66 }
67
68 /* Set/unset the octal and DTR enable bits. */
69 ret = spi_nor_write_enable(nor);
70 if (ret)
71 return ret;
72
73 if (enable)
74 *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
75 else
76 *buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
77
78 op = (struct spi_mem_op)
79 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
80 SPI_MEM_OP_ADDR(enable ? 3 : 4,
81 SPINOR_REG_CYPRESS_CFR5V,
82 1),
83 SPI_MEM_OP_NO_DUMMY,
84 SPI_MEM_OP_DATA_OUT(1, buf, 1));
85
86 if (!enable)
87 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
88
89 ret = spi_mem_exec_op(nor->spimem, &op);
90 if (ret)
91 return ret;
92
93 /* Read flash ID to make sure the switch was successful. */
94 op = (struct spi_mem_op)
95 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
96 SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1),
97 SPI_MEM_OP_DUMMY(enable ? 3 : 0, 1),
98 SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2),
99 buf, 1));
100
101 if (enable)
102 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
103
104 ret = spi_mem_exec_op(nor->spimem, &op);
105 if (ret)
106 return ret;
107
108 if (memcmp(buf, nor->info->id, nor->info->id_len))
109 return -EINVAL;
110
111 return 0;
112 }
113
s28hs512t_default_init(struct spi_nor * nor)114 static void s28hs512t_default_init(struct spi_nor *nor)
115 {
116 nor->params->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
117 nor->params->writesize = 16;
118 }
119
s28hs512t_post_sfdp_fixup(struct spi_nor * nor)120 static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor)
121 {
122 /*
123 * On older versions of the flash the xSPI Profile 1.0 table has the
124 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
125 */
126 if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
127 nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
128 SPINOR_OP_CYPRESS_RD_FAST;
129
130 /* This flash is also missing the 4-byte Page Program opcode bit. */
131 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP],
132 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
133 /*
134 * Since xSPI Page Program opcode is backward compatible with
135 * Legacy SPI, use Legacy SPI opcode there as well.
136 */
137 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
138 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
139
140 /*
141 * The xSPI Profile 1.0 table advertises the number of additional
142 * address bytes needed for Read Status Register command as 0 but the
143 * actual value for that is 4.
144 */
145 nor->params->rdsr_addr_nbytes = 4;
146 }
147
s28hs512t_post_bfpt_fixup(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)148 static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor,
149 const struct sfdp_parameter_header *bfpt_header,
150 const struct sfdp_bfpt *bfpt)
151 {
152 /*
153 * The BFPT table advertises a 512B page size but the page size is
154 * actually configurable (with the default being 256B). Read from
155 * CFR3V[4] and set the correct size.
156 */
157 struct spi_mem_op op =
158 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
159 SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR3V, 1),
160 SPI_MEM_OP_NO_DUMMY,
161 SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
162 int ret;
163
164 ret = spi_mem_exec_op(nor->spimem, &op);
165 if (ret)
166 return ret;
167
168 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
169 nor->params->page_size = 512;
170 else
171 nor->params->page_size = 256;
172
173 return 0;
174 }
175
176 static struct spi_nor_fixups s28hs512t_fixups = {
177 .default_init = s28hs512t_default_init,
178 .post_sfdp = s28hs512t_post_sfdp_fixup,
179 .post_bfpt = s28hs512t_post_bfpt_fixup,
180 };
181
182 static int
s25fs_s_post_bfpt_fixups(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)183 s25fs_s_post_bfpt_fixups(struct spi_nor *nor,
184 const struct sfdp_parameter_header *bfpt_header,
185 const struct sfdp_bfpt *bfpt)
186 {
187 /*
188 * The S25FS-S chip family reports 512-byte pages in BFPT but
189 * in reality the write buffer still wraps at the safe default
190 * of 256 bytes. Overwrite the page size advertised by BFPT
191 * to get the writes working.
192 */
193 nor->params->page_size = 256;
194
195 return 0;
196 }
197
198 static struct spi_nor_fixups s25fs_s_fixups = {
199 .post_bfpt = s25fs_s_post_bfpt_fixups,
200 };
201
202 static const struct flash_info spansion_parts[] = {
203 /* Spansion/Cypress -- single (large) sector size only, at least
204 * for the chips listed here (without boot sectors).
205 */
206 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64,
207 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
208 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128,
209 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
210 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
211 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
212 USE_CLSR) },
213 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
214 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
215 USE_CLSR) },
216 { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128,
217 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
218 USE_CLSR) },
219 { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512,
220 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
221 USE_CLSR) },
222 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
223 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
224 SPI_NOR_HAS_LOCK | USE_CLSR) },
225 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256,
226 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
227 .fixups = &s25fs_s_fixups, },
228 { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128,
229 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
230 USE_CLSR) },
231 { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512,
232 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
233 USE_CLSR) },
234 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
235 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
236 .fixups = &s25fs_s_fixups, },
237 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
238 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
239 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64,
240 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
241 USE_CLSR) },
242 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256,
243 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
244 USE_CLSR) },
245 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
246 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
247 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
248 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
249 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
250 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8,
251 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
252 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16,
253 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
254 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32,
255 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
256 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128,
257 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
258 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32,
259 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
260 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
261 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
262 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8,
263 SECT_4K | SPI_NOR_DUAL_READ) },
264 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16,
265 SECT_4K | SPI_NOR_DUAL_READ) },
266 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128,
267 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
268 SPI_NOR_4B_OPCODES) },
269 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256,
270 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
271 SPI_NOR_4B_OPCODES) },
272 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512,
273 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
274 SPI_NOR_4B_OPCODES) },
275 { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1,
276 SPI_NOR_NO_ERASE) },
277 { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256,
278 SECT_4K | SPI_NOR_OCTAL_DTR_READ |
279 SPI_NOR_OCTAL_DTR_PP)
280 .fixups = &s28hs512t_fixups,
281 },
282 };
283
spansion_post_sfdp_fixups(struct spi_nor * nor)284 static void spansion_post_sfdp_fixups(struct spi_nor *nor)
285 {
286 if (nor->params->size <= SZ_16M)
287 return;
288
289 nor->flags |= SNOR_F_4B_OPCODES;
290 /* No small sector erase for 4-byte command set */
291 nor->erase_opcode = SPINOR_OP_SE;
292 nor->mtd.erasesize = nor->info->sector_size;
293 }
294
295 static const struct spi_nor_fixups spansion_fixups = {
296 .post_sfdp = spansion_post_sfdp_fixups,
297 };
298
299 const struct spi_nor_manufacturer spi_nor_spansion = {
300 .name = "spansion",
301 .parts = spansion_parts,
302 .nparts = ARRAY_SIZE(spansion_parts),
303 .fixups = &spansion_fixups,
304 };
305