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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Broadcom GENET MDIO routines
4  *
5  * Copyright (c) 2014-2017 Broadcom
6  */
7 
8 #include <linux/acpi.h>
9 #include <linux/types.h>
10 #include <linux/delay.h>
11 #include <linux/wait.h>
12 #include <linux/mii.h>
13 #include <linux/ethtool.h>
14 #include <linux/bitops.h>
15 #include <linux/netdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <linux/brcmphy.h>
20 #include <linux/of.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/platform_data/bcmgenet.h>
24 #include <linux/platform_data/mdio-bcm-unimac.h>
25 
26 #include "bcmgenet.h"
27 
28 
29 /* setup netdev link state when PHY link status change and
30  * update UMAC and RGMII block when link up
31  */
bcmgenet_mii_setup(struct net_device * dev)32 void bcmgenet_mii_setup(struct net_device *dev)
33 {
34 	struct bcmgenet_priv *priv = netdev_priv(dev);
35 	struct phy_device *phydev = dev->phydev;
36 	u32 reg, cmd_bits = 0;
37 	bool status_changed = false;
38 
39 	if (priv->old_link != phydev->link) {
40 		status_changed = true;
41 		priv->old_link = phydev->link;
42 	}
43 
44 	if (phydev->link) {
45 		/* check speed/duplex/pause changes */
46 		if (priv->old_speed != phydev->speed) {
47 			status_changed = true;
48 			priv->old_speed = phydev->speed;
49 		}
50 
51 		if (priv->old_duplex != phydev->duplex) {
52 			status_changed = true;
53 			priv->old_duplex = phydev->duplex;
54 		}
55 
56 		if (priv->old_pause != phydev->pause) {
57 			status_changed = true;
58 			priv->old_pause = phydev->pause;
59 		}
60 
61 		/* done if nothing has changed */
62 		if (!status_changed)
63 			return;
64 
65 		/* speed */
66 		if (phydev->speed == SPEED_1000)
67 			cmd_bits = CMD_SPEED_1000;
68 		else if (phydev->speed == SPEED_100)
69 			cmd_bits = CMD_SPEED_100;
70 		else
71 			cmd_bits = CMD_SPEED_10;
72 		cmd_bits <<= CMD_SPEED_SHIFT;
73 
74 		/* duplex */
75 		if (phydev->duplex != DUPLEX_FULL)
76 			cmd_bits |= CMD_HD_EN;
77 
78 		/* pause capability */
79 		if (!phydev->pause)
80 			cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
81 
82 		/*
83 		 * Program UMAC and RGMII block based on established
84 		 * link speed, duplex, and pause. The speed set in
85 		 * umac->cmd tell RGMII block which clock to use for
86 		 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
87 		 * Receive clock is provided by the PHY.
88 		 */
89 		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
90 		reg &= ~OOB_DISABLE;
91 		reg |= RGMII_LINK;
92 		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
93 
94 		reg = bcmgenet_umac_readl(priv, UMAC_CMD);
95 		reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
96 			       CMD_HD_EN |
97 			       CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
98 		reg |= cmd_bits;
99 		if (reg & CMD_SW_RESET) {
100 			reg &= ~CMD_SW_RESET;
101 			bcmgenet_umac_writel(priv, reg, UMAC_CMD);
102 			udelay(2);
103 			reg |= CMD_TX_EN | CMD_RX_EN;
104 		}
105 		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
106 
107 		priv->eee.eee_active = phy_init_eee(phydev, 0) >= 0;
108 		bcmgenet_eee_enable_set(dev,
109 					priv->eee.eee_enabled && priv->eee.eee_active,
110 					priv->eee.tx_lpi_enabled);
111 	} else {
112 		/* done if nothing has changed */
113 		if (!status_changed)
114 			return;
115 
116 		/* needed for MoCA fixed PHY to reflect correct link status */
117 		netif_carrier_off(dev);
118 	}
119 
120 	phy_print_status(phydev);
121 }
122 
123 
bcmgenet_fixed_phy_link_update(struct net_device * dev,struct fixed_phy_status * status)124 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
125 					  struct fixed_phy_status *status)
126 {
127 	struct bcmgenet_priv *priv;
128 	u32 reg;
129 
130 	if (dev && dev->phydev && status) {
131 		priv = netdev_priv(dev);
132 		reg = bcmgenet_umac_readl(priv, UMAC_MODE);
133 		status->link = !!(reg & MODE_LINK_STATUS);
134 	}
135 
136 	return 0;
137 }
138 
bcmgenet_phy_power_set(struct net_device * dev,bool enable)139 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
140 {
141 	struct bcmgenet_priv *priv = netdev_priv(dev);
142 	u32 reg = 0;
143 
144 	/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
145 	if (GENET_IS_V4(priv)) {
146 		reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
147 		if (enable) {
148 			reg &= ~EXT_CK25_DIS;
149 			bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
150 			mdelay(1);
151 
152 			reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
153 			reg |= EXT_GPHY_RESET;
154 			bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
155 			mdelay(1);
156 
157 			reg &= ~EXT_GPHY_RESET;
158 		} else {
159 			reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
160 			       EXT_GPHY_RESET;
161 			bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
162 			mdelay(1);
163 			reg |= EXT_CK25_DIS;
164 		}
165 		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
166 		udelay(60);
167 	} else {
168 		mdelay(1);
169 	}
170 }
171 
bcmgenet_moca_phy_setup(struct bcmgenet_priv * priv)172 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
173 {
174 	if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
175 		fixed_phy_set_link_update(priv->dev->phydev,
176 					  bcmgenet_fixed_phy_link_update);
177 }
178 
bcmgenet_mii_config(struct net_device * dev,bool init)179 int bcmgenet_mii_config(struct net_device *dev, bool init)
180 {
181 	struct bcmgenet_priv *priv = netdev_priv(dev);
182 	struct phy_device *phydev = dev->phydev;
183 	struct device *kdev = &priv->pdev->dev;
184 	const char *phy_name = NULL;
185 	u32 id_mode_dis = 0;
186 	u32 port_ctrl;
187 	u32 reg;
188 
189 	switch (priv->phy_interface) {
190 	case PHY_INTERFACE_MODE_INTERNAL:
191 		phy_name = "internal PHY";
192 		fallthrough;
193 	case PHY_INTERFACE_MODE_MOCA:
194 		/* Irrespective of the actually configured PHY speed (100 or
195 		 * 1000) GENETv4 only has an internal GPHY so we will just end
196 		 * up masking the Gigabit features from what we support, not
197 		 * switching to the EPHY
198 		 */
199 		if (GENET_IS_V4(priv))
200 			port_ctrl = PORT_MODE_INT_GPHY;
201 		else
202 			port_ctrl = PORT_MODE_INT_EPHY;
203 
204 		if (!phy_name) {
205 			phy_name = "MoCA";
206 			if (!GENET_IS_V5(priv))
207 				port_ctrl |= LED_ACT_SOURCE_MAC;
208 			bcmgenet_moca_phy_setup(priv);
209 		}
210 		break;
211 
212 	case PHY_INTERFACE_MODE_MII:
213 		phy_name = "external MII";
214 		phy_set_max_speed(phydev, SPEED_100);
215 		port_ctrl = PORT_MODE_EXT_EPHY;
216 		break;
217 
218 	case PHY_INTERFACE_MODE_REVMII:
219 		phy_name = "external RvMII";
220 		/* of_mdiobus_register took care of reading the 'max-speed'
221 		 * PHY property for us, effectively limiting the PHY supported
222 		 * capabilities, use that knowledge to also configure the
223 		 * Reverse MII interface correctly.
224 		 */
225 		if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
226 				      dev->phydev->supported))
227 			port_ctrl = PORT_MODE_EXT_RVMII_50;
228 		else
229 			port_ctrl = PORT_MODE_EXT_RVMII_25;
230 		break;
231 
232 	case PHY_INTERFACE_MODE_RGMII:
233 		/* RGMII_NO_ID: TXC transitions at the same time as TXD
234 		 *		(requires PCB or receiver-side delay)
235 		 *
236 		 * ID is implicitly disabled for 100Mbps (RG)MII operation.
237 		 */
238 		phy_name = "external RGMII (no delay)";
239 		id_mode_dis = BIT(16);
240 		port_ctrl = PORT_MODE_EXT_GPHY;
241 		break;
242 
243 	case PHY_INTERFACE_MODE_RGMII_TXID:
244 		/* RGMII_TXID:	Add 2ns delay on TXC (90 degree shift) */
245 		phy_name = "external RGMII (TX delay)";
246 		port_ctrl = PORT_MODE_EXT_GPHY;
247 		break;
248 
249 	case PHY_INTERFACE_MODE_RGMII_RXID:
250 		phy_name = "external RGMII (RX delay)";
251 		port_ctrl = PORT_MODE_EXT_GPHY;
252 		break;
253 	default:
254 		dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
255 		return -EINVAL;
256 	}
257 
258 	bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
259 
260 	priv->ext_phy = !priv->internal_phy &&
261 			(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
262 
263 	/* This is an external PHY (xMII), so we need to enable the RGMII
264 	 * block for the interface to work
265 	 */
266 	if (priv->ext_phy) {
267 		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
268 		reg &= ~ID_MODE_DIS;
269 		reg |= id_mode_dis;
270 		if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
271 			reg |= RGMII_MODE_EN_V123;
272 		else
273 			reg |= RGMII_MODE_EN;
274 		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
275 	}
276 
277 	if (init)
278 		dev_info(kdev, "configuring instance for %s\n", phy_name);
279 
280 	return 0;
281 }
282 
bcmgenet_mii_probe(struct net_device * dev)283 int bcmgenet_mii_probe(struct net_device *dev)
284 {
285 	struct bcmgenet_priv *priv = netdev_priv(dev);
286 	struct device *kdev = &priv->pdev->dev;
287 	struct device_node *dn = kdev->of_node;
288 	struct phy_device *phydev;
289 	u32 phy_flags = 0;
290 	int ret;
291 
292 	/* Communicate the integrated PHY revision */
293 	if (priv->internal_phy)
294 		phy_flags = priv->gphy_rev;
295 
296 	/* Initialize link state variables that bcmgenet_mii_setup() uses */
297 	priv->old_link = -1;
298 	priv->old_speed = -1;
299 	priv->old_duplex = -1;
300 	priv->old_pause = -1;
301 
302 	if (dn) {
303 		phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
304 					phy_flags, priv->phy_interface);
305 		if (!phydev) {
306 			pr_err("could not attach to PHY\n");
307 			return -ENODEV;
308 		}
309 	} else {
310 		if (has_acpi_companion(kdev)) {
311 			char mdio_bus_id[MII_BUS_ID_SIZE];
312 			struct mii_bus *unimacbus;
313 
314 			snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
315 				 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
316 
317 			unimacbus = mdio_find_bus(mdio_bus_id);
318 			if (!unimacbus) {
319 				pr_err("Unable to find mii\n");
320 				return -ENODEV;
321 			}
322 			phydev = phy_find_first(unimacbus);
323 			put_device(&unimacbus->dev);
324 			if (!phydev) {
325 				pr_err("Unable to find PHY\n");
326 				return -ENODEV;
327 			}
328 		} else {
329 			phydev = dev->phydev;
330 		}
331 		phydev->dev_flags = phy_flags;
332 
333 		ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
334 					 priv->phy_interface);
335 		if (ret) {
336 			pr_err("could not attach to PHY\n");
337 			return -ENODEV;
338 		}
339 	}
340 
341 	/* Configure port multiplexer based on what the probed PHY device since
342 	 * reading the 'max-speed' property determines the maximum supported
343 	 * PHY speed which is needed for bcmgenet_mii_config() to configure
344 	 * things appropriately.
345 	 */
346 	ret = bcmgenet_mii_config(dev, true);
347 	if (ret) {
348 		phy_disconnect(dev->phydev);
349 		return ret;
350 	}
351 
352 	linkmode_copy(phydev->advertising, phydev->supported);
353 
354 	/* The internal PHY has its link interrupts routed to the
355 	 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
356 	 * that prevents the signaling of link UP interrupts when
357 	 * the link operates at 10Mbps, so fallback to polling for
358 	 * those versions of GENET.
359 	 */
360 	if (priv->internal_phy && !GENET_IS_V5(priv))
361 		dev->phydev->irq = PHY_MAC_INTERRUPT;
362 
363 	/* Indicate that the MAC is responsible for PHY PM */
364 	dev->phydev->mac_managed_pm = true;
365 
366 	return 0;
367 }
368 
bcmgenet_mii_of_find_mdio(struct bcmgenet_priv * priv)369 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
370 {
371 	struct device_node *dn = priv->pdev->dev.of_node;
372 	struct device *kdev = &priv->pdev->dev;
373 	char *compat;
374 
375 	compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
376 	if (!compat)
377 		return NULL;
378 
379 	priv->mdio_dn = of_get_compatible_child(dn, compat);
380 	kfree(compat);
381 	if (!priv->mdio_dn) {
382 		dev_err(kdev, "unable to find MDIO bus node\n");
383 		return NULL;
384 	}
385 
386 	return priv->mdio_dn;
387 }
388 
bcmgenet_mii_pdata_init(struct bcmgenet_priv * priv,struct unimac_mdio_pdata * ppd)389 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
390 				    struct unimac_mdio_pdata *ppd)
391 {
392 	struct device *kdev = &priv->pdev->dev;
393 	struct bcmgenet_platform_data *pd = kdev->platform_data;
394 
395 	if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
396 		/*
397 		 * Internal or external PHY with MDIO access
398 		 */
399 		if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
400 			ppd->phy_mask = 1 << pd->phy_address;
401 		else
402 			ppd->phy_mask = 0;
403 	}
404 }
405 
bcmgenet_mii_wait(void * wait_func_data)406 static int bcmgenet_mii_wait(void *wait_func_data)
407 {
408 	struct bcmgenet_priv *priv = wait_func_data;
409 
410 	wait_event_timeout(priv->wq,
411 			   !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
412 			   & MDIO_START_BUSY),
413 			   HZ / 100);
414 	return 0;
415 }
416 
bcmgenet_mii_register(struct bcmgenet_priv * priv)417 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
418 {
419 	struct platform_device *pdev = priv->pdev;
420 	struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
421 	struct device_node *dn = pdev->dev.of_node;
422 	struct unimac_mdio_pdata ppd;
423 	struct platform_device *ppdev;
424 	struct resource *pres, res;
425 	int id, ret;
426 
427 	pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
428 	if (!pres) {
429 		dev_err(&pdev->dev, "Invalid resource\n");
430 		return -EINVAL;
431 	}
432 	memset(&res, 0, sizeof(res));
433 	memset(&ppd, 0, sizeof(ppd));
434 
435 	ppd.wait_func = bcmgenet_mii_wait;
436 	ppd.wait_func_data = priv;
437 	ppd.bus_name = "bcmgenet MII bus";
438 
439 	/* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
440 	 * and is 2 * 32-bits word long, 8 bytes total.
441 	 */
442 	res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
443 	res.end = res.start + 8;
444 	res.flags = IORESOURCE_MEM;
445 
446 	if (dn)
447 		id = of_alias_get_id(dn, "eth");
448 	else
449 		id = pdev->id;
450 
451 	ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
452 	if (!ppdev)
453 		return -ENOMEM;
454 
455 	/* Retain this platform_device pointer for later cleanup */
456 	priv->mii_pdev = ppdev;
457 	ppdev->dev.parent = &pdev->dev;
458 	if (dn)
459 		ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
460 	else if (pdata)
461 		bcmgenet_mii_pdata_init(priv, &ppd);
462 	else
463 		ppd.phy_mask = ~0;
464 
465 	ret = platform_device_add_resources(ppdev, &res, 1);
466 	if (ret)
467 		goto out;
468 
469 	ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
470 	if (ret)
471 		goto out;
472 
473 	ret = platform_device_add(ppdev);
474 	if (ret)
475 		goto out;
476 
477 	return 0;
478 out:
479 	platform_device_put(ppdev);
480 	return ret;
481 }
482 
bcmgenet_phy_interface_init(struct bcmgenet_priv * priv)483 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv)
484 {
485 	struct device *kdev = &priv->pdev->dev;
486 	int phy_mode = device_get_phy_mode(kdev);
487 
488 	if (phy_mode < 0) {
489 		dev_err(kdev, "invalid PHY mode property\n");
490 		return phy_mode;
491 	}
492 
493 	priv->phy_interface = phy_mode;
494 
495 	/* We need to specifically look up whether this PHY interface is
496 	 * internal or not *before* we even try to probe the PHY driver
497 	 * over MDIO as we may have shut down the internal PHY for power
498 	 * saving purposes.
499 	 */
500 	if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
501 		priv->internal_phy = true;
502 
503 	return 0;
504 }
505 
bcmgenet_mii_of_init(struct bcmgenet_priv * priv)506 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
507 {
508 	struct device_node *dn = priv->pdev->dev.of_node;
509 	struct phy_device *phydev;
510 	int ret;
511 
512 	/* Fetch the PHY phandle */
513 	priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
514 
515 	/* In the case of a fixed PHY, the DT node associated
516 	 * to the PHY is the Ethernet MAC DT node.
517 	 */
518 	if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
519 		ret = of_phy_register_fixed_link(dn);
520 		if (ret)
521 			return ret;
522 
523 		priv->phy_dn = of_node_get(dn);
524 	}
525 
526 	/* Get the link mode */
527 	ret = bcmgenet_phy_interface_init(priv);
528 	if (ret)
529 		return ret;
530 
531 	/* Make sure we initialize MoCA PHYs with a link down */
532 	if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
533 		phydev = of_phy_find_device(dn);
534 		if (phydev) {
535 			phydev->link = 0;
536 			put_device(&phydev->mdio.dev);
537 		}
538 	}
539 
540 	return 0;
541 }
542 
bcmgenet_mii_pd_init(struct bcmgenet_priv * priv)543 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
544 {
545 	struct device *kdev = &priv->pdev->dev;
546 	struct bcmgenet_platform_data *pd = kdev->platform_data;
547 	char phy_name[MII_BUS_ID_SIZE + 3];
548 	char mdio_bus_id[MII_BUS_ID_SIZE];
549 	struct phy_device *phydev;
550 
551 	snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
552 		 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
553 
554 	if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
555 		snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
556 			 mdio_bus_id, pd->phy_address);
557 
558 		/*
559 		 * Internal or external PHY with MDIO access
560 		 */
561 		phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
562 		if (!phydev) {
563 			dev_err(kdev, "failed to register PHY device\n");
564 			return -ENODEV;
565 		}
566 	} else {
567 		/*
568 		 * MoCA port or no MDIO access.
569 		 * Use fixed PHY to represent the link layer.
570 		 */
571 		struct fixed_phy_status fphy_status = {
572 			.link = 1,
573 			.speed = pd->phy_speed,
574 			.duplex = pd->phy_duplex,
575 			.pause = 0,
576 			.asym_pause = 0,
577 		};
578 
579 		phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
580 		if (IS_ERR(phydev)) {
581 			dev_err(kdev, "failed to register fixed PHY device\n");
582 			return -ENODEV;
583 		}
584 
585 		/* Make sure we initialize MoCA PHYs with a link down */
586 		phydev->link = 0;
587 
588 	}
589 
590 	priv->phy_interface = pd->phy_interface;
591 
592 	return 0;
593 }
594 
bcmgenet_mii_bus_init(struct bcmgenet_priv * priv)595 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
596 {
597 	struct device *kdev = &priv->pdev->dev;
598 	struct device_node *dn = kdev->of_node;
599 
600 	if (dn)
601 		return bcmgenet_mii_of_init(priv);
602 	else if (has_acpi_companion(kdev))
603 		return bcmgenet_phy_interface_init(priv);
604 	else
605 		return bcmgenet_mii_pd_init(priv);
606 }
607 
bcmgenet_mii_init(struct net_device * dev)608 int bcmgenet_mii_init(struct net_device *dev)
609 {
610 	struct bcmgenet_priv *priv = netdev_priv(dev);
611 	int ret;
612 
613 	ret = bcmgenet_mii_register(priv);
614 	if (ret)
615 		return ret;
616 
617 	ret = bcmgenet_mii_bus_init(priv);
618 	if (ret)
619 		goto out;
620 
621 	return 0;
622 
623 out:
624 	bcmgenet_mii_exit(dev);
625 	return ret;
626 }
627 
bcmgenet_mii_exit(struct net_device * dev)628 void bcmgenet_mii_exit(struct net_device *dev)
629 {
630 	struct bcmgenet_priv *priv = netdev_priv(dev);
631 	struct device_node *dn = priv->pdev->dev.of_node;
632 
633 	if (of_phy_is_fixed_link(dn))
634 		of_phy_deregister_fixed_link(dn);
635 	of_node_put(priv->phy_dn);
636 	clk_prepare_enable(priv->clk);
637 	platform_device_unregister(priv->mii_pdev);
638 	clk_disable_unprepare(priv->clk);
639 }
640