1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/netdevice.h>
9 #include <linux/u64_stats_sync.h>
10 #include <linux/errno.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
17 #include <linux/skbuff.h>
18 #include <linux/smp.h>
19 #include <asm/byteorder.h>
20 #include <linux/ip.h>
21 #include <linux/tcp.h>
22 #include <linux/sctp.h>
23 #include <linux/ipv6.h>
24 #include <net/ipv6.h>
25 #include <net/checksum.h>
26 #include <net/ip6_checksum.h>
27
28 #include "hinic_common.h"
29 #include "hinic_hw_if.h"
30 #include "hinic_hw_wqe.h"
31 #include "hinic_hw_wq.h"
32 #include "hinic_hw_qp.h"
33 #include "hinic_hw_dev.h"
34 #include "hinic_dev.h"
35 #include "hinic_tx.h"
36
37 #define TX_IRQ_NO_PENDING 0
38 #define TX_IRQ_NO_COALESC 0
39 #define TX_IRQ_NO_LLI_TIMER 0
40 #define TX_IRQ_NO_CREDIT 0
41 #define TX_IRQ_NO_RESEND_TIMER 0
42
43 #define CI_UPDATE_NO_PENDING 0
44 #define CI_UPDATE_NO_COALESC 0
45
46 #define HW_CONS_IDX(sq) be16_to_cpu(*(u16 *)((sq)->hw_ci_addr))
47
48 #define MIN_SKB_LEN 32
49
50 #define MAX_PAYLOAD_OFFSET 221
51 #define TRANSPORT_OFFSET(l4_hdr, skb) ((u32)((l4_hdr) - (skb)->data))
52
53 union hinic_l3 {
54 struct iphdr *v4;
55 struct ipv6hdr *v6;
56 unsigned char *hdr;
57 };
58
59 union hinic_l4 {
60 struct tcphdr *tcp;
61 struct udphdr *udp;
62 unsigned char *hdr;
63 };
64
65 enum hinic_offload_type {
66 TX_OFFLOAD_TSO = BIT(0),
67 TX_OFFLOAD_CSUM = BIT(1),
68 TX_OFFLOAD_VLAN = BIT(2),
69 TX_OFFLOAD_INVALID = BIT(3),
70 };
71
72 /**
73 * hinic_txq_clean_stats - Clean the statistics of specific queue
74 * @txq: Logical Tx Queue
75 **/
hinic_txq_clean_stats(struct hinic_txq * txq)76 void hinic_txq_clean_stats(struct hinic_txq *txq)
77 {
78 struct hinic_txq_stats *txq_stats = &txq->txq_stats;
79
80 u64_stats_update_begin(&txq_stats->syncp);
81 txq_stats->pkts = 0;
82 txq_stats->bytes = 0;
83 txq_stats->tx_busy = 0;
84 txq_stats->tx_wake = 0;
85 txq_stats->tx_dropped = 0;
86 txq_stats->big_frags_pkts = 0;
87 u64_stats_update_end(&txq_stats->syncp);
88 }
89
90 /**
91 * hinic_txq_get_stats - get statistics of Tx Queue
92 * @txq: Logical Tx Queue
93 * @stats: return updated stats here
94 **/
hinic_txq_get_stats(struct hinic_txq * txq,struct hinic_txq_stats * stats)95 void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats)
96 {
97 struct hinic_txq_stats *txq_stats = &txq->txq_stats;
98 unsigned int start;
99
100 do {
101 start = u64_stats_fetch_begin_irq(&txq_stats->syncp);
102 stats->pkts = txq_stats->pkts;
103 stats->bytes = txq_stats->bytes;
104 stats->tx_busy = txq_stats->tx_busy;
105 stats->tx_wake = txq_stats->tx_wake;
106 stats->tx_dropped = txq_stats->tx_dropped;
107 stats->big_frags_pkts = txq_stats->big_frags_pkts;
108 } while (u64_stats_fetch_retry_irq(&txq_stats->syncp, start));
109 }
110
111 /**
112 * txq_stats_init - Initialize the statistics of specific queue
113 * @txq: Logical Tx Queue
114 **/
txq_stats_init(struct hinic_txq * txq)115 static void txq_stats_init(struct hinic_txq *txq)
116 {
117 struct hinic_txq_stats *txq_stats = &txq->txq_stats;
118
119 u64_stats_init(&txq_stats->syncp);
120 hinic_txq_clean_stats(txq);
121 }
122
123 /**
124 * tx_map_skb - dma mapping for skb and return sges
125 * @nic_dev: nic device
126 * @skb: the skb
127 * @sges: returned sges
128 *
129 * Return 0 - Success, negative - Failure
130 **/
tx_map_skb(struct hinic_dev * nic_dev,struct sk_buff * skb,struct hinic_sge * sges)131 static int tx_map_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
132 struct hinic_sge *sges)
133 {
134 struct hinic_hwdev *hwdev = nic_dev->hwdev;
135 struct hinic_hwif *hwif = hwdev->hwif;
136 struct pci_dev *pdev = hwif->pdev;
137 skb_frag_t *frag;
138 dma_addr_t dma_addr;
139 int i, j;
140
141 dma_addr = dma_map_single(&pdev->dev, skb->data, skb_headlen(skb),
142 DMA_TO_DEVICE);
143 if (dma_mapping_error(&pdev->dev, dma_addr)) {
144 dev_err(&pdev->dev, "Failed to map Tx skb data\n");
145 return -EFAULT;
146 }
147
148 hinic_set_sge(&sges[0], dma_addr, skb_headlen(skb));
149
150 for (i = 0 ; i < skb_shinfo(skb)->nr_frags; i++) {
151 frag = &skb_shinfo(skb)->frags[i];
152
153 dma_addr = skb_frag_dma_map(&pdev->dev, frag, 0,
154 skb_frag_size(frag),
155 DMA_TO_DEVICE);
156 if (dma_mapping_error(&pdev->dev, dma_addr)) {
157 dev_err(&pdev->dev, "Failed to map Tx skb frag\n");
158 goto err_tx_map;
159 }
160
161 hinic_set_sge(&sges[i + 1], dma_addr, skb_frag_size(frag));
162 }
163
164 return 0;
165
166 err_tx_map:
167 for (j = 0; j < i; j++)
168 dma_unmap_page(&pdev->dev, hinic_sge_to_dma(&sges[j + 1]),
169 sges[j + 1].len, DMA_TO_DEVICE);
170
171 dma_unmap_single(&pdev->dev, hinic_sge_to_dma(&sges[0]), sges[0].len,
172 DMA_TO_DEVICE);
173 return -EFAULT;
174 }
175
176 /**
177 * tx_unmap_skb - unmap the dma address of the skb
178 * @nic_dev: nic device
179 * @skb: the skb
180 * @sges: the sges that are connected to the skb
181 **/
tx_unmap_skb(struct hinic_dev * nic_dev,struct sk_buff * skb,struct hinic_sge * sges)182 static void tx_unmap_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
183 struct hinic_sge *sges)
184 {
185 struct hinic_hwdev *hwdev = nic_dev->hwdev;
186 struct hinic_hwif *hwif = hwdev->hwif;
187 struct pci_dev *pdev = hwif->pdev;
188 int i;
189
190 for (i = 0; i < skb_shinfo(skb)->nr_frags ; i++)
191 dma_unmap_page(&pdev->dev, hinic_sge_to_dma(&sges[i + 1]),
192 sges[i + 1].len, DMA_TO_DEVICE);
193
194 dma_unmap_single(&pdev->dev, hinic_sge_to_dma(&sges[0]), sges[0].len,
195 DMA_TO_DEVICE);
196 }
197
get_inner_l3_l4_type(struct sk_buff * skb,union hinic_l3 * ip,union hinic_l4 * l4,enum hinic_offload_type offload_type,enum hinic_l3_offload_type * l3_type,u8 * l4_proto)198 static void get_inner_l3_l4_type(struct sk_buff *skb, union hinic_l3 *ip,
199 union hinic_l4 *l4,
200 enum hinic_offload_type offload_type,
201 enum hinic_l3_offload_type *l3_type,
202 u8 *l4_proto)
203 {
204 u8 *exthdr;
205
206 if (ip->v4->version == 4) {
207 *l3_type = (offload_type == TX_OFFLOAD_CSUM) ?
208 IPV4_PKT_NO_CHKSUM_OFFLOAD :
209 IPV4_PKT_WITH_CHKSUM_OFFLOAD;
210 *l4_proto = ip->v4->protocol;
211 } else if (ip->v4->version == 6) {
212 *l3_type = IPV6_PKT;
213 exthdr = ip->hdr + sizeof(*ip->v6);
214 *l4_proto = ip->v6->nexthdr;
215 if (exthdr != l4->hdr) {
216 int start = exthdr - skb->data;
217 __be16 frag_off;
218
219 ipv6_skip_exthdr(skb, start, l4_proto, &frag_off);
220 }
221 } else {
222 *l3_type = L3TYPE_UNKNOWN;
223 *l4_proto = 0;
224 }
225 }
226
get_inner_l4_info(struct sk_buff * skb,union hinic_l4 * l4,enum hinic_offload_type offload_type,u8 l4_proto,enum hinic_l4_offload_type * l4_offload,u32 * l4_len,u32 * offset)227 static void get_inner_l4_info(struct sk_buff *skb, union hinic_l4 *l4,
228 enum hinic_offload_type offload_type, u8 l4_proto,
229 enum hinic_l4_offload_type *l4_offload,
230 u32 *l4_len, u32 *offset)
231 {
232 *l4_offload = OFFLOAD_DISABLE;
233 *offset = 0;
234 *l4_len = 0;
235
236 switch (l4_proto) {
237 case IPPROTO_TCP:
238 *l4_offload = TCP_OFFLOAD_ENABLE;
239 /* doff in unit of 4B */
240 *l4_len = l4->tcp->doff * 4;
241 *offset = *l4_len + TRANSPORT_OFFSET(l4->hdr, skb);
242 break;
243
244 case IPPROTO_UDP:
245 *l4_offload = UDP_OFFLOAD_ENABLE;
246 *l4_len = sizeof(struct udphdr);
247 *offset = TRANSPORT_OFFSET(l4->hdr, skb);
248 break;
249
250 case IPPROTO_SCTP:
251 /* only csum offload support sctp */
252 if (offload_type != TX_OFFLOAD_CSUM)
253 break;
254
255 *l4_offload = SCTP_OFFLOAD_ENABLE;
256 *l4_len = sizeof(struct sctphdr);
257 *offset = TRANSPORT_OFFSET(l4->hdr, skb);
258 break;
259
260 default:
261 break;
262 }
263 }
264
csum_magic(union hinic_l3 * ip,unsigned short proto)265 static __sum16 csum_magic(union hinic_l3 *ip, unsigned short proto)
266 {
267 return (ip->v4->version == 4) ?
268 csum_tcpudp_magic(ip->v4->saddr, ip->v4->daddr, 0, proto, 0) :
269 csum_ipv6_magic(&ip->v6->saddr, &ip->v6->daddr, 0, proto, 0);
270 }
271
offload_tso(struct hinic_sq_task * task,u32 * queue_info,struct sk_buff * skb)272 static int offload_tso(struct hinic_sq_task *task, u32 *queue_info,
273 struct sk_buff *skb)
274 {
275 u32 offset, l4_len, ip_identify, network_hdr_len;
276 enum hinic_l3_offload_type l3_offload;
277 enum hinic_l4_offload_type l4_offload;
278 union hinic_l3 ip;
279 union hinic_l4 l4;
280 u8 l4_proto;
281
282 if (!skb_is_gso(skb))
283 return 0;
284
285 if (skb_cow_head(skb, 0) < 0)
286 return -EPROTONOSUPPORT;
287
288 if (skb->encapsulation) {
289 u32 gso_type = skb_shinfo(skb)->gso_type;
290 u32 tunnel_type = 0;
291 u32 l4_tunnel_len;
292
293 ip.hdr = skb_network_header(skb);
294 l4.hdr = skb_transport_header(skb);
295 network_hdr_len = skb_inner_network_header_len(skb);
296
297 if (ip.v4->version == 4) {
298 ip.v4->tot_len = 0;
299 l3_offload = IPV4_PKT_WITH_CHKSUM_OFFLOAD;
300 } else if (ip.v4->version == 6) {
301 l3_offload = IPV6_PKT;
302 } else {
303 l3_offload = 0;
304 }
305
306 hinic_task_set_outter_l3(task, l3_offload,
307 skb_network_header_len(skb));
308
309 if (gso_type & SKB_GSO_UDP_TUNNEL_CSUM) {
310 l4.udp->check = ~csum_magic(&ip, IPPROTO_UDP);
311 tunnel_type = TUNNEL_UDP_CSUM;
312 } else if (gso_type & SKB_GSO_UDP_TUNNEL) {
313 tunnel_type = TUNNEL_UDP_NO_CSUM;
314 }
315
316 l4_tunnel_len = skb_inner_network_offset(skb) -
317 skb_transport_offset(skb);
318 hinic_task_set_tunnel_l4(task, tunnel_type, l4_tunnel_len);
319
320 ip.hdr = skb_inner_network_header(skb);
321 l4.hdr = skb_inner_transport_header(skb);
322 } else {
323 ip.hdr = skb_network_header(skb);
324 l4.hdr = skb_transport_header(skb);
325 network_hdr_len = skb_network_header_len(skb);
326 }
327
328 /* initialize inner IP header fields */
329 if (ip.v4->version == 4)
330 ip.v4->tot_len = 0;
331 else
332 ip.v6->payload_len = 0;
333
334 get_inner_l3_l4_type(skb, &ip, &l4, TX_OFFLOAD_TSO, &l3_offload,
335 &l4_proto);
336
337 hinic_task_set_inner_l3(task, l3_offload, network_hdr_len);
338
339 ip_identify = 0;
340 if (l4_proto == IPPROTO_TCP)
341 l4.tcp->check = ~csum_magic(&ip, IPPROTO_TCP);
342
343 get_inner_l4_info(skb, &l4, TX_OFFLOAD_TSO, l4_proto, &l4_offload,
344 &l4_len, &offset);
345
346 hinic_set_tso_inner_l4(task, queue_info, l4_offload, l4_len, offset,
347 ip_identify, skb_shinfo(skb)->gso_size);
348
349 return 1;
350 }
351
offload_csum(struct hinic_sq_task * task,u32 * queue_info,struct sk_buff * skb)352 static int offload_csum(struct hinic_sq_task *task, u32 *queue_info,
353 struct sk_buff *skb)
354 {
355 enum hinic_l4_offload_type l4_offload;
356 u32 offset, l4_len, network_hdr_len;
357 enum hinic_l3_offload_type l3_type;
358 u32 tunnel_type = NOT_TUNNEL;
359 union hinic_l3 ip;
360 union hinic_l4 l4;
361 u8 l4_proto;
362
363 if (skb->ip_summed != CHECKSUM_PARTIAL)
364 return 0;
365
366 if (skb->encapsulation) {
367 u32 l4_tunnel_len;
368
369 tunnel_type = TUNNEL_UDP_NO_CSUM;
370 ip.hdr = skb_network_header(skb);
371
372 if (ip.v4->version == 4) {
373 l3_type = IPV4_PKT_NO_CHKSUM_OFFLOAD;
374 l4_proto = ip.v4->protocol;
375 } else if (ip.v4->version == 6) {
376 unsigned char *exthdr;
377 __be16 frag_off;
378
379 l3_type = IPV6_PKT;
380 tunnel_type = TUNNEL_UDP_CSUM;
381 exthdr = ip.hdr + sizeof(*ip.v6);
382 l4_proto = ip.v6->nexthdr;
383 l4.hdr = skb_transport_header(skb);
384 if (l4.hdr != exthdr)
385 ipv6_skip_exthdr(skb, exthdr - skb->data,
386 &l4_proto, &frag_off);
387 } else {
388 l3_type = L3TYPE_UNKNOWN;
389 l4_proto = IPPROTO_RAW;
390 }
391
392 hinic_task_set_outter_l3(task, l3_type,
393 skb_network_header_len(skb));
394
395 switch (l4_proto) {
396 case IPPROTO_UDP:
397 l4_tunnel_len = skb_inner_network_offset(skb) -
398 skb_transport_offset(skb);
399 ip.hdr = skb_inner_network_header(skb);
400 l4.hdr = skb_inner_transport_header(skb);
401 network_hdr_len = skb_inner_network_header_len(skb);
402 break;
403 case IPPROTO_IPIP:
404 case IPPROTO_IPV6:
405 tunnel_type = NOT_TUNNEL;
406 l4_tunnel_len = 0;
407
408 ip.hdr = skb_inner_network_header(skb);
409 l4.hdr = skb_transport_header(skb);
410 network_hdr_len = skb_network_header_len(skb);
411 break;
412 default:
413 /* Unsupported tunnel packet, disable csum offload */
414 skb_checksum_help(skb);
415 return 0;
416 }
417
418 hinic_task_set_tunnel_l4(task, tunnel_type, l4_tunnel_len);
419 } else {
420 ip.hdr = skb_network_header(skb);
421 l4.hdr = skb_transport_header(skb);
422 network_hdr_len = skb_network_header_len(skb);
423 }
424
425 get_inner_l3_l4_type(skb, &ip, &l4, TX_OFFLOAD_CSUM, &l3_type,
426 &l4_proto);
427
428 hinic_task_set_inner_l3(task, l3_type, network_hdr_len);
429
430 get_inner_l4_info(skb, &l4, TX_OFFLOAD_CSUM, l4_proto, &l4_offload,
431 &l4_len, &offset);
432
433 hinic_set_cs_inner_l4(task, queue_info, l4_offload, l4_len, offset);
434
435 return 1;
436 }
437
offload_vlan(struct hinic_sq_task * task,u32 * queue_info,u16 vlan_tag,u16 vlan_pri)438 static void offload_vlan(struct hinic_sq_task *task, u32 *queue_info,
439 u16 vlan_tag, u16 vlan_pri)
440 {
441 task->pkt_info0 |= HINIC_SQ_TASK_INFO0_SET(vlan_tag, VLAN_TAG) |
442 HINIC_SQ_TASK_INFO0_SET(1U, VLAN_OFFLOAD);
443
444 *queue_info |= HINIC_SQ_CTRL_SET(vlan_pri, QUEUE_INFO_PRI);
445 }
446
hinic_tx_offload(struct sk_buff * skb,struct hinic_sq_task * task,u32 * queue_info)447 static int hinic_tx_offload(struct sk_buff *skb, struct hinic_sq_task *task,
448 u32 *queue_info)
449 {
450 enum hinic_offload_type offload = 0;
451 u16 vlan_tag;
452 int enabled;
453
454 enabled = offload_tso(task, queue_info, skb);
455 if (enabled > 0) {
456 offload |= TX_OFFLOAD_TSO;
457 } else if (enabled == 0) {
458 enabled = offload_csum(task, queue_info, skb);
459 if (enabled)
460 offload |= TX_OFFLOAD_CSUM;
461 } else {
462 return -EPROTONOSUPPORT;
463 }
464
465 if (unlikely(skb_vlan_tag_present(skb))) {
466 vlan_tag = skb_vlan_tag_get(skb);
467 offload_vlan(task, queue_info, vlan_tag,
468 vlan_tag >> VLAN_PRIO_SHIFT);
469 offload |= TX_OFFLOAD_VLAN;
470 }
471
472 if (offload)
473 hinic_task_set_l2hdr(task, skb_network_offset(skb));
474
475 /* payload offset should not more than 221 */
476 if (HINIC_SQ_CTRL_GET(*queue_info, QUEUE_INFO_PLDOFF) >
477 MAX_PAYLOAD_OFFSET) {
478 return -EPROTONOSUPPORT;
479 }
480
481 /* mss should not less than 80 */
482 if (HINIC_SQ_CTRL_GET(*queue_info, QUEUE_INFO_MSS) < HINIC_MSS_MIN) {
483 *queue_info = HINIC_SQ_CTRL_CLEAR(*queue_info, QUEUE_INFO_MSS);
484 *queue_info |= HINIC_SQ_CTRL_SET(HINIC_MSS_MIN, QUEUE_INFO_MSS);
485 }
486
487 return 0;
488 }
489
hinic_lb_xmit_frame(struct sk_buff * skb,struct net_device * netdev)490 netdev_tx_t hinic_lb_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
491 {
492 struct hinic_dev *nic_dev = netdev_priv(netdev);
493 u16 prod_idx, q_id = skb->queue_mapping;
494 struct netdev_queue *netdev_txq;
495 int nr_sges, err = NETDEV_TX_OK;
496 struct hinic_sq_wqe *sq_wqe;
497 unsigned int wqe_size;
498 struct hinic_txq *txq;
499 struct hinic_qp *qp;
500
501 txq = &nic_dev->txqs[q_id];
502 qp = container_of(txq->sq, struct hinic_qp, sq);
503 nr_sges = skb_shinfo(skb)->nr_frags + 1;
504
505 err = tx_map_skb(nic_dev, skb, txq->sges);
506 if (err)
507 goto skb_error;
508
509 wqe_size = HINIC_SQ_WQE_SIZE(nr_sges);
510
511 sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
512 if (!sq_wqe) {
513 netif_stop_subqueue(netdev, qp->q_id);
514
515 sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
516 if (sq_wqe) {
517 netif_wake_subqueue(nic_dev->netdev, qp->q_id);
518 goto process_sq_wqe;
519 }
520
521 tx_unmap_skb(nic_dev, skb, txq->sges);
522
523 u64_stats_update_begin(&txq->txq_stats.syncp);
524 txq->txq_stats.tx_busy++;
525 u64_stats_update_end(&txq->txq_stats.syncp);
526 err = NETDEV_TX_BUSY;
527 wqe_size = 0;
528 goto flush_skbs;
529 }
530
531 process_sq_wqe:
532 hinic_sq_prepare_wqe(txq->sq, prod_idx, sq_wqe, txq->sges, nr_sges);
533 hinic_sq_write_wqe(txq->sq, prod_idx, sq_wqe, skb, wqe_size);
534
535 flush_skbs:
536 netdev_txq = netdev_get_tx_queue(netdev, q_id);
537 if ((!netdev_xmit_more()) || (netif_xmit_stopped(netdev_txq)))
538 hinic_sq_write_db(txq->sq, prod_idx, wqe_size, 0);
539
540 return err;
541
542 skb_error:
543 dev_kfree_skb_any(skb);
544 u64_stats_update_begin(&txq->txq_stats.syncp);
545 txq->txq_stats.tx_dropped++;
546 u64_stats_update_end(&txq->txq_stats.syncp);
547
548 return NETDEV_TX_OK;
549 }
550
hinic_xmit_frame(struct sk_buff * skb,struct net_device * netdev)551 netdev_tx_t hinic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
552 {
553 struct hinic_dev *nic_dev = netdev_priv(netdev);
554 u16 prod_idx, q_id = skb->queue_mapping;
555 struct netdev_queue *netdev_txq;
556 int nr_sges, err = NETDEV_TX_OK;
557 struct hinic_sq_wqe *sq_wqe;
558 unsigned int wqe_size;
559 struct hinic_txq *txq;
560 struct hinic_qp *qp;
561
562 txq = &nic_dev->txqs[q_id];
563 qp = container_of(txq->sq, struct hinic_qp, sq);
564
565 if (skb->len < MIN_SKB_LEN) {
566 if (skb_pad(skb, MIN_SKB_LEN - skb->len)) {
567 netdev_err(netdev, "Failed to pad skb\n");
568 goto update_error_stats;
569 }
570
571 skb->len = MIN_SKB_LEN;
572 }
573
574 nr_sges = skb_shinfo(skb)->nr_frags + 1;
575 if (nr_sges > 17) {
576 u64_stats_update_begin(&txq->txq_stats.syncp);
577 txq->txq_stats.big_frags_pkts++;
578 u64_stats_update_end(&txq->txq_stats.syncp);
579 }
580
581 if (nr_sges > txq->max_sges) {
582 netdev_err(netdev, "Too many Tx sges\n");
583 goto skb_error;
584 }
585
586 err = tx_map_skb(nic_dev, skb, txq->sges);
587 if (err)
588 goto skb_error;
589
590 wqe_size = HINIC_SQ_WQE_SIZE(nr_sges);
591
592 sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
593 if (!sq_wqe) {
594 netif_stop_subqueue(netdev, qp->q_id);
595
596 /* Check for the case free_tx_poll is called in another cpu
597 * and we stopped the subqueue after free_tx_poll check.
598 */
599 sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
600 if (sq_wqe) {
601 netif_wake_subqueue(nic_dev->netdev, qp->q_id);
602 goto process_sq_wqe;
603 }
604
605 tx_unmap_skb(nic_dev, skb, txq->sges);
606
607 u64_stats_update_begin(&txq->txq_stats.syncp);
608 txq->txq_stats.tx_busy++;
609 u64_stats_update_end(&txq->txq_stats.syncp);
610 err = NETDEV_TX_BUSY;
611 wqe_size = 0;
612 goto flush_skbs;
613 }
614
615 process_sq_wqe:
616 hinic_sq_prepare_wqe(txq->sq, prod_idx, sq_wqe, txq->sges, nr_sges);
617
618 err = hinic_tx_offload(skb, &sq_wqe->task, &sq_wqe->ctrl.queue_info);
619 if (err)
620 goto offload_error;
621
622 hinic_sq_write_wqe(txq->sq, prod_idx, sq_wqe, skb, wqe_size);
623
624 flush_skbs:
625 netdev_txq = netdev_get_tx_queue(netdev, q_id);
626 if ((!netdev_xmit_more()) || (netif_xmit_stopped(netdev_txq)))
627 hinic_sq_write_db(txq->sq, prod_idx, wqe_size, 0);
628
629 return err;
630
631 offload_error:
632 hinic_sq_return_wqe(txq->sq, wqe_size);
633 tx_unmap_skb(nic_dev, skb, txq->sges);
634
635 skb_error:
636 dev_kfree_skb_any(skb);
637
638 update_error_stats:
639 u64_stats_update_begin(&txq->txq_stats.syncp);
640 txq->txq_stats.tx_dropped++;
641 u64_stats_update_end(&txq->txq_stats.syncp);
642
643 return NETDEV_TX_OK;
644 }
645
646 /**
647 * tx_free_skb - unmap and free skb
648 * @nic_dev: nic device
649 * @skb: the skb
650 * @sges: the sges that are connected to the skb
651 **/
tx_free_skb(struct hinic_dev * nic_dev,struct sk_buff * skb,struct hinic_sge * sges)652 static void tx_free_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
653 struct hinic_sge *sges)
654 {
655 tx_unmap_skb(nic_dev, skb, sges);
656
657 dev_kfree_skb_any(skb);
658 }
659
660 /**
661 * free_all_tx_skbs - free all skbs in tx queue
662 * @txq: tx queue
663 **/
free_all_tx_skbs(struct hinic_txq * txq)664 static void free_all_tx_skbs(struct hinic_txq *txq)
665 {
666 struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
667 struct hinic_sq *sq = txq->sq;
668 struct hinic_sq_wqe *sq_wqe;
669 unsigned int wqe_size;
670 struct sk_buff *skb;
671 int nr_sges;
672 u16 ci;
673
674 while ((sq_wqe = hinic_sq_read_wqebb(sq, &skb, &wqe_size, &ci))) {
675 sq_wqe = hinic_sq_read_wqe(sq, &skb, wqe_size, &ci);
676 if (!sq_wqe)
677 break;
678
679 nr_sges = skb_shinfo(skb)->nr_frags + 1;
680
681 hinic_sq_get_sges(sq_wqe, txq->free_sges, nr_sges);
682
683 hinic_sq_put_wqe(sq, wqe_size);
684
685 tx_free_skb(nic_dev, skb, txq->free_sges);
686 }
687 }
688
689 /**
690 * free_tx_poll - free finished tx skbs in tx queue that connected to napi
691 * @napi: napi
692 * @budget: number of tx
693 *
694 * Return 0 - Success, negative - Failure
695 **/
free_tx_poll(struct napi_struct * napi,int budget)696 static int free_tx_poll(struct napi_struct *napi, int budget)
697 {
698 struct hinic_txq *txq = container_of(napi, struct hinic_txq, napi);
699 struct hinic_qp *qp = container_of(txq->sq, struct hinic_qp, sq);
700 struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
701 struct netdev_queue *netdev_txq;
702 struct hinic_sq *sq = txq->sq;
703 struct hinic_wq *wq = sq->wq;
704 struct hinic_sq_wqe *sq_wqe;
705 unsigned int wqe_size;
706 int nr_sges, pkts = 0;
707 struct sk_buff *skb;
708 u64 tx_bytes = 0;
709 u16 hw_ci, sw_ci;
710
711 do {
712 hw_ci = HW_CONS_IDX(sq) & wq->mask;
713
714 dma_rmb();
715
716 /* Reading a WQEBB to get real WQE size and consumer index. */
717 sq_wqe = hinic_sq_read_wqebb(sq, &skb, &wqe_size, &sw_ci);
718 if (!sq_wqe ||
719 (((hw_ci - sw_ci) & wq->mask) * wq->wqebb_size < wqe_size))
720 break;
721
722 /* If this WQE have multiple WQEBBs, we will read again to get
723 * full size WQE.
724 */
725 if (wqe_size > wq->wqebb_size) {
726 sq_wqe = hinic_sq_read_wqe(sq, &skb, wqe_size, &sw_ci);
727 if (unlikely(!sq_wqe))
728 break;
729 }
730
731 tx_bytes += skb->len;
732 pkts++;
733
734 nr_sges = skb_shinfo(skb)->nr_frags + 1;
735
736 hinic_sq_get_sges(sq_wqe, txq->free_sges, nr_sges);
737
738 hinic_sq_put_wqe(sq, wqe_size);
739
740 tx_free_skb(nic_dev, skb, txq->free_sges);
741 } while (pkts < budget);
742
743 if (__netif_subqueue_stopped(nic_dev->netdev, qp->q_id) &&
744 hinic_get_sq_free_wqebbs(sq) >= HINIC_MIN_TX_NUM_WQEBBS(sq)) {
745 netdev_txq = netdev_get_tx_queue(txq->netdev, qp->q_id);
746
747 __netif_tx_lock(netdev_txq, smp_processor_id());
748 if (!netif_testing(nic_dev->netdev))
749 netif_wake_subqueue(nic_dev->netdev, qp->q_id);
750
751 __netif_tx_unlock(netdev_txq);
752
753 u64_stats_update_begin(&txq->txq_stats.syncp);
754 txq->txq_stats.tx_wake++;
755 u64_stats_update_end(&txq->txq_stats.syncp);
756 }
757
758 u64_stats_update_begin(&txq->txq_stats.syncp);
759 txq->txq_stats.bytes += tx_bytes;
760 txq->txq_stats.pkts += pkts;
761 u64_stats_update_end(&txq->txq_stats.syncp);
762
763 if (pkts < budget) {
764 napi_complete(napi);
765 if (!HINIC_IS_VF(nic_dev->hwdev->hwif))
766 hinic_hwdev_set_msix_state(nic_dev->hwdev,
767 sq->msix_entry,
768 HINIC_MSIX_ENABLE);
769
770 return pkts;
771 }
772
773 return budget;
774 }
775
tx_irq(int irq,void * data)776 static irqreturn_t tx_irq(int irq, void *data)
777 {
778 struct hinic_txq *txq = data;
779 struct hinic_dev *nic_dev;
780
781 nic_dev = netdev_priv(txq->netdev);
782
783 if (!HINIC_IS_VF(nic_dev->hwdev->hwif))
784 /* Disable the interrupt until napi will be completed */
785 hinic_hwdev_set_msix_state(nic_dev->hwdev,
786 txq->sq->msix_entry,
787 HINIC_MSIX_DISABLE);
788
789 hinic_hwdev_msix_cnt_set(nic_dev->hwdev, txq->sq->msix_entry);
790
791 napi_schedule(&txq->napi);
792 return IRQ_HANDLED;
793 }
794
tx_request_irq(struct hinic_txq * txq)795 static int tx_request_irq(struct hinic_txq *txq)
796 {
797 struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
798 struct hinic_msix_config interrupt_info = {0};
799 struct hinic_intr_coal_info *intr_coal = NULL;
800 struct hinic_hwdev *hwdev = nic_dev->hwdev;
801 struct hinic_hwif *hwif = hwdev->hwif;
802 struct pci_dev *pdev = hwif->pdev;
803 struct hinic_sq *sq = txq->sq;
804 struct hinic_qp *qp;
805 int err;
806
807 qp = container_of(sq, struct hinic_qp, sq);
808
809 netif_napi_add(txq->netdev, &txq->napi, free_tx_poll, nic_dev->tx_weight);
810
811 hinic_hwdev_msix_set(nic_dev->hwdev, sq->msix_entry,
812 TX_IRQ_NO_PENDING, TX_IRQ_NO_COALESC,
813 TX_IRQ_NO_LLI_TIMER, TX_IRQ_NO_CREDIT,
814 TX_IRQ_NO_RESEND_TIMER);
815
816 intr_coal = &nic_dev->tx_intr_coalesce[qp->q_id];
817 interrupt_info.msix_index = sq->msix_entry;
818 interrupt_info.coalesce_timer_cnt = intr_coal->coalesce_timer_cfg;
819 interrupt_info.pending_cnt = intr_coal->pending_limt;
820 interrupt_info.resend_timer_cnt = intr_coal->resend_timer_cfg;
821
822 err = hinic_set_interrupt_cfg(hwdev, &interrupt_info);
823 if (err) {
824 netif_err(nic_dev, drv, txq->netdev,
825 "Failed to set TX interrupt coalescing attribute\n");
826 netif_napi_del(&txq->napi);
827 return err;
828 }
829
830 err = request_irq(sq->irq, tx_irq, 0, txq->irq_name, txq);
831 if (err) {
832 dev_err(&pdev->dev, "Failed to request Tx irq\n");
833 netif_napi_del(&txq->napi);
834 return err;
835 }
836
837 return 0;
838 }
839
tx_free_irq(struct hinic_txq * txq)840 static void tx_free_irq(struct hinic_txq *txq)
841 {
842 struct hinic_sq *sq = txq->sq;
843
844 free_irq(sq->irq, txq);
845 netif_napi_del(&txq->napi);
846 }
847
848 /**
849 * hinic_init_txq - Initialize the Tx Queue
850 * @txq: Logical Tx Queue
851 * @sq: Hardware Tx Queue to connect the Logical queue with
852 * @netdev: network device to connect the Logical queue with
853 *
854 * Return 0 - Success, negative - Failure
855 **/
hinic_init_txq(struct hinic_txq * txq,struct hinic_sq * sq,struct net_device * netdev)856 int hinic_init_txq(struct hinic_txq *txq, struct hinic_sq *sq,
857 struct net_device *netdev)
858 {
859 struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq);
860 struct hinic_dev *nic_dev = netdev_priv(netdev);
861 struct hinic_hwdev *hwdev = nic_dev->hwdev;
862 int err, irqname_len;
863
864 txq->netdev = netdev;
865 txq->sq = sq;
866
867 txq_stats_init(txq);
868
869 txq->max_sges = HINIC_MAX_SQ_BUFDESCS;
870
871 txq->sges = devm_kcalloc(&netdev->dev, txq->max_sges,
872 sizeof(*txq->sges), GFP_KERNEL);
873 if (!txq->sges)
874 return -ENOMEM;
875
876 txq->free_sges = devm_kcalloc(&netdev->dev, txq->max_sges,
877 sizeof(*txq->free_sges), GFP_KERNEL);
878 if (!txq->free_sges) {
879 err = -ENOMEM;
880 goto err_alloc_free_sges;
881 }
882
883 irqname_len = snprintf(NULL, 0, "%s_txq%d", netdev->name, qp->q_id) + 1;
884 txq->irq_name = devm_kzalloc(&netdev->dev, irqname_len, GFP_KERNEL);
885 if (!txq->irq_name) {
886 err = -ENOMEM;
887 goto err_alloc_irqname;
888 }
889
890 sprintf(txq->irq_name, "%s_txq%d", netdev->name, qp->q_id);
891
892 err = hinic_hwdev_hw_ci_addr_set(hwdev, sq, CI_UPDATE_NO_PENDING,
893 CI_UPDATE_NO_COALESC);
894 if (err)
895 goto err_hw_ci;
896
897 err = tx_request_irq(txq);
898 if (err) {
899 netdev_err(netdev, "Failed to request Tx irq\n");
900 goto err_req_tx_irq;
901 }
902
903 return 0;
904
905 err_req_tx_irq:
906 err_hw_ci:
907 devm_kfree(&netdev->dev, txq->irq_name);
908
909 err_alloc_irqname:
910 devm_kfree(&netdev->dev, txq->free_sges);
911
912 err_alloc_free_sges:
913 devm_kfree(&netdev->dev, txq->sges);
914 return err;
915 }
916
917 /**
918 * hinic_clean_txq - Clean the Tx Queue
919 * @txq: Logical Tx Queue
920 **/
hinic_clean_txq(struct hinic_txq * txq)921 void hinic_clean_txq(struct hinic_txq *txq)
922 {
923 struct net_device *netdev = txq->netdev;
924
925 tx_free_irq(txq);
926
927 free_all_tx_skbs(txq);
928
929 devm_kfree(&netdev->dev, txq->irq_name);
930 devm_kfree(&netdev->dev, txq->free_sges);
931 devm_kfree(&netdev->dev, txq->sges);
932 }
933