1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include <linux/types.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/netdevice.h>
8 #include <linux/vmalloc.h>
9 #include <linux/string.h>
10 #include <linux/in.h>
11 #include <linux/interrupt.h>
12 #include <linux/ip.h>
13 #include <linux/tcp.h>
14 #include <linux/sctp.h>
15 #include <linux/pkt_sched.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/etherdevice.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/if_macvlan.h>
25 #include <linux/if_bridge.h>
26 #include <linux/prefetch.h>
27 #include <linux/bpf.h>
28 #include <linux/bpf_trace.h>
29 #include <linux/atomic.h>
30 #include <linux/numa.h>
31 #include <generated/utsrelease.h>
32 #include <scsi/fc/fc_fcoe.h>
33 #include <net/udp_tunnel.h>
34 #include <net/pkt_cls.h>
35 #include <net/tc_act/tc_gact.h>
36 #include <net/tc_act/tc_mirred.h>
37 #include <net/vxlan.h>
38 #include <net/mpls.h>
39 #include <net/xdp_sock_drv.h>
40 #include <net/xfrm.h>
41
42 #include "ixgbe.h"
43 #include "ixgbe_common.h"
44 #include "ixgbe_dcb_82599.h"
45 #include "ixgbe_phy.h"
46 #include "ixgbe_sriov.h"
47 #include "ixgbe_model.h"
48 #include "ixgbe_txrx_common.h"
49
50 char ixgbe_driver_name[] = "ixgbe";
51 static const char ixgbe_driver_string[] =
52 "Intel(R) 10 Gigabit PCI Express Network Driver";
53 #ifdef IXGBE_FCOE
54 char ixgbe_default_device_descr[] =
55 "Intel(R) 10 Gigabit Network Connection";
56 #else
57 static char ixgbe_default_device_descr[] =
58 "Intel(R) 10 Gigabit Network Connection";
59 #endif
60 static const char ixgbe_copyright[] =
61 "Copyright (c) 1999-2016 Intel Corporation.";
62
63 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
64
65 static const struct ixgbe_info *ixgbe_info_tbl[] = {
66 [board_82598] = &ixgbe_82598_info,
67 [board_82599] = &ixgbe_82599_info,
68 [board_X540] = &ixgbe_X540_info,
69 [board_X550] = &ixgbe_X550_info,
70 [board_X550EM_x] = &ixgbe_X550EM_x_info,
71 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info,
72 [board_x550em_a] = &ixgbe_x550em_a_info,
73 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info,
74 };
75
76 /* ixgbe_pci_tbl - PCI Device ID Table
77 *
78 * Wildcard entries (PCI_ANY_ID) should come last
79 * Last entry must be all 0s
80 *
81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
82 * Class, Class Mask, private data (not used) }
83 */
84 static const struct pci_device_id ixgbe_pci_tbl[] = {
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x},
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw},
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
132 /* required last entry */
133 {0, }
134 };
135 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
136
137 #ifdef CONFIG_IXGBE_DCA
138 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
139 void *p);
140 static struct notifier_block dca_notifier = {
141 .notifier_call = ixgbe_notify_dca,
142 .next = NULL,
143 .priority = 0
144 };
145 #endif
146
147 #ifdef CONFIG_PCI_IOV
148 static unsigned int max_vfs;
149 module_param(max_vfs, uint, 0);
150 MODULE_PARM_DESC(max_vfs,
151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
152 #endif /* CONFIG_PCI_IOV */
153
154 static unsigned int allow_unsupported_sfp;
155 module_param(allow_unsupported_sfp, uint, 0);
156 MODULE_PARM_DESC(allow_unsupported_sfp,
157 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
158
159 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
160 static int debug = -1;
161 module_param(debug, int, 0);
162 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
163
164 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
165 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
166 MODULE_LICENSE("GPL v2");
167
168 static struct workqueue_struct *ixgbe_wq;
169
170 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
171 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
172
173 static const struct net_device_ops ixgbe_netdev_ops;
174
netif_is_ixgbe(struct net_device * dev)175 static bool netif_is_ixgbe(struct net_device *dev)
176 {
177 return dev && (dev->netdev_ops == &ixgbe_netdev_ops);
178 }
179
ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter * adapter,u32 reg,u16 * value)180 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
181 u32 reg, u16 *value)
182 {
183 struct pci_dev *parent_dev;
184 struct pci_bus *parent_bus;
185
186 parent_bus = adapter->pdev->bus->parent;
187 if (!parent_bus)
188 return -1;
189
190 parent_dev = parent_bus->self;
191 if (!parent_dev)
192 return -1;
193
194 if (!pci_is_pcie(parent_dev))
195 return -1;
196
197 pcie_capability_read_word(parent_dev, reg, value);
198 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
200 return -1;
201 return 0;
202 }
203
ixgbe_get_parent_bus_info(struct ixgbe_adapter * adapter)204 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
205 {
206 struct ixgbe_hw *hw = &adapter->hw;
207 u16 link_status = 0;
208 int err;
209
210 hw->bus.type = ixgbe_bus_type_pci_express;
211
212 /* Get the negotiated link width and speed from PCI config space of the
213 * parent, as this device is behind a switch
214 */
215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
216
217 /* assume caller will handle error case */
218 if (err)
219 return err;
220
221 hw->bus.width = ixgbe_convert_bus_width(link_status);
222 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
223
224 return 0;
225 }
226
227 /**
228 * ixgbe_pcie_from_parent - Determine whether PCIe info should come from parent
229 * @hw: hw specific details
230 *
231 * This function is used by probe to determine whether a device's PCI-Express
232 * bandwidth details should be gathered from the parent bus instead of from the
233 * device. Used to ensure that various locations all have the correct device ID
234 * checks.
235 */
ixgbe_pcie_from_parent(struct ixgbe_hw * hw)236 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
237 {
238 switch (hw->device_id) {
239 case IXGBE_DEV_ID_82599_SFP_SF_QP:
240 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
241 return true;
242 default:
243 return false;
244 }
245 }
246
ixgbe_check_minimum_link(struct ixgbe_adapter * adapter,int expected_gts)247 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
248 int expected_gts)
249 {
250 struct ixgbe_hw *hw = &adapter->hw;
251 struct pci_dev *pdev;
252
253 /* Some devices are not connected over PCIe and thus do not negotiate
254 * speed. These devices do not have valid bus info, and thus any report
255 * we generate may not be correct.
256 */
257 if (hw->bus.type == ixgbe_bus_type_internal)
258 return;
259
260 /* determine whether to use the parent device */
261 if (ixgbe_pcie_from_parent(&adapter->hw))
262 pdev = adapter->pdev->bus->parent->self;
263 else
264 pdev = adapter->pdev;
265
266 pcie_print_link_status(pdev);
267 }
268
ixgbe_service_event_schedule(struct ixgbe_adapter * adapter)269 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
270 {
271 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
272 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
273 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
274 queue_work(ixgbe_wq, &adapter->service_task);
275 }
276
ixgbe_remove_adapter(struct ixgbe_hw * hw)277 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
278 {
279 struct ixgbe_adapter *adapter = hw->back;
280
281 if (!hw->hw_addr)
282 return;
283 hw->hw_addr = NULL;
284 e_dev_err("Adapter removed\n");
285 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
286 ixgbe_service_event_schedule(adapter);
287 }
288
ixgbe_check_remove(struct ixgbe_hw * hw,u32 reg)289 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
290 {
291 u8 __iomem *reg_addr;
292 u32 value;
293 int i;
294
295 reg_addr = READ_ONCE(hw->hw_addr);
296 if (ixgbe_removed(reg_addr))
297 return IXGBE_FAILED_READ_REG;
298
299 /* Register read of 0xFFFFFFF can indicate the adapter has been removed,
300 * so perform several status register reads to determine if the adapter
301 * has been removed.
302 */
303 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) {
304 value = readl(reg_addr + IXGBE_STATUS);
305 if (value != IXGBE_FAILED_READ_REG)
306 break;
307 mdelay(3);
308 }
309
310 if (value == IXGBE_FAILED_READ_REG)
311 ixgbe_remove_adapter(hw);
312 else
313 value = readl(reg_addr + reg);
314 return value;
315 }
316
317 /**
318 * ixgbe_read_reg - Read from device register
319 * @hw: hw specific details
320 * @reg: offset of register to read
321 *
322 * Returns : value read or IXGBE_FAILED_READ_REG if removed
323 *
324 * This function is used to read device registers. It checks for device
325 * removal by confirming any read that returns all ones by checking the
326 * status register value for all ones. This function avoids reading from
327 * the hardware if a removal was previously detected in which case it
328 * returns IXGBE_FAILED_READ_REG (all ones).
329 */
ixgbe_read_reg(struct ixgbe_hw * hw,u32 reg)330 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
331 {
332 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
333 u32 value;
334
335 if (ixgbe_removed(reg_addr))
336 return IXGBE_FAILED_READ_REG;
337 if (unlikely(hw->phy.nw_mng_if_sel &
338 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) {
339 struct ixgbe_adapter *adapter;
340 int i;
341
342 for (i = 0; i < 200; ++i) {
343 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
344 if (likely(!value))
345 goto writes_completed;
346 if (value == IXGBE_FAILED_READ_REG) {
347 ixgbe_remove_adapter(hw);
348 return IXGBE_FAILED_READ_REG;
349 }
350 udelay(5);
351 }
352
353 adapter = hw->back;
354 e_warn(hw, "register writes incomplete %08x\n", value);
355 }
356
357 writes_completed:
358 value = readl(reg_addr + reg);
359 if (unlikely(value == IXGBE_FAILED_READ_REG))
360 value = ixgbe_check_remove(hw, reg);
361 return value;
362 }
363
ixgbe_check_cfg_remove(struct ixgbe_hw * hw,struct pci_dev * pdev)364 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
365 {
366 u16 value;
367
368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD) {
370 ixgbe_remove_adapter(hw);
371 return true;
372 }
373 return false;
374 }
375
ixgbe_read_pci_cfg_word(struct ixgbe_hw * hw,u32 reg)376 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
377 {
378 struct ixgbe_adapter *adapter = hw->back;
379 u16 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_WORD;
383 pci_read_config_word(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_WORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_WORD;
387 return value;
388 }
389
390 #ifdef CONFIG_PCI_IOV
ixgbe_read_pci_cfg_dword(struct ixgbe_hw * hw,u32 reg)391 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
392 {
393 struct ixgbe_adapter *adapter = hw->back;
394 u32 value;
395
396 if (ixgbe_removed(hw->hw_addr))
397 return IXGBE_FAILED_READ_CFG_DWORD;
398 pci_read_config_dword(adapter->pdev, reg, &value);
399 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
400 ixgbe_check_cfg_remove(hw, adapter->pdev))
401 return IXGBE_FAILED_READ_CFG_DWORD;
402 return value;
403 }
404 #endif /* CONFIG_PCI_IOV */
405
ixgbe_write_pci_cfg_word(struct ixgbe_hw * hw,u32 reg,u16 value)406 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
407 {
408 struct ixgbe_adapter *adapter = hw->back;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return;
412 pci_write_config_word(adapter->pdev, reg, value);
413 }
414
ixgbe_service_event_complete(struct ixgbe_adapter * adapter)415 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
416 {
417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
418
419 /* flush memory to make sure state is correct before next watchdog */
420 smp_mb__before_atomic();
421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
422 }
423
424 struct ixgbe_reg_info {
425 u32 ofs;
426 char *name;
427 };
428
429 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
430
431 /* General Registers */
432 {IXGBE_CTRL, "CTRL"},
433 {IXGBE_STATUS, "STATUS"},
434 {IXGBE_CTRL_EXT, "CTRL_EXT"},
435
436 /* Interrupt Registers */
437 {IXGBE_EICR, "EICR"},
438
439 /* RX Registers */
440 {IXGBE_SRRCTL(0), "SRRCTL"},
441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
442 {IXGBE_RDLEN(0), "RDLEN"},
443 {IXGBE_RDH(0), "RDH"},
444 {IXGBE_RDT(0), "RDT"},
445 {IXGBE_RXDCTL(0), "RXDCTL"},
446 {IXGBE_RDBAL(0), "RDBAL"},
447 {IXGBE_RDBAH(0), "RDBAH"},
448
449 /* TX Registers */
450 {IXGBE_TDBAL(0), "TDBAL"},
451 {IXGBE_TDBAH(0), "TDBAH"},
452 {IXGBE_TDLEN(0), "TDLEN"},
453 {IXGBE_TDH(0), "TDH"},
454 {IXGBE_TDT(0), "TDT"},
455 {IXGBE_TXDCTL(0), "TXDCTL"},
456
457 /* List Terminator */
458 { .name = NULL }
459 };
460
461
462 /*
463 * ixgbe_regdump - register printout routine
464 */
ixgbe_regdump(struct ixgbe_hw * hw,struct ixgbe_reg_info * reginfo)465 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
466 {
467 int i;
468 char rname[16];
469 u32 regs[64];
470
471 switch (reginfo->ofs) {
472 case IXGBE_SRRCTL(0):
473 for (i = 0; i < 64; i++)
474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
475 break;
476 case IXGBE_DCA_RXCTRL(0):
477 for (i = 0; i < 64; i++)
478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
479 break;
480 case IXGBE_RDLEN(0):
481 for (i = 0; i < 64; i++)
482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
483 break;
484 case IXGBE_RDH(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
487 break;
488 case IXGBE_RDT(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
491 break;
492 case IXGBE_RXDCTL(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
495 break;
496 case IXGBE_RDBAL(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
499 break;
500 case IXGBE_RDBAH(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
503 break;
504 case IXGBE_TDBAL(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
507 break;
508 case IXGBE_TDBAH(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
511 break;
512 case IXGBE_TDLEN(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
515 break;
516 case IXGBE_TDH(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
519 break;
520 case IXGBE_TDT(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
523 break;
524 case IXGBE_TXDCTL(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
527 break;
528 default:
529 pr_info("%-15s %08x\n",
530 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs));
531 return;
532 }
533
534 i = 0;
535 while (i < 64) {
536 int j;
537 char buf[9 * 8 + 1];
538 char *p = buf;
539
540 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7);
541 for (j = 0; j < 8; j++)
542 p += sprintf(p, " %08x", regs[i++]);
543 pr_err("%-15s%s\n", rname, buf);
544 }
545
546 }
547
ixgbe_print_buffer(struct ixgbe_ring * ring,int n)548 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n)
549 {
550 struct ixgbe_tx_buffer *tx_buffer;
551
552 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean];
553 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
554 n, ring->next_to_use, ring->next_to_clean,
555 (u64)dma_unmap_addr(tx_buffer, dma),
556 dma_unmap_len(tx_buffer, len),
557 tx_buffer->next_to_watch,
558 (u64)tx_buffer->time_stamp);
559 }
560
561 /*
562 * ixgbe_dump - Print registers, tx-rings and rx-rings
563 */
ixgbe_dump(struct ixgbe_adapter * adapter)564 static void ixgbe_dump(struct ixgbe_adapter *adapter)
565 {
566 struct net_device *netdev = adapter->netdev;
567 struct ixgbe_hw *hw = &adapter->hw;
568 struct ixgbe_reg_info *reginfo;
569 int n = 0;
570 struct ixgbe_ring *ring;
571 struct ixgbe_tx_buffer *tx_buffer;
572 union ixgbe_adv_tx_desc *tx_desc;
573 struct my_u0 { u64 a; u64 b; } *u0;
574 struct ixgbe_ring *rx_ring;
575 union ixgbe_adv_rx_desc *rx_desc;
576 struct ixgbe_rx_buffer *rx_buffer_info;
577 int i = 0;
578
579 if (!netif_msg_hw(adapter))
580 return;
581
582 /* Print netdevice Info */
583 if (netdev) {
584 dev_info(&adapter->pdev->dev, "Net device Info\n");
585 pr_info("Device Name state "
586 "trans_start\n");
587 pr_info("%-15s %016lX %016lX\n",
588 netdev->name,
589 netdev->state,
590 dev_trans_start(netdev));
591 }
592
593 /* Print Registers */
594 dev_info(&adapter->pdev->dev, "Register Dump\n");
595 pr_info(" Register Name Value\n");
596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
597 reginfo->name; reginfo++) {
598 ixgbe_regdump(hw, reginfo);
599 }
600
601 /* Print TX Ring Summary */
602 if (!netdev || !netif_running(netdev))
603 return;
604
605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
606 pr_info(" %s %s %s %s\n",
607 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
608 "leng", "ntw", "timestamp");
609 for (n = 0; n < adapter->num_tx_queues; n++) {
610 ring = adapter->tx_ring[n];
611 ixgbe_print_buffer(ring, n);
612 }
613
614 for (n = 0; n < adapter->num_xdp_queues; n++) {
615 ring = adapter->xdp_ring[n];
616 ixgbe_print_buffer(ring, n);
617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
627 * 82598 Advanced Transmit Descriptor
628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 ring = adapter->tx_ring[n];
662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index);
664 pr_info("------------------------------------\n");
665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
669
670 for (i = 0; ring->desc && (i < ring->count); i++) {
671 tx_desc = IXGBE_TX_DESC(ring, i);
672 tx_buffer = &ring->tx_buffer_info[i];
673 u0 = (struct my_u0 *)tx_desc;
674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 const char *ring_desc;
676
677 if (i == ring->next_to_use &&
678 i == ring->next_to_clean)
679 ring_desc = " NTC/U";
680 else if (i == ring->next_to_use)
681 ring_desc = " NTU";
682 else if (i == ring->next_to_clean)
683 ring_desc = " NTC";
684 else
685 ring_desc = "";
686 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s",
687 i,
688 le64_to_cpu((__force __le64)u0->a),
689 le64_to_cpu((__force __le64)u0->b),
690 (u64)dma_unmap_addr(tx_buffer, dma),
691 dma_unmap_len(tx_buffer, len),
692 tx_buffer->next_to_watch,
693 (u64)tx_buffer->time_stamp,
694 tx_buffer->skb,
695 ring_desc);
696
697 if (netif_msg_pktdata(adapter) &&
698 tx_buffer->skb)
699 print_hex_dump(KERN_INFO, "",
700 DUMP_PREFIX_ADDRESS, 16, 1,
701 tx_buffer->skb->data,
702 dma_unmap_len(tx_buffer, len),
703 true);
704 }
705 }
706 }
707
708 /* Print RX Rings Summary */
709 rx_ring_summary:
710 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
711 pr_info("Queue [NTU] [NTC]\n");
712 for (n = 0; n < adapter->num_rx_queues; n++) {
713 rx_ring = adapter->rx_ring[n];
714 pr_info("%5d %5X %5X\n",
715 n, rx_ring->next_to_use, rx_ring->next_to_clean);
716 }
717
718 /* Print RX Rings */
719 if (!netif_msg_rx_status(adapter))
720 return;
721
722 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
723
724 /* Receive Descriptor Formats
725 *
726 * 82598 Advanced Receive Descriptor (Read) Format
727 * 63 1 0
728 * +-----------------------------------------------------+
729 * 0 | Packet Buffer Address [63:1] |A0/NSE|
730 * +----------------------------------------------+------+
731 * 8 | Header Buffer Address [63:1] | DD |
732 * +-----------------------------------------------------+
733 *
734 *
735 * 82598 Advanced Receive Descriptor (Write-Back) Format
736 *
737 * 63 48 47 32 31 30 21 20 16 15 4 3 0
738 * +------------------------------------------------------+
739 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
740 * | Packet | IP | | | | Type | Type |
741 * | Checksum | Ident | | | | | |
742 * +------------------------------------------------------+
743 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
744 * +------------------------------------------------------+
745 * 63 48 47 32 31 20 19 0
746 *
747 * 82599+ Advanced Receive Descriptor (Read) Format
748 * 63 1 0
749 * +-----------------------------------------------------+
750 * 0 | Packet Buffer Address [63:1] |A0/NSE|
751 * +----------------------------------------------+------+
752 * 8 | Header Buffer Address [63:1] | DD |
753 * +-----------------------------------------------------+
754 *
755 *
756 * 82599+ Advanced Receive Descriptor (Write-Back) Format
757 *
758 * 63 48 47 32 31 30 21 20 17 16 4 3 0
759 * +------------------------------------------------------+
760 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
761 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
762 * |/ Flow Dir Flt ID | | | | | |
763 * +------------------------------------------------------+
764 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
765 * +------------------------------------------------------+
766 * 63 48 47 32 31 20 19 0
767 */
768
769 for (n = 0; n < adapter->num_rx_queues; n++) {
770 rx_ring = adapter->rx_ring[n];
771 pr_info("------------------------------------\n");
772 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
773 pr_info("------------------------------------\n");
774 pr_info("%s%s%s\n",
775 "R [desc] [ PktBuf A0] ",
776 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
777 "<-- Adv Rx Read format");
778 pr_info("%s%s%s\n",
779 "RWB[desc] [PcsmIpSHl PtRs] ",
780 "[vl er S cks ln] ---------------- [bi->skb ] ",
781 "<-- Adv Rx Write-Back format");
782
783 for (i = 0; i < rx_ring->count; i++) {
784 const char *ring_desc;
785
786 if (i == rx_ring->next_to_use)
787 ring_desc = " NTU";
788 else if (i == rx_ring->next_to_clean)
789 ring_desc = " NTC";
790 else
791 ring_desc = "";
792
793 rx_buffer_info = &rx_ring->rx_buffer_info[i];
794 rx_desc = IXGBE_RX_DESC(rx_ring, i);
795 u0 = (struct my_u0 *)rx_desc;
796 if (rx_desc->wb.upper.length) {
797 /* Descriptor Done */
798 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n",
799 i,
800 le64_to_cpu((__force __le64)u0->a),
801 le64_to_cpu((__force __le64)u0->b),
802 rx_buffer_info->skb,
803 ring_desc);
804 } else {
805 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n",
806 i,
807 le64_to_cpu((__force __le64)u0->a),
808 le64_to_cpu((__force __le64)u0->b),
809 (u64)rx_buffer_info->dma,
810 rx_buffer_info->skb,
811 ring_desc);
812
813 if (netif_msg_pktdata(adapter) &&
814 rx_buffer_info->dma) {
815 print_hex_dump(KERN_INFO, "",
816 DUMP_PREFIX_ADDRESS, 16, 1,
817 page_address(rx_buffer_info->page) +
818 rx_buffer_info->page_offset,
819 ixgbe_rx_bufsz(rx_ring), true);
820 }
821 }
822 }
823 }
824 }
825
ixgbe_release_hw_control(struct ixgbe_adapter * adapter)826 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
827 {
828 u32 ctrl_ext;
829
830 /* Let firmware take over control of h/w */
831 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
833 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
834 }
835
ixgbe_get_hw_control(struct ixgbe_adapter * adapter)836 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
837 {
838 u32 ctrl_ext;
839
840 /* Let firmware know the driver has taken over */
841 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
843 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
844 }
845
846 /**
847 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
848 * @adapter: pointer to adapter struct
849 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
850 * @queue: queue to map the corresponding interrupt to
851 * @msix_vector: the vector to map to the corresponding queue
852 *
853 */
ixgbe_set_ivar(struct ixgbe_adapter * adapter,s8 direction,u8 queue,u8 msix_vector)854 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
855 u8 queue, u8 msix_vector)
856 {
857 u32 ivar, index;
858 struct ixgbe_hw *hw = &adapter->hw;
859 switch (hw->mac.type) {
860 case ixgbe_mac_82598EB:
861 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
862 if (direction == -1)
863 direction = 0;
864 index = (((direction * 64) + queue) >> 2) & 0x1F;
865 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
866 ivar &= ~(0xFF << (8 * (queue & 0x3)));
867 ivar |= (msix_vector << (8 * (queue & 0x3)));
868 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
869 break;
870 case ixgbe_mac_82599EB:
871 case ixgbe_mac_X540:
872 case ixgbe_mac_X550:
873 case ixgbe_mac_X550EM_x:
874 case ixgbe_mac_x550em_a:
875 if (direction == -1) {
876 /* other causes */
877 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
878 index = ((queue & 1) * 8);
879 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
880 ivar &= ~(0xFF << index);
881 ivar |= (msix_vector << index);
882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
883 break;
884 } else {
885 /* tx or rx causes */
886 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
887 index = ((16 * (queue & 1)) + (8 * direction));
888 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
889 ivar &= ~(0xFF << index);
890 ivar |= (msix_vector << index);
891 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
892 break;
893 }
894 default:
895 break;
896 }
897 }
898
ixgbe_irq_rearm_queues(struct ixgbe_adapter * adapter,u64 qmask)899 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
900 u64 qmask)
901 {
902 u32 mask;
903
904 switch (adapter->hw.mac.type) {
905 case ixgbe_mac_82598EB:
906 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
908 break;
909 case ixgbe_mac_82599EB:
910 case ixgbe_mac_X540:
911 case ixgbe_mac_X550:
912 case ixgbe_mac_X550EM_x:
913 case ixgbe_mac_x550em_a:
914 mask = (qmask & 0xFFFFFFFF);
915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
916 mask = (qmask >> 32);
917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
918 break;
919 default:
920 break;
921 }
922 }
923
ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter * adapter)924 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
925 {
926 struct ixgbe_hw *hw = &adapter->hw;
927 struct ixgbe_hw_stats *hwstats = &adapter->stats;
928 int i;
929 u32 data;
930
931 if ((hw->fc.current_mode != ixgbe_fc_full) &&
932 (hw->fc.current_mode != ixgbe_fc_rx_pause))
933 return;
934
935 switch (hw->mac.type) {
936 case ixgbe_mac_82598EB:
937 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
938 break;
939 default:
940 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
941 }
942 hwstats->lxoffrxc += data;
943
944 /* refill credits (no tx hang) if we received xoff */
945 if (!data)
946 return;
947
948 for (i = 0; i < adapter->num_tx_queues; i++)
949 clear_bit(__IXGBE_HANG_CHECK_ARMED,
950 &adapter->tx_ring[i]->state);
951
952 for (i = 0; i < adapter->num_xdp_queues; i++)
953 clear_bit(__IXGBE_HANG_CHECK_ARMED,
954 &adapter->xdp_ring[i]->state);
955 }
956
ixgbe_update_xoff_received(struct ixgbe_adapter * adapter)957 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
958 {
959 struct ixgbe_hw *hw = &adapter->hw;
960 struct ixgbe_hw_stats *hwstats = &adapter->stats;
961 u32 xoff[8] = {0};
962 u8 tc;
963 int i;
964 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
965
966 if (adapter->ixgbe_ieee_pfc)
967 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
968
969 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
970 ixgbe_update_xoff_rx_lfc(adapter);
971 return;
972 }
973
974 /* update stats for each tc, only valid with PFC enabled */
975 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
976 u32 pxoffrxc;
977
978 switch (hw->mac.type) {
979 case ixgbe_mac_82598EB:
980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
981 break;
982 default:
983 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
984 }
985 hwstats->pxoffrxc[i] += pxoffrxc;
986 /* Get the TC for given UP */
987 tc = netdev_get_prio_tc_map(adapter->netdev, i);
988 xoff[tc] += pxoffrxc;
989 }
990
991 /* disarm tx queues that have received xoff frames */
992 for (i = 0; i < adapter->num_tx_queues; i++) {
993 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
994
995 tc = tx_ring->dcb_tc;
996 if (xoff[tc])
997 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
998 }
999
1000 for (i = 0; i < adapter->num_xdp_queues; i++) {
1001 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
1002
1003 tc = xdp_ring->dcb_tc;
1004 if (xoff[tc])
1005 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state);
1006 }
1007 }
1008
ixgbe_get_tx_completed(struct ixgbe_ring * ring)1009 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1010 {
1011 return ring->stats.packets;
1012 }
1013
ixgbe_get_tx_pending(struct ixgbe_ring * ring)1014 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1015 {
1016 unsigned int head, tail;
1017
1018 head = ring->next_to_clean;
1019 tail = ring->next_to_use;
1020
1021 return ((head <= tail) ? tail : tail + ring->count) - head;
1022 }
1023
ixgbe_check_tx_hang(struct ixgbe_ring * tx_ring)1024 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1025 {
1026 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1027 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1028 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1029
1030 clear_check_for_tx_hang(tx_ring);
1031
1032 /*
1033 * Check for a hung queue, but be thorough. This verifies
1034 * that a transmit has been completed since the previous
1035 * check AND there is at least one packet pending. The
1036 * ARMED bit is set to indicate a potential hang. The
1037 * bit is cleared if a pause frame is received to remove
1038 * false hang detection due to PFC or 802.3x frames. By
1039 * requiring this to fail twice we avoid races with
1040 * pfc clearing the ARMED bit and conditions where we
1041 * run the check_tx_hang logic with a transmit completion
1042 * pending but without time to complete it yet.
1043 */
1044 if (tx_done_old == tx_done && tx_pending)
1045 /* make sure it is true for two checks in a row */
1046 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1047 &tx_ring->state);
1048 /* update completed stats and continue */
1049 tx_ring->tx_stats.tx_done_old = tx_done;
1050 /* reset the countdown */
1051 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1052
1053 return false;
1054 }
1055
1056 /**
1057 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1058 * @adapter: driver private struct
1059 **/
ixgbe_tx_timeout_reset(struct ixgbe_adapter * adapter)1060 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1061 {
1062
1063 /* Do the reset outside of interrupt context */
1064 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1065 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
1066 e_warn(drv, "initiating reset due to tx timeout\n");
1067 ixgbe_service_event_schedule(adapter);
1068 }
1069 }
1070
1071 /**
1072 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1073 * @netdev: network interface device structure
1074 * @queue_index: Tx queue to set
1075 * @maxrate: desired maximum transmit bitrate
1076 **/
ixgbe_tx_maxrate(struct net_device * netdev,int queue_index,u32 maxrate)1077 static int ixgbe_tx_maxrate(struct net_device *netdev,
1078 int queue_index, u32 maxrate)
1079 {
1080 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1081 struct ixgbe_hw *hw = &adapter->hw;
1082 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1083
1084 if (!maxrate)
1085 return 0;
1086
1087 /* Calculate the rate factor values to set */
1088 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1089 bcnrc_val /= maxrate;
1090
1091 /* clear everything but the rate factor */
1092 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1093 IXGBE_RTTBCNRC_RF_DEC_MASK;
1094
1095 /* enable the rate scheduler */
1096 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1097
1098 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1099 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1100
1101 return 0;
1102 }
1103
1104 /**
1105 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1106 * @q_vector: structure containing interrupt and ring information
1107 * @tx_ring: tx ring to clean
1108 * @napi_budget: Used to determine if we are in netpoll
1109 **/
ixgbe_clean_tx_irq(struct ixgbe_q_vector * q_vector,struct ixgbe_ring * tx_ring,int napi_budget)1110 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1111 struct ixgbe_ring *tx_ring, int napi_budget)
1112 {
1113 struct ixgbe_adapter *adapter = q_vector->adapter;
1114 struct ixgbe_tx_buffer *tx_buffer;
1115 union ixgbe_adv_tx_desc *tx_desc;
1116 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0;
1117 unsigned int budget = q_vector->tx.work_limit;
1118 unsigned int i = tx_ring->next_to_clean;
1119
1120 if (test_bit(__IXGBE_DOWN, &adapter->state))
1121 return true;
1122
1123 tx_buffer = &tx_ring->tx_buffer_info[i];
1124 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1125 i -= tx_ring->count;
1126
1127 do {
1128 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1129
1130 /* if next_to_watch is not set then there is no work pending */
1131 if (!eop_desc)
1132 break;
1133
1134 /* prevent any other reads prior to eop_desc */
1135 smp_rmb();
1136
1137 /* if DD is not set pending work has not been completed */
1138 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1139 break;
1140
1141 /* clear next_to_watch to prevent false hangs */
1142 tx_buffer->next_to_watch = NULL;
1143
1144 /* update the statistics for this packet */
1145 total_bytes += tx_buffer->bytecount;
1146 total_packets += tx_buffer->gso_segs;
1147 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC)
1148 total_ipsec++;
1149
1150 /* free the skb */
1151 if (ring_is_xdp(tx_ring))
1152 xdp_return_frame(tx_buffer->xdpf);
1153 else
1154 napi_consume_skb(tx_buffer->skb, napi_budget);
1155
1156 /* unmap skb header data */
1157 dma_unmap_single(tx_ring->dev,
1158 dma_unmap_addr(tx_buffer, dma),
1159 dma_unmap_len(tx_buffer, len),
1160 DMA_TO_DEVICE);
1161
1162 /* clear tx_buffer data */
1163 dma_unmap_len_set(tx_buffer, len, 0);
1164
1165 /* unmap remaining buffers */
1166 while (tx_desc != eop_desc) {
1167 tx_buffer++;
1168 tx_desc++;
1169 i++;
1170 if (unlikely(!i)) {
1171 i -= tx_ring->count;
1172 tx_buffer = tx_ring->tx_buffer_info;
1173 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1174 }
1175
1176 /* unmap any remaining paged data */
1177 if (dma_unmap_len(tx_buffer, len)) {
1178 dma_unmap_page(tx_ring->dev,
1179 dma_unmap_addr(tx_buffer, dma),
1180 dma_unmap_len(tx_buffer, len),
1181 DMA_TO_DEVICE);
1182 dma_unmap_len_set(tx_buffer, len, 0);
1183 }
1184 }
1185
1186 /* move us one more past the eop_desc for start of next pkt */
1187 tx_buffer++;
1188 tx_desc++;
1189 i++;
1190 if (unlikely(!i)) {
1191 i -= tx_ring->count;
1192 tx_buffer = tx_ring->tx_buffer_info;
1193 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1194 }
1195
1196 /* issue prefetch for next Tx descriptor */
1197 prefetch(tx_desc);
1198
1199 /* update budget accounting */
1200 budget--;
1201 } while (likely(budget));
1202
1203 i += tx_ring->count;
1204 tx_ring->next_to_clean = i;
1205 u64_stats_update_begin(&tx_ring->syncp);
1206 tx_ring->stats.bytes += total_bytes;
1207 tx_ring->stats.packets += total_packets;
1208 u64_stats_update_end(&tx_ring->syncp);
1209 q_vector->tx.total_bytes += total_bytes;
1210 q_vector->tx.total_packets += total_packets;
1211 adapter->tx_ipsec += total_ipsec;
1212
1213 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1214 /* schedule immediate reset if we believe we hung */
1215 struct ixgbe_hw *hw = &adapter->hw;
1216 e_err(drv, "Detected Tx Unit Hang %s\n"
1217 " Tx Queue <%d>\n"
1218 " TDH, TDT <%x>, <%x>\n"
1219 " next_to_use <%x>\n"
1220 " next_to_clean <%x>\n"
1221 "tx_buffer_info[next_to_clean]\n"
1222 " time_stamp <%lx>\n"
1223 " jiffies <%lx>\n",
1224 ring_is_xdp(tx_ring) ? "(XDP)" : "",
1225 tx_ring->queue_index,
1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1228 tx_ring->next_to_use, i,
1229 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1230
1231 if (!ring_is_xdp(tx_ring))
1232 netif_stop_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
1234
1235 e_info(probe,
1236 "tx hang %d detected on queue %d, resetting adapter\n",
1237 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1238
1239 /* schedule immediate reset if we believe we hung */
1240 ixgbe_tx_timeout_reset(adapter);
1241
1242 /* the adapter is about to reset, no point in enabling stuff */
1243 return true;
1244 }
1245
1246 if (ring_is_xdp(tx_ring))
1247 return !!budget;
1248
1249 netdev_tx_completed_queue(txring_txq(tx_ring),
1250 total_packets, total_bytes);
1251
1252 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1254 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1255 /* Make sure that anybody stopping the queue after this
1256 * sees the new next_to_clean.
1257 */
1258 smp_mb();
1259 if (__netif_subqueue_stopped(tx_ring->netdev,
1260 tx_ring->queue_index)
1261 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1262 netif_wake_subqueue(tx_ring->netdev,
1263 tx_ring->queue_index);
1264 ++tx_ring->tx_stats.restart_queue;
1265 }
1266 }
1267
1268 return !!budget;
1269 }
1270
1271 #ifdef CONFIG_IXGBE_DCA
ixgbe_update_tx_dca(struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring,int cpu)1272 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1273 struct ixgbe_ring *tx_ring,
1274 int cpu)
1275 {
1276 struct ixgbe_hw *hw = &adapter->hw;
1277 u32 txctrl = 0;
1278 u16 reg_offset;
1279
1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1282
1283 switch (hw->mac.type) {
1284 case ixgbe_mac_82598EB:
1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1286 break;
1287 case ixgbe_mac_82599EB:
1288 case ixgbe_mac_X540:
1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1290 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1291 break;
1292 default:
1293 /* for unknown hardware do not write register */
1294 return;
1295 }
1296
1297 /*
1298 * We can enable relaxed ordering for reads, but not writes when
1299 * DCA is enabled. This is due to a known issue in some chipsets
1300 * which will cause the DCA tag to be cleared.
1301 */
1302 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1303 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1304 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1305
1306 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1307 }
1308
ixgbe_update_rx_dca(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring,int cpu)1309 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1310 struct ixgbe_ring *rx_ring,
1311 int cpu)
1312 {
1313 struct ixgbe_hw *hw = &adapter->hw;
1314 u32 rxctrl = 0;
1315 u8 reg_idx = rx_ring->reg_idx;
1316
1317 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1318 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1319
1320 switch (hw->mac.type) {
1321 case ixgbe_mac_82599EB:
1322 case ixgbe_mac_X540:
1323 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1324 break;
1325 default:
1326 break;
1327 }
1328
1329 /*
1330 * We can enable relaxed ordering for reads, but not writes when
1331 * DCA is enabled. This is due to a known issue in some chipsets
1332 * which will cause the DCA tag to be cleared.
1333 */
1334 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1335 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1336 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1337
1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1339 }
1340
ixgbe_update_dca(struct ixgbe_q_vector * q_vector)1341 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1342 {
1343 struct ixgbe_adapter *adapter = q_vector->adapter;
1344 struct ixgbe_ring *ring;
1345 int cpu = get_cpu();
1346
1347 if (q_vector->cpu == cpu)
1348 goto out_no_update;
1349
1350 ixgbe_for_each_ring(ring, q_vector->tx)
1351 ixgbe_update_tx_dca(adapter, ring, cpu);
1352
1353 ixgbe_for_each_ring(ring, q_vector->rx)
1354 ixgbe_update_rx_dca(adapter, ring, cpu);
1355
1356 q_vector->cpu = cpu;
1357 out_no_update:
1358 put_cpu();
1359 }
1360
ixgbe_setup_dca(struct ixgbe_adapter * adapter)1361 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1362 {
1363 int i;
1364
1365 /* always use CB2 mode, difference is masked in the CB driver */
1366 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1368 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1369 else
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1371 IXGBE_DCA_CTRL_DCA_DISABLE);
1372
1373 for (i = 0; i < adapter->num_q_vectors; i++) {
1374 adapter->q_vector[i]->cpu = -1;
1375 ixgbe_update_dca(adapter->q_vector[i]);
1376 }
1377 }
1378
__ixgbe_notify_dca(struct device * dev,void * data)1379 static int __ixgbe_notify_dca(struct device *dev, void *data)
1380 {
1381 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1382 unsigned long event = *(unsigned long *)data;
1383
1384 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1385 return 0;
1386
1387 switch (event) {
1388 case DCA_PROVIDER_ADD:
1389 /* if we're already enabled, don't do it again */
1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1391 break;
1392 if (dca_add_requester(dev) == 0) {
1393 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1395 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1396 break;
1397 }
1398 fallthrough; /* DCA is disabled. */
1399 case DCA_PROVIDER_REMOVE:
1400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1401 dca_remove_requester(dev);
1402 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1404 IXGBE_DCA_CTRL_DCA_DISABLE);
1405 }
1406 break;
1407 }
1408
1409 return 0;
1410 }
1411
1412 #endif /* CONFIG_IXGBE_DCA */
1413
1414 #define IXGBE_RSS_L4_TYPES_MASK \
1415 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1419
ixgbe_rx_hash(struct ixgbe_ring * ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1420 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1421 union ixgbe_adv_rx_desc *rx_desc,
1422 struct sk_buff *skb)
1423 {
1424 u16 rss_type;
1425
1426 if (!(ring->netdev->features & NETIF_F_RXHASH))
1427 return;
1428
1429 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1430 IXGBE_RXDADV_RSSTYPE_MASK;
1431
1432 if (!rss_type)
1433 return;
1434
1435 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1436 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1437 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1438 }
1439
1440 #ifdef IXGBE_FCOE
1441 /**
1442 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1443 * @ring: structure containing ring specific data
1444 * @rx_desc: advanced rx descriptor
1445 *
1446 * Returns : true if it is FCoE pkt
1447 */
ixgbe_rx_is_fcoe(struct ixgbe_ring * ring,union ixgbe_adv_rx_desc * rx_desc)1448 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1449 union ixgbe_adv_rx_desc *rx_desc)
1450 {
1451 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1452
1453 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1454 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1455 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1456 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1457 }
1458
1459 #endif /* IXGBE_FCOE */
1460 /**
1461 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1462 * @ring: structure containing ring specific data
1463 * @rx_desc: current Rx descriptor being processed
1464 * @skb: skb currently being received and modified
1465 **/
ixgbe_rx_checksum(struct ixgbe_ring * ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1466 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1467 union ixgbe_adv_rx_desc *rx_desc,
1468 struct sk_buff *skb)
1469 {
1470 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1471 bool encap_pkt = false;
1472
1473 skb_checksum_none_assert(skb);
1474
1475 /* Rx csum disabled */
1476 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1477 return;
1478
1479 /* check for VXLAN and Geneve packets */
1480 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
1481 encap_pkt = true;
1482 skb->encapsulation = 1;
1483 }
1484
1485 /* if IP and error */
1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1487 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1488 ring->rx_stats.csum_err++;
1489 return;
1490 }
1491
1492 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1493 return;
1494
1495 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1496 /*
1497 * 82599 errata, UDP frames with a 0 checksum can be marked as
1498 * checksum errors.
1499 */
1500 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1501 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1502 return;
1503
1504 ring->rx_stats.csum_err++;
1505 return;
1506 }
1507
1508 /* It must be a TCP or UDP packet with a valid checksum */
1509 skb->ip_summed = CHECKSUM_UNNECESSARY;
1510 if (encap_pkt) {
1511 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1512 return;
1513
1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1515 skb->ip_summed = CHECKSUM_NONE;
1516 return;
1517 }
1518 /* If we checked the outer header let the stack know */
1519 skb->csum_level = 1;
1520 }
1521 }
1522
ixgbe_rx_offset(struct ixgbe_ring * rx_ring)1523 static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
1524 {
1525 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1526 }
1527
ixgbe_alloc_mapped_page(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * bi)1528 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1529 struct ixgbe_rx_buffer *bi)
1530 {
1531 struct page *page = bi->page;
1532 dma_addr_t dma;
1533
1534 /* since we are recycling buffers we should seldom need to alloc */
1535 if (likely(page))
1536 return true;
1537
1538 /* alloc new page for storage */
1539 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1540 if (unlikely(!page)) {
1541 rx_ring->rx_stats.alloc_rx_page_failed++;
1542 return false;
1543 }
1544
1545 /* map page for use */
1546 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1547 ixgbe_rx_pg_size(rx_ring),
1548 DMA_FROM_DEVICE,
1549 IXGBE_RX_DMA_ATTR);
1550
1551 /*
1552 * if mapping failed free memory back to system since
1553 * there isn't much point in holding memory we can't use
1554 */
1555 if (dma_mapping_error(rx_ring->dev, dma)) {
1556 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1557
1558 rx_ring->rx_stats.alloc_rx_page_failed++;
1559 return false;
1560 }
1561
1562 bi->dma = dma;
1563 bi->page = page;
1564 bi->page_offset = rx_ring->rx_offset;
1565 page_ref_add(page, USHRT_MAX - 1);
1566 bi->pagecnt_bias = USHRT_MAX;
1567 rx_ring->rx_stats.alloc_rx_page++;
1568
1569 return true;
1570 }
1571
1572 /**
1573 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1574 * @rx_ring: ring to place buffers on
1575 * @cleaned_count: number of buffers to replace
1576 **/
ixgbe_alloc_rx_buffers(struct ixgbe_ring * rx_ring,u16 cleaned_count)1577 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1578 {
1579 union ixgbe_adv_rx_desc *rx_desc;
1580 struct ixgbe_rx_buffer *bi;
1581 u16 i = rx_ring->next_to_use;
1582 u16 bufsz;
1583
1584 /* nothing to do */
1585 if (!cleaned_count)
1586 return;
1587
1588 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1589 bi = &rx_ring->rx_buffer_info[i];
1590 i -= rx_ring->count;
1591
1592 bufsz = ixgbe_rx_bufsz(rx_ring);
1593
1594 do {
1595 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1596 break;
1597
1598 /* sync the buffer for use by the device */
1599 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1600 bi->page_offset, bufsz,
1601 DMA_FROM_DEVICE);
1602
1603 /*
1604 * Refresh the desc even if buffer_addrs didn't change
1605 * because each write-back erases this info.
1606 */
1607 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1608
1609 rx_desc++;
1610 bi++;
1611 i++;
1612 if (unlikely(!i)) {
1613 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1614 bi = rx_ring->rx_buffer_info;
1615 i -= rx_ring->count;
1616 }
1617
1618 /* clear the length for the next_to_use descriptor */
1619 rx_desc->wb.upper.length = 0;
1620
1621 cleaned_count--;
1622 } while (cleaned_count);
1623
1624 i += rx_ring->count;
1625
1626 if (rx_ring->next_to_use != i) {
1627 rx_ring->next_to_use = i;
1628
1629 /* update next to alloc since we have filled the ring */
1630 rx_ring->next_to_alloc = i;
1631
1632 /* Force memory writes to complete before letting h/w
1633 * know there are new descriptors to fetch. (Only
1634 * applicable for weak-ordered memory model archs,
1635 * such as IA-64).
1636 */
1637 wmb();
1638 writel(i, rx_ring->tail);
1639 }
1640 }
1641
ixgbe_set_rsc_gso_size(struct ixgbe_ring * ring,struct sk_buff * skb)1642 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1643 struct sk_buff *skb)
1644 {
1645 u16 hdr_len = skb_headlen(skb);
1646
1647 /* set gso_size to avoid messing up TCP MSS */
1648 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1649 IXGBE_CB(skb)->append_cnt);
1650 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1651 }
1652
ixgbe_update_rsc_stats(struct ixgbe_ring * rx_ring,struct sk_buff * skb)1653 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1654 struct sk_buff *skb)
1655 {
1656 /* if append_cnt is 0 then frame is not RSC */
1657 if (!IXGBE_CB(skb)->append_cnt)
1658 return;
1659
1660 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1661 rx_ring->rx_stats.rsc_flush++;
1662
1663 ixgbe_set_rsc_gso_size(rx_ring, skb);
1664
1665 /* gso_size is computed using append_cnt so always clear it last */
1666 IXGBE_CB(skb)->append_cnt = 0;
1667 }
1668
1669 /**
1670 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1671 * @rx_ring: rx descriptor ring packet is being transacted on
1672 * @rx_desc: pointer to the EOP Rx descriptor
1673 * @skb: pointer to current skb being populated
1674 *
1675 * This function checks the ring, descriptor, and packet information in
1676 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1677 * other fields within the skb.
1678 **/
ixgbe_process_skb_fields(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1679 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1680 union ixgbe_adv_rx_desc *rx_desc,
1681 struct sk_buff *skb)
1682 {
1683 struct net_device *dev = rx_ring->netdev;
1684 u32 flags = rx_ring->q_vector->adapter->flags;
1685
1686 ixgbe_update_rsc_stats(rx_ring, skb);
1687
1688 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1689
1690 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1691
1692 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1693 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1694
1695 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1696 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1697 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1699 }
1700
1701 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP))
1702 ixgbe_ipsec_rx(rx_ring, rx_desc, skb);
1703
1704 /* record Rx queue, or update MACVLAN statistics */
1705 if (netif_is_ixgbe(dev))
1706 skb_record_rx_queue(skb, rx_ring->queue_index);
1707 else
1708 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true,
1709 false);
1710
1711 skb->protocol = eth_type_trans(skb, dev);
1712 }
1713
ixgbe_rx_skb(struct ixgbe_q_vector * q_vector,struct sk_buff * skb)1714 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1715 struct sk_buff *skb)
1716 {
1717 napi_gro_receive(&q_vector->napi, skb);
1718 }
1719
1720 /**
1721 * ixgbe_is_non_eop - process handling of non-EOP buffers
1722 * @rx_ring: Rx ring being processed
1723 * @rx_desc: Rx descriptor for current buffer
1724 * @skb: Current socket buffer containing buffer in progress
1725 *
1726 * This function updates next to clean. If the buffer is an EOP buffer
1727 * this function exits returning false, otherwise it will place the
1728 * sk_buff in the next buffer to be chained and return true indicating
1729 * that this is in fact a non-EOP buffer.
1730 **/
ixgbe_is_non_eop(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1731 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1732 union ixgbe_adv_rx_desc *rx_desc,
1733 struct sk_buff *skb)
1734 {
1735 u32 ntc = rx_ring->next_to_clean + 1;
1736
1737 /* fetch, update, and store next to clean */
1738 ntc = (ntc < rx_ring->count) ? ntc : 0;
1739 rx_ring->next_to_clean = ntc;
1740
1741 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1742
1743 /* update RSC append count if present */
1744 if (ring_is_rsc_enabled(rx_ring)) {
1745 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1746 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1747
1748 if (unlikely(rsc_enabled)) {
1749 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1750
1751 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1752 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1753
1754 /* update ntc based on RSC value */
1755 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1756 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1757 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1758 }
1759 }
1760
1761 /* if we are the last buffer then there is nothing else to do */
1762 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1763 return false;
1764
1765 /* place skb in next buffer to be received */
1766 rx_ring->rx_buffer_info[ntc].skb = skb;
1767 rx_ring->rx_stats.non_eop_descs++;
1768
1769 return true;
1770 }
1771
1772 /**
1773 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1774 * @rx_ring: rx descriptor ring packet is being transacted on
1775 * @skb: pointer to current skb being adjusted
1776 *
1777 * This function is an ixgbe specific version of __pskb_pull_tail. The
1778 * main difference between this version and the original function is that
1779 * this function can make several assumptions about the state of things
1780 * that allow for significant optimizations versus the standard function.
1781 * As a result we can do things like drop a frag and maintain an accurate
1782 * truesize for the skb.
1783 */
ixgbe_pull_tail(struct ixgbe_ring * rx_ring,struct sk_buff * skb)1784 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1785 struct sk_buff *skb)
1786 {
1787 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1788 unsigned char *va;
1789 unsigned int pull_len;
1790
1791 /*
1792 * it is valid to use page_address instead of kmap since we are
1793 * working with pages allocated out of the lomem pool per
1794 * alloc_page(GFP_ATOMIC)
1795 */
1796 va = skb_frag_address(frag);
1797
1798 /*
1799 * we need the header to contain the greater of either ETH_HLEN or
1800 * 60 bytes if the skb->len is less than 60 for skb_pad.
1801 */
1802 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE);
1803
1804 /* align pull length to size of long to optimize memcpy performance */
1805 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1806
1807 /* update all of the pointers */
1808 skb_frag_size_sub(frag, pull_len);
1809 skb_frag_off_add(frag, pull_len);
1810 skb->data_len -= pull_len;
1811 skb->tail += pull_len;
1812 }
1813
1814 /**
1815 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1816 * @rx_ring: rx descriptor ring packet is being transacted on
1817 * @skb: pointer to current skb being updated
1818 *
1819 * This function provides a basic DMA sync up for the first fragment of an
1820 * skb. The reason for doing this is that the first fragment cannot be
1821 * unmapped until we have reached the end of packet descriptor for a buffer
1822 * chain.
1823 */
ixgbe_dma_sync_frag(struct ixgbe_ring * rx_ring,struct sk_buff * skb)1824 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1825 struct sk_buff *skb)
1826 {
1827 if (ring_uses_build_skb(rx_ring)) {
1828 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1;
1829 unsigned long offset = (unsigned long)(skb->data) & mask;
1830
1831 dma_sync_single_range_for_cpu(rx_ring->dev,
1832 IXGBE_CB(skb)->dma,
1833 offset,
1834 skb_headlen(skb),
1835 DMA_FROM_DEVICE);
1836 } else {
1837 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1838
1839 dma_sync_single_range_for_cpu(rx_ring->dev,
1840 IXGBE_CB(skb)->dma,
1841 skb_frag_off(frag),
1842 skb_frag_size(frag),
1843 DMA_FROM_DEVICE);
1844 }
1845
1846 /* If the page was released, just unmap it. */
1847 if (unlikely(IXGBE_CB(skb)->page_released)) {
1848 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1849 ixgbe_rx_pg_size(rx_ring),
1850 DMA_FROM_DEVICE,
1851 IXGBE_RX_DMA_ATTR);
1852 }
1853 }
1854
1855 /**
1856 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1857 * @rx_ring: rx descriptor ring packet is being transacted on
1858 * @rx_desc: pointer to the EOP Rx descriptor
1859 * @skb: pointer to current skb being fixed
1860 *
1861 * Check if the skb is valid in the XDP case it will be an error pointer.
1862 * Return true in this case to abort processing and advance to next
1863 * descriptor.
1864 *
1865 * Check for corrupted packet headers caused by senders on the local L2
1866 * embedded NIC switch not setting up their Tx Descriptors right. These
1867 * should be very rare.
1868 *
1869 * Also address the case where we are pulling data in on pages only
1870 * and as such no data is present in the skb header.
1871 *
1872 * In addition if skb is not at least 60 bytes we need to pad it so that
1873 * it is large enough to qualify as a valid Ethernet frame.
1874 *
1875 * Returns true if an error was encountered and skb was freed.
1876 **/
ixgbe_cleanup_headers(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1877 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1878 union ixgbe_adv_rx_desc *rx_desc,
1879 struct sk_buff *skb)
1880 {
1881 struct net_device *netdev = rx_ring->netdev;
1882
1883 /* XDP packets use error pointer so abort at this point */
1884 if (IS_ERR(skb))
1885 return true;
1886
1887 /* Verify netdev is present, and that packet does not have any
1888 * errors that would be unacceptable to the netdev.
1889 */
1890 if (!netdev ||
1891 (unlikely(ixgbe_test_staterr(rx_desc,
1892 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1893 !(netdev->features & NETIF_F_RXALL)))) {
1894 dev_kfree_skb_any(skb);
1895 return true;
1896 }
1897
1898 /* place header in linear portion of buffer */
1899 if (!skb_headlen(skb))
1900 ixgbe_pull_tail(rx_ring, skb);
1901
1902 #ifdef IXGBE_FCOE
1903 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1904 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1905 return false;
1906
1907 #endif
1908 /* if eth_skb_pad returns an error the skb was freed */
1909 if (eth_skb_pad(skb))
1910 return true;
1911
1912 return false;
1913 }
1914
1915 /**
1916 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1917 * @rx_ring: rx descriptor ring to store buffers on
1918 * @old_buff: donor buffer to have page reused
1919 *
1920 * Synchronizes page for reuse by the adapter
1921 **/
ixgbe_reuse_rx_page(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * old_buff)1922 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1923 struct ixgbe_rx_buffer *old_buff)
1924 {
1925 struct ixgbe_rx_buffer *new_buff;
1926 u16 nta = rx_ring->next_to_alloc;
1927
1928 new_buff = &rx_ring->rx_buffer_info[nta];
1929
1930 /* update, and store next to alloc */
1931 nta++;
1932 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1933
1934 /* Transfer page from old buffer to new buffer.
1935 * Move each member individually to avoid possible store
1936 * forwarding stalls and unnecessary copy of skb.
1937 */
1938 new_buff->dma = old_buff->dma;
1939 new_buff->page = old_buff->page;
1940 new_buff->page_offset = old_buff->page_offset;
1941 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1942 }
1943
ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer * rx_buffer,int rx_buffer_pgcnt)1944 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer,
1945 int rx_buffer_pgcnt)
1946 {
1947 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1948 struct page *page = rx_buffer->page;
1949
1950 /* avoid re-using remote and pfmemalloc pages */
1951 if (!dev_page_is_reusable(page))
1952 return false;
1953
1954 #if (PAGE_SIZE < 8192)
1955 /* if we are only owner of page we can reuse it */
1956 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
1957 return false;
1958 #else
1959 /* The last offset is a bit aggressive in that we assume the
1960 * worst case of FCoE being enabled and using a 3K buffer.
1961 * However this should have minimal impact as the 1K extra is
1962 * still less than one buffer in size.
1963 */
1964 #define IXGBE_LAST_OFFSET \
1965 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
1966 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
1967 return false;
1968 #endif
1969
1970 /* If we have drained the page fragment pool we need to update
1971 * the pagecnt_bias and page count so that we fully restock the
1972 * number of references the driver holds.
1973 */
1974 if (unlikely(pagecnt_bias == 1)) {
1975 page_ref_add(page, USHRT_MAX - 1);
1976 rx_buffer->pagecnt_bias = USHRT_MAX;
1977 }
1978
1979 return true;
1980 }
1981
1982 /**
1983 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1984 * @rx_ring: rx descriptor ring to transact packets on
1985 * @rx_buffer: buffer containing page to add
1986 * @skb: sk_buff to place the data into
1987 * @size: size of data in rx_buffer
1988 *
1989 * This function will add the data contained in rx_buffer->page to the skb.
1990 * This is done either through a direct copy if the data in the buffer is
1991 * less than the skb header size, otherwise it will just attach the page as
1992 * a frag to the skb.
1993 *
1994 * The function will then update the page offset if necessary and return
1995 * true if the buffer can be reused by the adapter.
1996 **/
ixgbe_add_rx_frag(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,struct sk_buff * skb,unsigned int size)1997 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1998 struct ixgbe_rx_buffer *rx_buffer,
1999 struct sk_buff *skb,
2000 unsigned int size)
2001 {
2002 #if (PAGE_SIZE < 8192)
2003 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2004 #else
2005 unsigned int truesize = rx_ring->rx_offset ?
2006 SKB_DATA_ALIGN(rx_ring->rx_offset + size) :
2007 SKB_DATA_ALIGN(size);
2008 #endif
2009 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
2010 rx_buffer->page_offset, size, truesize);
2011 #if (PAGE_SIZE < 8192)
2012 rx_buffer->page_offset ^= truesize;
2013 #else
2014 rx_buffer->page_offset += truesize;
2015 #endif
2016 }
2017
ixgbe_get_rx_buffer(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff ** skb,const unsigned int size,int * rx_buffer_pgcnt)2018 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2019 union ixgbe_adv_rx_desc *rx_desc,
2020 struct sk_buff **skb,
2021 const unsigned int size,
2022 int *rx_buffer_pgcnt)
2023 {
2024 struct ixgbe_rx_buffer *rx_buffer;
2025
2026 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2027 *rx_buffer_pgcnt =
2028 #if (PAGE_SIZE < 8192)
2029 page_count(rx_buffer->page);
2030 #else
2031 0;
2032 #endif
2033 prefetchw(rx_buffer->page);
2034 *skb = rx_buffer->skb;
2035
2036 /* Delay unmapping of the first packet. It carries the header
2037 * information, HW may still access the header after the writeback.
2038 * Only unmap it when EOP is reached
2039 */
2040 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2041 if (!*skb)
2042 goto skip_sync;
2043 } else {
2044 if (*skb)
2045 ixgbe_dma_sync_frag(rx_ring, *skb);
2046 }
2047
2048 /* we are reusing so sync this buffer for CPU use */
2049 dma_sync_single_range_for_cpu(rx_ring->dev,
2050 rx_buffer->dma,
2051 rx_buffer->page_offset,
2052 size,
2053 DMA_FROM_DEVICE);
2054 skip_sync:
2055 rx_buffer->pagecnt_bias--;
2056
2057 return rx_buffer;
2058 }
2059
ixgbe_put_rx_buffer(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,struct sk_buff * skb,int rx_buffer_pgcnt)2060 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2061 struct ixgbe_rx_buffer *rx_buffer,
2062 struct sk_buff *skb,
2063 int rx_buffer_pgcnt)
2064 {
2065 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
2066 /* hand second half of page back to the ring */
2067 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2068 } else {
2069 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) {
2070 /* the page has been released from the ring */
2071 IXGBE_CB(skb)->page_released = true;
2072 } else {
2073 /* we are not reusing the buffer so unmap it */
2074 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2075 ixgbe_rx_pg_size(rx_ring),
2076 DMA_FROM_DEVICE,
2077 IXGBE_RX_DMA_ATTR);
2078 }
2079 __page_frag_cache_drain(rx_buffer->page,
2080 rx_buffer->pagecnt_bias);
2081 }
2082
2083 /* clear contents of rx_buffer */
2084 rx_buffer->page = NULL;
2085 rx_buffer->skb = NULL;
2086 }
2087
ixgbe_construct_skb(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,struct xdp_buff * xdp,union ixgbe_adv_rx_desc * rx_desc)2088 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2089 struct ixgbe_rx_buffer *rx_buffer,
2090 struct xdp_buff *xdp,
2091 union ixgbe_adv_rx_desc *rx_desc)
2092 {
2093 unsigned int size = xdp->data_end - xdp->data;
2094 #if (PAGE_SIZE < 8192)
2095 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2096 #else
2097 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
2098 xdp->data_hard_start);
2099 #endif
2100 struct sk_buff *skb;
2101
2102 /* prefetch first cache line of first page */
2103 net_prefetch(xdp->data);
2104
2105 /* Note, we get here by enabling legacy-rx via:
2106 *
2107 * ethtool --set-priv-flags <dev> legacy-rx on
2108 *
2109 * In this mode, we currently get 0 extra XDP headroom as
2110 * opposed to having legacy-rx off, where we process XDP
2111 * packets going to stack via ixgbe_build_skb(). The latter
2112 * provides us currently with 192 bytes of headroom.
2113 *
2114 * For ixgbe_construct_skb() mode it means that the
2115 * xdp->data_meta will always point to xdp->data, since
2116 * the helper cannot expand the head. Should this ever
2117 * change in future for legacy-rx mode on, then lets also
2118 * add xdp->data_meta handling here.
2119 */
2120
2121 /* allocate a skb to store the frags */
2122 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2123 if (unlikely(!skb))
2124 return NULL;
2125
2126 if (size > IXGBE_RX_HDR_SIZE) {
2127 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2128 IXGBE_CB(skb)->dma = rx_buffer->dma;
2129
2130 skb_add_rx_frag(skb, 0, rx_buffer->page,
2131 xdp->data - page_address(rx_buffer->page),
2132 size, truesize);
2133 #if (PAGE_SIZE < 8192)
2134 rx_buffer->page_offset ^= truesize;
2135 #else
2136 rx_buffer->page_offset += truesize;
2137 #endif
2138 } else {
2139 memcpy(__skb_put(skb, size),
2140 xdp->data, ALIGN(size, sizeof(long)));
2141 rx_buffer->pagecnt_bias++;
2142 }
2143
2144 return skb;
2145 }
2146
ixgbe_build_skb(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,struct xdp_buff * xdp,union ixgbe_adv_rx_desc * rx_desc)2147 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2148 struct ixgbe_rx_buffer *rx_buffer,
2149 struct xdp_buff *xdp,
2150 union ixgbe_adv_rx_desc *rx_desc)
2151 {
2152 unsigned int metasize = xdp->data - xdp->data_meta;
2153 #if (PAGE_SIZE < 8192)
2154 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2155 #else
2156 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2157 SKB_DATA_ALIGN(xdp->data_end -
2158 xdp->data_hard_start);
2159 #endif
2160 struct sk_buff *skb;
2161
2162 /* Prefetch first cache line of first page. If xdp->data_meta
2163 * is unused, this points extactly as xdp->data, otherwise we
2164 * likely have a consumer accessing first few bytes of meta
2165 * data, and then actual data.
2166 */
2167 net_prefetch(xdp->data_meta);
2168
2169 /* build an skb to around the page buffer */
2170 skb = build_skb(xdp->data_hard_start, truesize);
2171 if (unlikely(!skb))
2172 return NULL;
2173
2174 /* update pointers within the skb to store the data */
2175 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2176 __skb_put(skb, xdp->data_end - xdp->data);
2177 if (metasize)
2178 skb_metadata_set(skb, metasize);
2179
2180 /* record DMA address if this is the start of a chain of buffers */
2181 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2182 IXGBE_CB(skb)->dma = rx_buffer->dma;
2183
2184 /* update buffer offset */
2185 #if (PAGE_SIZE < 8192)
2186 rx_buffer->page_offset ^= truesize;
2187 #else
2188 rx_buffer->page_offset += truesize;
2189 #endif
2190
2191 return skb;
2192 }
2193
ixgbe_run_xdp(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring,struct xdp_buff * xdp)2194 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter,
2195 struct ixgbe_ring *rx_ring,
2196 struct xdp_buff *xdp)
2197 {
2198 int err, result = IXGBE_XDP_PASS;
2199 struct bpf_prog *xdp_prog;
2200 struct xdp_frame *xdpf;
2201 u32 act;
2202
2203 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2204
2205 if (!xdp_prog)
2206 goto xdp_out;
2207
2208 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2209
2210 act = bpf_prog_run_xdp(xdp_prog, xdp);
2211 switch (act) {
2212 case XDP_PASS:
2213 break;
2214 case XDP_TX:
2215 xdpf = xdp_convert_buff_to_frame(xdp);
2216 if (unlikely(!xdpf))
2217 goto out_failure;
2218 result = ixgbe_xmit_xdp_ring(adapter, xdpf);
2219 if (result == IXGBE_XDP_CONSUMED)
2220 goto out_failure;
2221 break;
2222 case XDP_REDIRECT:
2223 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
2224 if (err)
2225 goto out_failure;
2226 result = IXGBE_XDP_REDIR;
2227 break;
2228 default:
2229 bpf_warn_invalid_xdp_action(act);
2230 fallthrough;
2231 case XDP_ABORTED:
2232 out_failure:
2233 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2234 fallthrough; /* handle aborts by dropping packet */
2235 case XDP_DROP:
2236 result = IXGBE_XDP_CONSUMED;
2237 break;
2238 }
2239 xdp_out:
2240 return ERR_PTR(-result);
2241 }
2242
ixgbe_rx_frame_truesize(struct ixgbe_ring * rx_ring,unsigned int size)2243 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring,
2244 unsigned int size)
2245 {
2246 unsigned int truesize;
2247
2248 #if (PAGE_SIZE < 8192)
2249 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
2250 #else
2251 truesize = rx_ring->rx_offset ?
2252 SKB_DATA_ALIGN(rx_ring->rx_offset + size) +
2253 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
2254 SKB_DATA_ALIGN(size);
2255 #endif
2256 return truesize;
2257 }
2258
ixgbe_rx_buffer_flip(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,unsigned int size)2259 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring,
2260 struct ixgbe_rx_buffer *rx_buffer,
2261 unsigned int size)
2262 {
2263 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size);
2264 #if (PAGE_SIZE < 8192)
2265 rx_buffer->page_offset ^= truesize;
2266 #else
2267 rx_buffer->page_offset += truesize;
2268 #endif
2269 }
2270
2271 /**
2272 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2273 * @q_vector: structure containing interrupt and ring information
2274 * @rx_ring: rx descriptor ring to transact packets on
2275 * @budget: Total limit on number of packets to process
2276 *
2277 * This function provides a "bounce buffer" approach to Rx interrupt
2278 * processing. The advantage to this is that on systems that have
2279 * expensive overhead for IOMMU access this provides a means of avoiding
2280 * it by maintaining the mapping of the page to the syste.
2281 *
2282 * Returns amount of work completed
2283 **/
ixgbe_clean_rx_irq(struct ixgbe_q_vector * q_vector,struct ixgbe_ring * rx_ring,const int budget)2284 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2285 struct ixgbe_ring *rx_ring,
2286 const int budget)
2287 {
2288 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0;
2289 struct ixgbe_adapter *adapter = q_vector->adapter;
2290 #ifdef IXGBE_FCOE
2291 int ddp_bytes;
2292 unsigned int mss = 0;
2293 #endif /* IXGBE_FCOE */
2294 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2295 unsigned int offset = rx_ring->rx_offset;
2296 unsigned int xdp_xmit = 0;
2297 struct xdp_buff xdp;
2298
2299 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
2300 #if (PAGE_SIZE < 8192)
2301 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0);
2302 #endif
2303 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
2304
2305 while (likely(total_rx_packets < budget)) {
2306 union ixgbe_adv_rx_desc *rx_desc;
2307 struct ixgbe_rx_buffer *rx_buffer;
2308 struct sk_buff *skb;
2309 int rx_buffer_pgcnt;
2310 unsigned int size;
2311
2312 /* return some buffers to hardware, one at a time is too slow */
2313 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2314 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2315 cleaned_count = 0;
2316 }
2317
2318 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2319 size = le16_to_cpu(rx_desc->wb.upper.length);
2320 if (!size)
2321 break;
2322
2323 /* This memory barrier is needed to keep us from reading
2324 * any other fields out of the rx_desc until we know the
2325 * descriptor has been written back
2326 */
2327 dma_rmb();
2328
2329 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt);
2330
2331 /* retrieve a buffer from the ring */
2332 if (!skb) {
2333 unsigned char *hard_start;
2334
2335 hard_start = page_address(rx_buffer->page) +
2336 rx_buffer->page_offset - offset;
2337 xdp_prepare_buff(&xdp, hard_start, offset, size, true);
2338 #if (PAGE_SIZE > 4096)
2339 /* At larger PAGE_SIZE, frame_sz depend on len size */
2340 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size);
2341 #endif
2342 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp);
2343 }
2344
2345 if (IS_ERR(skb)) {
2346 unsigned int xdp_res = -PTR_ERR(skb);
2347
2348 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) {
2349 xdp_xmit |= xdp_res;
2350 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size);
2351 } else {
2352 rx_buffer->pagecnt_bias++;
2353 }
2354 total_rx_packets++;
2355 total_rx_bytes += size;
2356 } else if (skb) {
2357 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
2358 } else if (ring_uses_build_skb(rx_ring)) {
2359 skb = ixgbe_build_skb(rx_ring, rx_buffer,
2360 &xdp, rx_desc);
2361 } else {
2362 skb = ixgbe_construct_skb(rx_ring, rx_buffer,
2363 &xdp, rx_desc);
2364 }
2365
2366 /* exit if we failed to retrieve a buffer */
2367 if (!skb) {
2368 rx_ring->rx_stats.alloc_rx_buff_failed++;
2369 rx_buffer->pagecnt_bias++;
2370 break;
2371 }
2372
2373 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
2374 cleaned_count++;
2375
2376 /* place incomplete frames back on ring for completion */
2377 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2378 continue;
2379
2380 /* verify the packet layout is correct */
2381 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2382 continue;
2383
2384 /* probably a little skewed due to removing CRC */
2385 total_rx_bytes += skb->len;
2386
2387 /* populate checksum, timestamp, VLAN, and protocol */
2388 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2389
2390 #ifdef IXGBE_FCOE
2391 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2392 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2393 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2394 /* include DDPed FCoE data */
2395 if (ddp_bytes > 0) {
2396 if (!mss) {
2397 mss = rx_ring->netdev->mtu -
2398 sizeof(struct fcoe_hdr) -
2399 sizeof(struct fc_frame_header) -
2400 sizeof(struct fcoe_crc_eof);
2401 if (mss > 512)
2402 mss &= ~511;
2403 }
2404 total_rx_bytes += ddp_bytes;
2405 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2406 mss);
2407 }
2408 if (!ddp_bytes) {
2409 dev_kfree_skb_any(skb);
2410 continue;
2411 }
2412 }
2413
2414 #endif /* IXGBE_FCOE */
2415 ixgbe_rx_skb(q_vector, skb);
2416
2417 /* update budget accounting */
2418 total_rx_packets++;
2419 }
2420
2421 if (xdp_xmit & IXGBE_XDP_REDIR)
2422 xdp_do_flush_map();
2423
2424 if (xdp_xmit & IXGBE_XDP_TX) {
2425 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
2426
2427 /* Force memory writes to complete before letting h/w
2428 * know there are new descriptors to fetch.
2429 */
2430 wmb();
2431 writel(ring->next_to_use, ring->tail);
2432 }
2433
2434 u64_stats_update_begin(&rx_ring->syncp);
2435 rx_ring->stats.packets += total_rx_packets;
2436 rx_ring->stats.bytes += total_rx_bytes;
2437 u64_stats_update_end(&rx_ring->syncp);
2438 q_vector->rx.total_packets += total_rx_packets;
2439 q_vector->rx.total_bytes += total_rx_bytes;
2440
2441 return total_rx_packets;
2442 }
2443
2444 /**
2445 * ixgbe_configure_msix - Configure MSI-X hardware
2446 * @adapter: board private structure
2447 *
2448 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2449 * interrupts.
2450 **/
ixgbe_configure_msix(struct ixgbe_adapter * adapter)2451 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2452 {
2453 struct ixgbe_q_vector *q_vector;
2454 int v_idx;
2455 u32 mask;
2456
2457 /* Populate MSIX to EITR Select */
2458 if (adapter->num_vfs > 32) {
2459 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
2460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2461 }
2462
2463 /*
2464 * Populate the IVAR table and set the ITR values to the
2465 * corresponding register.
2466 */
2467 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2468 struct ixgbe_ring *ring;
2469 q_vector = adapter->q_vector[v_idx];
2470
2471 ixgbe_for_each_ring(ring, q_vector->rx)
2472 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2473
2474 ixgbe_for_each_ring(ring, q_vector->tx)
2475 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2476
2477 ixgbe_write_eitr(q_vector);
2478 }
2479
2480 switch (adapter->hw.mac.type) {
2481 case ixgbe_mac_82598EB:
2482 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2483 v_idx);
2484 break;
2485 case ixgbe_mac_82599EB:
2486 case ixgbe_mac_X540:
2487 case ixgbe_mac_X550:
2488 case ixgbe_mac_X550EM_x:
2489 case ixgbe_mac_x550em_a:
2490 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2491 break;
2492 default:
2493 break;
2494 }
2495 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2496
2497 /* set up to autoclear timer, and the vectors */
2498 mask = IXGBE_EIMS_ENABLE_MASK;
2499 mask &= ~(IXGBE_EIMS_OTHER |
2500 IXGBE_EIMS_MAILBOX |
2501 IXGBE_EIMS_LSC);
2502
2503 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2504 }
2505
2506 /**
2507 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2508 * @q_vector: structure containing interrupt and ring information
2509 * @ring_container: structure containing ring performance data
2510 *
2511 * Stores a new ITR value based on packets and byte
2512 * counts during the last interrupt. The advantage of per interrupt
2513 * computation is faster updates and more accurate ITR for the current
2514 * traffic pattern. Constants in this function were computed
2515 * based on theoretical maximum wire speed and thresholds were set based
2516 * on testing data as well as attempting to minimize response time
2517 * while increasing bulk throughput.
2518 **/
ixgbe_update_itr(struct ixgbe_q_vector * q_vector,struct ixgbe_ring_container * ring_container)2519 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2520 struct ixgbe_ring_container *ring_container)
2521 {
2522 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS |
2523 IXGBE_ITR_ADAPTIVE_LATENCY;
2524 unsigned int avg_wire_size, packets, bytes;
2525 unsigned long next_update = jiffies;
2526
2527 /* If we don't have any rings just leave ourselves set for maximum
2528 * possible latency so we take ourselves out of the equation.
2529 */
2530 if (!ring_container->ring)
2531 return;
2532
2533 /* If we didn't update within up to 1 - 2 jiffies we can assume
2534 * that either packets are coming in so slow there hasn't been
2535 * any work, or that there is so much work that NAPI is dealing
2536 * with interrupt moderation and we don't need to do anything.
2537 */
2538 if (time_after(next_update, ring_container->next_update))
2539 goto clear_counts;
2540
2541 packets = ring_container->total_packets;
2542
2543 /* We have no packets to actually measure against. This means
2544 * either one of the other queues on this vector is active or
2545 * we are a Tx queue doing TSO with too high of an interrupt rate.
2546 *
2547 * When this occurs just tick up our delay by the minimum value
2548 * and hope that this extra delay will prevent us from being called
2549 * without any work on our queue.
2550 */
2551 if (!packets) {
2552 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2553 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2554 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2555 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY;
2556 goto clear_counts;
2557 }
2558
2559 bytes = ring_container->total_bytes;
2560
2561 /* If packets are less than 4 or bytes are less than 9000 assume
2562 * insufficient data to use bulk rate limiting approach. We are
2563 * likely latency driven.
2564 */
2565 if (packets < 4 && bytes < 9000) {
2566 itr = IXGBE_ITR_ADAPTIVE_LATENCY;
2567 goto adjust_by_size;
2568 }
2569
2570 /* Between 4 and 48 we can assume that our current interrupt delay
2571 * is only slightly too low. As such we should increase it by a small
2572 * fixed amount.
2573 */
2574 if (packets < 48) {
2575 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2576 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2577 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2578 goto clear_counts;
2579 }
2580
2581 /* Between 48 and 96 is our "goldilocks" zone where we are working
2582 * out "just right". Just report that our current ITR is good for us.
2583 */
2584 if (packets < 96) {
2585 itr = q_vector->itr >> 2;
2586 goto clear_counts;
2587 }
2588
2589 /* If packet count is 96 or greater we are likely looking at a slight
2590 * overrun of the delay we want. Try halving our delay to see if that
2591 * will cut the number of packets in half per interrupt.
2592 */
2593 if (packets < 256) {
2594 itr = q_vector->itr >> 3;
2595 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS)
2596 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS;
2597 goto clear_counts;
2598 }
2599
2600 /* The paths below assume we are dealing with a bulk ITR since number
2601 * of packets is 256 or greater. We are just going to have to compute
2602 * a value and try to bring the count under control, though for smaller
2603 * packet sizes there isn't much we can do as NAPI polling will likely
2604 * be kicking in sooner rather than later.
2605 */
2606 itr = IXGBE_ITR_ADAPTIVE_BULK;
2607
2608 adjust_by_size:
2609 /* If packet counts are 256 or greater we can assume we have a gross
2610 * overestimation of what the rate should be. Instead of trying to fine
2611 * tune it just use the formula below to try and dial in an exact value
2612 * give the current packet size of the frame.
2613 */
2614 avg_wire_size = bytes / packets;
2615
2616 /* The following is a crude approximation of:
2617 * wmem_default / (size + overhead) = desired_pkts_per_int
2618 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
2619 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
2620 *
2621 * Assuming wmem_default is 212992 and overhead is 640 bytes per
2622 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
2623 * formula down to
2624 *
2625 * (170 * (size + 24)) / (size + 640) = ITR
2626 *
2627 * We first do some math on the packet size and then finally bitshift
2628 * by 8 after rounding up. We also have to account for PCIe link speed
2629 * difference as ITR scales based on this.
2630 */
2631 if (avg_wire_size <= 60) {
2632 /* Start at 50k ints/sec */
2633 avg_wire_size = 5120;
2634 } else if (avg_wire_size <= 316) {
2635 /* 50K ints/sec to 16K ints/sec */
2636 avg_wire_size *= 40;
2637 avg_wire_size += 2720;
2638 } else if (avg_wire_size <= 1084) {
2639 /* 16K ints/sec to 9.2K ints/sec */
2640 avg_wire_size *= 15;
2641 avg_wire_size += 11452;
2642 } else if (avg_wire_size < 1968) {
2643 /* 9.2K ints/sec to 8K ints/sec */
2644 avg_wire_size *= 5;
2645 avg_wire_size += 22420;
2646 } else {
2647 /* plateau at a limit of 8K ints/sec */
2648 avg_wire_size = 32256;
2649 }
2650
2651 /* If we are in low latency mode half our delay which doubles the rate
2652 * to somewhere between 100K to 16K ints/sec
2653 */
2654 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY)
2655 avg_wire_size >>= 1;
2656
2657 /* Resultant value is 256 times larger than it needs to be. This
2658 * gives us room to adjust the value as needed to either increase
2659 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
2660 *
2661 * Use addition as we have already recorded the new latency flag
2662 * for the ITR value.
2663 */
2664 switch (q_vector->adapter->link_speed) {
2665 case IXGBE_LINK_SPEED_10GB_FULL:
2666 case IXGBE_LINK_SPEED_100_FULL:
2667 default:
2668 itr += DIV_ROUND_UP(avg_wire_size,
2669 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) *
2670 IXGBE_ITR_ADAPTIVE_MIN_INC;
2671 break;
2672 case IXGBE_LINK_SPEED_2_5GB_FULL:
2673 case IXGBE_LINK_SPEED_1GB_FULL:
2674 case IXGBE_LINK_SPEED_10_FULL:
2675 if (avg_wire_size > 8064)
2676 avg_wire_size = 8064;
2677 itr += DIV_ROUND_UP(avg_wire_size,
2678 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) *
2679 IXGBE_ITR_ADAPTIVE_MIN_INC;
2680 break;
2681 }
2682
2683 clear_counts:
2684 /* write back value */
2685 ring_container->itr = itr;
2686
2687 /* next update should occur within next jiffy */
2688 ring_container->next_update = next_update + 1;
2689
2690 ring_container->total_bytes = 0;
2691 ring_container->total_packets = 0;
2692 }
2693
2694 /**
2695 * ixgbe_write_eitr - write EITR register in hardware specific way
2696 * @q_vector: structure containing interrupt and ring information
2697 *
2698 * This function is made to be called by ethtool and by the driver
2699 * when it needs to update EITR registers at runtime. Hardware
2700 * specific quirks/differences are taken care of here.
2701 */
ixgbe_write_eitr(struct ixgbe_q_vector * q_vector)2702 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2703 {
2704 struct ixgbe_adapter *adapter = q_vector->adapter;
2705 struct ixgbe_hw *hw = &adapter->hw;
2706 int v_idx = q_vector->v_idx;
2707 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2708
2709 switch (adapter->hw.mac.type) {
2710 case ixgbe_mac_82598EB:
2711 /* must write high and low 16 bits to reset counter */
2712 itr_reg |= (itr_reg << 16);
2713 break;
2714 case ixgbe_mac_82599EB:
2715 case ixgbe_mac_X540:
2716 case ixgbe_mac_X550:
2717 case ixgbe_mac_X550EM_x:
2718 case ixgbe_mac_x550em_a:
2719 /*
2720 * set the WDIS bit to not clear the timer bits and cause an
2721 * immediate assertion of the interrupt
2722 */
2723 itr_reg |= IXGBE_EITR_CNT_WDIS;
2724 break;
2725 default:
2726 break;
2727 }
2728 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2729 }
2730
ixgbe_set_itr(struct ixgbe_q_vector * q_vector)2731 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2732 {
2733 u32 new_itr;
2734
2735 ixgbe_update_itr(q_vector, &q_vector->tx);
2736 ixgbe_update_itr(q_vector, &q_vector->rx);
2737
2738 /* use the smallest value of new ITR delay calculations */
2739 new_itr = min(q_vector->rx.itr, q_vector->tx.itr);
2740
2741 /* Clear latency flag if set, shift into correct position */
2742 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY;
2743 new_itr <<= 2;
2744
2745 if (new_itr != q_vector->itr) {
2746 /* save the algorithm value here */
2747 q_vector->itr = new_itr;
2748
2749 ixgbe_write_eitr(q_vector);
2750 }
2751 }
2752
2753 /**
2754 * ixgbe_check_overtemp_subtask - check for over temperature
2755 * @adapter: pointer to adapter
2756 **/
ixgbe_check_overtemp_subtask(struct ixgbe_adapter * adapter)2757 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2758 {
2759 struct ixgbe_hw *hw = &adapter->hw;
2760 u32 eicr = adapter->interrupt_event;
2761
2762 if (test_bit(__IXGBE_DOWN, &adapter->state))
2763 return;
2764
2765 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2766 return;
2767
2768 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2769
2770 switch (hw->device_id) {
2771 case IXGBE_DEV_ID_82599_T3_LOM:
2772 /*
2773 * Since the warning interrupt is for both ports
2774 * we don't have to check if:
2775 * - This interrupt wasn't for our port.
2776 * - We may have missed the interrupt so always have to
2777 * check if we got a LSC
2778 */
2779 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2780 !(eicr & IXGBE_EICR_LSC))
2781 return;
2782
2783 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2784 u32 speed;
2785 bool link_up = false;
2786
2787 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2788
2789 if (link_up)
2790 return;
2791 }
2792
2793 /* Check if this is not due to overtemp */
2794 if (!hw->phy.ops.check_overtemp(hw))
2795 return;
2796
2797 break;
2798 case IXGBE_DEV_ID_X550EM_A_1G_T:
2799 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2800 if (!hw->phy.ops.check_overtemp(hw))
2801 return;
2802 break;
2803 default:
2804 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2805 return;
2806 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2807 return;
2808 break;
2809 }
2810 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2811
2812 adapter->interrupt_event = 0;
2813 }
2814
ixgbe_check_fan_failure(struct ixgbe_adapter * adapter,u32 eicr)2815 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2816 {
2817 struct ixgbe_hw *hw = &adapter->hw;
2818
2819 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2820 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2821 e_crit(probe, "Fan has stopped, replace the adapter\n");
2822 /* write to clear the interrupt */
2823 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2824 }
2825 }
2826
ixgbe_check_overtemp_event(struct ixgbe_adapter * adapter,u32 eicr)2827 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2828 {
2829 struct ixgbe_hw *hw = &adapter->hw;
2830
2831 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2832 return;
2833
2834 switch (adapter->hw.mac.type) {
2835 case ixgbe_mac_82599EB:
2836 /*
2837 * Need to check link state so complete overtemp check
2838 * on service task
2839 */
2840 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2841 (eicr & IXGBE_EICR_LSC)) &&
2842 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2843 adapter->interrupt_event = eicr;
2844 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2845 ixgbe_service_event_schedule(adapter);
2846 return;
2847 }
2848 return;
2849 case ixgbe_mac_x550em_a:
2850 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2851 adapter->interrupt_event = eicr;
2852 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2853 ixgbe_service_event_schedule(adapter);
2854 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2855 IXGBE_EICR_GPI_SDP0_X550EM_a);
2856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2857 IXGBE_EICR_GPI_SDP0_X550EM_a);
2858 }
2859 return;
2860 case ixgbe_mac_X550:
2861 case ixgbe_mac_X540:
2862 if (!(eicr & IXGBE_EICR_TS))
2863 return;
2864 break;
2865 default:
2866 return;
2867 }
2868
2869 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2870 }
2871
ixgbe_is_sfp(struct ixgbe_hw * hw)2872 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2873 {
2874 switch (hw->mac.type) {
2875 case ixgbe_mac_82598EB:
2876 if (hw->phy.type == ixgbe_phy_nl)
2877 return true;
2878 return false;
2879 case ixgbe_mac_82599EB:
2880 case ixgbe_mac_X550EM_x:
2881 case ixgbe_mac_x550em_a:
2882 switch (hw->mac.ops.get_media_type(hw)) {
2883 case ixgbe_media_type_fiber:
2884 case ixgbe_media_type_fiber_qsfp:
2885 return true;
2886 default:
2887 return false;
2888 }
2889 default:
2890 return false;
2891 }
2892 }
2893
ixgbe_check_sfp_event(struct ixgbe_adapter * adapter,u32 eicr)2894 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2895 {
2896 struct ixgbe_hw *hw = &adapter->hw;
2897 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2898
2899 if (!ixgbe_is_sfp(hw))
2900 return;
2901
2902 /* Later MAC's use different SDP */
2903 if (hw->mac.type >= ixgbe_mac_X540)
2904 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2905
2906 if (eicr & eicr_mask) {
2907 /* Clear the interrupt */
2908 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2909 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2910 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2911 adapter->sfp_poll_time = 0;
2912 ixgbe_service_event_schedule(adapter);
2913 }
2914 }
2915
2916 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2917 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2918 /* Clear the interrupt */
2919 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2920 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2921 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2922 ixgbe_service_event_schedule(adapter);
2923 }
2924 }
2925 }
2926
ixgbe_check_lsc(struct ixgbe_adapter * adapter)2927 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2928 {
2929 struct ixgbe_hw *hw = &adapter->hw;
2930
2931 adapter->lsc_int++;
2932 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2933 adapter->link_check_timeout = jiffies;
2934 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2935 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2936 IXGBE_WRITE_FLUSH(hw);
2937 ixgbe_service_event_schedule(adapter);
2938 }
2939 }
2940
ixgbe_irq_enable_queues(struct ixgbe_adapter * adapter,u64 qmask)2941 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2942 u64 qmask)
2943 {
2944 u32 mask;
2945 struct ixgbe_hw *hw = &adapter->hw;
2946
2947 switch (hw->mac.type) {
2948 case ixgbe_mac_82598EB:
2949 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2950 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2951 break;
2952 case ixgbe_mac_82599EB:
2953 case ixgbe_mac_X540:
2954 case ixgbe_mac_X550:
2955 case ixgbe_mac_X550EM_x:
2956 case ixgbe_mac_x550em_a:
2957 mask = (qmask & 0xFFFFFFFF);
2958 if (mask)
2959 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2960 mask = (qmask >> 32);
2961 if (mask)
2962 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2963 break;
2964 default:
2965 break;
2966 }
2967 /* skip the flush */
2968 }
2969
2970 /**
2971 * ixgbe_irq_enable - Enable default interrupt generation settings
2972 * @adapter: board private structure
2973 * @queues: enable irqs for queues
2974 * @flush: flush register write
2975 **/
ixgbe_irq_enable(struct ixgbe_adapter * adapter,bool queues,bool flush)2976 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2977 bool flush)
2978 {
2979 struct ixgbe_hw *hw = &adapter->hw;
2980 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2981
2982 /* don't reenable LSC while waiting for link */
2983 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2984 mask &= ~IXGBE_EIMS_LSC;
2985
2986 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2987 switch (adapter->hw.mac.type) {
2988 case ixgbe_mac_82599EB:
2989 mask |= IXGBE_EIMS_GPI_SDP0(hw);
2990 break;
2991 case ixgbe_mac_X540:
2992 case ixgbe_mac_X550:
2993 case ixgbe_mac_X550EM_x:
2994 case ixgbe_mac_x550em_a:
2995 mask |= IXGBE_EIMS_TS;
2996 break;
2997 default:
2998 break;
2999 }
3000 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3001 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3002 switch (adapter->hw.mac.type) {
3003 case ixgbe_mac_82599EB:
3004 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3005 mask |= IXGBE_EIMS_GPI_SDP2(hw);
3006 fallthrough;
3007 case ixgbe_mac_X540:
3008 case ixgbe_mac_X550:
3009 case ixgbe_mac_X550EM_x:
3010 case ixgbe_mac_x550em_a:
3011 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
3012 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
3013 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
3014 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
3015 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
3016 mask |= IXGBE_EICR_GPI_SDP0_X540;
3017 mask |= IXGBE_EIMS_ECC;
3018 mask |= IXGBE_EIMS_MAILBOX;
3019 break;
3020 default:
3021 break;
3022 }
3023
3024 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
3025 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
3026 mask |= IXGBE_EIMS_FLOW_DIR;
3027
3028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
3029 if (queues)
3030 ixgbe_irq_enable_queues(adapter, ~0);
3031 if (flush)
3032 IXGBE_WRITE_FLUSH(&adapter->hw);
3033 }
3034
ixgbe_msix_other(int irq,void * data)3035 static irqreturn_t ixgbe_msix_other(int irq, void *data)
3036 {
3037 struct ixgbe_adapter *adapter = data;
3038 struct ixgbe_hw *hw = &adapter->hw;
3039 u32 eicr;
3040
3041 /*
3042 * Workaround for Silicon errata. Use clear-by-write instead
3043 * of clear-by-read. Reading with EICS will return the
3044 * interrupt causes without clearing, which later be done
3045 * with the write to EICR.
3046 */
3047 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3048
3049 /* The lower 16bits of the EICR register are for the queue interrupts
3050 * which should be masked here in order to not accidentally clear them if
3051 * the bits are high when ixgbe_msix_other is called. There is a race
3052 * condition otherwise which results in possible performance loss
3053 * especially if the ixgbe_msix_other interrupt is triggering
3054 * consistently (as it would when PPS is turned on for the X540 device)
3055 */
3056 eicr &= 0xFFFF0000;
3057
3058 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3059
3060 if (eicr & IXGBE_EICR_LSC)
3061 ixgbe_check_lsc(adapter);
3062
3063 if (eicr & IXGBE_EICR_MAILBOX)
3064 ixgbe_msg_task(adapter);
3065
3066 switch (hw->mac.type) {
3067 case ixgbe_mac_82599EB:
3068 case ixgbe_mac_X540:
3069 case ixgbe_mac_X550:
3070 case ixgbe_mac_X550EM_x:
3071 case ixgbe_mac_x550em_a:
3072 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
3073 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3074 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
3075 ixgbe_service_event_schedule(adapter);
3076 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3077 IXGBE_EICR_GPI_SDP0_X540);
3078 }
3079 if (eicr & IXGBE_EICR_ECC) {
3080 e_info(link, "Received ECC Err, initiating reset\n");
3081 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3082 ixgbe_service_event_schedule(adapter);
3083 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3084 }
3085 /* Handle Flow Director Full threshold interrupt */
3086 if (eicr & IXGBE_EICR_FLOW_DIR) {
3087 int reinit_count = 0;
3088 int i;
3089 for (i = 0; i < adapter->num_tx_queues; i++) {
3090 struct ixgbe_ring *ring = adapter->tx_ring[i];
3091 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
3092 &ring->state))
3093 reinit_count++;
3094 }
3095 if (reinit_count) {
3096 /* no more flow director interrupts until after init */
3097 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
3098 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
3099 ixgbe_service_event_schedule(adapter);
3100 }
3101 }
3102 ixgbe_check_sfp_event(adapter, eicr);
3103 ixgbe_check_overtemp_event(adapter, eicr);
3104 break;
3105 default:
3106 break;
3107 }
3108
3109 ixgbe_check_fan_failure(adapter, eicr);
3110
3111 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3112 ixgbe_ptp_check_pps_event(adapter);
3113
3114 /* re-enable the original interrupt state, no lsc, no queues */
3115 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3116 ixgbe_irq_enable(adapter, false, false);
3117
3118 return IRQ_HANDLED;
3119 }
3120
ixgbe_msix_clean_rings(int irq,void * data)3121 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
3122 {
3123 struct ixgbe_q_vector *q_vector = data;
3124
3125 /* EIAM disabled interrupts (on this vector) for us */
3126
3127 if (q_vector->rx.ring || q_vector->tx.ring)
3128 napi_schedule_irqoff(&q_vector->napi);
3129
3130 return IRQ_HANDLED;
3131 }
3132
3133 /**
3134 * ixgbe_poll - NAPI Rx polling callback
3135 * @napi: structure for representing this polling device
3136 * @budget: how many packets driver is allowed to clean
3137 *
3138 * This function is used for legacy and MSI, NAPI mode
3139 **/
ixgbe_poll(struct napi_struct * napi,int budget)3140 int ixgbe_poll(struct napi_struct *napi, int budget)
3141 {
3142 struct ixgbe_q_vector *q_vector =
3143 container_of(napi, struct ixgbe_q_vector, napi);
3144 struct ixgbe_adapter *adapter = q_vector->adapter;
3145 struct ixgbe_ring *ring;
3146 int per_ring_budget, work_done = 0;
3147 bool clean_complete = true;
3148
3149 #ifdef CONFIG_IXGBE_DCA
3150 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3151 ixgbe_update_dca(q_vector);
3152 #endif
3153
3154 ixgbe_for_each_ring(ring, q_vector->tx) {
3155 bool wd = ring->xsk_pool ?
3156 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) :
3157 ixgbe_clean_tx_irq(q_vector, ring, budget);
3158
3159 if (!wd)
3160 clean_complete = false;
3161 }
3162
3163 /* Exit if we are called by netpoll */
3164 if (budget <= 0)
3165 return budget;
3166
3167 /* attempt to distribute budget to each queue fairly, but don't allow
3168 * the budget to go below 1 because we'll exit polling */
3169 if (q_vector->rx.count > 1)
3170 per_ring_budget = max(budget/q_vector->rx.count, 1);
3171 else
3172 per_ring_budget = budget;
3173
3174 ixgbe_for_each_ring(ring, q_vector->rx) {
3175 int cleaned = ring->xsk_pool ?
3176 ixgbe_clean_rx_irq_zc(q_vector, ring,
3177 per_ring_budget) :
3178 ixgbe_clean_rx_irq(q_vector, ring,
3179 per_ring_budget);
3180
3181 work_done += cleaned;
3182 if (cleaned >= per_ring_budget)
3183 clean_complete = false;
3184 }
3185
3186 /* If all work not completed, return budget and keep polling */
3187 if (!clean_complete)
3188 return budget;
3189
3190 /* all work done, exit the polling mode */
3191 if (likely(napi_complete_done(napi, work_done))) {
3192 if (adapter->rx_itr_setting & 1)
3193 ixgbe_set_itr(q_vector);
3194 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3195 ixgbe_irq_enable_queues(adapter,
3196 BIT_ULL(q_vector->v_idx));
3197 }
3198
3199 return min(work_done, budget - 1);
3200 }
3201
3202 /**
3203 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
3204 * @adapter: board private structure
3205 *
3206 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
3207 * interrupts from the kernel.
3208 **/
ixgbe_request_msix_irqs(struct ixgbe_adapter * adapter)3209 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
3210 {
3211 struct net_device *netdev = adapter->netdev;
3212 unsigned int ri = 0, ti = 0;
3213 int vector, err;
3214
3215 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3216 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3217 struct msix_entry *entry = &adapter->msix_entries[vector];
3218
3219 if (q_vector->tx.ring && q_vector->rx.ring) {
3220 snprintf(q_vector->name, sizeof(q_vector->name),
3221 "%s-TxRx-%u", netdev->name, ri++);
3222 ti++;
3223 } else if (q_vector->rx.ring) {
3224 snprintf(q_vector->name, sizeof(q_vector->name),
3225 "%s-rx-%u", netdev->name, ri++);
3226 } else if (q_vector->tx.ring) {
3227 snprintf(q_vector->name, sizeof(q_vector->name),
3228 "%s-tx-%u", netdev->name, ti++);
3229 } else {
3230 /* skip this unused q_vector */
3231 continue;
3232 }
3233 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3234 q_vector->name, q_vector);
3235 if (err) {
3236 e_err(probe, "request_irq failed for MSIX interrupt "
3237 "Error: %d\n", err);
3238 goto free_queue_irqs;
3239 }
3240 /* If Flow Director is enabled, set interrupt affinity */
3241 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3242 /* assign the mask for this irq */
3243 irq_set_affinity_hint(entry->vector,
3244 &q_vector->affinity_mask);
3245 }
3246 }
3247
3248 err = request_irq(adapter->msix_entries[vector].vector,
3249 ixgbe_msix_other, 0, netdev->name, adapter);
3250 if (err) {
3251 e_err(probe, "request_irq for msix_other failed: %d\n", err);
3252 goto free_queue_irqs;
3253 }
3254
3255 return 0;
3256
3257 free_queue_irqs:
3258 while (vector) {
3259 vector--;
3260 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
3261 NULL);
3262 free_irq(adapter->msix_entries[vector].vector,
3263 adapter->q_vector[vector]);
3264 }
3265 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3266 pci_disable_msix(adapter->pdev);
3267 kfree(adapter->msix_entries);
3268 adapter->msix_entries = NULL;
3269 return err;
3270 }
3271
3272 /**
3273 * ixgbe_intr - legacy mode Interrupt Handler
3274 * @irq: interrupt number
3275 * @data: pointer to a network interface device structure
3276 **/
ixgbe_intr(int irq,void * data)3277 static irqreturn_t ixgbe_intr(int irq, void *data)
3278 {
3279 struct ixgbe_adapter *adapter = data;
3280 struct ixgbe_hw *hw = &adapter->hw;
3281 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3282 u32 eicr;
3283
3284 /*
3285 * Workaround for silicon errata #26 on 82598. Mask the interrupt
3286 * before the read of EICR.
3287 */
3288 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3289
3290 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
3291 * therefore no explicit interrupt disable is necessary */
3292 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3293 if (!eicr) {
3294 /*
3295 * shared interrupt alert!
3296 * make sure interrupts are enabled because the read will
3297 * have disabled interrupts due to EIAM
3298 * finish the workaround of silicon errata on 82598. Unmask
3299 * the interrupt that we masked before the EICR read.
3300 */
3301 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3302 ixgbe_irq_enable(adapter, true, true);
3303 return IRQ_NONE; /* Not our interrupt */
3304 }
3305
3306 if (eicr & IXGBE_EICR_LSC)
3307 ixgbe_check_lsc(adapter);
3308
3309 switch (hw->mac.type) {
3310 case ixgbe_mac_82599EB:
3311 ixgbe_check_sfp_event(adapter, eicr);
3312 fallthrough;
3313 case ixgbe_mac_X540:
3314 case ixgbe_mac_X550:
3315 case ixgbe_mac_X550EM_x:
3316 case ixgbe_mac_x550em_a:
3317 if (eicr & IXGBE_EICR_ECC) {
3318 e_info(link, "Received ECC Err, initiating reset\n");
3319 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3320 ixgbe_service_event_schedule(adapter);
3321 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3322 }
3323 ixgbe_check_overtemp_event(adapter, eicr);
3324 break;
3325 default:
3326 break;
3327 }
3328
3329 ixgbe_check_fan_failure(adapter, eicr);
3330 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3331 ixgbe_ptp_check_pps_event(adapter);
3332
3333 /* would disable interrupts here but EIAM disabled it */
3334 napi_schedule_irqoff(&q_vector->napi);
3335
3336 /*
3337 * re-enable link(maybe) and non-queue interrupts, no flush.
3338 * ixgbe_poll will re-enable the queue interrupts
3339 */
3340 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3341 ixgbe_irq_enable(adapter, false, false);
3342
3343 return IRQ_HANDLED;
3344 }
3345
3346 /**
3347 * ixgbe_request_irq - initialize interrupts
3348 * @adapter: board private structure
3349 *
3350 * Attempts to configure interrupts using the best available
3351 * capabilities of the hardware and kernel.
3352 **/
ixgbe_request_irq(struct ixgbe_adapter * adapter)3353 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
3354 {
3355 struct net_device *netdev = adapter->netdev;
3356 int err;
3357
3358 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3359 err = ixgbe_request_msix_irqs(adapter);
3360 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3361 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3362 netdev->name, adapter);
3363 else
3364 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3365 netdev->name, adapter);
3366
3367 if (err)
3368 e_err(probe, "request_irq failed, Error %d\n", err);
3369
3370 return err;
3371 }
3372
ixgbe_free_irq(struct ixgbe_adapter * adapter)3373 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3374 {
3375 int vector;
3376
3377 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3378 free_irq(adapter->pdev->irq, adapter);
3379 return;
3380 }
3381
3382 if (!adapter->msix_entries)
3383 return;
3384
3385 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3386 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3387 struct msix_entry *entry = &adapter->msix_entries[vector];
3388
3389 /* free only the irqs that were actually requested */
3390 if (!q_vector->rx.ring && !q_vector->tx.ring)
3391 continue;
3392
3393 /* clear the affinity_mask in the IRQ descriptor */
3394 irq_set_affinity_hint(entry->vector, NULL);
3395
3396 free_irq(entry->vector, q_vector);
3397 }
3398
3399 free_irq(adapter->msix_entries[vector].vector, adapter);
3400 }
3401
3402 /**
3403 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3404 * @adapter: board private structure
3405 **/
ixgbe_irq_disable(struct ixgbe_adapter * adapter)3406 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3407 {
3408 switch (adapter->hw.mac.type) {
3409 case ixgbe_mac_82598EB:
3410 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3411 break;
3412 case ixgbe_mac_82599EB:
3413 case ixgbe_mac_X540:
3414 case ixgbe_mac_X550:
3415 case ixgbe_mac_X550EM_x:
3416 case ixgbe_mac_x550em_a:
3417 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3418 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3419 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3420 break;
3421 default:
3422 break;
3423 }
3424 IXGBE_WRITE_FLUSH(&adapter->hw);
3425 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3426 int vector;
3427
3428 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3429 synchronize_irq(adapter->msix_entries[vector].vector);
3430
3431 synchronize_irq(adapter->msix_entries[vector++].vector);
3432 } else {
3433 synchronize_irq(adapter->pdev->irq);
3434 }
3435 }
3436
3437 /**
3438 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3439 * @adapter: board private structure
3440 *
3441 **/
ixgbe_configure_msi_and_legacy(struct ixgbe_adapter * adapter)3442 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3443 {
3444 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3445
3446 ixgbe_write_eitr(q_vector);
3447
3448 ixgbe_set_ivar(adapter, 0, 0, 0);
3449 ixgbe_set_ivar(adapter, 1, 0, 0);
3450
3451 e_info(hw, "Legacy interrupt IVAR setup done\n");
3452 }
3453
3454 /**
3455 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3456 * @adapter: board private structure
3457 * @ring: structure containing ring specific data
3458 *
3459 * Configure the Tx descriptor ring after a reset.
3460 **/
ixgbe_configure_tx_ring(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)3461 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3462 struct ixgbe_ring *ring)
3463 {
3464 struct ixgbe_hw *hw = &adapter->hw;
3465 u64 tdba = ring->dma;
3466 int wait_loop = 10;
3467 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3468 u8 reg_idx = ring->reg_idx;
3469
3470 ring->xsk_pool = NULL;
3471 if (ring_is_xdp(ring))
3472 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
3473
3474 /* disable queue to avoid issues while updating state */
3475 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3476 IXGBE_WRITE_FLUSH(hw);
3477
3478 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3479 (tdba & DMA_BIT_MASK(32)));
3480 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3481 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3482 ring->count * sizeof(union ixgbe_adv_tx_desc));
3483 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3484 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3485 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3486
3487 /*
3488 * set WTHRESH to encourage burst writeback, it should not be set
3489 * higher than 1 when:
3490 * - ITR is 0 as it could cause false TX hangs
3491 * - ITR is set to > 100k int/sec and BQL is enabled
3492 *
3493 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3494 * to or less than the number of on chip descriptors, which is
3495 * currently 40.
3496 */
3497 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3498 txdctl |= 1u << 16; /* WTHRESH = 1 */
3499 else
3500 txdctl |= 8u << 16; /* WTHRESH = 8 */
3501
3502 /*
3503 * Setting PTHRESH to 32 both improves performance
3504 * and avoids a TX hang with DFP enabled
3505 */
3506 txdctl |= (1u << 8) | /* HTHRESH = 1 */
3507 32; /* PTHRESH = 32 */
3508
3509 /* reinitialize flowdirector state */
3510 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3511 ring->atr_sample_rate = adapter->atr_sample_rate;
3512 ring->atr_count = 0;
3513 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3514 } else {
3515 ring->atr_sample_rate = 0;
3516 }
3517
3518 /* initialize XPS */
3519 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3520 struct ixgbe_q_vector *q_vector = ring->q_vector;
3521
3522 if (q_vector)
3523 netif_set_xps_queue(ring->netdev,
3524 &q_vector->affinity_mask,
3525 ring->queue_index);
3526 }
3527
3528 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3529
3530 /* reinitialize tx_buffer_info */
3531 memset(ring->tx_buffer_info, 0,
3532 sizeof(struct ixgbe_tx_buffer) * ring->count);
3533
3534 /* enable queue */
3535 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3536
3537 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3538 if (hw->mac.type == ixgbe_mac_82598EB &&
3539 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3540 return;
3541
3542 /* poll to verify queue is enabled */
3543 do {
3544 usleep_range(1000, 2000);
3545 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3546 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3547 if (!wait_loop)
3548 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
3549 }
3550
ixgbe_setup_mtqc(struct ixgbe_adapter * adapter)3551 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3552 {
3553 struct ixgbe_hw *hw = &adapter->hw;
3554 u32 rttdcs, mtqc;
3555 u8 tcs = adapter->hw_tcs;
3556
3557 if (hw->mac.type == ixgbe_mac_82598EB)
3558 return;
3559
3560 /* disable the arbiter while setting MTQC */
3561 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3562 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3563 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3564
3565 /* set transmit pool layout */
3566 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3567 mtqc = IXGBE_MTQC_VT_ENA;
3568 if (tcs > 4)
3569 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3570 else if (tcs > 1)
3571 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3572 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3573 IXGBE_82599_VMDQ_4Q_MASK)
3574 mtqc |= IXGBE_MTQC_32VF;
3575 else
3576 mtqc |= IXGBE_MTQC_64VF;
3577 } else {
3578 if (tcs > 4) {
3579 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3580 } else if (tcs > 1) {
3581 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3582 } else {
3583 u8 max_txq = adapter->num_tx_queues +
3584 adapter->num_xdp_queues;
3585 if (max_txq > 63)
3586 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3587 else
3588 mtqc = IXGBE_MTQC_64Q_1PB;
3589 }
3590 }
3591
3592 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3593
3594 /* Enable Security TX Buffer IFG for multiple pb */
3595 if (tcs) {
3596 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3597 sectx |= IXGBE_SECTX_DCB;
3598 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3599 }
3600
3601 /* re-enable the arbiter */
3602 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3603 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3604 }
3605
3606 /**
3607 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3608 * @adapter: board private structure
3609 *
3610 * Configure the Tx unit of the MAC after a reset.
3611 **/
ixgbe_configure_tx(struct ixgbe_adapter * adapter)3612 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3613 {
3614 struct ixgbe_hw *hw = &adapter->hw;
3615 u32 dmatxctl;
3616 u32 i;
3617
3618 ixgbe_setup_mtqc(adapter);
3619
3620 if (hw->mac.type != ixgbe_mac_82598EB) {
3621 /* DMATXCTL.EN must be before Tx queues are enabled */
3622 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3623 dmatxctl |= IXGBE_DMATXCTL_TE;
3624 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3625 }
3626
3627 /* Setup the HW Tx Head and Tail descriptor pointers */
3628 for (i = 0; i < adapter->num_tx_queues; i++)
3629 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3630 for (i = 0; i < adapter->num_xdp_queues; i++)
3631 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]);
3632 }
3633
ixgbe_enable_rx_drop(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)3634 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3635 struct ixgbe_ring *ring)
3636 {
3637 struct ixgbe_hw *hw = &adapter->hw;
3638 u8 reg_idx = ring->reg_idx;
3639 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3640
3641 srrctl |= IXGBE_SRRCTL_DROP_EN;
3642
3643 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3644 }
3645
ixgbe_disable_rx_drop(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)3646 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3647 struct ixgbe_ring *ring)
3648 {
3649 struct ixgbe_hw *hw = &adapter->hw;
3650 u8 reg_idx = ring->reg_idx;
3651 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3652
3653 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3654
3655 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3656 }
3657
3658 #ifdef CONFIG_IXGBE_DCB
ixgbe_set_rx_drop_en(struct ixgbe_adapter * adapter)3659 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3660 #else
3661 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3662 #endif
3663 {
3664 int i;
3665 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3666
3667 if (adapter->ixgbe_ieee_pfc)
3668 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3669
3670 /*
3671 * We should set the drop enable bit if:
3672 * SR-IOV is enabled
3673 * or
3674 * Number of Rx queues > 1 and flow control is disabled
3675 *
3676 * This allows us to avoid head of line blocking for security
3677 * and performance reasons.
3678 */
3679 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3680 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3681 for (i = 0; i < adapter->num_rx_queues; i++)
3682 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3683 } else {
3684 for (i = 0; i < adapter->num_rx_queues; i++)
3685 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3686 }
3687 }
3688
3689 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3690
ixgbe_configure_srrctl(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring)3691 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3692 struct ixgbe_ring *rx_ring)
3693 {
3694 struct ixgbe_hw *hw = &adapter->hw;
3695 u32 srrctl;
3696 u8 reg_idx = rx_ring->reg_idx;
3697
3698 if (hw->mac.type == ixgbe_mac_82598EB) {
3699 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3700
3701 /*
3702 * if VMDq is not active we must program one srrctl register
3703 * per RSS queue since we have enabled RDRXCTL.MVMEN
3704 */
3705 reg_idx &= mask;
3706 }
3707
3708 /* configure header buffer length, needed for RSC */
3709 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3710
3711 /* configure the packet buffer length */
3712 if (rx_ring->xsk_pool) {
3713 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool);
3714
3715 /* If the MAC support setting RXDCTL.RLPML, the
3716 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and
3717 * RXDCTL.RLPML is set to the actual UMEM buffer
3718 * size. If not, then we are stuck with a 1k buffer
3719 * size resolution. In this case frames larger than
3720 * the UMEM buffer size viewed in a 1k resolution will
3721 * be dropped.
3722 */
3723 if (hw->mac.type != ixgbe_mac_82599EB)
3724 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3725 else
3726 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3727 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) {
3728 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3729 } else {
3730 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3731 }
3732
3733 /* configure descriptor type */
3734 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3735
3736 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3737 }
3738
3739 /**
3740 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3741 * @adapter: device handle
3742 *
3743 * - 82598/82599/X540: 128
3744 * - X550(non-SRIOV mode): 512
3745 * - X550(SRIOV mode): 64
3746 */
ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter * adapter)3747 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3748 {
3749 if (adapter->hw.mac.type < ixgbe_mac_X550)
3750 return 128;
3751 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3752 return 64;
3753 else
3754 return 512;
3755 }
3756
3757 /**
3758 * ixgbe_store_key - Write the RSS key to HW
3759 * @adapter: device handle
3760 *
3761 * Write the RSS key stored in adapter.rss_key to HW.
3762 */
ixgbe_store_key(struct ixgbe_adapter * adapter)3763 void ixgbe_store_key(struct ixgbe_adapter *adapter)
3764 {
3765 struct ixgbe_hw *hw = &adapter->hw;
3766 int i;
3767
3768 for (i = 0; i < 10; i++)
3769 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3770 }
3771
3772 /**
3773 * ixgbe_init_rss_key - Initialize adapter RSS key
3774 * @adapter: device handle
3775 *
3776 * Allocates and initializes the RSS key if it is not allocated.
3777 **/
ixgbe_init_rss_key(struct ixgbe_adapter * adapter)3778 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter)
3779 {
3780 u32 *rss_key;
3781
3782 if (!adapter->rss_key) {
3783 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL);
3784 if (unlikely(!rss_key))
3785 return -ENOMEM;
3786
3787 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE);
3788 adapter->rss_key = rss_key;
3789 }
3790
3791 return 0;
3792 }
3793
3794 /**
3795 * ixgbe_store_reta - Write the RETA table to HW
3796 * @adapter: device handle
3797 *
3798 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3799 */
ixgbe_store_reta(struct ixgbe_adapter * adapter)3800 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3801 {
3802 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3803 struct ixgbe_hw *hw = &adapter->hw;
3804 u32 reta = 0;
3805 u32 indices_multi;
3806 u8 *indir_tbl = adapter->rss_indir_tbl;
3807
3808 /* Fill out the redirection table as follows:
3809 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3810 * indices.
3811 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3812 * - X550: 8 bit wide entries containing 6 bit RSS index
3813 */
3814 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3815 indices_multi = 0x11;
3816 else
3817 indices_multi = 0x1;
3818
3819 /* Write redirection table to HW */
3820 for (i = 0; i < reta_entries; i++) {
3821 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3822 if ((i & 3) == 3) {
3823 if (i < 128)
3824 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3825 else
3826 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3827 reta);
3828 reta = 0;
3829 }
3830 }
3831 }
3832
3833 /**
3834 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3835 * @adapter: device handle
3836 *
3837 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3838 */
ixgbe_store_vfreta(struct ixgbe_adapter * adapter)3839 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3840 {
3841 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3842 struct ixgbe_hw *hw = &adapter->hw;
3843 u32 vfreta = 0;
3844
3845 /* Write redirection table to HW */
3846 for (i = 0; i < reta_entries; i++) {
3847 u16 pool = adapter->num_rx_pools;
3848
3849 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3850 if ((i & 3) != 3)
3851 continue;
3852
3853 while (pool--)
3854 IXGBE_WRITE_REG(hw,
3855 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)),
3856 vfreta);
3857 vfreta = 0;
3858 }
3859 }
3860
ixgbe_setup_reta(struct ixgbe_adapter * adapter)3861 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3862 {
3863 u32 i, j;
3864 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3865 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3866
3867 /* Program table for at least 4 queues w/ SR-IOV so that VFs can
3868 * make full use of any rings they may have. We will use the
3869 * PSRTYPE register to control how many rings we use within the PF.
3870 */
3871 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3872 rss_i = 4;
3873
3874 /* Fill out hash function seeds */
3875 ixgbe_store_key(adapter);
3876
3877 /* Fill out redirection table */
3878 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3879
3880 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3881 if (j == rss_i)
3882 j = 0;
3883
3884 adapter->rss_indir_tbl[i] = j;
3885 }
3886
3887 ixgbe_store_reta(adapter);
3888 }
3889
ixgbe_setup_vfreta(struct ixgbe_adapter * adapter)3890 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3891 {
3892 struct ixgbe_hw *hw = &adapter->hw;
3893 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3894 int i, j;
3895
3896 /* Fill out hash function seeds */
3897 for (i = 0; i < 10; i++) {
3898 u16 pool = adapter->num_rx_pools;
3899
3900 while (pool--)
3901 IXGBE_WRITE_REG(hw,
3902 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)),
3903 *(adapter->rss_key + i));
3904 }
3905
3906 /* Fill out the redirection table */
3907 for (i = 0, j = 0; i < 64; i++, j++) {
3908 if (j == rss_i)
3909 j = 0;
3910
3911 adapter->rss_indir_tbl[i] = j;
3912 }
3913
3914 ixgbe_store_vfreta(adapter);
3915 }
3916
ixgbe_setup_mrqc(struct ixgbe_adapter * adapter)3917 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3918 {
3919 struct ixgbe_hw *hw = &adapter->hw;
3920 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3921 u32 rxcsum;
3922
3923 /* Disable indicating checksum in descriptor, enables RSS hash */
3924 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3925 rxcsum |= IXGBE_RXCSUM_PCSD;
3926 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3927
3928 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3929 if (adapter->ring_feature[RING_F_RSS].mask)
3930 mrqc = IXGBE_MRQC_RSSEN;
3931 } else {
3932 u8 tcs = adapter->hw_tcs;
3933
3934 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3935 if (tcs > 4)
3936 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3937 else if (tcs > 1)
3938 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3939 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3940 IXGBE_82599_VMDQ_4Q_MASK)
3941 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3942 else
3943 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3944
3945 /* Enable L3/L4 for Tx Switched packets only for X550,
3946 * older devices do not support this feature
3947 */
3948 if (hw->mac.type >= ixgbe_mac_X550)
3949 mrqc |= IXGBE_MRQC_L3L4TXSWEN;
3950 } else {
3951 if (tcs > 4)
3952 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3953 else if (tcs > 1)
3954 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3955 else
3956 mrqc = IXGBE_MRQC_RSSEN;
3957 }
3958 }
3959
3960 /* Perform hash on these packet types */
3961 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3962 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3963 IXGBE_MRQC_RSS_FIELD_IPV6 |
3964 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3965
3966 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3967 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3968 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3969 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3970
3971 if ((hw->mac.type >= ixgbe_mac_X550) &&
3972 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3973 u16 pool = adapter->num_rx_pools;
3974
3975 /* Enable VF RSS mode */
3976 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3977 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3978
3979 /* Setup RSS through the VF registers */
3980 ixgbe_setup_vfreta(adapter);
3981 vfmrqc = IXGBE_MRQC_RSSEN;
3982 vfmrqc |= rss_field;
3983
3984 while (pool--)
3985 IXGBE_WRITE_REG(hw,
3986 IXGBE_PFVFMRQC(VMDQ_P(pool)),
3987 vfmrqc);
3988 } else {
3989 ixgbe_setup_reta(adapter);
3990 mrqc |= rss_field;
3991 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3992 }
3993 }
3994
3995 /**
3996 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3997 * @adapter: address of board private structure
3998 * @ring: structure containing ring specific data
3999 **/
ixgbe_configure_rscctl(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)4000 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
4001 struct ixgbe_ring *ring)
4002 {
4003 struct ixgbe_hw *hw = &adapter->hw;
4004 u32 rscctrl;
4005 u8 reg_idx = ring->reg_idx;
4006
4007 if (!ring_is_rsc_enabled(ring))
4008 return;
4009
4010 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
4011 rscctrl |= IXGBE_RSCCTL_RSCEN;
4012 /*
4013 * we must limit the number of descriptors so that the
4014 * total size of max desc * buf_len is not greater
4015 * than 65536
4016 */
4017 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
4018 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
4019 }
4020
4021 #define IXGBE_MAX_RX_DESC_POLL 10
ixgbe_rx_desc_queue_enable(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)4022 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
4023 struct ixgbe_ring *ring)
4024 {
4025 struct ixgbe_hw *hw = &adapter->hw;
4026 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
4027 u32 rxdctl;
4028 u8 reg_idx = ring->reg_idx;
4029
4030 if (ixgbe_removed(hw->hw_addr))
4031 return;
4032 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
4033 if (hw->mac.type == ixgbe_mac_82598EB &&
4034 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
4035 return;
4036
4037 do {
4038 usleep_range(1000, 2000);
4039 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4040 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4041
4042 if (!wait_loop) {
4043 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
4044 "the polling period\n", reg_idx);
4045 }
4046 }
4047
ixgbe_configure_rx_ring(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)4048 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
4049 struct ixgbe_ring *ring)
4050 {
4051 struct ixgbe_hw *hw = &adapter->hw;
4052 union ixgbe_adv_rx_desc *rx_desc;
4053 u64 rdba = ring->dma;
4054 u32 rxdctl;
4055 u8 reg_idx = ring->reg_idx;
4056
4057 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4058 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
4059 if (ring->xsk_pool) {
4060 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4061 MEM_TYPE_XSK_BUFF_POOL,
4062 NULL));
4063 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
4064 } else {
4065 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4066 MEM_TYPE_PAGE_SHARED, NULL));
4067 }
4068
4069 /* disable queue to avoid use of these values while updating state */
4070 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4071 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4072
4073 /* write value back with RXDCTL.ENABLE bit cleared */
4074 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4075 IXGBE_WRITE_FLUSH(hw);
4076
4077 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
4078 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
4079 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
4080 ring->count * sizeof(union ixgbe_adv_rx_desc));
4081 /* Force flushing of IXGBE_RDLEN to prevent MDD */
4082 IXGBE_WRITE_FLUSH(hw);
4083
4084 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
4085 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
4086 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
4087
4088 ixgbe_configure_srrctl(adapter, ring);
4089 ixgbe_configure_rscctl(adapter, ring);
4090
4091 if (hw->mac.type == ixgbe_mac_82598EB) {
4092 /*
4093 * enable cache line friendly hardware writes:
4094 * PTHRESH=32 descriptors (half the internal cache),
4095 * this also removes ugly rx_no_buffer_count increment
4096 * HTHRESH=4 descriptors (to minimize latency on fetch)
4097 * WTHRESH=8 burst writeback up to two cache lines
4098 */
4099 rxdctl &= ~0x3FFFFF;
4100 rxdctl |= 0x080420;
4101 #if (PAGE_SIZE < 8192)
4102 /* RXDCTL.RLPML does not work on 82599 */
4103 } else if (hw->mac.type != ixgbe_mac_82599EB) {
4104 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4105 IXGBE_RXDCTL_RLPML_EN);
4106
4107 /* Limit the maximum frame size so we don't overrun the skb.
4108 * This can happen in SRIOV mode when the MTU of the VF is
4109 * higher than the MTU of the PF.
4110 */
4111 if (ring_uses_build_skb(ring) &&
4112 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
4113 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
4114 IXGBE_RXDCTL_RLPML_EN;
4115 #endif
4116 }
4117
4118 ring->rx_offset = ixgbe_rx_offset(ring);
4119
4120 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) {
4121 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool);
4122
4123 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4124 IXGBE_RXDCTL_RLPML_EN);
4125 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN;
4126
4127 ring->rx_buf_len = xsk_buf_len;
4128 }
4129
4130 /* initialize rx_buffer_info */
4131 memset(ring->rx_buffer_info, 0,
4132 sizeof(struct ixgbe_rx_buffer) * ring->count);
4133
4134 /* initialize Rx descriptor 0 */
4135 rx_desc = IXGBE_RX_DESC(ring, 0);
4136 rx_desc->wb.upper.length = 0;
4137
4138 /* enable receive descriptor ring */
4139 rxdctl |= IXGBE_RXDCTL_ENABLE;
4140 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4141
4142 ixgbe_rx_desc_queue_enable(adapter, ring);
4143 if (ring->xsk_pool)
4144 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring));
4145 else
4146 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
4147 }
4148
ixgbe_setup_psrtype(struct ixgbe_adapter * adapter)4149 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
4150 {
4151 struct ixgbe_hw *hw = &adapter->hw;
4152 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
4153 u16 pool = adapter->num_rx_pools;
4154
4155 /* PSRTYPE must be initialized in non 82598 adapters */
4156 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4157 IXGBE_PSRTYPE_UDPHDR |
4158 IXGBE_PSRTYPE_IPV4HDR |
4159 IXGBE_PSRTYPE_L2HDR |
4160 IXGBE_PSRTYPE_IPV6HDR;
4161
4162 if (hw->mac.type == ixgbe_mac_82598EB)
4163 return;
4164
4165 if (rss_i > 3)
4166 psrtype |= 2u << 29;
4167 else if (rss_i > 1)
4168 psrtype |= 1u << 29;
4169
4170 while (pool--)
4171 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4172 }
4173
ixgbe_configure_virtualization(struct ixgbe_adapter * adapter)4174 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
4175 {
4176 struct ixgbe_hw *hw = &adapter->hw;
4177 u16 pool = adapter->num_rx_pools;
4178 u32 reg_offset, vf_shift, vmolr;
4179 u32 gcr_ext, vmdctl;
4180 int i;
4181
4182 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
4183 return;
4184
4185 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4186 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
4187 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
4188 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
4189 vmdctl |= IXGBE_VT_CTL_REPLEN;
4190 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
4191
4192 /* accept untagged packets until a vlan tag is
4193 * specifically set for the VMDQ queue/pool
4194 */
4195 vmolr = IXGBE_VMOLR_AUPE;
4196 while (pool--)
4197 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr);
4198
4199 vf_shift = VMDQ_P(0) % 32;
4200 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
4201
4202 /* Enable only the PF's pool for Tx/Rx */
4203 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
4204 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
4205 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
4206 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
4207 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
4208 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4209
4210 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
4211 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
4212
4213 /* clear VLAN promisc flag so VFTA will be updated if necessary */
4214 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4215
4216 /*
4217 * Set up VF register offsets for selected VT Mode,
4218 * i.e. 32 or 64 VFs for SR-IOV
4219 */
4220 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4221 case IXGBE_82599_VMDQ_8Q_MASK:
4222 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
4223 break;
4224 case IXGBE_82599_VMDQ_4Q_MASK:
4225 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
4226 break;
4227 default:
4228 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
4229 break;
4230 }
4231
4232 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4233
4234 for (i = 0; i < adapter->num_vfs; i++) {
4235 /* configure spoof checking */
4236 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
4237 adapter->vfinfo[i].spoofchk_enabled);
4238
4239 /* Enable/Disable RSS query feature */
4240 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
4241 adapter->vfinfo[i].rss_query_enabled);
4242 }
4243 }
4244
ixgbe_set_rx_buffer_len(struct ixgbe_adapter * adapter)4245 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
4246 {
4247 struct ixgbe_hw *hw = &adapter->hw;
4248 struct net_device *netdev = adapter->netdev;
4249 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4250 struct ixgbe_ring *rx_ring;
4251 int i;
4252 u32 mhadd, hlreg0;
4253
4254 #ifdef IXGBE_FCOE
4255 /* adjust max frame to be able to do baby jumbo for FCoE */
4256 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4257 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
4258 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4259
4260 #endif /* IXGBE_FCOE */
4261
4262 /* adjust max frame to be at least the size of a standard frame */
4263 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4264 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
4265
4266 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4267 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
4268 mhadd &= ~IXGBE_MHADD_MFS_MASK;
4269 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
4270
4271 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4272 }
4273
4274 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4275 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
4276 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4277 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4278
4279 /*
4280 * Setup the HW Rx Head and Tail Descriptor Pointers and
4281 * the Base and Length of the Rx Descriptor Ring
4282 */
4283 for (i = 0; i < adapter->num_rx_queues; i++) {
4284 rx_ring = adapter->rx_ring[i];
4285
4286 clear_ring_rsc_enabled(rx_ring);
4287 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4288 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4289
4290 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4291 set_ring_rsc_enabled(rx_ring);
4292
4293 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
4294 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4295
4296 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
4297 continue;
4298
4299 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4300
4301 #if (PAGE_SIZE < 8192)
4302 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4303 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4304
4305 if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
4306 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4307 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4308 #endif
4309 }
4310 }
4311
ixgbe_setup_rdrxctl(struct ixgbe_adapter * adapter)4312 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
4313 {
4314 struct ixgbe_hw *hw = &adapter->hw;
4315 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4316
4317 switch (hw->mac.type) {
4318 case ixgbe_mac_82598EB:
4319 /*
4320 * For VMDq support of different descriptor types or
4321 * buffer sizes through the use of multiple SRRCTL
4322 * registers, RDRXCTL.MVMEN must be set to 1
4323 *
4324 * also, the manual doesn't mention it clearly but DCA hints
4325 * will only use queue 0's tags unless this bit is set. Side
4326 * effects of setting this bit are only that SRRCTL must be
4327 * fully programmed [0..15]
4328 */
4329 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4330 break;
4331 case ixgbe_mac_X550:
4332 case ixgbe_mac_X550EM_x:
4333 case ixgbe_mac_x550em_a:
4334 if (adapter->num_vfs)
4335 rdrxctl |= IXGBE_RDRXCTL_PSP;
4336 fallthrough;
4337 case ixgbe_mac_82599EB:
4338 case ixgbe_mac_X540:
4339 /* Disable RSC for ACK packets */
4340 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4341 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4342 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4343 /* hardware requires some bits to be set by default */
4344 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4345 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4346 break;
4347 default:
4348 /* We should do nothing since we don't know this hardware */
4349 return;
4350 }
4351
4352 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4353 }
4354
4355 /**
4356 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4357 * @adapter: board private structure
4358 *
4359 * Configure the Rx unit of the MAC after a reset.
4360 **/
ixgbe_configure_rx(struct ixgbe_adapter * adapter)4361 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4362 {
4363 struct ixgbe_hw *hw = &adapter->hw;
4364 int i;
4365 u32 rxctrl, rfctl;
4366
4367 /* disable receives while setting up the descriptors */
4368 hw->mac.ops.disable_rx(hw);
4369
4370 ixgbe_setup_psrtype(adapter);
4371 ixgbe_setup_rdrxctl(adapter);
4372
4373 /* RSC Setup */
4374 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4375 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4376 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4377 rfctl |= IXGBE_RFCTL_RSC_DIS;
4378
4379 /* disable NFS filtering */
4380 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
4381 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4382
4383 /* Program registers for the distribution of queues */
4384 ixgbe_setup_mrqc(adapter);
4385
4386 /* set_rx_buffer_len must be called before ring initialization */
4387 ixgbe_set_rx_buffer_len(adapter);
4388
4389 /*
4390 * Setup the HW Rx Head and Tail Descriptor Pointers and
4391 * the Base and Length of the Rx Descriptor Ring
4392 */
4393 for (i = 0; i < adapter->num_rx_queues; i++)
4394 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
4395
4396 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4397 /* disable drop enable for 82598 parts */
4398 if (hw->mac.type == ixgbe_mac_82598EB)
4399 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4400
4401 /* enable all receives */
4402 rxctrl |= IXGBE_RXCTRL_RXEN;
4403 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4404 }
4405
ixgbe_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)4406 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4407 __be16 proto, u16 vid)
4408 {
4409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4410 struct ixgbe_hw *hw = &adapter->hw;
4411
4412 /* add VID to filter table */
4413 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4414 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4415
4416 set_bit(vid, adapter->active_vlans);
4417
4418 return 0;
4419 }
4420
ixgbe_find_vlvf_entry(struct ixgbe_hw * hw,u32 vlan)4421 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4422 {
4423 u32 vlvf;
4424 int idx;
4425
4426 /* short cut the special case */
4427 if (vlan == 0)
4428 return 0;
4429
4430 /* Search for the vlan id in the VLVF entries */
4431 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4432 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4433 if ((vlvf & VLAN_VID_MASK) == vlan)
4434 break;
4435 }
4436
4437 return idx;
4438 }
4439
ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter * adapter,u32 vid)4440 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4441 {
4442 struct ixgbe_hw *hw = &adapter->hw;
4443 u32 bits, word;
4444 int idx;
4445
4446 idx = ixgbe_find_vlvf_entry(hw, vid);
4447 if (!idx)
4448 return;
4449
4450 /* See if any other pools are set for this VLAN filter
4451 * entry other than the PF.
4452 */
4453 word = idx * 2 + (VMDQ_P(0) / 32);
4454 bits = ~BIT(VMDQ_P(0) % 32);
4455 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4456
4457 /* Disable the filter so this falls into the default pool. */
4458 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4459 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4460 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4461 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4462 }
4463 }
4464
ixgbe_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)4465 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4466 __be16 proto, u16 vid)
4467 {
4468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4469 struct ixgbe_hw *hw = &adapter->hw;
4470
4471 /* remove VID from filter table */
4472 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4473 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4474
4475 clear_bit(vid, adapter->active_vlans);
4476
4477 return 0;
4478 }
4479
4480 /**
4481 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4482 * @adapter: driver data
4483 */
ixgbe_vlan_strip_disable(struct ixgbe_adapter * adapter)4484 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4485 {
4486 struct ixgbe_hw *hw = &adapter->hw;
4487 u32 vlnctrl;
4488 int i, j;
4489
4490 switch (hw->mac.type) {
4491 case ixgbe_mac_82598EB:
4492 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4493 vlnctrl &= ~IXGBE_VLNCTRL_VME;
4494 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4495 break;
4496 case ixgbe_mac_82599EB:
4497 case ixgbe_mac_X540:
4498 case ixgbe_mac_X550:
4499 case ixgbe_mac_X550EM_x:
4500 case ixgbe_mac_x550em_a:
4501 for (i = 0; i < adapter->num_rx_queues; i++) {
4502 struct ixgbe_ring *ring = adapter->rx_ring[i];
4503
4504 if (!netif_is_ixgbe(ring->netdev))
4505 continue;
4506
4507 j = ring->reg_idx;
4508 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4509 vlnctrl &= ~IXGBE_RXDCTL_VME;
4510 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4511 }
4512 break;
4513 default:
4514 break;
4515 }
4516 }
4517
4518 /**
4519 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4520 * @adapter: driver data
4521 */
ixgbe_vlan_strip_enable(struct ixgbe_adapter * adapter)4522 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4523 {
4524 struct ixgbe_hw *hw = &adapter->hw;
4525 u32 vlnctrl;
4526 int i, j;
4527
4528 switch (hw->mac.type) {
4529 case ixgbe_mac_82598EB:
4530 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4531 vlnctrl |= IXGBE_VLNCTRL_VME;
4532 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4533 break;
4534 case ixgbe_mac_82599EB:
4535 case ixgbe_mac_X540:
4536 case ixgbe_mac_X550:
4537 case ixgbe_mac_X550EM_x:
4538 case ixgbe_mac_x550em_a:
4539 for (i = 0; i < adapter->num_rx_queues; i++) {
4540 struct ixgbe_ring *ring = adapter->rx_ring[i];
4541
4542 if (!netif_is_ixgbe(ring->netdev))
4543 continue;
4544
4545 j = ring->reg_idx;
4546 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4547 vlnctrl |= IXGBE_RXDCTL_VME;
4548 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4549 }
4550 break;
4551 default:
4552 break;
4553 }
4554 }
4555
ixgbe_vlan_promisc_enable(struct ixgbe_adapter * adapter)4556 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4557 {
4558 struct ixgbe_hw *hw = &adapter->hw;
4559 u32 vlnctrl, i;
4560
4561 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4562
4563 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4564 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4565 vlnctrl |= IXGBE_VLNCTRL_VFE;
4566 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4567 } else {
4568 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
4569 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4570 return;
4571 }
4572
4573 /* Nothing to do for 82598 */
4574 if (hw->mac.type == ixgbe_mac_82598EB)
4575 return;
4576
4577 /* We are already in VLAN promisc, nothing to do */
4578 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4579 return;
4580
4581 /* Set flag so we don't redo unnecessary work */
4582 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4583
4584 /* Add PF to all active pools */
4585 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4586 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4587 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4588
4589 vlvfb |= BIT(VMDQ_P(0) % 32);
4590 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4591 }
4592
4593 /* Set all bits in the VLAN filter table array */
4594 for (i = hw->mac.vft_size; i--;)
4595 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4596 }
4597
4598 #define VFTA_BLOCK_SIZE 8
ixgbe_scrub_vfta(struct ixgbe_adapter * adapter,u32 vfta_offset)4599 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4600 {
4601 struct ixgbe_hw *hw = &adapter->hw;
4602 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4603 u32 vid_start = vfta_offset * 32;
4604 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4605 u32 i, vid, word, bits;
4606
4607 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4608 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4609
4610 /* pull VLAN ID from VLVF */
4611 vid = vlvf & VLAN_VID_MASK;
4612
4613 /* only concern outselves with a certain range */
4614 if (vid < vid_start || vid >= vid_end)
4615 continue;
4616
4617 if (vlvf) {
4618 /* record VLAN ID in VFTA */
4619 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4620
4621 /* if PF is part of this then continue */
4622 if (test_bit(vid, adapter->active_vlans))
4623 continue;
4624 }
4625
4626 /* remove PF from the pool */
4627 word = i * 2 + VMDQ_P(0) / 32;
4628 bits = ~BIT(VMDQ_P(0) % 32);
4629 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4630 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4631 }
4632
4633 /* extract values from active_vlans and write back to VFTA */
4634 for (i = VFTA_BLOCK_SIZE; i--;) {
4635 vid = (vfta_offset + i) * 32;
4636 word = vid / BITS_PER_LONG;
4637 bits = vid % BITS_PER_LONG;
4638
4639 vfta[i] |= adapter->active_vlans[word] >> bits;
4640
4641 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4642 }
4643 }
4644
ixgbe_vlan_promisc_disable(struct ixgbe_adapter * adapter)4645 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4646 {
4647 struct ixgbe_hw *hw = &adapter->hw;
4648 u32 vlnctrl, i;
4649
4650 /* Set VLAN filtering to enabled */
4651 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4652 vlnctrl |= IXGBE_VLNCTRL_VFE;
4653 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4654
4655 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4656 hw->mac.type == ixgbe_mac_82598EB)
4657 return;
4658
4659 /* We are not in VLAN promisc, nothing to do */
4660 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4661 return;
4662
4663 /* Set flag so we don't redo unnecessary work */
4664 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4665
4666 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4667 ixgbe_scrub_vfta(adapter, i);
4668 }
4669
ixgbe_restore_vlan(struct ixgbe_adapter * adapter)4670 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4671 {
4672 u16 vid = 1;
4673
4674 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4675
4676 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4677 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4678 }
4679
4680 /**
4681 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4682 * @netdev: network interface device structure
4683 *
4684 * Writes multicast address list to the MTA hash table.
4685 * Returns: -ENOMEM on failure
4686 * 0 on no addresses written
4687 * X on writing X addresses to MTA
4688 **/
ixgbe_write_mc_addr_list(struct net_device * netdev)4689 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4690 {
4691 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4692 struct ixgbe_hw *hw = &adapter->hw;
4693
4694 if (!netif_running(netdev))
4695 return 0;
4696
4697 if (hw->mac.ops.update_mc_addr_list)
4698 hw->mac.ops.update_mc_addr_list(hw, netdev);
4699 else
4700 return -ENOMEM;
4701
4702 #ifdef CONFIG_PCI_IOV
4703 ixgbe_restore_vf_multicasts(adapter);
4704 #endif
4705
4706 return netdev_mc_count(netdev);
4707 }
4708
4709 #ifdef CONFIG_PCI_IOV
ixgbe_full_sync_mac_table(struct ixgbe_adapter * adapter)4710 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4711 {
4712 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4713 struct ixgbe_hw *hw = &adapter->hw;
4714 int i;
4715
4716 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4717 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4718
4719 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4720 hw->mac.ops.set_rar(hw, i,
4721 mac_table->addr,
4722 mac_table->pool,
4723 IXGBE_RAH_AV);
4724 else
4725 hw->mac.ops.clear_rar(hw, i);
4726 }
4727 }
4728
4729 #endif
ixgbe_sync_mac_table(struct ixgbe_adapter * adapter)4730 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4731 {
4732 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4733 struct ixgbe_hw *hw = &adapter->hw;
4734 int i;
4735
4736 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4737 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4738 continue;
4739
4740 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4741
4742 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4743 hw->mac.ops.set_rar(hw, i,
4744 mac_table->addr,
4745 mac_table->pool,
4746 IXGBE_RAH_AV);
4747 else
4748 hw->mac.ops.clear_rar(hw, i);
4749 }
4750 }
4751
ixgbe_flush_sw_mac_table(struct ixgbe_adapter * adapter)4752 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4753 {
4754 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4755 struct ixgbe_hw *hw = &adapter->hw;
4756 int i;
4757
4758 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4759 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4760 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4761 }
4762
4763 ixgbe_sync_mac_table(adapter);
4764 }
4765
ixgbe_available_rars(struct ixgbe_adapter * adapter,u16 pool)4766 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4767 {
4768 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4769 struct ixgbe_hw *hw = &adapter->hw;
4770 int i, count = 0;
4771
4772 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4773 /* do not count default RAR as available */
4774 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4775 continue;
4776
4777 /* only count unused and addresses that belong to us */
4778 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4779 if (mac_table->pool != pool)
4780 continue;
4781 }
4782
4783 count++;
4784 }
4785
4786 return count;
4787 }
4788
4789 /* this function destroys the first RAR entry */
ixgbe_mac_set_default_filter(struct ixgbe_adapter * adapter)4790 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4791 {
4792 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4793 struct ixgbe_hw *hw = &adapter->hw;
4794
4795 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4796 mac_table->pool = VMDQ_P(0);
4797
4798 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4799
4800 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4801 IXGBE_RAH_AV);
4802 }
4803
ixgbe_add_mac_filter(struct ixgbe_adapter * adapter,const u8 * addr,u16 pool)4804 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4805 const u8 *addr, u16 pool)
4806 {
4807 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4808 struct ixgbe_hw *hw = &adapter->hw;
4809 int i;
4810
4811 if (is_zero_ether_addr(addr))
4812 return -EINVAL;
4813
4814 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4815 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4816 continue;
4817
4818 ether_addr_copy(mac_table->addr, addr);
4819 mac_table->pool = pool;
4820
4821 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4822 IXGBE_MAC_STATE_IN_USE;
4823
4824 ixgbe_sync_mac_table(adapter);
4825
4826 return i;
4827 }
4828
4829 return -ENOMEM;
4830 }
4831
ixgbe_del_mac_filter(struct ixgbe_adapter * adapter,const u8 * addr,u16 pool)4832 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4833 const u8 *addr, u16 pool)
4834 {
4835 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4836 struct ixgbe_hw *hw = &adapter->hw;
4837 int i;
4838
4839 if (is_zero_ether_addr(addr))
4840 return -EINVAL;
4841
4842 /* search table for addr, if found clear IN_USE flag and sync */
4843 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4844 /* we can only delete an entry if it is in use */
4845 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4846 continue;
4847 /* we only care about entries that belong to the given pool */
4848 if (mac_table->pool != pool)
4849 continue;
4850 /* we only care about a specific MAC address */
4851 if (!ether_addr_equal(addr, mac_table->addr))
4852 continue;
4853
4854 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4855 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4856
4857 ixgbe_sync_mac_table(adapter);
4858
4859 return 0;
4860 }
4861
4862 return -ENOMEM;
4863 }
4864
ixgbe_uc_sync(struct net_device * netdev,const unsigned char * addr)4865 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4866 {
4867 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4868 int ret;
4869
4870 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4871
4872 return min_t(int, ret, 0);
4873 }
4874
ixgbe_uc_unsync(struct net_device * netdev,const unsigned char * addr)4875 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4876 {
4877 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4878
4879 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4880
4881 return 0;
4882 }
4883
4884 /**
4885 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4886 * @netdev: network interface device structure
4887 *
4888 * The set_rx_method entry point is called whenever the unicast/multicast
4889 * address list or the network interface flags are updated. This routine is
4890 * responsible for configuring the hardware for proper unicast, multicast and
4891 * promiscuous mode.
4892 **/
ixgbe_set_rx_mode(struct net_device * netdev)4893 void ixgbe_set_rx_mode(struct net_device *netdev)
4894 {
4895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4896 struct ixgbe_hw *hw = &adapter->hw;
4897 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4898 netdev_features_t features = netdev->features;
4899 int count;
4900
4901 /* Check for Promiscuous and All Multicast modes */
4902 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4903
4904 /* set all bits that we expect to always be set */
4905 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4906 fctrl |= IXGBE_FCTRL_BAM;
4907 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4908 fctrl |= IXGBE_FCTRL_PMCF;
4909
4910 /* clear the bits we are changing the status of */
4911 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4912 if (netdev->flags & IFF_PROMISC) {
4913 hw->addr_ctrl.user_set_promisc = true;
4914 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4915 vmolr |= IXGBE_VMOLR_MPE;
4916 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4917 } else {
4918 if (netdev->flags & IFF_ALLMULTI) {
4919 fctrl |= IXGBE_FCTRL_MPE;
4920 vmolr |= IXGBE_VMOLR_MPE;
4921 }
4922 hw->addr_ctrl.user_set_promisc = false;
4923 }
4924
4925 /*
4926 * Write addresses to available RAR registers, if there is not
4927 * sufficient space to store all the addresses then enable
4928 * unicast promiscuous mode
4929 */
4930 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4931 fctrl |= IXGBE_FCTRL_UPE;
4932 vmolr |= IXGBE_VMOLR_ROPE;
4933 }
4934
4935 /* Write addresses to the MTA, if the attempt fails
4936 * then we should just turn on promiscuous mode so
4937 * that we can at least receive multicast traffic
4938 */
4939 count = ixgbe_write_mc_addr_list(netdev);
4940 if (count < 0) {
4941 fctrl |= IXGBE_FCTRL_MPE;
4942 vmolr |= IXGBE_VMOLR_MPE;
4943 } else if (count) {
4944 vmolr |= IXGBE_VMOLR_ROMPE;
4945 }
4946
4947 if (hw->mac.type != ixgbe_mac_82598EB) {
4948 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4949 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4950 IXGBE_VMOLR_ROPE);
4951 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4952 }
4953
4954 /* This is useful for sniffing bad packets. */
4955 if (features & NETIF_F_RXALL) {
4956 /* UPE and MPE will be handled by normal PROMISC logic
4957 * in e1000e_set_rx_mode */
4958 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4959 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4960 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4961
4962 fctrl &= ~(IXGBE_FCTRL_DPF);
4963 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4964 }
4965
4966 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4967
4968 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4969 ixgbe_vlan_strip_enable(adapter);
4970 else
4971 ixgbe_vlan_strip_disable(adapter);
4972
4973 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4974 ixgbe_vlan_promisc_disable(adapter);
4975 else
4976 ixgbe_vlan_promisc_enable(adapter);
4977 }
4978
ixgbe_napi_enable_all(struct ixgbe_adapter * adapter)4979 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4980 {
4981 int q_idx;
4982
4983 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4984 napi_enable(&adapter->q_vector[q_idx]->napi);
4985 }
4986
ixgbe_napi_disable_all(struct ixgbe_adapter * adapter)4987 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4988 {
4989 int q_idx;
4990
4991 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4992 napi_disable(&adapter->q_vector[q_idx]->napi);
4993 }
4994
ixgbe_udp_tunnel_sync(struct net_device * dev,unsigned int table)4995 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table)
4996 {
4997 struct ixgbe_adapter *adapter = netdev_priv(dev);
4998 struct ixgbe_hw *hw = &adapter->hw;
4999 struct udp_tunnel_info ti;
5000
5001 udp_tunnel_nic_get_port(dev, table, 0, &ti);
5002 if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
5003 adapter->vxlan_port = ti.port;
5004 else
5005 adapter->geneve_port = ti.port;
5006
5007 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL,
5008 ntohs(adapter->vxlan_port) |
5009 ntohs(adapter->geneve_port) <<
5010 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT);
5011 return 0;
5012 }
5013
5014 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = {
5015 .sync_table = ixgbe_udp_tunnel_sync,
5016 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5017 .tables = {
5018 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5019 },
5020 };
5021
5022 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = {
5023 .sync_table = ixgbe_udp_tunnel_sync,
5024 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5025 .tables = {
5026 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5027 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
5028 },
5029 };
5030
5031 #ifdef CONFIG_IXGBE_DCB
5032 /**
5033 * ixgbe_configure_dcb - Configure DCB hardware
5034 * @adapter: ixgbe adapter struct
5035 *
5036 * This is called by the driver on open to configure the DCB hardware.
5037 * This is also called by the gennetlink interface when reconfiguring
5038 * the DCB state.
5039 */
ixgbe_configure_dcb(struct ixgbe_adapter * adapter)5040 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
5041 {
5042 struct ixgbe_hw *hw = &adapter->hw;
5043 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5044
5045 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
5046 if (hw->mac.type == ixgbe_mac_82598EB)
5047 netif_set_gso_max_size(adapter->netdev, 65536);
5048 return;
5049 }
5050
5051 if (hw->mac.type == ixgbe_mac_82598EB)
5052 netif_set_gso_max_size(adapter->netdev, 32768);
5053
5054 #ifdef IXGBE_FCOE
5055 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
5056 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
5057 #endif
5058
5059 /* reconfigure the hardware */
5060 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
5061 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5062 DCB_TX_CONFIG);
5063 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5064 DCB_RX_CONFIG);
5065 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
5066 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
5067 ixgbe_dcb_hw_ets(&adapter->hw,
5068 adapter->ixgbe_ieee_ets,
5069 max_frame);
5070 ixgbe_dcb_hw_pfc_config(&adapter->hw,
5071 adapter->ixgbe_ieee_pfc->pfc_en,
5072 adapter->ixgbe_ieee_ets->prio_tc);
5073 }
5074
5075 /* Enable RSS Hash per TC */
5076 if (hw->mac.type != ixgbe_mac_82598EB) {
5077 u32 msb = 0;
5078 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
5079
5080 while (rss_i) {
5081 msb++;
5082 rss_i >>= 1;
5083 }
5084
5085 /* write msb to all 8 TCs in one write */
5086 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
5087 }
5088 }
5089 #endif
5090
5091 /* Additional bittime to account for IXGBE framing */
5092 #define IXGBE_ETH_FRAMING 20
5093
5094 /**
5095 * ixgbe_hpbthresh - calculate high water mark for flow control
5096 *
5097 * @adapter: board private structure to calculate for
5098 * @pb: packet buffer to calculate
5099 */
ixgbe_hpbthresh(struct ixgbe_adapter * adapter,int pb)5100 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
5101 {
5102 struct ixgbe_hw *hw = &adapter->hw;
5103 struct net_device *dev = adapter->netdev;
5104 int link, tc, kb, marker;
5105 u32 dv_id, rx_pba;
5106
5107 /* Calculate max LAN frame size */
5108 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
5109
5110 #ifdef IXGBE_FCOE
5111 /* FCoE traffic class uses FCOE jumbo frames */
5112 if ((dev->features & NETIF_F_FCOE_MTU) &&
5113 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5114 (pb == ixgbe_fcoe_get_tc(adapter)))
5115 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5116 #endif
5117
5118 /* Calculate delay value for device */
5119 switch (hw->mac.type) {
5120 case ixgbe_mac_X540:
5121 case ixgbe_mac_X550:
5122 case ixgbe_mac_X550EM_x:
5123 case ixgbe_mac_x550em_a:
5124 dv_id = IXGBE_DV_X540(link, tc);
5125 break;
5126 default:
5127 dv_id = IXGBE_DV(link, tc);
5128 break;
5129 }
5130
5131 /* Loopback switch introduces additional latency */
5132 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5133 dv_id += IXGBE_B2BT(tc);
5134
5135 /* Delay value is calculated in bit times convert to KB */
5136 kb = IXGBE_BT2KB(dv_id);
5137 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
5138
5139 marker = rx_pba - kb;
5140
5141 /* It is possible that the packet buffer is not large enough
5142 * to provide required headroom. In this case throw an error
5143 * to user and a do the best we can.
5144 */
5145 if (marker < 0) {
5146 e_warn(drv, "Packet Buffer(%i) can not provide enough"
5147 "headroom to support flow control."
5148 "Decrease MTU or number of traffic classes\n", pb);
5149 marker = tc + 1;
5150 }
5151
5152 return marker;
5153 }
5154
5155 /**
5156 * ixgbe_lpbthresh - calculate low water mark for for flow control
5157 *
5158 * @adapter: board private structure to calculate for
5159 * @pb: packet buffer to calculate
5160 */
ixgbe_lpbthresh(struct ixgbe_adapter * adapter,int pb)5161 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
5162 {
5163 struct ixgbe_hw *hw = &adapter->hw;
5164 struct net_device *dev = adapter->netdev;
5165 int tc;
5166 u32 dv_id;
5167
5168 /* Calculate max LAN frame size */
5169 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5170
5171 #ifdef IXGBE_FCOE
5172 /* FCoE traffic class uses FCOE jumbo frames */
5173 if ((dev->features & NETIF_F_FCOE_MTU) &&
5174 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5175 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
5176 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5177 #endif
5178
5179 /* Calculate delay value for device */
5180 switch (hw->mac.type) {
5181 case ixgbe_mac_X540:
5182 case ixgbe_mac_X550:
5183 case ixgbe_mac_X550EM_x:
5184 case ixgbe_mac_x550em_a:
5185 dv_id = IXGBE_LOW_DV_X540(tc);
5186 break;
5187 default:
5188 dv_id = IXGBE_LOW_DV(tc);
5189 break;
5190 }
5191
5192 /* Delay value is calculated in bit times convert to KB */
5193 return IXGBE_BT2KB(dv_id);
5194 }
5195
5196 /*
5197 * ixgbe_pbthresh_setup - calculate and setup high low water marks
5198 */
ixgbe_pbthresh_setup(struct ixgbe_adapter * adapter)5199 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
5200 {
5201 struct ixgbe_hw *hw = &adapter->hw;
5202 int num_tc = adapter->hw_tcs;
5203 int i;
5204
5205 if (!num_tc)
5206 num_tc = 1;
5207
5208 for (i = 0; i < num_tc; i++) {
5209 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
5210 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
5211
5212 /* Low water marks must not be larger than high water marks */
5213 if (hw->fc.low_water[i] > hw->fc.high_water[i])
5214 hw->fc.low_water[i] = 0;
5215 }
5216
5217 for (; i < MAX_TRAFFIC_CLASS; i++)
5218 hw->fc.high_water[i] = 0;
5219 }
5220
ixgbe_configure_pb(struct ixgbe_adapter * adapter)5221 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
5222 {
5223 struct ixgbe_hw *hw = &adapter->hw;
5224 int hdrm;
5225 u8 tc = adapter->hw_tcs;
5226
5227 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5228 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5229 hdrm = 32 << adapter->fdir_pballoc;
5230 else
5231 hdrm = 0;
5232
5233 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
5234 ixgbe_pbthresh_setup(adapter);
5235 }
5236
ixgbe_fdir_filter_restore(struct ixgbe_adapter * adapter)5237 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
5238 {
5239 struct ixgbe_hw *hw = &adapter->hw;
5240 struct hlist_node *node2;
5241 struct ixgbe_fdir_filter *filter;
5242 u8 queue;
5243
5244 spin_lock(&adapter->fdir_perfect_lock);
5245
5246 if (!hlist_empty(&adapter->fdir_filter_list))
5247 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
5248
5249 hlist_for_each_entry_safe(filter, node2,
5250 &adapter->fdir_filter_list, fdir_node) {
5251 if (filter->action == IXGBE_FDIR_DROP_QUEUE) {
5252 queue = IXGBE_FDIR_DROP_QUEUE;
5253 } else {
5254 u32 ring = ethtool_get_flow_spec_ring(filter->action);
5255 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action);
5256
5257 if (!vf && (ring >= adapter->num_rx_queues)) {
5258 e_err(drv, "FDIR restore failed without VF, ring: %u\n",
5259 ring);
5260 continue;
5261 } else if (vf &&
5262 ((vf > adapter->num_vfs) ||
5263 ring >= adapter->num_rx_queues_per_pool)) {
5264 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n",
5265 vf, ring);
5266 continue;
5267 }
5268
5269 /* Map the ring onto the absolute queue index */
5270 if (!vf)
5271 queue = adapter->rx_ring[ring]->reg_idx;
5272 else
5273 queue = ((vf - 1) *
5274 adapter->num_rx_queues_per_pool) + ring;
5275 }
5276
5277 ixgbe_fdir_write_perfect_filter_82599(hw,
5278 &filter->filter, filter->sw_idx, queue);
5279 }
5280
5281 spin_unlock(&adapter->fdir_perfect_lock);
5282 }
5283
5284 /**
5285 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
5286 * @rx_ring: ring to free buffers from
5287 **/
ixgbe_clean_rx_ring(struct ixgbe_ring * rx_ring)5288 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
5289 {
5290 u16 i = rx_ring->next_to_clean;
5291 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
5292
5293 if (rx_ring->xsk_pool) {
5294 ixgbe_xsk_clean_rx_ring(rx_ring);
5295 goto skip_free;
5296 }
5297
5298 /* Free all the Rx ring sk_buffs */
5299 while (i != rx_ring->next_to_alloc) {
5300 if (rx_buffer->skb) {
5301 struct sk_buff *skb = rx_buffer->skb;
5302 if (IXGBE_CB(skb)->page_released)
5303 dma_unmap_page_attrs(rx_ring->dev,
5304 IXGBE_CB(skb)->dma,
5305 ixgbe_rx_pg_size(rx_ring),
5306 DMA_FROM_DEVICE,
5307 IXGBE_RX_DMA_ATTR);
5308 dev_kfree_skb(skb);
5309 }
5310
5311 /* Invalidate cache lines that may have been written to by
5312 * device so that we avoid corrupting memory.
5313 */
5314 dma_sync_single_range_for_cpu(rx_ring->dev,
5315 rx_buffer->dma,
5316 rx_buffer->page_offset,
5317 ixgbe_rx_bufsz(rx_ring),
5318 DMA_FROM_DEVICE);
5319
5320 /* free resources associated with mapping */
5321 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
5322 ixgbe_rx_pg_size(rx_ring),
5323 DMA_FROM_DEVICE,
5324 IXGBE_RX_DMA_ATTR);
5325 __page_frag_cache_drain(rx_buffer->page,
5326 rx_buffer->pagecnt_bias);
5327
5328 i++;
5329 rx_buffer++;
5330 if (i == rx_ring->count) {
5331 i = 0;
5332 rx_buffer = rx_ring->rx_buffer_info;
5333 }
5334 }
5335
5336 skip_free:
5337 rx_ring->next_to_alloc = 0;
5338 rx_ring->next_to_clean = 0;
5339 rx_ring->next_to_use = 0;
5340 }
5341
ixgbe_fwd_ring_up(struct ixgbe_adapter * adapter,struct ixgbe_fwd_adapter * accel)5342 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter,
5343 struct ixgbe_fwd_adapter *accel)
5344 {
5345 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
5346 int num_tc = netdev_get_num_tc(adapter->netdev);
5347 struct net_device *vdev = accel->netdev;
5348 int i, baseq, err;
5349
5350 baseq = accel->pool * adapter->num_rx_queues_per_pool;
5351 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n",
5352 accel->pool, adapter->num_rx_pools,
5353 baseq, baseq + adapter->num_rx_queues_per_pool);
5354
5355 accel->rx_base_queue = baseq;
5356 accel->tx_base_queue = baseq;
5357
5358 /* record configuration for macvlan interface in vdev */
5359 for (i = 0; i < num_tc; i++)
5360 netdev_bind_sb_channel_queue(adapter->netdev, vdev,
5361 i, rss_i, baseq + (rss_i * i));
5362
5363 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5364 adapter->rx_ring[baseq + i]->netdev = vdev;
5365
5366 /* Guarantee all rings are updated before we update the
5367 * MAC address filter.
5368 */
5369 wmb();
5370
5371 /* ixgbe_add_mac_filter will return an index if it succeeds, so we
5372 * need to only treat it as an error value if it is negative.
5373 */
5374 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr,
5375 VMDQ_P(accel->pool));
5376 if (err >= 0)
5377 return 0;
5378
5379 /* if we cannot add the MAC rule then disable the offload */
5380 macvlan_release_l2fw_offload(vdev);
5381
5382 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5383 adapter->rx_ring[baseq + i]->netdev = NULL;
5384
5385 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n");
5386
5387 /* unbind the queues and drop the subordinate channel config */
5388 netdev_unbind_sb_channel(adapter->netdev, vdev);
5389 netdev_set_sb_channel(vdev, 0);
5390
5391 clear_bit(accel->pool, adapter->fwd_bitmask);
5392 kfree(accel);
5393
5394 return err;
5395 }
5396
ixgbe_macvlan_up(struct net_device * vdev,struct netdev_nested_priv * priv)5397 static int ixgbe_macvlan_up(struct net_device *vdev,
5398 struct netdev_nested_priv *priv)
5399 {
5400 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
5401 struct ixgbe_fwd_adapter *accel;
5402
5403 if (!netif_is_macvlan(vdev))
5404 return 0;
5405
5406 accel = macvlan_accel_priv(vdev);
5407 if (!accel)
5408 return 0;
5409
5410 ixgbe_fwd_ring_up(adapter, accel);
5411
5412 return 0;
5413 }
5414
ixgbe_configure_dfwd(struct ixgbe_adapter * adapter)5415 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5416 {
5417 struct netdev_nested_priv priv = {
5418 .data = (void *)adapter,
5419 };
5420
5421 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5422 ixgbe_macvlan_up, &priv);
5423 }
5424
ixgbe_configure(struct ixgbe_adapter * adapter)5425 static void ixgbe_configure(struct ixgbe_adapter *adapter)
5426 {
5427 struct ixgbe_hw *hw = &adapter->hw;
5428
5429 ixgbe_configure_pb(adapter);
5430 #ifdef CONFIG_IXGBE_DCB
5431 ixgbe_configure_dcb(adapter);
5432 #endif
5433 /*
5434 * We must restore virtualization before VLANs or else
5435 * the VLVF registers will not be populated
5436 */
5437 ixgbe_configure_virtualization(adapter);
5438
5439 ixgbe_set_rx_mode(adapter->netdev);
5440 ixgbe_restore_vlan(adapter);
5441 ixgbe_ipsec_restore(adapter);
5442
5443 switch (hw->mac.type) {
5444 case ixgbe_mac_82599EB:
5445 case ixgbe_mac_X540:
5446 hw->mac.ops.disable_rx_buff(hw);
5447 break;
5448 default:
5449 break;
5450 }
5451
5452 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5453 ixgbe_init_fdir_signature_82599(&adapter->hw,
5454 adapter->fdir_pballoc);
5455 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5456 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5457 adapter->fdir_pballoc);
5458 ixgbe_fdir_filter_restore(adapter);
5459 }
5460
5461 switch (hw->mac.type) {
5462 case ixgbe_mac_82599EB:
5463 case ixgbe_mac_X540:
5464 hw->mac.ops.enable_rx_buff(hw);
5465 break;
5466 default:
5467 break;
5468 }
5469
5470 #ifdef CONFIG_IXGBE_DCA
5471 /* configure DCA */
5472 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5473 ixgbe_setup_dca(adapter);
5474 #endif /* CONFIG_IXGBE_DCA */
5475
5476 #ifdef IXGBE_FCOE
5477 /* configure FCoE L2 filters, redirection table, and Rx control */
5478 ixgbe_configure_fcoe(adapter);
5479
5480 #endif /* IXGBE_FCOE */
5481 ixgbe_configure_tx(adapter);
5482 ixgbe_configure_rx(adapter);
5483 ixgbe_configure_dfwd(adapter);
5484 }
5485
5486 /**
5487 * ixgbe_sfp_link_config - set up SFP+ link
5488 * @adapter: pointer to private adapter struct
5489 **/
ixgbe_sfp_link_config(struct ixgbe_adapter * adapter)5490 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5491 {
5492 /*
5493 * We are assuming the worst case scenario here, and that
5494 * is that an SFP was inserted/removed after the reset
5495 * but before SFP detection was enabled. As such the best
5496 * solution is to just start searching as soon as we start
5497 */
5498 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5499 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5500
5501 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5502 adapter->sfp_poll_time = 0;
5503 }
5504
5505 /**
5506 * ixgbe_non_sfp_link_config - set up non-SFP+ link
5507 * @hw: pointer to private hardware struct
5508 *
5509 * Returns 0 on success, negative on failure
5510 **/
ixgbe_non_sfp_link_config(struct ixgbe_hw * hw)5511 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5512 {
5513 u32 speed;
5514 bool autoneg, link_up = false;
5515 int ret = -EIO;
5516
5517 if (hw->mac.ops.check_link)
5518 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5519
5520 if (ret)
5521 return ret;
5522
5523 speed = hw->phy.autoneg_advertised;
5524 if (!speed && hw->mac.ops.get_link_capabilities) {
5525 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5526 &autoneg);
5527 /* remove NBASE-T speeds from default autonegotiation
5528 * to accommodate broken network switches in the field
5529 * which cannot cope with advertised NBASE-T speeds
5530 */
5531 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL |
5532 IXGBE_LINK_SPEED_2_5GB_FULL);
5533 }
5534
5535 if (ret)
5536 return ret;
5537
5538 if (hw->mac.ops.setup_link)
5539 ret = hw->mac.ops.setup_link(hw, speed, link_up);
5540
5541 return ret;
5542 }
5543
ixgbe_setup_gpie(struct ixgbe_adapter * adapter)5544 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5545 {
5546 struct ixgbe_hw *hw = &adapter->hw;
5547 u32 gpie = 0;
5548
5549 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5550 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5551 IXGBE_GPIE_OCD;
5552 gpie |= IXGBE_GPIE_EIAME;
5553 /*
5554 * use EIAM to auto-mask when MSI-X interrupt is asserted
5555 * this saves a register write for every interrupt
5556 */
5557 switch (hw->mac.type) {
5558 case ixgbe_mac_82598EB:
5559 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5560 break;
5561 case ixgbe_mac_82599EB:
5562 case ixgbe_mac_X540:
5563 case ixgbe_mac_X550:
5564 case ixgbe_mac_X550EM_x:
5565 case ixgbe_mac_x550em_a:
5566 default:
5567 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5568 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5569 break;
5570 }
5571 } else {
5572 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5573 * specifically only auto mask tx and rx interrupts */
5574 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5575 }
5576
5577 /* XXX: to interrupt immediately for EICS writes, enable this */
5578 /* gpie |= IXGBE_GPIE_EIMEN; */
5579
5580 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5581 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5582
5583 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5584 case IXGBE_82599_VMDQ_8Q_MASK:
5585 gpie |= IXGBE_GPIE_VTMODE_16;
5586 break;
5587 case IXGBE_82599_VMDQ_4Q_MASK:
5588 gpie |= IXGBE_GPIE_VTMODE_32;
5589 break;
5590 default:
5591 gpie |= IXGBE_GPIE_VTMODE_64;
5592 break;
5593 }
5594 }
5595
5596 /* Enable Thermal over heat sensor interrupt */
5597 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5598 switch (adapter->hw.mac.type) {
5599 case ixgbe_mac_82599EB:
5600 gpie |= IXGBE_SDP0_GPIEN_8259X;
5601 break;
5602 default:
5603 break;
5604 }
5605 }
5606
5607 /* Enable fan failure interrupt */
5608 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5609 gpie |= IXGBE_SDP1_GPIEN(hw);
5610
5611 switch (hw->mac.type) {
5612 case ixgbe_mac_82599EB:
5613 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5614 break;
5615 case ixgbe_mac_X550EM_x:
5616 case ixgbe_mac_x550em_a:
5617 gpie |= IXGBE_SDP0_GPIEN_X540;
5618 break;
5619 default:
5620 break;
5621 }
5622
5623 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5624 }
5625
ixgbe_up_complete(struct ixgbe_adapter * adapter)5626 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5627 {
5628 struct ixgbe_hw *hw = &adapter->hw;
5629 int err;
5630 u32 ctrl_ext;
5631
5632 ixgbe_get_hw_control(adapter);
5633 ixgbe_setup_gpie(adapter);
5634
5635 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5636 ixgbe_configure_msix(adapter);
5637 else
5638 ixgbe_configure_msi_and_legacy(adapter);
5639
5640 /* enable the optics for 82599 SFP+ fiber */
5641 if (hw->mac.ops.enable_tx_laser)
5642 hw->mac.ops.enable_tx_laser(hw);
5643
5644 if (hw->phy.ops.set_phy_power)
5645 hw->phy.ops.set_phy_power(hw, true);
5646
5647 smp_mb__before_atomic();
5648 clear_bit(__IXGBE_DOWN, &adapter->state);
5649 ixgbe_napi_enable_all(adapter);
5650
5651 if (ixgbe_is_sfp(hw)) {
5652 ixgbe_sfp_link_config(adapter);
5653 } else {
5654 err = ixgbe_non_sfp_link_config(hw);
5655 if (err)
5656 e_err(probe, "link_config FAILED %d\n", err);
5657 }
5658
5659 /* clear any pending interrupts, may auto mask */
5660 IXGBE_READ_REG(hw, IXGBE_EICR);
5661 ixgbe_irq_enable(adapter, true, true);
5662
5663 /*
5664 * If this adapter has a fan, check to see if we had a failure
5665 * before we enabled the interrupt.
5666 */
5667 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5668 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5669 if (esdp & IXGBE_ESDP_SDP1)
5670 e_crit(drv, "Fan has stopped, replace the adapter\n");
5671 }
5672
5673 /* bring the link up in the watchdog, this could race with our first
5674 * link up interrupt but shouldn't be a problem */
5675 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5676 adapter->link_check_timeout = jiffies;
5677 mod_timer(&adapter->service_timer, jiffies);
5678
5679 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5680 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5681 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5682 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5683 }
5684
ixgbe_reinit_locked(struct ixgbe_adapter * adapter)5685 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5686 {
5687 /* put off any impending NetWatchDogTimeout */
5688 netif_trans_update(adapter->netdev);
5689
5690 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5691 usleep_range(1000, 2000);
5692 if (adapter->hw.phy.type == ixgbe_phy_fw)
5693 ixgbe_watchdog_link_is_down(adapter);
5694 ixgbe_down(adapter);
5695 /*
5696 * If SR-IOV enabled then wait a bit before bringing the adapter
5697 * back up to give the VFs time to respond to the reset. The
5698 * two second wait is based upon the watchdog timer cycle in
5699 * the VF driver.
5700 */
5701 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5702 msleep(2000);
5703 ixgbe_up(adapter);
5704 clear_bit(__IXGBE_RESETTING, &adapter->state);
5705 }
5706
ixgbe_up(struct ixgbe_adapter * adapter)5707 void ixgbe_up(struct ixgbe_adapter *adapter)
5708 {
5709 /* hardware has been reset, we need to reload some things */
5710 ixgbe_configure(adapter);
5711
5712 ixgbe_up_complete(adapter);
5713 }
5714
ixgbe_get_completion_timeout(struct ixgbe_adapter * adapter)5715 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter)
5716 {
5717 u16 devctl2;
5718
5719 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2);
5720
5721 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) {
5722 case IXGBE_PCIDEVCTRL2_17_34s:
5723 case IXGBE_PCIDEVCTRL2_4_8s:
5724 /* For now we cap the upper limit on delay to 2 seconds
5725 * as we end up going up to 34 seconds of delay in worst
5726 * case timeout value.
5727 */
5728 case IXGBE_PCIDEVCTRL2_1_2s:
5729 return 2000000ul; /* 2.0 s */
5730 case IXGBE_PCIDEVCTRL2_260_520ms:
5731 return 520000ul; /* 520 ms */
5732 case IXGBE_PCIDEVCTRL2_65_130ms:
5733 return 130000ul; /* 130 ms */
5734 case IXGBE_PCIDEVCTRL2_16_32ms:
5735 return 32000ul; /* 32 ms */
5736 case IXGBE_PCIDEVCTRL2_1_2ms:
5737 return 2000ul; /* 2 ms */
5738 case IXGBE_PCIDEVCTRL2_50_100us:
5739 return 100ul; /* 100 us */
5740 case IXGBE_PCIDEVCTRL2_16_32ms_def:
5741 return 32000ul; /* 32 ms */
5742 default:
5743 break;
5744 }
5745
5746 /* We shouldn't need to hit this path, but just in case default as
5747 * though completion timeout is not supported and support 32ms.
5748 */
5749 return 32000ul;
5750 }
5751
ixgbe_disable_rx(struct ixgbe_adapter * adapter)5752 void ixgbe_disable_rx(struct ixgbe_adapter *adapter)
5753 {
5754 unsigned long wait_delay, delay_interval;
5755 struct ixgbe_hw *hw = &adapter->hw;
5756 int i, wait_loop;
5757 u32 rxdctl;
5758
5759 /* disable receives */
5760 hw->mac.ops.disable_rx(hw);
5761
5762 if (ixgbe_removed(hw->hw_addr))
5763 return;
5764
5765 /* disable all enabled Rx queues */
5766 for (i = 0; i < adapter->num_rx_queues; i++) {
5767 struct ixgbe_ring *ring = adapter->rx_ring[i];
5768 u8 reg_idx = ring->reg_idx;
5769
5770 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5771 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5772 rxdctl |= IXGBE_RXDCTL_SWFLSH;
5773
5774 /* write value back with RXDCTL.ENABLE bit cleared */
5775 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
5776 }
5777
5778 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
5779 if (hw->mac.type == ixgbe_mac_82598EB &&
5780 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5781 return;
5782
5783 /* Determine our minimum delay interval. We will increase this value
5784 * with each subsequent test. This way if the device returns quickly
5785 * we should spend as little time as possible waiting, however as
5786 * the time increases we will wait for larger periods of time.
5787 *
5788 * The trick here is that we increase the interval using the
5789 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5790 * of that wait is that it totals up to 100x whatever interval we
5791 * choose. Since our minimum wait is 100us we can just divide the
5792 * total timeout by 100 to get our minimum delay interval.
5793 */
5794 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5795
5796 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5797 wait_delay = delay_interval;
5798
5799 while (wait_loop--) {
5800 usleep_range(wait_delay, wait_delay + 10);
5801 wait_delay += delay_interval * 2;
5802 rxdctl = 0;
5803
5804 /* OR together the reading of all the active RXDCTL registers,
5805 * and then test the result. We need the disable to complete
5806 * before we start freeing the memory and invalidating the
5807 * DMA mappings.
5808 */
5809 for (i = 0; i < adapter->num_rx_queues; i++) {
5810 struct ixgbe_ring *ring = adapter->rx_ring[i];
5811 u8 reg_idx = ring->reg_idx;
5812
5813 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5814 }
5815
5816 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
5817 return;
5818 }
5819
5820 e_err(drv,
5821 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5822 }
5823
ixgbe_disable_tx(struct ixgbe_adapter * adapter)5824 void ixgbe_disable_tx(struct ixgbe_adapter *adapter)
5825 {
5826 unsigned long wait_delay, delay_interval;
5827 struct ixgbe_hw *hw = &adapter->hw;
5828 int i, wait_loop;
5829 u32 txdctl;
5830
5831 if (ixgbe_removed(hw->hw_addr))
5832 return;
5833
5834 /* disable all enabled Tx queues */
5835 for (i = 0; i < adapter->num_tx_queues; i++) {
5836 struct ixgbe_ring *ring = adapter->tx_ring[i];
5837 u8 reg_idx = ring->reg_idx;
5838
5839 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5840 }
5841
5842 /* disable all enabled XDP Tx queues */
5843 for (i = 0; i < adapter->num_xdp_queues; i++) {
5844 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5845 u8 reg_idx = ring->reg_idx;
5846
5847 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5848 }
5849
5850 /* If the link is not up there shouldn't be much in the way of
5851 * pending transactions. Those that are left will be flushed out
5852 * when the reset logic goes through the flush sequence to clean out
5853 * the pending Tx transactions.
5854 */
5855 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5856 goto dma_engine_disable;
5857
5858 /* Determine our minimum delay interval. We will increase this value
5859 * with each subsequent test. This way if the device returns quickly
5860 * we should spend as little time as possible waiting, however as
5861 * the time increases we will wait for larger periods of time.
5862 *
5863 * The trick here is that we increase the interval using the
5864 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5865 * of that wait is that it totals up to 100x whatever interval we
5866 * choose. Since our minimum wait is 100us we can just divide the
5867 * total timeout by 100 to get our minimum delay interval.
5868 */
5869 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5870
5871 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5872 wait_delay = delay_interval;
5873
5874 while (wait_loop--) {
5875 usleep_range(wait_delay, wait_delay + 10);
5876 wait_delay += delay_interval * 2;
5877 txdctl = 0;
5878
5879 /* OR together the reading of all the active TXDCTL registers,
5880 * and then test the result. We need the disable to complete
5881 * before we start freeing the memory and invalidating the
5882 * DMA mappings.
5883 */
5884 for (i = 0; i < adapter->num_tx_queues; i++) {
5885 struct ixgbe_ring *ring = adapter->tx_ring[i];
5886 u8 reg_idx = ring->reg_idx;
5887
5888 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5889 }
5890 for (i = 0; i < adapter->num_xdp_queues; i++) {
5891 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5892 u8 reg_idx = ring->reg_idx;
5893
5894 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5895 }
5896
5897 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
5898 goto dma_engine_disable;
5899 }
5900
5901 e_err(drv,
5902 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5903
5904 dma_engine_disable:
5905 /* Disable the Tx DMA engine on 82599 and later MAC */
5906 switch (hw->mac.type) {
5907 case ixgbe_mac_82599EB:
5908 case ixgbe_mac_X540:
5909 case ixgbe_mac_X550:
5910 case ixgbe_mac_X550EM_x:
5911 case ixgbe_mac_x550em_a:
5912 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5913 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5914 ~IXGBE_DMATXCTL_TE));
5915 fallthrough;
5916 default:
5917 break;
5918 }
5919 }
5920
ixgbe_reset(struct ixgbe_adapter * adapter)5921 void ixgbe_reset(struct ixgbe_adapter *adapter)
5922 {
5923 struct ixgbe_hw *hw = &adapter->hw;
5924 struct net_device *netdev = adapter->netdev;
5925 int err;
5926
5927 if (ixgbe_removed(hw->hw_addr))
5928 return;
5929 /* lock SFP init bit to prevent race conditions with the watchdog */
5930 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5931 usleep_range(1000, 2000);
5932
5933 /* clear all SFP and link config related flags while holding SFP_INIT */
5934 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5935 IXGBE_FLAG2_SFP_NEEDS_RESET);
5936 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5937
5938 err = hw->mac.ops.init_hw(hw);
5939 switch (err) {
5940 case 0:
5941 case -ENOENT:
5942 case -EOPNOTSUPP:
5943 break;
5944 case -EALREADY:
5945 e_dev_err("primary disable timed out\n");
5946 break;
5947 case -EACCES:
5948 /* We are running on a pre-production device, log a warning */
5949 e_dev_warn("This device is a pre-production adapter/LOM. "
5950 "Please be aware there may be issues associated with "
5951 "your hardware. If you are experiencing problems "
5952 "please contact your Intel or hardware "
5953 "representative who provided you with this "
5954 "hardware.\n");
5955 break;
5956 default:
5957 e_dev_err("Hardware Error: %d\n", err);
5958 }
5959
5960 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5961
5962 /* flush entries out of MAC table */
5963 ixgbe_flush_sw_mac_table(adapter);
5964 __dev_uc_unsync(netdev, NULL);
5965
5966 /* do not flush user set addresses */
5967 ixgbe_mac_set_default_filter(adapter);
5968
5969 /* update SAN MAC vmdq pool selection */
5970 if (hw->mac.san_mac_rar_index)
5971 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5972
5973 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5974 ixgbe_ptp_reset(adapter);
5975
5976 if (hw->phy.ops.set_phy_power) {
5977 if (!netif_running(adapter->netdev) && !adapter->wol)
5978 hw->phy.ops.set_phy_power(hw, false);
5979 else
5980 hw->phy.ops.set_phy_power(hw, true);
5981 }
5982 }
5983
5984 /**
5985 * ixgbe_clean_tx_ring - Free Tx Buffers
5986 * @tx_ring: ring to be cleaned
5987 **/
ixgbe_clean_tx_ring(struct ixgbe_ring * tx_ring)5988 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5989 {
5990 u16 i = tx_ring->next_to_clean;
5991 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
5992
5993 if (tx_ring->xsk_pool) {
5994 ixgbe_xsk_clean_tx_ring(tx_ring);
5995 goto out;
5996 }
5997
5998 while (i != tx_ring->next_to_use) {
5999 union ixgbe_adv_tx_desc *eop_desc, *tx_desc;
6000
6001 /* Free all the Tx ring sk_buffs */
6002 if (ring_is_xdp(tx_ring))
6003 xdp_return_frame(tx_buffer->xdpf);
6004 else
6005 dev_kfree_skb_any(tx_buffer->skb);
6006
6007 /* unmap skb header data */
6008 dma_unmap_single(tx_ring->dev,
6009 dma_unmap_addr(tx_buffer, dma),
6010 dma_unmap_len(tx_buffer, len),
6011 DMA_TO_DEVICE);
6012
6013 /* check for eop_desc to determine the end of the packet */
6014 eop_desc = tx_buffer->next_to_watch;
6015 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6016
6017 /* unmap remaining buffers */
6018 while (tx_desc != eop_desc) {
6019 tx_buffer++;
6020 tx_desc++;
6021 i++;
6022 if (unlikely(i == tx_ring->count)) {
6023 i = 0;
6024 tx_buffer = tx_ring->tx_buffer_info;
6025 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6026 }
6027
6028 /* unmap any remaining paged data */
6029 if (dma_unmap_len(tx_buffer, len))
6030 dma_unmap_page(tx_ring->dev,
6031 dma_unmap_addr(tx_buffer, dma),
6032 dma_unmap_len(tx_buffer, len),
6033 DMA_TO_DEVICE);
6034 }
6035
6036 /* move us one more past the eop_desc for start of next pkt */
6037 tx_buffer++;
6038 i++;
6039 if (unlikely(i == tx_ring->count)) {
6040 i = 0;
6041 tx_buffer = tx_ring->tx_buffer_info;
6042 }
6043 }
6044
6045 /* reset BQL for queue */
6046 if (!ring_is_xdp(tx_ring))
6047 netdev_tx_reset_queue(txring_txq(tx_ring));
6048
6049 out:
6050 /* reset next_to_use and next_to_clean */
6051 tx_ring->next_to_use = 0;
6052 tx_ring->next_to_clean = 0;
6053 }
6054
6055 /**
6056 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
6057 * @adapter: board private structure
6058 **/
ixgbe_clean_all_rx_rings(struct ixgbe_adapter * adapter)6059 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
6060 {
6061 int i;
6062
6063 for (i = 0; i < adapter->num_rx_queues; i++)
6064 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
6065 }
6066
6067 /**
6068 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
6069 * @adapter: board private structure
6070 **/
ixgbe_clean_all_tx_rings(struct ixgbe_adapter * adapter)6071 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
6072 {
6073 int i;
6074
6075 for (i = 0; i < adapter->num_tx_queues; i++)
6076 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
6077 for (i = 0; i < adapter->num_xdp_queues; i++)
6078 ixgbe_clean_tx_ring(adapter->xdp_ring[i]);
6079 }
6080
ixgbe_fdir_filter_exit(struct ixgbe_adapter * adapter)6081 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
6082 {
6083 struct hlist_node *node2;
6084 struct ixgbe_fdir_filter *filter;
6085
6086 spin_lock(&adapter->fdir_perfect_lock);
6087
6088 hlist_for_each_entry_safe(filter, node2,
6089 &adapter->fdir_filter_list, fdir_node) {
6090 hlist_del(&filter->fdir_node);
6091 kfree(filter);
6092 }
6093 adapter->fdir_filter_count = 0;
6094
6095 spin_unlock(&adapter->fdir_perfect_lock);
6096 }
6097
ixgbe_down(struct ixgbe_adapter * adapter)6098 void ixgbe_down(struct ixgbe_adapter *adapter)
6099 {
6100 struct net_device *netdev = adapter->netdev;
6101 struct ixgbe_hw *hw = &adapter->hw;
6102 int i;
6103
6104 /* signal that we are down to the interrupt handler */
6105 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
6106 return; /* do nothing if already down */
6107
6108 /* Shut off incoming Tx traffic */
6109 netif_tx_stop_all_queues(netdev);
6110
6111 /* call carrier off first to avoid false dev_watchdog timeouts */
6112 netif_carrier_off(netdev);
6113 netif_tx_disable(netdev);
6114
6115 /* Disable Rx */
6116 ixgbe_disable_rx(adapter);
6117
6118 /* synchronize_rcu() needed for pending XDP buffers to drain */
6119 if (adapter->xdp_ring[0])
6120 synchronize_rcu();
6121
6122 ixgbe_irq_disable(adapter);
6123
6124 ixgbe_napi_disable_all(adapter);
6125
6126 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
6127 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6128 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6129
6130 del_timer_sync(&adapter->service_timer);
6131
6132 if (adapter->num_vfs) {
6133 /* Clear EITR Select mapping */
6134 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
6135
6136 /* Mark all the VFs as inactive */
6137 for (i = 0 ; i < adapter->num_vfs; i++)
6138 adapter->vfinfo[i].clear_to_send = false;
6139
6140 /* ping all the active vfs to let them know we are going down */
6141 ixgbe_ping_all_vfs(adapter);
6142
6143 /* Disable all VFTE/VFRE TX/RX */
6144 ixgbe_disable_tx_rx(adapter);
6145 }
6146
6147 /* disable transmits in the hardware now that interrupts are off */
6148 ixgbe_disable_tx(adapter);
6149
6150 if (!pci_channel_offline(adapter->pdev))
6151 ixgbe_reset(adapter);
6152
6153 /* power down the optics for 82599 SFP+ fiber */
6154 if (hw->mac.ops.disable_tx_laser)
6155 hw->mac.ops.disable_tx_laser(hw);
6156
6157 ixgbe_clean_all_tx_rings(adapter);
6158 ixgbe_clean_all_rx_rings(adapter);
6159 }
6160
6161 /**
6162 * ixgbe_set_eee_capable - helper function to determine EEE support on X550
6163 * @adapter: board private structure
6164 */
ixgbe_set_eee_capable(struct ixgbe_adapter * adapter)6165 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
6166 {
6167 struct ixgbe_hw *hw = &adapter->hw;
6168
6169 switch (hw->device_id) {
6170 case IXGBE_DEV_ID_X550EM_A_1G_T:
6171 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6172 if (!hw->phy.eee_speeds_supported)
6173 break;
6174 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
6175 if (!hw->phy.eee_speeds_advertised)
6176 break;
6177 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
6178 break;
6179 default:
6180 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
6181 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
6182 break;
6183 }
6184 }
6185
6186 /**
6187 * ixgbe_tx_timeout - Respond to a Tx Hang
6188 * @netdev: network interface device structure
6189 * @txqueue: queue number that timed out
6190 **/
ixgbe_tx_timeout(struct net_device * netdev,unsigned int __always_unused txqueue)6191 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6192 {
6193 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6194
6195 /* Do the reset outside of interrupt context */
6196 ixgbe_tx_timeout_reset(adapter);
6197 }
6198
6199 #ifdef CONFIG_IXGBE_DCB
ixgbe_init_dcb(struct ixgbe_adapter * adapter)6200 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
6201 {
6202 struct ixgbe_hw *hw = &adapter->hw;
6203 struct tc_configuration *tc;
6204 int j;
6205
6206 switch (hw->mac.type) {
6207 case ixgbe_mac_82598EB:
6208 case ixgbe_mac_82599EB:
6209 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
6210 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
6211 break;
6212 case ixgbe_mac_X540:
6213 case ixgbe_mac_X550:
6214 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
6215 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
6216 break;
6217 case ixgbe_mac_X550EM_x:
6218 case ixgbe_mac_x550em_a:
6219 default:
6220 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
6221 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
6222 break;
6223 }
6224
6225 /* Configure DCB traffic classes */
6226 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
6227 tc = &adapter->dcb_cfg.tc_config[j];
6228 tc->path[DCB_TX_CONFIG].bwg_id = 0;
6229 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
6230 tc->path[DCB_RX_CONFIG].bwg_id = 0;
6231 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
6232 tc->dcb_pfc = pfc_disabled;
6233 }
6234
6235 /* Initialize default user to priority mapping, UPx->TC0 */
6236 tc = &adapter->dcb_cfg.tc_config[0];
6237 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
6238 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
6239
6240 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
6241 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
6242 adapter->dcb_cfg.pfc_mode_enable = false;
6243 adapter->dcb_set_bitmap = 0x00;
6244 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
6245 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
6246 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
6247 sizeof(adapter->temp_dcb_cfg));
6248 }
6249 #endif
6250
6251 /**
6252 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
6253 * @adapter: board private structure to initialize
6254 * @ii: pointer to ixgbe_info for device
6255 *
6256 * ixgbe_sw_init initializes the Adapter private data structure.
6257 * Fields are initialized based on PCI device information and
6258 * OS network device settings (MTU size).
6259 **/
ixgbe_sw_init(struct ixgbe_adapter * adapter,const struct ixgbe_info * ii)6260 static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
6261 const struct ixgbe_info *ii)
6262 {
6263 struct ixgbe_hw *hw = &adapter->hw;
6264 struct pci_dev *pdev = adapter->pdev;
6265 unsigned int rss, fdir;
6266 u32 fwsm;
6267 int i;
6268
6269 /* PCI config space info */
6270
6271 hw->vendor_id = pdev->vendor;
6272 hw->device_id = pdev->device;
6273 hw->revision_id = pdev->revision;
6274 hw->subsystem_vendor_id = pdev->subsystem_vendor;
6275 hw->subsystem_device_id = pdev->subsystem_device;
6276
6277 /* get_invariants needs the device IDs */
6278 ii->get_invariants(hw);
6279
6280 /* Set common capability flags and settings */
6281 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
6282 adapter->ring_feature[RING_F_RSS].limit = rss;
6283 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
6284 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
6285 adapter->atr_sample_rate = 20;
6286 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
6287 adapter->ring_feature[RING_F_FDIR].limit = fdir;
6288 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
6289 adapter->ring_feature[RING_F_VMDQ].limit = 1;
6290 #ifdef CONFIG_IXGBE_DCA
6291 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
6292 #endif
6293 #ifdef CONFIG_IXGBE_DCB
6294 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
6295 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6296 #endif
6297 #ifdef IXGBE_FCOE
6298 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
6299 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6300 #ifdef CONFIG_IXGBE_DCB
6301 /* Default traffic class to use for FCoE */
6302 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
6303 #endif /* CONFIG_IXGBE_DCB */
6304 #endif /* IXGBE_FCOE */
6305
6306 /* initialize static ixgbe jump table entries */
6307 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
6308 GFP_KERNEL);
6309 if (!adapter->jump_tables[0])
6310 return -ENOMEM;
6311 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
6312
6313 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
6314 adapter->jump_tables[i] = NULL;
6315
6316 adapter->mac_table = kcalloc(hw->mac.num_rar_entries,
6317 sizeof(struct ixgbe_mac_addr),
6318 GFP_KERNEL);
6319 if (!adapter->mac_table)
6320 return -ENOMEM;
6321
6322 if (ixgbe_init_rss_key(adapter))
6323 return -ENOMEM;
6324
6325 adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL);
6326 if (!adapter->af_xdp_zc_qps)
6327 return -ENOMEM;
6328
6329 /* Set MAC specific capability flags and exceptions */
6330 switch (hw->mac.type) {
6331 case ixgbe_mac_82598EB:
6332 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
6333
6334 if (hw->device_id == IXGBE_DEV_ID_82598AT)
6335 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
6336
6337 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
6338 adapter->ring_feature[RING_F_FDIR].limit = 0;
6339 adapter->atr_sample_rate = 0;
6340 adapter->fdir_pballoc = 0;
6341 #ifdef IXGBE_FCOE
6342 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6343 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6344 #ifdef CONFIG_IXGBE_DCB
6345 adapter->fcoe.up = 0;
6346 #endif /* IXGBE_DCB */
6347 #endif /* IXGBE_FCOE */
6348 break;
6349 case ixgbe_mac_82599EB:
6350 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
6351 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6352 break;
6353 case ixgbe_mac_X540:
6354 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
6355 if (fwsm & IXGBE_FWSM_TS_ENABLED)
6356 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6357 break;
6358 case ixgbe_mac_x550em_a:
6359 switch (hw->device_id) {
6360 case IXGBE_DEV_ID_X550EM_A_1G_T:
6361 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6362 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6363 break;
6364 default:
6365 break;
6366 }
6367 fallthrough;
6368 case ixgbe_mac_X550EM_x:
6369 #ifdef CONFIG_IXGBE_DCB
6370 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
6371 #endif
6372 #ifdef IXGBE_FCOE
6373 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6374 #ifdef CONFIG_IXGBE_DCB
6375 adapter->fcoe.up = 0;
6376 #endif /* IXGBE_DCB */
6377 #endif /* IXGBE_FCOE */
6378 fallthrough;
6379 case ixgbe_mac_X550:
6380 if (hw->mac.type == ixgbe_mac_X550)
6381 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6382 #ifdef CONFIG_IXGBE_DCA
6383 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
6384 #endif
6385 break;
6386 default:
6387 break;
6388 }
6389
6390 #ifdef IXGBE_FCOE
6391 /* FCoE support exists, always init the FCoE lock */
6392 spin_lock_init(&adapter->fcoe.lock);
6393
6394 #endif
6395 /* n-tuple support exists, always init our spinlock */
6396 spin_lock_init(&adapter->fdir_perfect_lock);
6397
6398 /* init spinlock to avoid concurrency of VF resources */
6399 spin_lock_init(&adapter->vfs_lock);
6400
6401 #ifdef CONFIG_IXGBE_DCB
6402 ixgbe_init_dcb(adapter);
6403 #endif
6404 ixgbe_init_ipsec_offload(adapter);
6405
6406 /* default flow control settings */
6407 hw->fc.requested_mode = ixgbe_fc_full;
6408 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
6409 ixgbe_pbthresh_setup(adapter);
6410 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
6411 hw->fc.send_xon = true;
6412 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
6413
6414 #ifdef CONFIG_PCI_IOV
6415 if (max_vfs > 0)
6416 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
6417
6418 /* assign number of SR-IOV VFs */
6419 if (hw->mac.type != ixgbe_mac_82598EB) {
6420 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
6421 max_vfs = 0;
6422 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
6423 }
6424 }
6425 #endif /* CONFIG_PCI_IOV */
6426
6427 /* enable itr by default in dynamic mode */
6428 adapter->rx_itr_setting = 1;
6429 adapter->tx_itr_setting = 1;
6430
6431 /* set default ring sizes */
6432 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
6433 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
6434
6435 /* set default work limits */
6436 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
6437
6438 /* initialize eeprom parameters */
6439 if (ixgbe_init_eeprom_params_generic(hw)) {
6440 e_dev_err("EEPROM initialization failed\n");
6441 return -EIO;
6442 }
6443
6444 /* PF holds first pool slot */
6445 set_bit(0, adapter->fwd_bitmask);
6446 set_bit(__IXGBE_DOWN, &adapter->state);
6447
6448 return 0;
6449 }
6450
6451 /**
6452 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
6453 * @tx_ring: tx descriptor ring (for a specific queue) to setup
6454 *
6455 * Return 0 on success, negative on failure
6456 **/
ixgbe_setup_tx_resources(struct ixgbe_ring * tx_ring)6457 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
6458 {
6459 struct device *dev = tx_ring->dev;
6460 int orig_node = dev_to_node(dev);
6461 int ring_node = NUMA_NO_NODE;
6462 int size;
6463
6464 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
6465
6466 if (tx_ring->q_vector)
6467 ring_node = tx_ring->q_vector->numa_node;
6468
6469 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node);
6470 if (!tx_ring->tx_buffer_info)
6471 tx_ring->tx_buffer_info = vmalloc(size);
6472 if (!tx_ring->tx_buffer_info)
6473 goto err;
6474
6475 /* round up to nearest 4K */
6476 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
6477 tx_ring->size = ALIGN(tx_ring->size, 4096);
6478
6479 set_dev_node(dev, ring_node);
6480 tx_ring->desc = dma_alloc_coherent(dev,
6481 tx_ring->size,
6482 &tx_ring->dma,
6483 GFP_KERNEL);
6484 set_dev_node(dev, orig_node);
6485 if (!tx_ring->desc)
6486 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
6487 &tx_ring->dma, GFP_KERNEL);
6488 if (!tx_ring->desc)
6489 goto err;
6490
6491 tx_ring->next_to_use = 0;
6492 tx_ring->next_to_clean = 0;
6493 return 0;
6494
6495 err:
6496 vfree(tx_ring->tx_buffer_info);
6497 tx_ring->tx_buffer_info = NULL;
6498 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
6499 return -ENOMEM;
6500 }
6501
6502 /**
6503 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6504 * @adapter: board private structure
6505 *
6506 * If this function returns with an error, then it's possible one or
6507 * more of the rings is populated (while the rest are not). It is the
6508 * callers duty to clean those orphaned rings.
6509 *
6510 * Return 0 on success, negative on failure
6511 **/
ixgbe_setup_all_tx_resources(struct ixgbe_adapter * adapter)6512 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6513 {
6514 int i, j = 0, err = 0;
6515
6516 for (i = 0; i < adapter->num_tx_queues; i++) {
6517 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
6518 if (!err)
6519 continue;
6520
6521 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
6522 goto err_setup_tx;
6523 }
6524 for (j = 0; j < adapter->num_xdp_queues; j++) {
6525 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]);
6526 if (!err)
6527 continue;
6528
6529 e_err(probe, "Allocation for Tx Queue %u failed\n", j);
6530 goto err_setup_tx;
6531 }
6532
6533 return 0;
6534 err_setup_tx:
6535 /* rewind the index freeing the rings as we go */
6536 while (j--)
6537 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
6538 while (i--)
6539 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6540 return err;
6541 }
6542
ixgbe_rx_napi_id(struct ixgbe_ring * rx_ring)6543 static int ixgbe_rx_napi_id(struct ixgbe_ring *rx_ring)
6544 {
6545 struct ixgbe_q_vector *q_vector = rx_ring->q_vector;
6546
6547 return q_vector ? q_vector->napi.napi_id : 0;
6548 }
6549
6550 /**
6551 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
6552 * @adapter: pointer to ixgbe_adapter
6553 * @rx_ring: rx descriptor ring (for a specific queue) to setup
6554 *
6555 * Returns 0 on success, negative on failure
6556 **/
ixgbe_setup_rx_resources(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring)6557 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
6558 struct ixgbe_ring *rx_ring)
6559 {
6560 struct device *dev = rx_ring->dev;
6561 int orig_node = dev_to_node(dev);
6562 int ring_node = NUMA_NO_NODE;
6563 int size;
6564
6565 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
6566
6567 if (rx_ring->q_vector)
6568 ring_node = rx_ring->q_vector->numa_node;
6569
6570 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node);
6571 if (!rx_ring->rx_buffer_info)
6572 rx_ring->rx_buffer_info = vmalloc(size);
6573 if (!rx_ring->rx_buffer_info)
6574 goto err;
6575
6576 /* Round up to nearest 4K */
6577 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6578 rx_ring->size = ALIGN(rx_ring->size, 4096);
6579
6580 set_dev_node(dev, ring_node);
6581 rx_ring->desc = dma_alloc_coherent(dev,
6582 rx_ring->size,
6583 &rx_ring->dma,
6584 GFP_KERNEL);
6585 set_dev_node(dev, orig_node);
6586 if (!rx_ring->desc)
6587 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6588 &rx_ring->dma, GFP_KERNEL);
6589 if (!rx_ring->desc)
6590 goto err;
6591
6592 rx_ring->next_to_clean = 0;
6593 rx_ring->next_to_use = 0;
6594
6595 /* XDP RX-queue info */
6596 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev,
6597 rx_ring->queue_index, ixgbe_rx_napi_id(rx_ring)) < 0)
6598 goto err;
6599
6600 rx_ring->xdp_prog = adapter->xdp_prog;
6601
6602 return 0;
6603 err:
6604 vfree(rx_ring->rx_buffer_info);
6605 rx_ring->rx_buffer_info = NULL;
6606 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
6607 return -ENOMEM;
6608 }
6609
6610 /**
6611 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6612 * @adapter: board private structure
6613 *
6614 * If this function returns with an error, then it's possible one or
6615 * more of the rings is populated (while the rest are not). It is the
6616 * callers duty to clean those orphaned rings.
6617 *
6618 * Return 0 on success, negative on failure
6619 **/
ixgbe_setup_all_rx_resources(struct ixgbe_adapter * adapter)6620 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6621 {
6622 int i, err = 0;
6623
6624 for (i = 0; i < adapter->num_rx_queues; i++) {
6625 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
6626 if (!err)
6627 continue;
6628
6629 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
6630 goto err_setup_rx;
6631 }
6632
6633 #ifdef IXGBE_FCOE
6634 err = ixgbe_setup_fcoe_ddp_resources(adapter);
6635 if (!err)
6636 #endif
6637 return 0;
6638 err_setup_rx:
6639 /* rewind the index freeing the rings as we go */
6640 while (i--)
6641 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6642 return err;
6643 }
6644
6645 /**
6646 * ixgbe_free_tx_resources - Free Tx Resources per Queue
6647 * @tx_ring: Tx descriptor ring for a specific queue
6648 *
6649 * Free all transmit software resources
6650 **/
ixgbe_free_tx_resources(struct ixgbe_ring * tx_ring)6651 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
6652 {
6653 ixgbe_clean_tx_ring(tx_ring);
6654
6655 vfree(tx_ring->tx_buffer_info);
6656 tx_ring->tx_buffer_info = NULL;
6657
6658 /* if not set, then don't free */
6659 if (!tx_ring->desc)
6660 return;
6661
6662 dma_free_coherent(tx_ring->dev, tx_ring->size,
6663 tx_ring->desc, tx_ring->dma);
6664
6665 tx_ring->desc = NULL;
6666 }
6667
6668 /**
6669 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6670 * @adapter: board private structure
6671 *
6672 * Free all transmit software resources
6673 **/
ixgbe_free_all_tx_resources(struct ixgbe_adapter * adapter)6674 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6675 {
6676 int i;
6677
6678 for (i = 0; i < adapter->num_tx_queues; i++)
6679 if (adapter->tx_ring[i]->desc)
6680 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6681 for (i = 0; i < adapter->num_xdp_queues; i++)
6682 if (adapter->xdp_ring[i]->desc)
6683 ixgbe_free_tx_resources(adapter->xdp_ring[i]);
6684 }
6685
6686 /**
6687 * ixgbe_free_rx_resources - Free Rx Resources
6688 * @rx_ring: ring to clean the resources from
6689 *
6690 * Free all receive software resources
6691 **/
ixgbe_free_rx_resources(struct ixgbe_ring * rx_ring)6692 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
6693 {
6694 ixgbe_clean_rx_ring(rx_ring);
6695
6696 rx_ring->xdp_prog = NULL;
6697 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
6698 vfree(rx_ring->rx_buffer_info);
6699 rx_ring->rx_buffer_info = NULL;
6700
6701 /* if not set, then don't free */
6702 if (!rx_ring->desc)
6703 return;
6704
6705 dma_free_coherent(rx_ring->dev, rx_ring->size,
6706 rx_ring->desc, rx_ring->dma);
6707
6708 rx_ring->desc = NULL;
6709 }
6710
6711 /**
6712 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6713 * @adapter: board private structure
6714 *
6715 * Free all receive software resources
6716 **/
ixgbe_free_all_rx_resources(struct ixgbe_adapter * adapter)6717 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6718 {
6719 int i;
6720
6721 #ifdef IXGBE_FCOE
6722 ixgbe_free_fcoe_ddp_resources(adapter);
6723
6724 #endif
6725 for (i = 0; i < adapter->num_rx_queues; i++)
6726 if (adapter->rx_ring[i]->desc)
6727 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6728 }
6729
6730 /**
6731 * ixgbe_max_xdp_frame_size - returns the maximum allowed frame size for XDP
6732 * @adapter: device handle, pointer to adapter
6733 */
ixgbe_max_xdp_frame_size(struct ixgbe_adapter * adapter)6734 static int ixgbe_max_xdp_frame_size(struct ixgbe_adapter *adapter)
6735 {
6736 if (PAGE_SIZE >= 8192 || adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
6737 return IXGBE_RXBUFFER_2K;
6738 else
6739 return IXGBE_RXBUFFER_3K;
6740 }
6741
6742 /**
6743 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6744 * @netdev: network interface device structure
6745 * @new_mtu: new value for maximum frame size
6746 *
6747 * Returns 0 on success, negative on failure
6748 **/
ixgbe_change_mtu(struct net_device * netdev,int new_mtu)6749 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6750 {
6751 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6752
6753 if (ixgbe_enabled_xdp_adapter(adapter)) {
6754 int new_frame_size = new_mtu + IXGBE_PKT_HDR_PAD;
6755
6756 if (new_frame_size > ixgbe_max_xdp_frame_size(adapter)) {
6757 e_warn(probe, "Requested MTU size is not supported with XDP\n");
6758 return -EINVAL;
6759 }
6760 }
6761
6762 /*
6763 * For 82599EB we cannot allow legacy VFs to enable their receive
6764 * paths when MTU greater than 1500 is configured. So display a
6765 * warning that legacy VFs will be disabled.
6766 */
6767 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6768 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
6769 (new_mtu > ETH_DATA_LEN))
6770 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
6771
6772 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6773 netdev->mtu, new_mtu);
6774
6775 /* must set new MTU before calling down or up */
6776 netdev->mtu = new_mtu;
6777
6778 if (netif_running(netdev))
6779 ixgbe_reinit_locked(adapter);
6780
6781 return 0;
6782 }
6783
6784 /**
6785 * ixgbe_open - Called when a network interface is made active
6786 * @netdev: network interface device structure
6787 *
6788 * Returns 0 on success, negative value on failure
6789 *
6790 * The open entry point is called when a network interface is made
6791 * active by the system (IFF_UP). At this point all resources needed
6792 * for transmit and receive operations are allocated, the interrupt
6793 * handler is registered with the OS, the watchdog timer is started,
6794 * and the stack is notified that the interface is ready.
6795 **/
ixgbe_open(struct net_device * netdev)6796 int ixgbe_open(struct net_device *netdev)
6797 {
6798 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6799 struct ixgbe_hw *hw = &adapter->hw;
6800 int err, queues;
6801
6802 /* disallow open during test */
6803 if (test_bit(__IXGBE_TESTING, &adapter->state))
6804 return -EBUSY;
6805
6806 netif_carrier_off(netdev);
6807
6808 /* allocate transmit descriptors */
6809 err = ixgbe_setup_all_tx_resources(adapter);
6810 if (err)
6811 goto err_setup_tx;
6812
6813 /* allocate receive descriptors */
6814 err = ixgbe_setup_all_rx_resources(adapter);
6815 if (err)
6816 goto err_setup_rx;
6817
6818 ixgbe_configure(adapter);
6819
6820 err = ixgbe_request_irq(adapter);
6821 if (err)
6822 goto err_req_irq;
6823
6824 /* Notify the stack of the actual queue counts. */
6825 queues = adapter->num_tx_queues;
6826 err = netif_set_real_num_tx_queues(netdev, queues);
6827 if (err)
6828 goto err_set_queues;
6829
6830 queues = adapter->num_rx_queues;
6831 err = netif_set_real_num_rx_queues(netdev, queues);
6832 if (err)
6833 goto err_set_queues;
6834
6835 ixgbe_ptp_init(adapter);
6836
6837 ixgbe_up_complete(adapter);
6838
6839 udp_tunnel_nic_reset_ntf(netdev);
6840
6841 return 0;
6842
6843 err_set_queues:
6844 ixgbe_free_irq(adapter);
6845 err_req_irq:
6846 ixgbe_free_all_rx_resources(adapter);
6847 if (hw->phy.ops.set_phy_power && !adapter->wol)
6848 hw->phy.ops.set_phy_power(&adapter->hw, false);
6849 err_setup_rx:
6850 ixgbe_free_all_tx_resources(adapter);
6851 err_setup_tx:
6852 ixgbe_reset(adapter);
6853
6854 return err;
6855 }
6856
ixgbe_close_suspend(struct ixgbe_adapter * adapter)6857 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6858 {
6859 ixgbe_ptp_suspend(adapter);
6860
6861 if (adapter->hw.phy.ops.enter_lplu) {
6862 adapter->hw.phy.reset_disable = true;
6863 ixgbe_down(adapter);
6864 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6865 adapter->hw.phy.reset_disable = false;
6866 } else {
6867 ixgbe_down(adapter);
6868 }
6869
6870 ixgbe_free_irq(adapter);
6871
6872 ixgbe_free_all_tx_resources(adapter);
6873 ixgbe_free_all_rx_resources(adapter);
6874 }
6875
6876 /**
6877 * ixgbe_close - Disables a network interface
6878 * @netdev: network interface device structure
6879 *
6880 * Returns 0, this is not allowed to fail
6881 *
6882 * The close entry point is called when an interface is de-activated
6883 * by the OS. The hardware is still under the drivers control, but
6884 * needs to be disabled. A global MAC reset is issued to stop the
6885 * hardware, and all transmit and receive resources are freed.
6886 **/
ixgbe_close(struct net_device * netdev)6887 int ixgbe_close(struct net_device *netdev)
6888 {
6889 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6890
6891 ixgbe_ptp_stop(adapter);
6892
6893 if (netif_device_present(netdev))
6894 ixgbe_close_suspend(adapter);
6895
6896 ixgbe_fdir_filter_exit(adapter);
6897
6898 ixgbe_release_hw_control(adapter);
6899
6900 return 0;
6901 }
6902
ixgbe_resume(struct device * dev_d)6903 static int __maybe_unused ixgbe_resume(struct device *dev_d)
6904 {
6905 struct pci_dev *pdev = to_pci_dev(dev_d);
6906 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6907 struct net_device *netdev = adapter->netdev;
6908 u32 err;
6909
6910 adapter->hw.hw_addr = adapter->io_addr;
6911
6912 err = pci_enable_device_mem(pdev);
6913 if (err) {
6914 e_dev_err("Cannot enable PCI device from suspend\n");
6915 return err;
6916 }
6917 smp_mb__before_atomic();
6918 clear_bit(__IXGBE_DISABLED, &adapter->state);
6919 pci_set_master(pdev);
6920
6921 device_wakeup_disable(dev_d);
6922
6923 ixgbe_reset(adapter);
6924
6925 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6926
6927 rtnl_lock();
6928 err = ixgbe_init_interrupt_scheme(adapter);
6929 if (!err && netif_running(netdev))
6930 err = ixgbe_open(netdev);
6931
6932
6933 if (!err)
6934 netif_device_attach(netdev);
6935 rtnl_unlock();
6936
6937 return err;
6938 }
6939
__ixgbe_shutdown(struct pci_dev * pdev,bool * enable_wake)6940 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
6941 {
6942 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6943 struct net_device *netdev = adapter->netdev;
6944 struct ixgbe_hw *hw = &adapter->hw;
6945 u32 ctrl;
6946 u32 wufc = adapter->wol;
6947
6948 rtnl_lock();
6949 netif_device_detach(netdev);
6950
6951 if (netif_running(netdev))
6952 ixgbe_close_suspend(adapter);
6953
6954 ixgbe_clear_interrupt_scheme(adapter);
6955 rtnl_unlock();
6956
6957 if (hw->mac.ops.stop_link_on_d3)
6958 hw->mac.ops.stop_link_on_d3(hw);
6959
6960 if (wufc) {
6961 u32 fctrl;
6962
6963 ixgbe_set_rx_mode(netdev);
6964
6965 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6966 if (hw->mac.ops.enable_tx_laser)
6967 hw->mac.ops.enable_tx_laser(hw);
6968
6969 /* enable the reception of multicast packets */
6970 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6971 fctrl |= IXGBE_FCTRL_MPE;
6972 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6973
6974 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6975 ctrl |= IXGBE_CTRL_GIO_DIS;
6976 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6977
6978 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6979 } else {
6980 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6981 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6982 }
6983
6984 switch (hw->mac.type) {
6985 case ixgbe_mac_82598EB:
6986 pci_wake_from_d3(pdev, false);
6987 break;
6988 case ixgbe_mac_82599EB:
6989 case ixgbe_mac_X540:
6990 case ixgbe_mac_X550:
6991 case ixgbe_mac_X550EM_x:
6992 case ixgbe_mac_x550em_a:
6993 pci_wake_from_d3(pdev, !!wufc);
6994 break;
6995 default:
6996 break;
6997 }
6998
6999 *enable_wake = !!wufc;
7000 if (hw->phy.ops.set_phy_power && !*enable_wake)
7001 hw->phy.ops.set_phy_power(hw, false);
7002
7003 ixgbe_release_hw_control(adapter);
7004
7005 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
7006 pci_disable_device(pdev);
7007
7008 return 0;
7009 }
7010
ixgbe_suspend(struct device * dev_d)7011 static int __maybe_unused ixgbe_suspend(struct device *dev_d)
7012 {
7013 struct pci_dev *pdev = to_pci_dev(dev_d);
7014 int retval;
7015 bool wake;
7016
7017 retval = __ixgbe_shutdown(pdev, &wake);
7018
7019 device_set_wakeup_enable(dev_d, wake);
7020
7021 return retval;
7022 }
7023
ixgbe_shutdown(struct pci_dev * pdev)7024 static void ixgbe_shutdown(struct pci_dev *pdev)
7025 {
7026 bool wake;
7027
7028 __ixgbe_shutdown(pdev, &wake);
7029
7030 if (system_state == SYSTEM_POWER_OFF) {
7031 pci_wake_from_d3(pdev, wake);
7032 pci_set_power_state(pdev, PCI_D3hot);
7033 }
7034 }
7035
7036 /**
7037 * ixgbe_update_stats - Update the board statistics counters.
7038 * @adapter: board private structure
7039 **/
ixgbe_update_stats(struct ixgbe_adapter * adapter)7040 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
7041 {
7042 struct net_device *netdev = adapter->netdev;
7043 struct ixgbe_hw *hw = &adapter->hw;
7044 struct ixgbe_hw_stats *hwstats = &adapter->stats;
7045 u64 total_mpc = 0;
7046 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
7047 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
7048 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
7049 u64 alloc_rx_page = 0;
7050 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7051
7052 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7053 test_bit(__IXGBE_RESETTING, &adapter->state))
7054 return;
7055
7056 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
7057 u64 rsc_count = 0;
7058 u64 rsc_flush = 0;
7059 for (i = 0; i < adapter->num_rx_queues; i++) {
7060 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
7061 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
7062 }
7063 adapter->rsc_total_count = rsc_count;
7064 adapter->rsc_total_flush = rsc_flush;
7065 }
7066
7067 for (i = 0; i < adapter->num_rx_queues; i++) {
7068 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]);
7069
7070 if (!rx_ring)
7071 continue;
7072 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
7073 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page;
7074 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
7075 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
7076 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
7077 bytes += rx_ring->stats.bytes;
7078 packets += rx_ring->stats.packets;
7079 }
7080 adapter->non_eop_descs = non_eop_descs;
7081 adapter->alloc_rx_page = alloc_rx_page;
7082 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
7083 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
7084 adapter->hw_csum_rx_error = hw_csum_rx_error;
7085 netdev->stats.rx_bytes = bytes;
7086 netdev->stats.rx_packets = packets;
7087
7088 bytes = 0;
7089 packets = 0;
7090 /* gather some stats to the adapter struct that are per queue */
7091 for (i = 0; i < adapter->num_tx_queues; i++) {
7092 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]);
7093
7094 if (!tx_ring)
7095 continue;
7096 restart_queue += tx_ring->tx_stats.restart_queue;
7097 tx_busy += tx_ring->tx_stats.tx_busy;
7098 bytes += tx_ring->stats.bytes;
7099 packets += tx_ring->stats.packets;
7100 }
7101 for (i = 0; i < adapter->num_xdp_queues; i++) {
7102 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]);
7103
7104 if (!xdp_ring)
7105 continue;
7106 restart_queue += xdp_ring->tx_stats.restart_queue;
7107 tx_busy += xdp_ring->tx_stats.tx_busy;
7108 bytes += xdp_ring->stats.bytes;
7109 packets += xdp_ring->stats.packets;
7110 }
7111 adapter->restart_queue = restart_queue;
7112 adapter->tx_busy = tx_busy;
7113 netdev->stats.tx_bytes = bytes;
7114 netdev->stats.tx_packets = packets;
7115
7116 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
7117
7118 /* 8 register reads */
7119 for (i = 0; i < 8; i++) {
7120 /* for packet buffers not used, the register should read 0 */
7121 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
7122 missed_rx += mpc;
7123 hwstats->mpc[i] += mpc;
7124 total_mpc += hwstats->mpc[i];
7125 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
7126 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
7127 switch (hw->mac.type) {
7128 case ixgbe_mac_82598EB:
7129 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
7130 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
7131 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7132 hwstats->pxonrxc[i] +=
7133 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
7134 break;
7135 case ixgbe_mac_82599EB:
7136 case ixgbe_mac_X540:
7137 case ixgbe_mac_X550:
7138 case ixgbe_mac_X550EM_x:
7139 case ixgbe_mac_x550em_a:
7140 hwstats->pxonrxc[i] +=
7141 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
7142 break;
7143 default:
7144 break;
7145 }
7146 }
7147
7148 /*16 register reads */
7149 for (i = 0; i < 16; i++) {
7150 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
7151 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
7152 if ((hw->mac.type == ixgbe_mac_82599EB) ||
7153 (hw->mac.type == ixgbe_mac_X540) ||
7154 (hw->mac.type == ixgbe_mac_X550) ||
7155 (hw->mac.type == ixgbe_mac_X550EM_x) ||
7156 (hw->mac.type == ixgbe_mac_x550em_a)) {
7157 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
7158 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
7159 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
7160 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
7161 }
7162 }
7163
7164 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
7165 /* work around hardware counting issue */
7166 hwstats->gprc -= missed_rx;
7167
7168 ixgbe_update_xoff_received(adapter);
7169
7170 /* 82598 hardware only has a 32 bit counter in the high register */
7171 switch (hw->mac.type) {
7172 case ixgbe_mac_82598EB:
7173 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
7174 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
7175 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
7176 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
7177 break;
7178 case ixgbe_mac_X540:
7179 case ixgbe_mac_X550:
7180 case ixgbe_mac_X550EM_x:
7181 case ixgbe_mac_x550em_a:
7182 /* OS2BMC stats are X540 and later */
7183 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
7184 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
7185 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
7186 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
7187 fallthrough;
7188 case ixgbe_mac_82599EB:
7189 for (i = 0; i < 16; i++)
7190 adapter->hw_rx_no_dma_resources +=
7191 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7192 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
7193 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7194 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
7195 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7196 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
7197 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7198 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7199 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
7200 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
7201 #ifdef IXGBE_FCOE
7202 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
7203 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
7204 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
7205 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
7206 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
7207 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7208 /* Add up per cpu counters for total ddp aloc fail */
7209 if (adapter->fcoe.ddp_pool) {
7210 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
7211 struct ixgbe_fcoe_ddp_pool *ddp_pool;
7212 unsigned int cpu;
7213 u64 noddp = 0, noddp_ext_buff = 0;
7214 for_each_possible_cpu(cpu) {
7215 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
7216 noddp += ddp_pool->noddp;
7217 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7218 }
7219 hwstats->fcoe_noddp = noddp;
7220 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7221 }
7222 #endif /* IXGBE_FCOE */
7223 break;
7224 default:
7225 break;
7226 }
7227 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7228 hwstats->bprc += bprc;
7229 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
7230 if (hw->mac.type == ixgbe_mac_82598EB)
7231 hwstats->mprc -= bprc;
7232 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
7233 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
7234 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
7235 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
7236 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
7237 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
7238 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
7239 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
7240 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7241 hwstats->lxontxc += lxon;
7242 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7243 hwstats->lxofftxc += lxoff;
7244 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
7245 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
7246 /*
7247 * 82598 errata - tx of flow control packets is included in tx counters
7248 */
7249 xon_off_tot = lxon + lxoff;
7250 hwstats->gptc -= xon_off_tot;
7251 hwstats->mptc -= xon_off_tot;
7252 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
7253 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
7254 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
7255 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
7256 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
7257 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
7258 hwstats->ptc64 -= xon_off_tot;
7259 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
7260 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
7261 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
7262 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
7263 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
7264 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
7265
7266 /* Fill out the OS statistics structure */
7267 netdev->stats.multicast = hwstats->mprc;
7268
7269 /* Rx Errors */
7270 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
7271 netdev->stats.rx_dropped = 0;
7272 netdev->stats.rx_length_errors = hwstats->rlec;
7273 netdev->stats.rx_crc_errors = hwstats->crcerrs;
7274 netdev->stats.rx_missed_errors = total_mpc;
7275 }
7276
7277 /**
7278 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
7279 * @adapter: pointer to the device adapter structure
7280 **/
ixgbe_fdir_reinit_subtask(struct ixgbe_adapter * adapter)7281 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
7282 {
7283 struct ixgbe_hw *hw = &adapter->hw;
7284 int i;
7285
7286 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
7287 return;
7288
7289 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7290
7291 /* if interface is down do nothing */
7292 if (test_bit(__IXGBE_DOWN, &adapter->state))
7293 return;
7294
7295 /* do nothing if we are not using signature filters */
7296 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
7297 return;
7298
7299 adapter->fdir_overflow++;
7300
7301 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
7302 for (i = 0; i < adapter->num_tx_queues; i++)
7303 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7304 &(adapter->tx_ring[i]->state));
7305 for (i = 0; i < adapter->num_xdp_queues; i++)
7306 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7307 &adapter->xdp_ring[i]->state);
7308 /* re-enable flow director interrupts */
7309 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
7310 } else {
7311 e_err(probe, "failed to finish FDIR re-initialization, "
7312 "ignored adding FDIR ATR filters\n");
7313 }
7314 }
7315
7316 /**
7317 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
7318 * @adapter: pointer to the device adapter structure
7319 *
7320 * This function serves two purposes. First it strobes the interrupt lines
7321 * in order to make certain interrupts are occurring. Secondly it sets the
7322 * bits needed to check for TX hangs. As a result we should immediately
7323 * determine if a hang has occurred.
7324 */
ixgbe_check_hang_subtask(struct ixgbe_adapter * adapter)7325 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
7326 {
7327 struct ixgbe_hw *hw = &adapter->hw;
7328 u64 eics = 0;
7329 int i;
7330
7331 /* If we're down, removing or resetting, just bail */
7332 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7333 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7334 test_bit(__IXGBE_RESETTING, &adapter->state))
7335 return;
7336
7337 /* Force detection of hung controller */
7338 if (netif_carrier_ok(adapter->netdev)) {
7339 for (i = 0; i < adapter->num_tx_queues; i++)
7340 set_check_for_tx_hang(adapter->tx_ring[i]);
7341 for (i = 0; i < adapter->num_xdp_queues; i++)
7342 set_check_for_tx_hang(adapter->xdp_ring[i]);
7343 }
7344
7345 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7346 /*
7347 * for legacy and MSI interrupts don't set any bits
7348 * that are enabled for EIAM, because this operation
7349 * would set *both* EIMS and EICS for any bit in EIAM
7350 */
7351 IXGBE_WRITE_REG(hw, IXGBE_EICS,
7352 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
7353 } else {
7354 /* get one bit for every active tx/rx interrupt vector */
7355 for (i = 0; i < adapter->num_q_vectors; i++) {
7356 struct ixgbe_q_vector *qv = adapter->q_vector[i];
7357 if (qv->rx.ring || qv->tx.ring)
7358 eics |= BIT_ULL(i);
7359 }
7360 }
7361
7362 /* Cause software interrupt to ensure rings are cleaned */
7363 ixgbe_irq_rearm_queues(adapter, eics);
7364 }
7365
7366 /**
7367 * ixgbe_watchdog_update_link - update the link status
7368 * @adapter: pointer to the device adapter structure
7369 **/
ixgbe_watchdog_update_link(struct ixgbe_adapter * adapter)7370 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
7371 {
7372 struct ixgbe_hw *hw = &adapter->hw;
7373 u32 link_speed = adapter->link_speed;
7374 bool link_up = adapter->link_up;
7375 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
7376
7377 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
7378 return;
7379
7380 if (hw->mac.ops.check_link) {
7381 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
7382 } else {
7383 /* always assume link is up, if no check link function */
7384 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
7385 link_up = true;
7386 }
7387
7388 if (adapter->ixgbe_ieee_pfc)
7389 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
7390
7391 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
7392 hw->mac.ops.fc_enable(hw);
7393 ixgbe_set_rx_drop_en(adapter);
7394 }
7395
7396 if (link_up ||
7397 time_after(jiffies, (adapter->link_check_timeout +
7398 IXGBE_TRY_LINK_TIMEOUT))) {
7399 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
7400 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
7401 IXGBE_WRITE_FLUSH(hw);
7402 }
7403
7404 adapter->link_up = link_up;
7405 adapter->link_speed = link_speed;
7406 }
7407
ixgbe_update_default_up(struct ixgbe_adapter * adapter)7408 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
7409 {
7410 #ifdef CONFIG_IXGBE_DCB
7411 struct net_device *netdev = adapter->netdev;
7412 struct dcb_app app = {
7413 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
7414 .protocol = 0,
7415 };
7416 u8 up = 0;
7417
7418 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
7419 up = dcb_ieee_getapp_mask(netdev, &app);
7420
7421 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
7422 #endif
7423 }
7424
7425 /**
7426 * ixgbe_watchdog_link_is_up - update netif_carrier status and
7427 * print link up message
7428 * @adapter: pointer to the device adapter structure
7429 **/
ixgbe_watchdog_link_is_up(struct ixgbe_adapter * adapter)7430 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
7431 {
7432 struct net_device *netdev = adapter->netdev;
7433 struct ixgbe_hw *hw = &adapter->hw;
7434 u32 link_speed = adapter->link_speed;
7435 const char *speed_str;
7436 bool flow_rx, flow_tx;
7437
7438 /* only continue if link was previously down */
7439 if (netif_carrier_ok(netdev))
7440 return;
7441
7442 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7443
7444 switch (hw->mac.type) {
7445 case ixgbe_mac_82598EB: {
7446 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7447 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
7448 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
7449 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
7450 }
7451 break;
7452 case ixgbe_mac_X540:
7453 case ixgbe_mac_X550:
7454 case ixgbe_mac_X550EM_x:
7455 case ixgbe_mac_x550em_a:
7456 case ixgbe_mac_82599EB: {
7457 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
7458 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
7459 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
7460 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
7461 }
7462 break;
7463 default:
7464 flow_tx = false;
7465 flow_rx = false;
7466 break;
7467 }
7468
7469 adapter->last_rx_ptp_check = jiffies;
7470
7471 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7472 ixgbe_ptp_start_cyclecounter(adapter);
7473
7474 switch (link_speed) {
7475 case IXGBE_LINK_SPEED_10GB_FULL:
7476 speed_str = "10 Gbps";
7477 break;
7478 case IXGBE_LINK_SPEED_5GB_FULL:
7479 speed_str = "5 Gbps";
7480 break;
7481 case IXGBE_LINK_SPEED_2_5GB_FULL:
7482 speed_str = "2.5 Gbps";
7483 break;
7484 case IXGBE_LINK_SPEED_1GB_FULL:
7485 speed_str = "1 Gbps";
7486 break;
7487 case IXGBE_LINK_SPEED_100_FULL:
7488 speed_str = "100 Mbps";
7489 break;
7490 case IXGBE_LINK_SPEED_10_FULL:
7491 speed_str = "10 Mbps";
7492 break;
7493 default:
7494 speed_str = "unknown speed";
7495 break;
7496 }
7497 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
7498 ((flow_rx && flow_tx) ? "RX/TX" :
7499 (flow_rx ? "RX" :
7500 (flow_tx ? "TX" : "None"))));
7501
7502 netif_carrier_on(netdev);
7503 ixgbe_check_vf_rate_limit(adapter);
7504
7505 /* enable transmits */
7506 netif_tx_wake_all_queues(adapter->netdev);
7507
7508 /* update the default user priority for VFs */
7509 ixgbe_update_default_up(adapter);
7510
7511 /* ping all the active vfs to let them know link has changed */
7512 ixgbe_ping_all_vfs(adapter);
7513 }
7514
7515 /**
7516 * ixgbe_watchdog_link_is_down - update netif_carrier status and
7517 * print link down message
7518 * @adapter: pointer to the adapter structure
7519 **/
ixgbe_watchdog_link_is_down(struct ixgbe_adapter * adapter)7520 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
7521 {
7522 struct net_device *netdev = adapter->netdev;
7523 struct ixgbe_hw *hw = &adapter->hw;
7524
7525 adapter->link_up = false;
7526 adapter->link_speed = 0;
7527
7528 /* only continue if link was up previously */
7529 if (!netif_carrier_ok(netdev))
7530 return;
7531
7532 /* poll for SFP+ cable when link is down */
7533 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7534 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
7535
7536 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7537 ixgbe_ptp_start_cyclecounter(adapter);
7538
7539 e_info(drv, "NIC Link is Down\n");
7540 netif_carrier_off(netdev);
7541
7542 /* ping all the active vfs to let them know link has changed */
7543 ixgbe_ping_all_vfs(adapter);
7544 }
7545
ixgbe_ring_tx_pending(struct ixgbe_adapter * adapter)7546 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7547 {
7548 int i;
7549
7550 for (i = 0; i < adapter->num_tx_queues; i++) {
7551 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7552
7553 if (tx_ring->next_to_use != tx_ring->next_to_clean)
7554 return true;
7555 }
7556
7557 for (i = 0; i < adapter->num_xdp_queues; i++) {
7558 struct ixgbe_ring *ring = adapter->xdp_ring[i];
7559
7560 if (ring->next_to_use != ring->next_to_clean)
7561 return true;
7562 }
7563
7564 return false;
7565 }
7566
ixgbe_vf_tx_pending(struct ixgbe_adapter * adapter)7567 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7568 {
7569 struct ixgbe_hw *hw = &adapter->hw;
7570 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7571 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7572
7573 int i, j;
7574
7575 if (!adapter->num_vfs)
7576 return false;
7577
7578 /* resetting the PF is only needed for MAC before X550 */
7579 if (hw->mac.type >= ixgbe_mac_X550)
7580 return false;
7581
7582 for (i = 0; i < adapter->num_vfs; i++) {
7583 for (j = 0; j < q_per_pool; j++) {
7584 u32 h, t;
7585
7586 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7587 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7588
7589 if (h != t)
7590 return true;
7591 }
7592 }
7593
7594 return false;
7595 }
7596
7597 /**
7598 * ixgbe_watchdog_flush_tx - flush queues on link down
7599 * @adapter: pointer to the device adapter structure
7600 **/
ixgbe_watchdog_flush_tx(struct ixgbe_adapter * adapter)7601 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7602 {
7603 if (!netif_carrier_ok(adapter->netdev)) {
7604 if (ixgbe_ring_tx_pending(adapter) ||
7605 ixgbe_vf_tx_pending(adapter)) {
7606 /* We've lost link, so the controller stops DMA,
7607 * but we've got queued Tx work that's never going
7608 * to get done, so reset controller to flush Tx.
7609 * (Do the reset outside of interrupt context).
7610 */
7611 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
7612 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
7613 }
7614 }
7615 }
7616
7617 #ifdef CONFIG_PCI_IOV
ixgbe_check_for_bad_vf(struct ixgbe_adapter * adapter)7618 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7619 {
7620 struct ixgbe_hw *hw = &adapter->hw;
7621 struct pci_dev *pdev = adapter->pdev;
7622 unsigned int vf;
7623 u32 gpc;
7624
7625 if (!(netif_carrier_ok(adapter->netdev)))
7626 return;
7627
7628 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7629 if (gpc) /* If incrementing then no need for the check below */
7630 return;
7631 /* Check to see if a bad DMA write target from an errant or
7632 * malicious VF has caused a PCIe error. If so then we can
7633 * issue a VFLR to the offending VF(s) and then resume without
7634 * requesting a full slot reset.
7635 */
7636
7637 if (!pdev)
7638 return;
7639
7640 /* check status reg for all VFs owned by this PF */
7641 for (vf = 0; vf < adapter->num_vfs; ++vf) {
7642 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7643 u16 status_reg;
7644
7645 if (!vfdev)
7646 continue;
7647 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7648 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7649 status_reg & PCI_STATUS_REC_MASTER_ABORT)
7650 pcie_flr(vfdev);
7651 }
7652 }
7653
ixgbe_spoof_check(struct ixgbe_adapter * adapter)7654 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7655 {
7656 u32 ssvpc;
7657
7658 /* Do not perform spoof check for 82598 or if not in IOV mode */
7659 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7660 adapter->num_vfs == 0)
7661 return;
7662
7663 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7664
7665 /*
7666 * ssvpc register is cleared on read, if zero then no
7667 * spoofed packets in the last interval.
7668 */
7669 if (!ssvpc)
7670 return;
7671
7672 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
7673 }
7674 #else
ixgbe_spoof_check(struct ixgbe_adapter __always_unused * adapter)7675 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7676 {
7677 }
7678
7679 static void
ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused * adapter)7680 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7681 {
7682 }
7683 #endif /* CONFIG_PCI_IOV */
7684
7685
7686 /**
7687 * ixgbe_watchdog_subtask - check and bring link up
7688 * @adapter: pointer to the device adapter structure
7689 **/
ixgbe_watchdog_subtask(struct ixgbe_adapter * adapter)7690 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7691 {
7692 /* if interface is down, removing or resetting, do nothing */
7693 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7694 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7695 test_bit(__IXGBE_RESETTING, &adapter->state))
7696 return;
7697
7698 ixgbe_watchdog_update_link(adapter);
7699
7700 if (adapter->link_up)
7701 ixgbe_watchdog_link_is_up(adapter);
7702 else
7703 ixgbe_watchdog_link_is_down(adapter);
7704
7705 ixgbe_check_for_bad_vf(adapter);
7706 ixgbe_spoof_check(adapter);
7707 ixgbe_update_stats(adapter);
7708
7709 ixgbe_watchdog_flush_tx(adapter);
7710 }
7711
7712 /**
7713 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
7714 * @adapter: the ixgbe adapter structure
7715 **/
ixgbe_sfp_detection_subtask(struct ixgbe_adapter * adapter)7716 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
7717 {
7718 struct ixgbe_hw *hw = &adapter->hw;
7719 s32 err;
7720
7721 /* not searching for SFP so there is nothing to do here */
7722 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7723 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7724 return;
7725
7726 if (adapter->sfp_poll_time &&
7727 time_after(adapter->sfp_poll_time, jiffies))
7728 return; /* If not yet time to poll for SFP */
7729
7730 /* someone else is in init, wait until next service event */
7731 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7732 return;
7733
7734 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7735
7736 err = hw->phy.ops.identify_sfp(hw);
7737 if (err == -EOPNOTSUPP)
7738 goto sfp_out;
7739
7740 if (err == -ENOENT) {
7741 /* If no cable is present, then we need to reset
7742 * the next time we find a good cable. */
7743 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
7744 }
7745
7746 /* exit on error */
7747 if (err)
7748 goto sfp_out;
7749
7750 /* exit if reset not needed */
7751 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7752 goto sfp_out;
7753
7754 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7755
7756 /*
7757 * A module may be identified correctly, but the EEPROM may not have
7758 * support for that module. setup_sfp() will fail in that case, so
7759 * we should not allow that module to load.
7760 */
7761 if (hw->mac.type == ixgbe_mac_82598EB)
7762 err = hw->phy.ops.reset(hw);
7763 else
7764 err = hw->mac.ops.setup_sfp(hw);
7765
7766 if (err == -EOPNOTSUPP)
7767 goto sfp_out;
7768
7769 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7770 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7771
7772 sfp_out:
7773 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7774
7775 if (err == -EOPNOTSUPP &&
7776 adapter->netdev->reg_state == NETREG_REGISTERED) {
7777 e_dev_err("failed to initialize because an unsupported "
7778 "SFP+ module type was detected.\n");
7779 e_dev_err("Reload the driver after installing a "
7780 "supported module.\n");
7781 unregister_netdev(adapter->netdev);
7782 }
7783 }
7784
7785 /**
7786 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7787 * @adapter: the ixgbe adapter structure
7788 **/
ixgbe_sfp_link_config_subtask(struct ixgbe_adapter * adapter)7789 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7790 {
7791 struct ixgbe_hw *hw = &adapter->hw;
7792 u32 cap_speed;
7793 u32 speed;
7794 bool autoneg = false;
7795
7796 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7797 return;
7798
7799 /* someone else is in init, wait until next service event */
7800 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7801 return;
7802
7803 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7804
7805 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg);
7806
7807 /* advertise highest capable link speed */
7808 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL))
7809 speed = IXGBE_LINK_SPEED_10GB_FULL;
7810 else
7811 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL |
7812 IXGBE_LINK_SPEED_1GB_FULL);
7813
7814 if (hw->mac.ops.setup_link)
7815 hw->mac.ops.setup_link(hw, speed, true);
7816
7817 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7818 adapter->link_check_timeout = jiffies;
7819 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7820 }
7821
7822 /**
7823 * ixgbe_service_timer - Timer Call-back
7824 * @t: pointer to timer_list structure
7825 **/
ixgbe_service_timer(struct timer_list * t)7826 static void ixgbe_service_timer(struct timer_list *t)
7827 {
7828 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer);
7829 unsigned long next_event_offset;
7830
7831 /* poll faster when waiting for link */
7832 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7833 next_event_offset = HZ / 10;
7834 else
7835 next_event_offset = HZ * 2;
7836
7837 /* Reset the timer */
7838 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7839
7840 ixgbe_service_event_schedule(adapter);
7841 }
7842
ixgbe_phy_interrupt_subtask(struct ixgbe_adapter * adapter)7843 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7844 {
7845 struct ixgbe_hw *hw = &adapter->hw;
7846 bool overtemp;
7847
7848 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7849 return;
7850
7851 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7852
7853 if (!hw->phy.ops.handle_lasi)
7854 return;
7855
7856 hw->phy.ops.handle_lasi(&adapter->hw, &overtemp);
7857 if (overtemp)
7858 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7859 }
7860
ixgbe_reset_subtask(struct ixgbe_adapter * adapter)7861 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7862 {
7863 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
7864 return;
7865
7866 rtnl_lock();
7867 /* If we're already down, removing or resetting, just bail */
7868 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7869 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7870 test_bit(__IXGBE_RESETTING, &adapter->state)) {
7871 rtnl_unlock();
7872 return;
7873 }
7874
7875 ixgbe_dump(adapter);
7876 netdev_err(adapter->netdev, "Reset adapter\n");
7877 adapter->tx_timeout_count++;
7878
7879 ixgbe_reinit_locked(adapter);
7880 rtnl_unlock();
7881 }
7882
7883 /**
7884 * ixgbe_check_fw_error - Check firmware for errors
7885 * @adapter: the adapter private structure
7886 *
7887 * Check firmware errors in register FWSM
7888 */
ixgbe_check_fw_error(struct ixgbe_adapter * adapter)7889 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter)
7890 {
7891 struct ixgbe_hw *hw = &adapter->hw;
7892 u32 fwsm;
7893
7894 /* read fwsm.ext_err_ind register and log errors */
7895 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
7896
7897 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK ||
7898 !(fwsm & IXGBE_FWSM_FW_VAL_BIT))
7899 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n",
7900 fwsm);
7901
7902 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
7903 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n");
7904 return true;
7905 }
7906
7907 return false;
7908 }
7909
7910 /**
7911 * ixgbe_service_task - manages and runs subtasks
7912 * @work: pointer to work_struct containing our data
7913 **/
ixgbe_service_task(struct work_struct * work)7914 static void ixgbe_service_task(struct work_struct *work)
7915 {
7916 struct ixgbe_adapter *adapter = container_of(work,
7917 struct ixgbe_adapter,
7918 service_task);
7919 if (ixgbe_removed(adapter->hw.hw_addr)) {
7920 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7921 rtnl_lock();
7922 ixgbe_down(adapter);
7923 rtnl_unlock();
7924 }
7925 ixgbe_service_event_complete(adapter);
7926 return;
7927 }
7928 if (ixgbe_check_fw_error(adapter)) {
7929 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7930 unregister_netdev(adapter->netdev);
7931 ixgbe_service_event_complete(adapter);
7932 return;
7933 }
7934 ixgbe_reset_subtask(adapter);
7935 ixgbe_phy_interrupt_subtask(adapter);
7936 ixgbe_sfp_detection_subtask(adapter);
7937 ixgbe_sfp_link_config_subtask(adapter);
7938 ixgbe_check_overtemp_subtask(adapter);
7939 ixgbe_watchdog_subtask(adapter);
7940 ixgbe_fdir_reinit_subtask(adapter);
7941 ixgbe_check_hang_subtask(adapter);
7942
7943 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
7944 ixgbe_ptp_overflow_check(adapter);
7945 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER)
7946 ixgbe_ptp_rx_hang(adapter);
7947 ixgbe_ptp_tx_hang(adapter);
7948 }
7949
7950 ixgbe_service_event_complete(adapter);
7951 }
7952
ixgbe_tso(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,u8 * hdr_len,struct ixgbe_ipsec_tx_data * itd)7953 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7954 struct ixgbe_tx_buffer *first,
7955 u8 *hdr_len,
7956 struct ixgbe_ipsec_tx_data *itd)
7957 {
7958 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7959 struct sk_buff *skb = first->skb;
7960 union {
7961 struct iphdr *v4;
7962 struct ipv6hdr *v6;
7963 unsigned char *hdr;
7964 } ip;
7965 union {
7966 struct tcphdr *tcp;
7967 struct udphdr *udp;
7968 unsigned char *hdr;
7969 } l4;
7970 u32 paylen, l4_offset;
7971 u32 fceof_saidx = 0;
7972 int err;
7973
7974 if (skb->ip_summed != CHECKSUM_PARTIAL)
7975 return 0;
7976
7977 if (!skb_is_gso(skb))
7978 return 0;
7979
7980 err = skb_cow_head(skb, 0);
7981 if (err < 0)
7982 return err;
7983
7984 if (eth_p_mpls(first->protocol))
7985 ip.hdr = skb_inner_network_header(skb);
7986 else
7987 ip.hdr = skb_network_header(skb);
7988 l4.hdr = skb_checksum_start(skb);
7989
7990 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7991 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
7992 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP;
7993
7994 /* initialize outer IP header fields */
7995 if (ip.v4->version == 4) {
7996 unsigned char *csum_start = skb_checksum_start(skb);
7997 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
7998 int len = csum_start - trans_start;
7999
8000 /* IP header will have to cancel out any data that
8001 * is not a part of the outer IP header, so set to
8002 * a reverse csum if needed, else init check to 0.
8003 */
8004 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ?
8005 csum_fold(csum_partial(trans_start,
8006 len, 0)) : 0;
8007 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
8008
8009 ip.v4->tot_len = 0;
8010 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
8011 IXGBE_TX_FLAGS_CSUM |
8012 IXGBE_TX_FLAGS_IPV4;
8013 } else {
8014 ip.v6->payload_len = 0;
8015 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
8016 IXGBE_TX_FLAGS_CSUM;
8017 }
8018
8019 /* determine offset of inner transport header */
8020 l4_offset = l4.hdr - skb->data;
8021
8022 /* remove payload length from inner checksum */
8023 paylen = skb->len - l4_offset;
8024
8025 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) {
8026 /* compute length of segmentation header */
8027 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
8028 csum_replace_by_diff(&l4.tcp->check,
8029 (__force __wsum)htonl(paylen));
8030 } else {
8031 /* compute length of segmentation header */
8032 *hdr_len = sizeof(*l4.udp) + l4_offset;
8033 csum_replace_by_diff(&l4.udp->check,
8034 (__force __wsum)htonl(paylen));
8035 }
8036
8037 /* update gso size and bytecount with header size */
8038 first->gso_segs = skb_shinfo(skb)->gso_segs;
8039 first->bytecount += (first->gso_segs - 1) * *hdr_len;
8040
8041 /* mss_l4len_id: use 0 as index for TSO */
8042 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
8043 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
8044
8045 fceof_saidx |= itd->sa_idx;
8046 type_tucmd |= itd->flags | itd->trailer_len;
8047
8048 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
8049 vlan_macip_lens = l4.hdr - ip.hdr;
8050 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
8051 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8052
8053 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd,
8054 mss_l4len_idx);
8055
8056 return 1;
8057 }
8058
ixgbe_tx_csum(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,struct ixgbe_ipsec_tx_data * itd)8059 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
8060 struct ixgbe_tx_buffer *first,
8061 struct ixgbe_ipsec_tx_data *itd)
8062 {
8063 struct sk_buff *skb = first->skb;
8064 u32 vlan_macip_lens = 0;
8065 u32 fceof_saidx = 0;
8066 u32 type_tucmd = 0;
8067
8068 if (skb->ip_summed != CHECKSUM_PARTIAL) {
8069 csum_failed:
8070 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
8071 IXGBE_TX_FLAGS_CC)))
8072 return;
8073 goto no_csum;
8074 }
8075
8076 switch (skb->csum_offset) {
8077 case offsetof(struct tcphdr, check):
8078 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
8079 fallthrough;
8080 case offsetof(struct udphdr, check):
8081 break;
8082 case offsetof(struct sctphdr, checksum):
8083 /* validate that this is actually an SCTP request */
8084 if (skb_csum_is_sctp(skb)) {
8085 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
8086 break;
8087 }
8088 fallthrough;
8089 default:
8090 skb_checksum_help(skb);
8091 goto csum_failed;
8092 }
8093
8094 /* update TX checksum flag */
8095 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
8096 vlan_macip_lens = skb_checksum_start_offset(skb) -
8097 skb_network_offset(skb);
8098 no_csum:
8099 /* vlan_macip_lens: MACLEN, VLAN tag */
8100 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
8101 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8102
8103 fceof_saidx |= itd->sa_idx;
8104 type_tucmd |= itd->flags | itd->trailer_len;
8105
8106 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0);
8107 }
8108
8109 #define IXGBE_SET_FLAG(_input, _flag, _result) \
8110 ((_flag <= _result) ? \
8111 ((u32)(_input & _flag) * (_result / _flag)) : \
8112 ((u32)(_input & _flag) / (_flag / _result)))
8113
ixgbe_tx_cmd_type(struct sk_buff * skb,u32 tx_flags)8114 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
8115 {
8116 /* set type for advanced descriptor with frame checksum insertion */
8117 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8118 IXGBE_ADVTXD_DCMD_DEXT |
8119 IXGBE_ADVTXD_DCMD_IFCS;
8120
8121 /* set HW vlan bit if vlan is present */
8122 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
8123 IXGBE_ADVTXD_DCMD_VLE);
8124
8125 /* set segmentation enable bits for TSO/FSO */
8126 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
8127 IXGBE_ADVTXD_DCMD_TSE);
8128
8129 /* set timestamp bit if present */
8130 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
8131 IXGBE_ADVTXD_MAC_TSTAMP);
8132
8133 /* insert frame checksum */
8134 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
8135
8136 return cmd_type;
8137 }
8138
ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)8139 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
8140 u32 tx_flags, unsigned int paylen)
8141 {
8142 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
8143
8144 /* enable L4 checksum for TSO and TX checksum offload */
8145 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8146 IXGBE_TX_FLAGS_CSUM,
8147 IXGBE_ADVTXD_POPTS_TXSM);
8148
8149 /* enable IPv4 checksum for TSO */
8150 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8151 IXGBE_TX_FLAGS_IPV4,
8152 IXGBE_ADVTXD_POPTS_IXSM);
8153
8154 /* enable IPsec */
8155 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8156 IXGBE_TX_FLAGS_IPSEC,
8157 IXGBE_ADVTXD_POPTS_IPSEC);
8158
8159 /*
8160 * Check Context must be set if Tx switch is enabled, which it
8161 * always is for case where virtual functions are running
8162 */
8163 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8164 IXGBE_TX_FLAGS_CC,
8165 IXGBE_ADVTXD_CC);
8166
8167 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
8168 }
8169
__ixgbe_maybe_stop_tx(struct ixgbe_ring * tx_ring,u16 size)8170 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8171 {
8172 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
8173
8174 /* Herbert's original patch had:
8175 * smp_mb__after_netif_stop_queue();
8176 * but since that doesn't exist yet, just open code it.
8177 */
8178 smp_mb();
8179
8180 /* We need to check again in a case another CPU has just
8181 * made room available.
8182 */
8183 if (likely(ixgbe_desc_unused(tx_ring) < size))
8184 return -EBUSY;
8185
8186 /* A reprieve! - use start_queue because it doesn't call schedule */
8187 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
8188 ++tx_ring->tx_stats.restart_queue;
8189 return 0;
8190 }
8191
ixgbe_maybe_stop_tx(struct ixgbe_ring * tx_ring,u16 size)8192 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8193 {
8194 if (likely(ixgbe_desc_unused(tx_ring) >= size))
8195 return 0;
8196
8197 return __ixgbe_maybe_stop_tx(tx_ring, size);
8198 }
8199
ixgbe_tx_map(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,const u8 hdr_len)8200 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring,
8201 struct ixgbe_tx_buffer *first,
8202 const u8 hdr_len)
8203 {
8204 struct sk_buff *skb = first->skb;
8205 struct ixgbe_tx_buffer *tx_buffer;
8206 union ixgbe_adv_tx_desc *tx_desc;
8207 skb_frag_t *frag;
8208 dma_addr_t dma;
8209 unsigned int data_len, size;
8210 u32 tx_flags = first->tx_flags;
8211 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
8212 u16 i = tx_ring->next_to_use;
8213
8214 tx_desc = IXGBE_TX_DESC(tx_ring, i);
8215
8216 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
8217
8218 size = skb_headlen(skb);
8219 data_len = skb->data_len;
8220
8221 #ifdef IXGBE_FCOE
8222 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
8223 if (data_len < sizeof(struct fcoe_crc_eof)) {
8224 size -= sizeof(struct fcoe_crc_eof) - data_len;
8225 data_len = 0;
8226 } else {
8227 data_len -= sizeof(struct fcoe_crc_eof);
8228 }
8229 }
8230
8231 #endif
8232 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8233
8234 tx_buffer = first;
8235
8236 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
8237 if (dma_mapping_error(tx_ring->dev, dma))
8238 goto dma_error;
8239
8240 /* record length, and DMA address */
8241 dma_unmap_len_set(tx_buffer, len, size);
8242 dma_unmap_addr_set(tx_buffer, dma, dma);
8243
8244 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8245
8246 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
8247 tx_desc->read.cmd_type_len =
8248 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
8249
8250 i++;
8251 tx_desc++;
8252 if (i == tx_ring->count) {
8253 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8254 i = 0;
8255 }
8256 tx_desc->read.olinfo_status = 0;
8257
8258 dma += IXGBE_MAX_DATA_PER_TXD;
8259 size -= IXGBE_MAX_DATA_PER_TXD;
8260
8261 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8262 }
8263
8264 if (likely(!data_len))
8265 break;
8266
8267 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
8268
8269 i++;
8270 tx_desc++;
8271 if (i == tx_ring->count) {
8272 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8273 i = 0;
8274 }
8275 tx_desc->read.olinfo_status = 0;
8276
8277 #ifdef IXGBE_FCOE
8278 size = min_t(unsigned int, data_len, skb_frag_size(frag));
8279 #else
8280 size = skb_frag_size(frag);
8281 #endif
8282 data_len -= size;
8283
8284 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
8285 DMA_TO_DEVICE);
8286
8287 tx_buffer = &tx_ring->tx_buffer_info[i];
8288 }
8289
8290 /* write last descriptor with RS and EOP bits */
8291 cmd_type |= size | IXGBE_TXD_CMD;
8292 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8293
8294 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
8295
8296 /* set the timestamp */
8297 first->time_stamp = jiffies;
8298
8299 skb_tx_timestamp(skb);
8300
8301 /*
8302 * Force memory writes to complete before letting h/w know there
8303 * are new descriptors to fetch. (Only applicable for weak-ordered
8304 * memory model archs, such as IA-64).
8305 *
8306 * We also need this memory barrier to make certain all of the
8307 * status bits have been updated before next_to_watch is written.
8308 */
8309 wmb();
8310
8311 /* set next_to_watch value indicating a packet is present */
8312 first->next_to_watch = tx_desc;
8313
8314 i++;
8315 if (i == tx_ring->count)
8316 i = 0;
8317
8318 tx_ring->next_to_use = i;
8319
8320 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
8321
8322 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
8323 writel(i, tx_ring->tail);
8324 }
8325
8326 return 0;
8327 dma_error:
8328 dev_err(tx_ring->dev, "TX DMA map failed\n");
8329
8330 /* clear dma mappings for failed tx_buffer_info map */
8331 for (;;) {
8332 tx_buffer = &tx_ring->tx_buffer_info[i];
8333 if (dma_unmap_len(tx_buffer, len))
8334 dma_unmap_page(tx_ring->dev,
8335 dma_unmap_addr(tx_buffer, dma),
8336 dma_unmap_len(tx_buffer, len),
8337 DMA_TO_DEVICE);
8338 dma_unmap_len_set(tx_buffer, len, 0);
8339 if (tx_buffer == first)
8340 break;
8341 if (i == 0)
8342 i += tx_ring->count;
8343 i--;
8344 }
8345
8346 dev_kfree_skb_any(first->skb);
8347 first->skb = NULL;
8348
8349 tx_ring->next_to_use = i;
8350
8351 return -1;
8352 }
8353
ixgbe_atr(struct ixgbe_ring * ring,struct ixgbe_tx_buffer * first)8354 static void ixgbe_atr(struct ixgbe_ring *ring,
8355 struct ixgbe_tx_buffer *first)
8356 {
8357 struct ixgbe_q_vector *q_vector = ring->q_vector;
8358 union ixgbe_atr_hash_dword input = { .dword = 0 };
8359 union ixgbe_atr_hash_dword common = { .dword = 0 };
8360 union {
8361 unsigned char *network;
8362 struct iphdr *ipv4;
8363 struct ipv6hdr *ipv6;
8364 } hdr;
8365 struct tcphdr *th;
8366 unsigned int hlen;
8367 struct sk_buff *skb;
8368 __be16 vlan_id;
8369 int l4_proto;
8370
8371 /* if ring doesn't have a interrupt vector, cannot perform ATR */
8372 if (!q_vector)
8373 return;
8374
8375 /* do nothing if sampling is disabled */
8376 if (!ring->atr_sample_rate)
8377 return;
8378
8379 ring->atr_count++;
8380
8381 /* currently only IPv4/IPv6 with TCP is supported */
8382 if ((first->protocol != htons(ETH_P_IP)) &&
8383 (first->protocol != htons(ETH_P_IPV6)))
8384 return;
8385
8386 /* snag network header to get L4 type and address */
8387 skb = first->skb;
8388 hdr.network = skb_network_header(skb);
8389 if (unlikely(hdr.network <= skb->data))
8390 return;
8391 if (skb->encapsulation &&
8392 first->protocol == htons(ETH_P_IP) &&
8393 hdr.ipv4->protocol == IPPROTO_UDP) {
8394 struct ixgbe_adapter *adapter = q_vector->adapter;
8395
8396 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8397 vxlan_headroom(0)))
8398 return;
8399
8400 /* verify the port is recognized as VXLAN */
8401 if (adapter->vxlan_port &&
8402 udp_hdr(skb)->dest == adapter->vxlan_port)
8403 hdr.network = skb_inner_network_header(skb);
8404
8405 if (adapter->geneve_port &&
8406 udp_hdr(skb)->dest == adapter->geneve_port)
8407 hdr.network = skb_inner_network_header(skb);
8408 }
8409
8410 /* Make sure we have at least [minimum IPv4 header + TCP]
8411 * or [IPv6 header] bytes
8412 */
8413 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
8414 return;
8415
8416 /* Currently only IPv4/IPv6 with TCP is supported */
8417 switch (hdr.ipv4->version) {
8418 case IPVERSION:
8419 /* access ihl as u8 to avoid unaligned access on ia64 */
8420 hlen = (hdr.network[0] & 0x0F) << 2;
8421 l4_proto = hdr.ipv4->protocol;
8422 break;
8423 case 6:
8424 hlen = hdr.network - skb->data;
8425 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
8426 hlen -= hdr.network - skb->data;
8427 break;
8428 default:
8429 return;
8430 }
8431
8432 if (l4_proto != IPPROTO_TCP)
8433 return;
8434
8435 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8436 hlen + sizeof(struct tcphdr)))
8437 return;
8438
8439 th = (struct tcphdr *)(hdr.network + hlen);
8440
8441 /* skip this packet since the socket is closing */
8442 if (th->fin)
8443 return;
8444
8445 /* sample on all syn packets or once every atr sample count */
8446 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
8447 return;
8448
8449 /* reset sample count */
8450 ring->atr_count = 0;
8451
8452 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
8453
8454 /*
8455 * src and dst are inverted, think how the receiver sees them
8456 *
8457 * The input is broken into two sections, a non-compressed section
8458 * containing vm_pool, vlan_id, and flow_type. The rest of the data
8459 * is XORed together and stored in the compressed dword.
8460 */
8461 input.formatted.vlan_id = vlan_id;
8462
8463 /*
8464 * since src port and flex bytes occupy the same word XOR them together
8465 * and write the value to source port portion of compressed dword
8466 */
8467 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
8468 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
8469 else
8470 common.port.src ^= th->dest ^ first->protocol;
8471 common.port.dst ^= th->source;
8472
8473 switch (hdr.ipv4->version) {
8474 case IPVERSION:
8475 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
8476 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
8477 break;
8478 case 6:
8479 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
8480 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
8481 hdr.ipv6->saddr.s6_addr32[1] ^
8482 hdr.ipv6->saddr.s6_addr32[2] ^
8483 hdr.ipv6->saddr.s6_addr32[3] ^
8484 hdr.ipv6->daddr.s6_addr32[0] ^
8485 hdr.ipv6->daddr.s6_addr32[1] ^
8486 hdr.ipv6->daddr.s6_addr32[2] ^
8487 hdr.ipv6->daddr.s6_addr32[3];
8488 break;
8489 default:
8490 break;
8491 }
8492
8493 if (hdr.network != skb_network_header(skb))
8494 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
8495
8496 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
8497 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
8498 input, common, ring->queue_index);
8499 }
8500
8501 #ifdef IXGBE_FCOE
ixgbe_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev)8502 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
8503 struct net_device *sb_dev)
8504 {
8505 struct ixgbe_adapter *adapter;
8506 struct ixgbe_ring_feature *f;
8507 int txq;
8508
8509 if (sb_dev) {
8510 u8 tc = netdev_get_prio_tc_map(dev, skb->priority);
8511 struct net_device *vdev = sb_dev;
8512
8513 txq = vdev->tc_to_txq[tc].offset;
8514 txq += reciprocal_scale(skb_get_hash(skb),
8515 vdev->tc_to_txq[tc].count);
8516
8517 return txq;
8518 }
8519
8520 /*
8521 * only execute the code below if protocol is FCoE
8522 * or FIP and we have FCoE enabled on the adapter
8523 */
8524 switch (vlan_get_protocol(skb)) {
8525 case htons(ETH_P_FCOE):
8526 case htons(ETH_P_FIP):
8527 adapter = netdev_priv(dev);
8528
8529 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
8530 break;
8531 fallthrough;
8532 default:
8533 return netdev_pick_tx(dev, skb, sb_dev);
8534 }
8535
8536 f = &adapter->ring_feature[RING_F_FCOE];
8537
8538 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
8539 smp_processor_id();
8540
8541 while (txq >= f->indices)
8542 txq -= f->indices;
8543
8544 return txq + f->offset;
8545 }
8546
8547 #endif
ixgbe_xmit_xdp_ring(struct ixgbe_adapter * adapter,struct xdp_frame * xdpf)8548 int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
8549 struct xdp_frame *xdpf)
8550 {
8551 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
8552 struct ixgbe_tx_buffer *tx_buffer;
8553 union ixgbe_adv_tx_desc *tx_desc;
8554 u32 len, cmd_type;
8555 dma_addr_t dma;
8556 u16 i;
8557
8558 len = xdpf->len;
8559
8560 if (unlikely(!ixgbe_desc_unused(ring)))
8561 return IXGBE_XDP_CONSUMED;
8562
8563 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE);
8564 if (dma_mapping_error(ring->dev, dma))
8565 return IXGBE_XDP_CONSUMED;
8566
8567 /* record the location of the first descriptor for this packet */
8568 tx_buffer = &ring->tx_buffer_info[ring->next_to_use];
8569 tx_buffer->bytecount = len;
8570 tx_buffer->gso_segs = 1;
8571 tx_buffer->protocol = 0;
8572
8573 i = ring->next_to_use;
8574 tx_desc = IXGBE_TX_DESC(ring, i);
8575
8576 dma_unmap_len_set(tx_buffer, len, len);
8577 dma_unmap_addr_set(tx_buffer, dma, dma);
8578 tx_buffer->xdpf = xdpf;
8579
8580 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8581
8582 /* put descriptor type bits */
8583 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8584 IXGBE_ADVTXD_DCMD_DEXT |
8585 IXGBE_ADVTXD_DCMD_IFCS;
8586 cmd_type |= len | IXGBE_TXD_CMD;
8587 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8588 tx_desc->read.olinfo_status =
8589 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT);
8590
8591 /* Avoid any potential race with xdp_xmit and cleanup */
8592 smp_wmb();
8593
8594 /* set next_to_watch value indicating a packet is present */
8595 i++;
8596 if (i == ring->count)
8597 i = 0;
8598
8599 tx_buffer->next_to_watch = tx_desc;
8600 ring->next_to_use = i;
8601
8602 return IXGBE_XDP_TX;
8603 }
8604
ixgbe_xmit_frame_ring(struct sk_buff * skb,struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring)8605 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
8606 struct ixgbe_adapter *adapter,
8607 struct ixgbe_ring *tx_ring)
8608 {
8609 struct ixgbe_tx_buffer *first;
8610 int tso;
8611 u32 tx_flags = 0;
8612 unsigned short f;
8613 u16 count = TXD_USE_COUNT(skb_headlen(skb));
8614 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 };
8615 __be16 protocol = skb->protocol;
8616 u8 hdr_len = 0;
8617
8618 /*
8619 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
8620 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
8621 * + 2 desc gap to keep tail from touching head,
8622 * + 1 desc for context descriptor,
8623 * otherwise try next time
8624 */
8625 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
8626 count += TXD_USE_COUNT(skb_frag_size(
8627 &skb_shinfo(skb)->frags[f]));
8628
8629 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8630 tx_ring->tx_stats.tx_busy++;
8631 return NETDEV_TX_BUSY;
8632 }
8633
8634 /* record the location of the first descriptor for this packet */
8635 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8636 first->skb = skb;
8637 first->bytecount = skb->len;
8638 first->gso_segs = 1;
8639
8640 /* if we have a HW VLAN tag being added default to the HW one */
8641 if (skb_vlan_tag_present(skb)) {
8642 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
8643 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8644 /* else if it is a SW VLAN check the next protocol and store the tag */
8645 } else if (protocol == htons(ETH_P_8021Q)) {
8646 struct vlan_hdr *vhdr, _vhdr;
8647 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8648 if (!vhdr)
8649 goto out_drop;
8650
8651 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8652 IXGBE_TX_FLAGS_VLAN_SHIFT;
8653 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8654 }
8655 protocol = vlan_get_protocol(skb);
8656
8657 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
8658 adapter->ptp_clock) {
8659 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
8660 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
8661 &adapter->state)) {
8662 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8663 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
8664
8665 /* schedule check for Tx timestamp */
8666 adapter->ptp_tx_skb = skb_get(skb);
8667 adapter->ptp_tx_start = jiffies;
8668 schedule_work(&adapter->ptp_tx_work);
8669 } else {
8670 adapter->tx_hwtstamp_skipped++;
8671 }
8672 }
8673
8674 #ifdef CONFIG_PCI_IOV
8675 /*
8676 * Use the l2switch_enable flag - would be false if the DMA
8677 * Tx switch had been disabled.
8678 */
8679 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8680 tx_flags |= IXGBE_TX_FLAGS_CC;
8681
8682 #endif
8683 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
8684 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8685 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8686 (skb->priority != TC_PRIO_CONTROL))) {
8687 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
8688 tx_flags |= (skb->priority & 0x7) <<
8689 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
8690 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8691 struct vlan_ethhdr *vhdr;
8692
8693 if (skb_cow_head(skb, 0))
8694 goto out_drop;
8695 vhdr = skb_vlan_eth_hdr(skb);
8696 vhdr->h_vlan_TCI = htons(tx_flags >>
8697 IXGBE_TX_FLAGS_VLAN_SHIFT);
8698 } else {
8699 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8700 }
8701 }
8702
8703 /* record initial flags and protocol */
8704 first->tx_flags = tx_flags;
8705 first->protocol = protocol;
8706
8707 #ifdef IXGBE_FCOE
8708 /* setup tx offload for FCoE */
8709 if ((protocol == htons(ETH_P_FCOE)) &&
8710 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
8711 tso = ixgbe_fso(tx_ring, first, &hdr_len);
8712 if (tso < 0)
8713 goto out_drop;
8714
8715 goto xmit_fcoe;
8716 }
8717
8718 #endif /* IXGBE_FCOE */
8719
8720 #ifdef CONFIG_IXGBE_IPSEC
8721 if (xfrm_offload(skb) &&
8722 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx))
8723 goto out_drop;
8724 #endif
8725 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx);
8726 if (tso < 0)
8727 goto out_drop;
8728 else if (!tso)
8729 ixgbe_tx_csum(tx_ring, first, &ipsec_tx);
8730
8731 /* add the ATR filter if ATR is on */
8732 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
8733 ixgbe_atr(tx_ring, first);
8734
8735 #ifdef IXGBE_FCOE
8736 xmit_fcoe:
8737 #endif /* IXGBE_FCOE */
8738 if (ixgbe_tx_map(tx_ring, first, hdr_len))
8739 goto cleanup_tx_timestamp;
8740
8741 return NETDEV_TX_OK;
8742
8743 out_drop:
8744 dev_kfree_skb_any(first->skb);
8745 first->skb = NULL;
8746 cleanup_tx_timestamp:
8747 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) {
8748 dev_kfree_skb_any(adapter->ptp_tx_skb);
8749 adapter->ptp_tx_skb = NULL;
8750 cancel_work_sync(&adapter->ptp_tx_work);
8751 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
8752 }
8753
8754 return NETDEV_TX_OK;
8755 }
8756
__ixgbe_xmit_frame(struct sk_buff * skb,struct net_device * netdev,struct ixgbe_ring * ring)8757 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8758 struct net_device *netdev,
8759 struct ixgbe_ring *ring)
8760 {
8761 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8762 struct ixgbe_ring *tx_ring;
8763
8764 /*
8765 * The minimum packet size for olinfo paylen is 17 so pad the skb
8766 * in order to meet this minimum size requirement.
8767 */
8768 if (skb_put_padto(skb, 17))
8769 return NETDEV_TX_OK;
8770
8771 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)];
8772 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state)))
8773 return NETDEV_TX_BUSY;
8774
8775 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
8776 }
8777
ixgbe_xmit_frame(struct sk_buff * skb,struct net_device * netdev)8778 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8779 struct net_device *netdev)
8780 {
8781 return __ixgbe_xmit_frame(skb, netdev, NULL);
8782 }
8783
8784 /**
8785 * ixgbe_set_mac - Change the Ethernet Address of the NIC
8786 * @netdev: network interface device structure
8787 * @p: pointer to an address structure
8788 *
8789 * Returns 0 on success, negative on failure
8790 **/
ixgbe_set_mac(struct net_device * netdev,void * p)8791 static int ixgbe_set_mac(struct net_device *netdev, void *p)
8792 {
8793 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8794 struct ixgbe_hw *hw = &adapter->hw;
8795 struct sockaddr *addr = p;
8796
8797 if (!is_valid_ether_addr(addr->sa_data))
8798 return -EADDRNOTAVAIL;
8799
8800 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
8801 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
8802
8803 ixgbe_mac_set_default_filter(adapter);
8804
8805 return 0;
8806 }
8807
8808 static int
ixgbe_mdio_read(struct net_device * netdev,int prtad,int devad,u16 addr)8809 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8810 {
8811 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8812 struct ixgbe_hw *hw = &adapter->hw;
8813 u16 value;
8814 int rc;
8815
8816 if (adapter->mii_bus) {
8817 int regnum = addr;
8818
8819 if (devad != MDIO_DEVAD_NONE)
8820 regnum |= (devad << 16) | MII_ADDR_C45;
8821
8822 return mdiobus_read(adapter->mii_bus, prtad, regnum);
8823 }
8824
8825 if (prtad != hw->phy.mdio.prtad)
8826 return -EINVAL;
8827 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8828 if (!rc)
8829 rc = value;
8830 return rc;
8831 }
8832
ixgbe_mdio_write(struct net_device * netdev,int prtad,int devad,u16 addr,u16 value)8833 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8834 u16 addr, u16 value)
8835 {
8836 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8837 struct ixgbe_hw *hw = &adapter->hw;
8838
8839 if (adapter->mii_bus) {
8840 int regnum = addr;
8841
8842 if (devad != MDIO_DEVAD_NONE)
8843 regnum |= (devad << 16) | MII_ADDR_C45;
8844
8845 return mdiobus_write(adapter->mii_bus, prtad, regnum, value);
8846 }
8847
8848 if (prtad != hw->phy.mdio.prtad)
8849 return -EINVAL;
8850 return hw->phy.ops.write_reg(hw, addr, devad, value);
8851 }
8852
ixgbe_ioctl(struct net_device * netdev,struct ifreq * req,int cmd)8853 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8854 {
8855 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8856
8857 switch (cmd) {
8858 case SIOCSHWTSTAMP:
8859 return ixgbe_ptp_set_ts_config(adapter, req);
8860 case SIOCGHWTSTAMP:
8861 return ixgbe_ptp_get_ts_config(adapter, req);
8862 case SIOCGMIIPHY:
8863 if (!adapter->hw.phy.ops.read_reg)
8864 return -EOPNOTSUPP;
8865 fallthrough;
8866 default:
8867 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8868 }
8869 }
8870
8871 /**
8872 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
8873 * netdev->dev_addrs
8874 * @dev: network interface device structure
8875 *
8876 * Returns non-zero on failure
8877 **/
ixgbe_add_sanmac_netdev(struct net_device * dev)8878 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8879 {
8880 int err = 0;
8881 struct ixgbe_adapter *adapter = netdev_priv(dev);
8882 struct ixgbe_hw *hw = &adapter->hw;
8883
8884 if (is_valid_ether_addr(hw->mac.san_addr)) {
8885 rtnl_lock();
8886 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
8887 rtnl_unlock();
8888
8889 /* update SAN MAC vmdq pool selection */
8890 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
8891 }
8892 return err;
8893 }
8894
8895 /**
8896 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
8897 * netdev->dev_addrs
8898 * @dev: network interface device structure
8899 *
8900 * Returns non-zero on failure
8901 **/
ixgbe_del_sanmac_netdev(struct net_device * dev)8902 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8903 {
8904 int err = 0;
8905 struct ixgbe_adapter *adapter = netdev_priv(dev);
8906 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8907
8908 if (is_valid_ether_addr(mac->san_addr)) {
8909 rtnl_lock();
8910 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8911 rtnl_unlock();
8912 }
8913 return err;
8914 }
8915
ixgbe_get_ring_stats64(struct rtnl_link_stats64 * stats,struct ixgbe_ring * ring)8916 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats,
8917 struct ixgbe_ring *ring)
8918 {
8919 u64 bytes, packets;
8920 unsigned int start;
8921
8922 if (ring) {
8923 do {
8924 start = u64_stats_fetch_begin_irq(&ring->syncp);
8925 packets = ring->stats.packets;
8926 bytes = ring->stats.bytes;
8927 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8928 stats->tx_packets += packets;
8929 stats->tx_bytes += bytes;
8930 }
8931 }
8932
ixgbe_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)8933 static void ixgbe_get_stats64(struct net_device *netdev,
8934 struct rtnl_link_stats64 *stats)
8935 {
8936 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8937 int i;
8938
8939 rcu_read_lock();
8940 for (i = 0; i < adapter->num_rx_queues; i++) {
8941 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]);
8942 u64 bytes, packets;
8943 unsigned int start;
8944
8945 if (ring) {
8946 do {
8947 start = u64_stats_fetch_begin_irq(&ring->syncp);
8948 packets = ring->stats.packets;
8949 bytes = ring->stats.bytes;
8950 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8951 stats->rx_packets += packets;
8952 stats->rx_bytes += bytes;
8953 }
8954 }
8955
8956 for (i = 0; i < adapter->num_tx_queues; i++) {
8957 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]);
8958
8959 ixgbe_get_ring_stats64(stats, ring);
8960 }
8961 for (i = 0; i < adapter->num_xdp_queues; i++) {
8962 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]);
8963
8964 ixgbe_get_ring_stats64(stats, ring);
8965 }
8966 rcu_read_unlock();
8967
8968 /* following stats updated by ixgbe_watchdog_task() */
8969 stats->multicast = netdev->stats.multicast;
8970 stats->rx_errors = netdev->stats.rx_errors;
8971 stats->rx_length_errors = netdev->stats.rx_length_errors;
8972 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8973 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8974 }
8975
8976 #ifdef CONFIG_IXGBE_DCB
8977 /**
8978 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8979 * @adapter: pointer to ixgbe_adapter
8980 * @tc: number of traffic classes currently enabled
8981 *
8982 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8983 * 802.1Q priority maps to a packet buffer that exists.
8984 */
ixgbe_validate_rtr(struct ixgbe_adapter * adapter,u8 tc)8985 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8986 {
8987 struct ixgbe_hw *hw = &adapter->hw;
8988 u32 reg, rsave;
8989 int i;
8990
8991 /* 82598 have a static priority to TC mapping that can not
8992 * be changed so no validation is needed.
8993 */
8994 if (hw->mac.type == ixgbe_mac_82598EB)
8995 return;
8996
8997 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8998 rsave = reg;
8999
9000 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
9001 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
9002
9003 /* If up2tc is out of bounds default to zero */
9004 if (up2tc > tc)
9005 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
9006 }
9007
9008 if (reg != rsave)
9009 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
9010
9011 return;
9012 }
9013
9014 /**
9015 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
9016 * @adapter: Pointer to adapter struct
9017 *
9018 * Populate the netdev user priority to tc map
9019 */
ixgbe_set_prio_tc_map(struct ixgbe_adapter * adapter)9020 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
9021 {
9022 struct net_device *dev = adapter->netdev;
9023 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
9024 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
9025 u8 prio;
9026
9027 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
9028 u8 tc = 0;
9029
9030 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
9031 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
9032 else if (ets)
9033 tc = ets->prio_tc[prio];
9034
9035 netdev_set_prio_tc_map(dev, prio, tc);
9036 }
9037 }
9038
9039 #endif /* CONFIG_IXGBE_DCB */
ixgbe_reassign_macvlan_pool(struct net_device * vdev,struct netdev_nested_priv * priv)9040 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev,
9041 struct netdev_nested_priv *priv)
9042 {
9043 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
9044 struct ixgbe_fwd_adapter *accel;
9045 int pool;
9046
9047 /* we only care about macvlans... */
9048 if (!netif_is_macvlan(vdev))
9049 return 0;
9050
9051 /* that have hardware offload enabled... */
9052 accel = macvlan_accel_priv(vdev);
9053 if (!accel)
9054 return 0;
9055
9056 /* If we can relocate to a different bit do so */
9057 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9058 if (pool < adapter->num_rx_pools) {
9059 set_bit(pool, adapter->fwd_bitmask);
9060 accel->pool = pool;
9061 return 0;
9062 }
9063
9064 /* if we cannot find a free pool then disable the offload */
9065 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n");
9066 macvlan_release_l2fw_offload(vdev);
9067
9068 /* unbind the queues and drop the subordinate channel config */
9069 netdev_unbind_sb_channel(adapter->netdev, vdev);
9070 netdev_set_sb_channel(vdev, 0);
9071
9072 kfree(accel);
9073
9074 return 0;
9075 }
9076
ixgbe_defrag_macvlan_pools(struct net_device * dev)9077 static void ixgbe_defrag_macvlan_pools(struct net_device *dev)
9078 {
9079 struct ixgbe_adapter *adapter = netdev_priv(dev);
9080 struct netdev_nested_priv priv = {
9081 .data = (void *)adapter,
9082 };
9083
9084 /* flush any stale bits out of the fwd bitmask */
9085 bitmap_clear(adapter->fwd_bitmask, 1, 63);
9086
9087 /* walk through upper devices reassigning pools */
9088 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool,
9089 &priv);
9090 }
9091
9092 /**
9093 * ixgbe_setup_tc - configure net_device for multiple traffic classes
9094 *
9095 * @dev: net device to configure
9096 * @tc: number of traffic classes to enable
9097 */
ixgbe_setup_tc(struct net_device * dev,u8 tc)9098 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
9099 {
9100 struct ixgbe_adapter *adapter = netdev_priv(dev);
9101 struct ixgbe_hw *hw = &adapter->hw;
9102
9103 /* Hardware supports up to 8 traffic classes */
9104 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
9105 return -EINVAL;
9106
9107 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
9108 return -EINVAL;
9109
9110 /* Hardware has to reinitialize queues and interrupts to
9111 * match packet buffer alignment. Unfortunately, the
9112 * hardware is not flexible enough to do this dynamically.
9113 */
9114 if (netif_running(dev))
9115 ixgbe_close(dev);
9116 else
9117 ixgbe_reset(adapter);
9118
9119 ixgbe_clear_interrupt_scheme(adapter);
9120
9121 #ifdef CONFIG_IXGBE_DCB
9122 if (tc) {
9123 if (adapter->xdp_prog) {
9124 e_warn(probe, "DCB is not supported with XDP\n");
9125
9126 ixgbe_init_interrupt_scheme(adapter);
9127 if (netif_running(dev))
9128 ixgbe_open(dev);
9129 return -EINVAL;
9130 }
9131
9132 netdev_set_num_tc(dev, tc);
9133 ixgbe_set_prio_tc_map(adapter);
9134
9135 adapter->hw_tcs = tc;
9136 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
9137
9138 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
9139 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
9140 adapter->hw.fc.requested_mode = ixgbe_fc_none;
9141 }
9142 } else {
9143 netdev_reset_tc(dev);
9144
9145 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9146 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
9147
9148 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
9149 adapter->hw_tcs = tc;
9150
9151 adapter->temp_dcb_cfg.pfc_mode_enable = false;
9152 adapter->dcb_cfg.pfc_mode_enable = false;
9153 }
9154
9155 ixgbe_validate_rtr(adapter, tc);
9156
9157 #endif /* CONFIG_IXGBE_DCB */
9158 ixgbe_init_interrupt_scheme(adapter);
9159
9160 ixgbe_defrag_macvlan_pools(dev);
9161
9162 if (netif_running(dev))
9163 return ixgbe_open(dev);
9164
9165 return 0;
9166 }
9167
ixgbe_delete_clsu32(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls)9168 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
9169 struct tc_cls_u32_offload *cls)
9170 {
9171 u32 hdl = cls->knode.handle;
9172 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
9173 u32 loc = cls->knode.handle & 0xfffff;
9174 int err = 0, i, j;
9175 struct ixgbe_jump_table *jump = NULL;
9176
9177 if (loc > IXGBE_MAX_HW_ENTRIES)
9178 return -EINVAL;
9179
9180 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
9181 return -EINVAL;
9182
9183 /* Clear this filter in the link data it is associated with */
9184 if (uhtid != 0x800) {
9185 jump = adapter->jump_tables[uhtid];
9186 if (!jump)
9187 return -EINVAL;
9188 if (!test_bit(loc - 1, jump->child_loc_map))
9189 return -EINVAL;
9190 clear_bit(loc - 1, jump->child_loc_map);
9191 }
9192
9193 /* Check if the filter being deleted is a link */
9194 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9195 jump = adapter->jump_tables[i];
9196 if (jump && jump->link_hdl == hdl) {
9197 /* Delete filters in the hardware in the child hash
9198 * table associated with this link
9199 */
9200 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
9201 if (!test_bit(j, jump->child_loc_map))
9202 continue;
9203 spin_lock(&adapter->fdir_perfect_lock);
9204 err = ixgbe_update_ethtool_fdir_entry(adapter,
9205 NULL,
9206 j + 1);
9207 spin_unlock(&adapter->fdir_perfect_lock);
9208 clear_bit(j, jump->child_loc_map);
9209 }
9210 /* Remove resources for this link */
9211 kfree(jump->input);
9212 kfree(jump->mask);
9213 kfree(jump);
9214 adapter->jump_tables[i] = NULL;
9215 return err;
9216 }
9217 }
9218
9219 spin_lock(&adapter->fdir_perfect_lock);
9220 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
9221 spin_unlock(&adapter->fdir_perfect_lock);
9222 return err;
9223 }
9224
ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls)9225 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
9226 struct tc_cls_u32_offload *cls)
9227 {
9228 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9229
9230 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9231 return -EINVAL;
9232
9233 /* This ixgbe devices do not support hash tables at the moment
9234 * so abort when given hash tables.
9235 */
9236 if (cls->hnode.divisor > 0)
9237 return -EINVAL;
9238
9239 set_bit(uhtid - 1, &adapter->tables);
9240 return 0;
9241 }
9242
ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls)9243 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
9244 struct tc_cls_u32_offload *cls)
9245 {
9246 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9247
9248 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9249 return -EINVAL;
9250
9251 clear_bit(uhtid - 1, &adapter->tables);
9252 return 0;
9253 }
9254
9255 #ifdef CONFIG_NET_CLS_ACT
9256 struct upper_walk_data {
9257 struct ixgbe_adapter *adapter;
9258 u64 action;
9259 int ifindex;
9260 u8 queue;
9261 };
9262
get_macvlan_queue(struct net_device * upper,struct netdev_nested_priv * priv)9263 static int get_macvlan_queue(struct net_device *upper,
9264 struct netdev_nested_priv *priv)
9265 {
9266 if (netif_is_macvlan(upper)) {
9267 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper);
9268 struct ixgbe_adapter *adapter;
9269 struct upper_walk_data *data;
9270 int ifindex;
9271
9272 data = (struct upper_walk_data *)priv->data;
9273 ifindex = data->ifindex;
9274 adapter = data->adapter;
9275 if (vadapter && upper->ifindex == ifindex) {
9276 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
9277 data->action = data->queue;
9278 return 1;
9279 }
9280 }
9281
9282 return 0;
9283 }
9284
handle_redirect_action(struct ixgbe_adapter * adapter,int ifindex,u8 * queue,u64 * action)9285 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
9286 u8 *queue, u64 *action)
9287 {
9288 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
9289 unsigned int num_vfs = adapter->num_vfs, vf;
9290 struct netdev_nested_priv priv;
9291 struct upper_walk_data data;
9292 struct net_device *upper;
9293
9294 /* redirect to a SRIOV VF */
9295 for (vf = 0; vf < num_vfs; ++vf) {
9296 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
9297 if (upper->ifindex == ifindex) {
9298 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask);
9299 *action = vf + 1;
9300 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
9301 return 0;
9302 }
9303 }
9304
9305 /* redirect to a offloaded macvlan netdev */
9306 data.adapter = adapter;
9307 data.ifindex = ifindex;
9308 data.action = 0;
9309 data.queue = 0;
9310 priv.data = (void *)&data;
9311 if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
9312 get_macvlan_queue, &priv)) {
9313 *action = data.action;
9314 *queue = data.queue;
9315
9316 return 0;
9317 }
9318
9319 return -EINVAL;
9320 }
9321
parse_tc_actions(struct ixgbe_adapter * adapter,struct tcf_exts * exts,u64 * action,u8 * queue)9322 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9323 struct tcf_exts *exts, u64 *action, u8 *queue)
9324 {
9325 const struct tc_action *a;
9326 int i;
9327
9328 if (!tcf_exts_has_actions(exts))
9329 return -EINVAL;
9330
9331 tcf_exts_for_each_action(i, a, exts) {
9332 /* Drop action */
9333 if (is_tcf_gact_shot(a)) {
9334 *action = IXGBE_FDIR_DROP_QUEUE;
9335 *queue = IXGBE_FDIR_DROP_QUEUE;
9336 return 0;
9337 }
9338
9339 /* Redirect to a VF or a offloaded macvlan */
9340 if (is_tcf_mirred_egress_redirect(a)) {
9341 struct net_device *dev = tcf_mirred_dev(a);
9342
9343 if (!dev)
9344 return -EINVAL;
9345 return handle_redirect_action(adapter, dev->ifindex,
9346 queue, action);
9347 }
9348
9349 return -EINVAL;
9350 }
9351
9352 return -EINVAL;
9353 }
9354 #else
parse_tc_actions(struct ixgbe_adapter * adapter,struct tcf_exts * exts,u64 * action,u8 * queue)9355 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9356 struct tcf_exts *exts, u64 *action, u8 *queue)
9357 {
9358 return -EINVAL;
9359 }
9360 #endif /* CONFIG_NET_CLS_ACT */
9361
ixgbe_clsu32_build_input(struct ixgbe_fdir_filter * input,union ixgbe_atr_input * mask,struct tc_cls_u32_offload * cls,struct ixgbe_mat_field * field_ptr,struct ixgbe_nexthdr * nexthdr)9362 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
9363 union ixgbe_atr_input *mask,
9364 struct tc_cls_u32_offload *cls,
9365 struct ixgbe_mat_field *field_ptr,
9366 struct ixgbe_nexthdr *nexthdr)
9367 {
9368 int i, j, off;
9369 __be32 val, m;
9370 bool found_entry = false, found_jump_field = false;
9371
9372 for (i = 0; i < cls->knode.sel->nkeys; i++) {
9373 off = cls->knode.sel->keys[i].off;
9374 val = cls->knode.sel->keys[i].val;
9375 m = cls->knode.sel->keys[i].mask;
9376
9377 for (j = 0; field_ptr[j].val; j++) {
9378 if (field_ptr[j].off == off) {
9379 field_ptr[j].val(input, mask, (__force u32)val,
9380 (__force u32)m);
9381 input->filter.formatted.flow_type |=
9382 field_ptr[j].type;
9383 found_entry = true;
9384 break;
9385 }
9386 }
9387 if (nexthdr) {
9388 if (nexthdr->off == cls->knode.sel->keys[i].off &&
9389 nexthdr->val ==
9390 (__force u32)cls->knode.sel->keys[i].val &&
9391 nexthdr->mask ==
9392 (__force u32)cls->knode.sel->keys[i].mask)
9393 found_jump_field = true;
9394 else
9395 continue;
9396 }
9397 }
9398
9399 if (nexthdr && !found_jump_field)
9400 return -EINVAL;
9401
9402 if (!found_entry)
9403 return 0;
9404
9405 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
9406 IXGBE_ATR_L4TYPE_MASK;
9407
9408 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
9409 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
9410
9411 return 0;
9412 }
9413
ixgbe_configure_clsu32(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls)9414 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
9415 struct tc_cls_u32_offload *cls)
9416 {
9417 __be16 protocol = cls->common.protocol;
9418 u32 loc = cls->knode.handle & 0xfffff;
9419 struct ixgbe_hw *hw = &adapter->hw;
9420 struct ixgbe_mat_field *field_ptr;
9421 struct ixgbe_fdir_filter *input = NULL;
9422 union ixgbe_atr_input *mask = NULL;
9423 struct ixgbe_jump_table *jump = NULL;
9424 int i, err = -EINVAL;
9425 u8 queue;
9426 u32 uhtid, link_uhtid;
9427
9428 uhtid = TC_U32_USERHTID(cls->knode.handle);
9429 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
9430
9431 /* At the moment cls_u32 jumps to network layer and skips past
9432 * L2 headers. The canonical method to match L2 frames is to use
9433 * negative values. However this is error prone at best but really
9434 * just broken because there is no way to "know" what sort of hdr
9435 * is in front of the network layer. Fix cls_u32 to support L2
9436 * headers when needed.
9437 */
9438 if (protocol != htons(ETH_P_IP))
9439 return err;
9440
9441 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
9442 e_err(drv, "Location out of range\n");
9443 return err;
9444 }
9445
9446 /* cls u32 is a graph starting at root node 0x800. The driver tracks
9447 * links and also the fields used to advance the parser across each
9448 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
9449 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
9450 * To add support for new nodes update ixgbe_model.h parse structures
9451 * this function _should_ be generic try not to hardcode values here.
9452 */
9453 if (uhtid == 0x800) {
9454 field_ptr = (adapter->jump_tables[0])->mat;
9455 } else {
9456 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9457 return err;
9458 if (!adapter->jump_tables[uhtid])
9459 return err;
9460 field_ptr = (adapter->jump_tables[uhtid])->mat;
9461 }
9462
9463 if (!field_ptr)
9464 return err;
9465
9466 /* At this point we know the field_ptr is valid and need to either
9467 * build cls_u32 link or attach filter. Because adding a link to
9468 * a handle that does not exist is invalid and the same for adding
9469 * rules to handles that don't exist.
9470 */
9471
9472 if (link_uhtid) {
9473 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
9474
9475 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
9476 return err;
9477
9478 if (!test_bit(link_uhtid - 1, &adapter->tables))
9479 return err;
9480
9481 /* Multiple filters as links to the same hash table are not
9482 * supported. To add a new filter with the same next header
9483 * but different match/jump conditions, create a new hash table
9484 * and link to it.
9485 */
9486 if (adapter->jump_tables[link_uhtid] &&
9487 (adapter->jump_tables[link_uhtid])->link_hdl) {
9488 e_err(drv, "Link filter exists for link: %x\n",
9489 link_uhtid);
9490 return err;
9491 }
9492
9493 for (i = 0; nexthdr[i].jump; i++) {
9494 if (nexthdr[i].o != cls->knode.sel->offoff ||
9495 nexthdr[i].s != cls->knode.sel->offshift ||
9496 nexthdr[i].m !=
9497 (__force u32)cls->knode.sel->offmask)
9498 return err;
9499
9500 jump = kzalloc(sizeof(*jump), GFP_KERNEL);
9501 if (!jump)
9502 return -ENOMEM;
9503 input = kzalloc(sizeof(*input), GFP_KERNEL);
9504 if (!input) {
9505 err = -ENOMEM;
9506 goto free_jump;
9507 }
9508 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9509 if (!mask) {
9510 err = -ENOMEM;
9511 goto free_input;
9512 }
9513 jump->input = input;
9514 jump->mask = mask;
9515 jump->link_hdl = cls->knode.handle;
9516
9517 err = ixgbe_clsu32_build_input(input, mask, cls,
9518 field_ptr, &nexthdr[i]);
9519 if (!err) {
9520 jump->mat = nexthdr[i].jump;
9521 adapter->jump_tables[link_uhtid] = jump;
9522 break;
9523 } else {
9524 kfree(mask);
9525 kfree(input);
9526 kfree(jump);
9527 }
9528 }
9529 return 0;
9530 }
9531
9532 input = kzalloc(sizeof(*input), GFP_KERNEL);
9533 if (!input)
9534 return -ENOMEM;
9535 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9536 if (!mask) {
9537 err = -ENOMEM;
9538 goto free_input;
9539 }
9540
9541 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
9542 if ((adapter->jump_tables[uhtid])->input)
9543 memcpy(input, (adapter->jump_tables[uhtid])->input,
9544 sizeof(*input));
9545 if ((adapter->jump_tables[uhtid])->mask)
9546 memcpy(mask, (adapter->jump_tables[uhtid])->mask,
9547 sizeof(*mask));
9548
9549 /* Lookup in all child hash tables if this location is already
9550 * filled with a filter
9551 */
9552 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9553 struct ixgbe_jump_table *link = adapter->jump_tables[i];
9554
9555 if (link && (test_bit(loc - 1, link->child_loc_map))) {
9556 e_err(drv, "Filter exists in location: %x\n",
9557 loc);
9558 err = -EINVAL;
9559 goto err_out;
9560 }
9561 }
9562 }
9563 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
9564 if (err)
9565 goto err_out;
9566
9567 err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
9568 &queue);
9569 if (err < 0)
9570 goto err_out;
9571
9572 input->sw_idx = loc;
9573
9574 spin_lock(&adapter->fdir_perfect_lock);
9575
9576 if (hlist_empty(&adapter->fdir_filter_list)) {
9577 memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
9578 err = ixgbe_fdir_set_input_mask_82599(hw, mask);
9579 if (err)
9580 goto err_out_w_lock;
9581 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
9582 err = -EINVAL;
9583 goto err_out_w_lock;
9584 }
9585
9586 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
9587 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
9588 input->sw_idx, queue);
9589 if (err)
9590 goto err_out_w_lock;
9591
9592 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
9593 spin_unlock(&adapter->fdir_perfect_lock);
9594
9595 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
9596 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
9597
9598 kfree(mask);
9599 return err;
9600 err_out_w_lock:
9601 spin_unlock(&adapter->fdir_perfect_lock);
9602 err_out:
9603 kfree(mask);
9604 free_input:
9605 kfree(input);
9606 free_jump:
9607 kfree(jump);
9608 return err;
9609 }
9610
ixgbe_setup_tc_cls_u32(struct ixgbe_adapter * adapter,struct tc_cls_u32_offload * cls_u32)9611 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter,
9612 struct tc_cls_u32_offload *cls_u32)
9613 {
9614 switch (cls_u32->command) {
9615 case TC_CLSU32_NEW_KNODE:
9616 case TC_CLSU32_REPLACE_KNODE:
9617 return ixgbe_configure_clsu32(adapter, cls_u32);
9618 case TC_CLSU32_DELETE_KNODE:
9619 return ixgbe_delete_clsu32(adapter, cls_u32);
9620 case TC_CLSU32_NEW_HNODE:
9621 case TC_CLSU32_REPLACE_HNODE:
9622 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32);
9623 case TC_CLSU32_DELETE_HNODE:
9624 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32);
9625 default:
9626 return -EOPNOTSUPP;
9627 }
9628 }
9629
ixgbe_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)9630 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9631 void *cb_priv)
9632 {
9633 struct ixgbe_adapter *adapter = cb_priv;
9634
9635 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
9636 return -EOPNOTSUPP;
9637
9638 switch (type) {
9639 case TC_SETUP_CLSU32:
9640 return ixgbe_setup_tc_cls_u32(adapter, type_data);
9641 default:
9642 return -EOPNOTSUPP;
9643 }
9644 }
9645
ixgbe_setup_tc_mqprio(struct net_device * dev,struct tc_mqprio_qopt * mqprio)9646 static int ixgbe_setup_tc_mqprio(struct net_device *dev,
9647 struct tc_mqprio_qopt *mqprio)
9648 {
9649 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9650 return ixgbe_setup_tc(dev, mqprio->num_tc);
9651 }
9652
9653 static LIST_HEAD(ixgbe_block_cb_list);
9654
__ixgbe_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)9655 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type,
9656 void *type_data)
9657 {
9658 struct ixgbe_adapter *adapter = netdev_priv(dev);
9659
9660 switch (type) {
9661 case TC_SETUP_BLOCK:
9662 return flow_block_cb_setup_simple(type_data,
9663 &ixgbe_block_cb_list,
9664 ixgbe_setup_tc_block_cb,
9665 adapter, adapter, true);
9666 case TC_SETUP_QDISC_MQPRIO:
9667 return ixgbe_setup_tc_mqprio(dev, type_data);
9668 default:
9669 return -EOPNOTSUPP;
9670 }
9671 }
9672
9673 #ifdef CONFIG_PCI_IOV
ixgbe_sriov_reinit(struct ixgbe_adapter * adapter)9674 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
9675 {
9676 struct net_device *netdev = adapter->netdev;
9677
9678 rtnl_lock();
9679 ixgbe_setup_tc(netdev, adapter->hw_tcs);
9680 rtnl_unlock();
9681 }
9682
9683 #endif
ixgbe_do_reset(struct net_device * netdev)9684 void ixgbe_do_reset(struct net_device *netdev)
9685 {
9686 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9687
9688 if (netif_running(netdev))
9689 ixgbe_reinit_locked(adapter);
9690 else
9691 ixgbe_reset(adapter);
9692 }
9693
ixgbe_fix_features(struct net_device * netdev,netdev_features_t features)9694 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
9695 netdev_features_t features)
9696 {
9697 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9698
9699 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
9700 if (!(features & NETIF_F_RXCSUM))
9701 features &= ~NETIF_F_LRO;
9702
9703 /* Turn off LRO if not RSC capable */
9704 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
9705 features &= ~NETIF_F_LRO;
9706
9707 if (adapter->xdp_prog && (features & NETIF_F_LRO)) {
9708 e_dev_err("LRO is not supported with XDP\n");
9709 features &= ~NETIF_F_LRO;
9710 }
9711
9712 return features;
9713 }
9714
ixgbe_reset_l2fw_offload(struct ixgbe_adapter * adapter)9715 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter)
9716 {
9717 int rss = min_t(int, ixgbe_max_rss_indices(adapter),
9718 num_online_cpus());
9719
9720 /* go back to full RSS if we're not running SR-IOV */
9721 if (!adapter->ring_feature[RING_F_VMDQ].offset)
9722 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED |
9723 IXGBE_FLAG_SRIOV_ENABLED);
9724
9725 adapter->ring_feature[RING_F_RSS].limit = rss;
9726 adapter->ring_feature[RING_F_VMDQ].limit = 1;
9727
9728 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs);
9729 }
9730
ixgbe_set_features(struct net_device * netdev,netdev_features_t features)9731 static int ixgbe_set_features(struct net_device *netdev,
9732 netdev_features_t features)
9733 {
9734 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9735 netdev_features_t changed = netdev->features ^ features;
9736 bool need_reset = false;
9737
9738 /* Make sure RSC matches LRO, reset if change */
9739 if (!(features & NETIF_F_LRO)) {
9740 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9741 need_reset = true;
9742 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
9743 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
9744 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
9745 if (adapter->rx_itr_setting == 1 ||
9746 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
9747 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9748 need_reset = true;
9749 } else if ((changed ^ features) & NETIF_F_LRO) {
9750 e_info(probe, "rx-usecs set too low, "
9751 "disabling RSC\n");
9752 }
9753 }
9754
9755 /*
9756 * Check if Flow Director n-tuple support or hw_tc support was
9757 * enabled or disabled. If the state changed, we need to reset.
9758 */
9759 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
9760 /* turn off ATR, enable perfect filters and reset */
9761 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
9762 need_reset = true;
9763
9764 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
9765 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9766 } else {
9767 /* turn off perfect filters, enable ATR and reset */
9768 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
9769 need_reset = true;
9770
9771 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9772
9773 /* We cannot enable ATR if SR-IOV is enabled */
9774 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9775 /* We cannot enable ATR if we have 2 or more tcs */
9776 (adapter->hw_tcs > 1) ||
9777 /* We cannot enable ATR if RSS is disabled */
9778 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9779 /* A sample rate of 0 indicates ATR disabled */
9780 (!adapter->atr_sample_rate))
9781 ; /* do nothing not supported */
9782 else /* otherwise supported and set the flag */
9783 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
9784 }
9785
9786 if (changed & NETIF_F_RXALL)
9787 need_reset = true;
9788
9789 netdev->features = features;
9790
9791 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1)
9792 ixgbe_reset_l2fw_offload(adapter);
9793 else if (need_reset)
9794 ixgbe_do_reset(netdev);
9795 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9796 NETIF_F_HW_VLAN_CTAG_FILTER))
9797 ixgbe_set_rx_mode(netdev);
9798
9799 return 1;
9800 }
9801
ixgbe_ndo_fdb_add(struct ndmsg * ndm,struct nlattr * tb[],struct net_device * dev,const unsigned char * addr,u16 vid,u16 flags,struct netlink_ext_ack * extack)9802 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
9803 struct net_device *dev,
9804 const unsigned char *addr, u16 vid,
9805 u16 flags,
9806 struct netlink_ext_ack *extack)
9807 {
9808 /* guarantee we can provide a unique filter for the unicast address */
9809 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
9810 struct ixgbe_adapter *adapter = netdev_priv(dev);
9811 u16 pool = VMDQ_P(0);
9812
9813 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
9814 return -ENOMEM;
9815 }
9816
9817 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
9818 }
9819
9820 /**
9821 * ixgbe_configure_bridge_mode - set various bridge modes
9822 * @adapter: the private structure
9823 * @mode: requested bridge mode
9824 *
9825 * Configure some settings require for various bridge modes.
9826 **/
ixgbe_configure_bridge_mode(struct ixgbe_adapter * adapter,__u16 mode)9827 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9828 __u16 mode)
9829 {
9830 struct ixgbe_hw *hw = &adapter->hw;
9831 unsigned int p, num_pools;
9832 u32 vmdctl;
9833
9834 switch (mode) {
9835 case BRIDGE_MODE_VEPA:
9836 /* disable Tx loopback, rely on switch hairpin mode */
9837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
9838
9839 /* must enable Rx switching replication to allow multicast
9840 * packet reception on all VFs, and to enable source address
9841 * pruning.
9842 */
9843 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9844 vmdctl |= IXGBE_VT_CTL_REPLEN;
9845 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9846
9847 /* enable Rx source address pruning. Note, this requires
9848 * replication to be enabled or else it does nothing.
9849 */
9850 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9851 for (p = 0; p < num_pools; p++) {
9852 if (hw->mac.ops.set_source_address_pruning)
9853 hw->mac.ops.set_source_address_pruning(hw,
9854 true,
9855 p);
9856 }
9857 break;
9858 case BRIDGE_MODE_VEB:
9859 /* enable Tx loopback for internal VF/PF communication */
9860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9861 IXGBE_PFDTXGSWC_VT_LBEN);
9862
9863 /* disable Rx switching replication unless we have SR-IOV
9864 * virtual functions
9865 */
9866 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9867 if (!adapter->num_vfs)
9868 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9869 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9870
9871 /* disable Rx source address pruning, since we don't expect to
9872 * be receiving external loopback of our transmitted frames.
9873 */
9874 num_pools = adapter->num_vfs + adapter->num_rx_pools;
9875 for (p = 0; p < num_pools; p++) {
9876 if (hw->mac.ops.set_source_address_pruning)
9877 hw->mac.ops.set_source_address_pruning(hw,
9878 false,
9879 p);
9880 }
9881 break;
9882 default:
9883 return -EINVAL;
9884 }
9885
9886 adapter->bridge_mode = mode;
9887
9888 e_info(drv, "enabling bridge mode: %s\n",
9889 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9890
9891 return 0;
9892 }
9893
ixgbe_ndo_bridge_setlink(struct net_device * dev,struct nlmsghdr * nlh,u16 flags,struct netlink_ext_ack * extack)9894 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
9895 struct nlmsghdr *nlh, u16 flags,
9896 struct netlink_ext_ack *extack)
9897 {
9898 struct ixgbe_adapter *adapter = netdev_priv(dev);
9899 struct nlattr *attr, *br_spec;
9900 int rem;
9901
9902 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9903 return -EOPNOTSUPP;
9904
9905 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
9906 if (!br_spec)
9907 return -EINVAL;
9908
9909 nla_for_each_nested(attr, br_spec, rem) {
9910 int status;
9911 __u16 mode;
9912
9913 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9914 continue;
9915
9916 if (nla_len(attr) < sizeof(mode))
9917 return -EINVAL;
9918
9919 mode = nla_get_u16(attr);
9920 status = ixgbe_configure_bridge_mode(adapter, mode);
9921 if (status)
9922 return status;
9923
9924 break;
9925 }
9926
9927 return 0;
9928 }
9929
ixgbe_ndo_bridge_getlink(struct sk_buff * skb,u32 pid,u32 seq,struct net_device * dev,u32 filter_mask,int nlflags)9930 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
9931 struct net_device *dev,
9932 u32 filter_mask, int nlflags)
9933 {
9934 struct ixgbe_adapter *adapter = netdev_priv(dev);
9935
9936 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9937 return 0;
9938
9939 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
9940 adapter->bridge_mode, 0, 0, nlflags,
9941 filter_mask, NULL);
9942 }
9943
ixgbe_fwd_add(struct net_device * pdev,struct net_device * vdev)9944 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9945 {
9946 struct ixgbe_adapter *adapter = netdev_priv(pdev);
9947 struct ixgbe_fwd_adapter *accel;
9948 int tcs = adapter->hw_tcs ? : 1;
9949 int pool, err;
9950
9951 if (adapter->xdp_prog) {
9952 e_warn(probe, "L2FW offload is not supported with XDP\n");
9953 return ERR_PTR(-EINVAL);
9954 }
9955
9956 /* The hardware supported by ixgbe only filters on the destination MAC
9957 * address. In order to avoid issues we only support offloading modes
9958 * where the hardware can actually provide the functionality.
9959 */
9960 if (!macvlan_supports_dest_filter(vdev))
9961 return ERR_PTR(-EMEDIUMTYPE);
9962
9963 /* We need to lock down the macvlan to be a single queue device so that
9964 * we can reuse the tc_to_txq field in the macvlan netdev to represent
9965 * the queue mapping to our netdev.
9966 */
9967 if (netif_is_multiqueue(vdev))
9968 return ERR_PTR(-ERANGE);
9969
9970 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9971 if (pool == adapter->num_rx_pools) {
9972 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools;
9973 u16 reserved_pools;
9974
9975 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
9976 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) ||
9977 adapter->num_rx_pools > IXGBE_MAX_MACVLANS)
9978 return ERR_PTR(-EBUSY);
9979
9980 /* Hardware has a limited number of available pools. Each VF,
9981 * and the PF require a pool. Check to ensure we don't
9982 * attempt to use more then the available number of pools.
9983 */
9984 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
9985 return ERR_PTR(-EBUSY);
9986
9987 /* Enable VMDq flag so device will be set in VM mode */
9988 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED |
9989 IXGBE_FLAG_SRIOV_ENABLED;
9990
9991 /* Try to reserve as many queues per pool as possible,
9992 * we start with the configurations that support 4 queues
9993 * per pools, followed by 2, and then by just 1 per pool.
9994 */
9995 if (used_pools < 32 && adapter->num_rx_pools < 16)
9996 reserved_pools = min_t(u16,
9997 32 - used_pools,
9998 16 - adapter->num_rx_pools);
9999 else if (adapter->num_rx_pools < 32)
10000 reserved_pools = min_t(u16,
10001 64 - used_pools,
10002 32 - adapter->num_rx_pools);
10003 else
10004 reserved_pools = 64 - used_pools;
10005
10006
10007 if (!reserved_pools)
10008 return ERR_PTR(-EBUSY);
10009
10010 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools;
10011
10012 /* Force reinit of ring allocation with VMDQ enabled */
10013 err = ixgbe_setup_tc(pdev, adapter->hw_tcs);
10014 if (err)
10015 return ERR_PTR(err);
10016
10017 if (pool >= adapter->num_rx_pools)
10018 return ERR_PTR(-ENOMEM);
10019 }
10020
10021 accel = kzalloc(sizeof(*accel), GFP_KERNEL);
10022 if (!accel)
10023 return ERR_PTR(-ENOMEM);
10024
10025 set_bit(pool, adapter->fwd_bitmask);
10026 netdev_set_sb_channel(vdev, pool);
10027 accel->pool = pool;
10028 accel->netdev = vdev;
10029
10030 if (!netif_running(pdev))
10031 return accel;
10032
10033 err = ixgbe_fwd_ring_up(adapter, accel);
10034 if (err)
10035 return ERR_PTR(err);
10036
10037 return accel;
10038 }
10039
ixgbe_fwd_del(struct net_device * pdev,void * priv)10040 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
10041 {
10042 struct ixgbe_fwd_adapter *accel = priv;
10043 struct ixgbe_adapter *adapter = netdev_priv(pdev);
10044 unsigned int rxbase = accel->rx_base_queue;
10045 unsigned int i;
10046
10047 /* delete unicast filter associated with offloaded interface */
10048 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr,
10049 VMDQ_P(accel->pool));
10050
10051 /* Allow remaining Rx packets to get flushed out of the
10052 * Rx FIFO before we drop the netdev for the ring.
10053 */
10054 usleep_range(10000, 20000);
10055
10056 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
10057 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i];
10058 struct ixgbe_q_vector *qv = ring->q_vector;
10059
10060 /* Make sure we aren't processing any packets and clear
10061 * netdev to shut down the ring.
10062 */
10063 if (netif_running(adapter->netdev))
10064 napi_synchronize(&qv->napi);
10065 ring->netdev = NULL;
10066 }
10067
10068 /* unbind the queues and drop the subordinate channel config */
10069 netdev_unbind_sb_channel(pdev, accel->netdev);
10070 netdev_set_sb_channel(accel->netdev, 0);
10071
10072 clear_bit(accel->pool, adapter->fwd_bitmask);
10073 kfree(accel);
10074 }
10075
10076 #define IXGBE_MAX_MAC_HDR_LEN 127
10077 #define IXGBE_MAX_NETWORK_HDR_LEN 511
10078
10079 static netdev_features_t
ixgbe_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)10080 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
10081 netdev_features_t features)
10082 {
10083 unsigned int network_hdr_len, mac_hdr_len;
10084
10085 /* Make certain the headers can be described by a context descriptor */
10086 mac_hdr_len = skb_network_header(skb) - skb->data;
10087 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
10088 return features & ~(NETIF_F_HW_CSUM |
10089 NETIF_F_SCTP_CRC |
10090 NETIF_F_GSO_UDP_L4 |
10091 NETIF_F_HW_VLAN_CTAG_TX |
10092 NETIF_F_TSO |
10093 NETIF_F_TSO6);
10094
10095 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
10096 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
10097 return features & ~(NETIF_F_HW_CSUM |
10098 NETIF_F_SCTP_CRC |
10099 NETIF_F_GSO_UDP_L4 |
10100 NETIF_F_TSO |
10101 NETIF_F_TSO6);
10102
10103 /* We can only support IPV4 TSO in tunnels if we can mangle the
10104 * inner IP ID field, so strip TSO if MANGLEID is not supported.
10105 * IPsec offoad sets skb->encapsulation but still can handle
10106 * the TSO, so it's the exception.
10107 */
10108 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) {
10109 #ifdef CONFIG_IXGBE_IPSEC
10110 if (!secpath_exists(skb))
10111 #endif
10112 features &= ~NETIF_F_TSO;
10113 }
10114
10115 return features;
10116 }
10117
ixgbe_xdp_setup(struct net_device * dev,struct bpf_prog * prog)10118 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
10119 {
10120 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
10121 struct ixgbe_adapter *adapter = netdev_priv(dev);
10122 struct bpf_prog *old_prog;
10123 bool need_reset;
10124 int num_queues;
10125
10126 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
10127 return -EINVAL;
10128
10129 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
10130 return -EINVAL;
10131
10132 /* verify ixgbe ring attributes are sufficient for XDP */
10133 for (i = 0; i < adapter->num_rx_queues; i++) {
10134 struct ixgbe_ring *ring = adapter->rx_ring[i];
10135
10136 if (ring_is_rsc_enabled(ring))
10137 return -EINVAL;
10138
10139 if (frame_size > ixgbe_rx_bufsz(ring))
10140 return -EINVAL;
10141 }
10142
10143 if (nr_cpu_ids > MAX_XDP_QUEUES)
10144 return -ENOMEM;
10145
10146 old_prog = xchg(&adapter->xdp_prog, prog);
10147 need_reset = (!!prog != !!old_prog);
10148
10149 /* If transitioning XDP modes reconfigure rings */
10150 if (need_reset) {
10151 int err;
10152
10153 if (!prog)
10154 /* Wait until ndo_xsk_wakeup completes. */
10155 synchronize_rcu();
10156 err = ixgbe_setup_tc(dev, adapter->hw_tcs);
10157
10158 if (err) {
10159 rcu_assign_pointer(adapter->xdp_prog, old_prog);
10160 return -EINVAL;
10161 }
10162 } else {
10163 for (i = 0; i < adapter->num_rx_queues; i++)
10164 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
10165 adapter->xdp_prog);
10166 }
10167
10168 if (old_prog)
10169 bpf_prog_put(old_prog);
10170
10171 /* Kick start the NAPI context if there is an AF_XDP socket open
10172 * on that queue id. This so that receiving will start.
10173 */
10174 if (need_reset && prog) {
10175 num_queues = min_t(int, adapter->num_rx_queues,
10176 adapter->num_xdp_queues);
10177 for (i = 0; i < num_queues; i++)
10178 if (adapter->xdp_ring[i]->xsk_pool)
10179 (void)ixgbe_xsk_wakeup(adapter->netdev, i,
10180 XDP_WAKEUP_RX);
10181 }
10182
10183 return 0;
10184 }
10185
ixgbe_xdp(struct net_device * dev,struct netdev_bpf * xdp)10186 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp)
10187 {
10188 struct ixgbe_adapter *adapter = netdev_priv(dev);
10189
10190 switch (xdp->command) {
10191 case XDP_SETUP_PROG:
10192 return ixgbe_xdp_setup(dev, xdp->prog);
10193 case XDP_SETUP_XSK_POOL:
10194 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool,
10195 xdp->xsk.queue_id);
10196
10197 default:
10198 return -EINVAL;
10199 }
10200 }
10201
ixgbe_xdp_ring_update_tail(struct ixgbe_ring * ring)10202 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring)
10203 {
10204 /* Force memory writes to complete before letting h/w know there
10205 * are new descriptors to fetch.
10206 */
10207 wmb();
10208 writel(ring->next_to_use, ring->tail);
10209 }
10210
ixgbe_xdp_xmit(struct net_device * dev,int n,struct xdp_frame ** frames,u32 flags)10211 static int ixgbe_xdp_xmit(struct net_device *dev, int n,
10212 struct xdp_frame **frames, u32 flags)
10213 {
10214 struct ixgbe_adapter *adapter = netdev_priv(dev);
10215 struct ixgbe_ring *ring;
10216 int nxmit = 0;
10217 int i;
10218
10219 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
10220 return -ENETDOWN;
10221
10222 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
10223 return -EINVAL;
10224
10225 /* During program transitions its possible adapter->xdp_prog is assigned
10226 * but ring has not been configured yet. In this case simply abort xmit.
10227 */
10228 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL;
10229 if (unlikely(!ring))
10230 return -ENXIO;
10231
10232 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state)))
10233 return -ENXIO;
10234
10235 for (i = 0; i < n; i++) {
10236 struct xdp_frame *xdpf = frames[i];
10237 int err;
10238
10239 err = ixgbe_xmit_xdp_ring(adapter, xdpf);
10240 if (err != IXGBE_XDP_TX)
10241 break;
10242 nxmit++;
10243 }
10244
10245 if (unlikely(flags & XDP_XMIT_FLUSH))
10246 ixgbe_xdp_ring_update_tail(ring);
10247
10248 return nxmit;
10249 }
10250
10251 static const struct net_device_ops ixgbe_netdev_ops = {
10252 .ndo_open = ixgbe_open,
10253 .ndo_stop = ixgbe_close,
10254 .ndo_start_xmit = ixgbe_xmit_frame,
10255 .ndo_set_rx_mode = ixgbe_set_rx_mode,
10256 .ndo_validate_addr = eth_validate_addr,
10257 .ndo_set_mac_address = ixgbe_set_mac,
10258 .ndo_change_mtu = ixgbe_change_mtu,
10259 .ndo_tx_timeout = ixgbe_tx_timeout,
10260 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
10261 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
10262 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
10263 .ndo_eth_ioctl = ixgbe_ioctl,
10264 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
10265 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
10266 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
10267 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
10268 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
10269 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
10270 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
10271 .ndo_get_stats64 = ixgbe_get_stats64,
10272 .ndo_setup_tc = __ixgbe_setup_tc,
10273 #ifdef IXGBE_FCOE
10274 .ndo_select_queue = ixgbe_select_queue,
10275 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
10276 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
10277 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
10278 .ndo_fcoe_enable = ixgbe_fcoe_enable,
10279 .ndo_fcoe_disable = ixgbe_fcoe_disable,
10280 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
10281 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
10282 #endif /* IXGBE_FCOE */
10283 .ndo_set_features = ixgbe_set_features,
10284 .ndo_fix_features = ixgbe_fix_features,
10285 .ndo_fdb_add = ixgbe_ndo_fdb_add,
10286 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
10287 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
10288 .ndo_dfwd_add_station = ixgbe_fwd_add,
10289 .ndo_dfwd_del_station = ixgbe_fwd_del,
10290 .ndo_features_check = ixgbe_features_check,
10291 .ndo_bpf = ixgbe_xdp,
10292 .ndo_xdp_xmit = ixgbe_xdp_xmit,
10293 .ndo_xsk_wakeup = ixgbe_xsk_wakeup,
10294 };
10295
ixgbe_disable_txr_hw(struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring)10296 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter,
10297 struct ixgbe_ring *tx_ring)
10298 {
10299 unsigned long wait_delay, delay_interval;
10300 struct ixgbe_hw *hw = &adapter->hw;
10301 u8 reg_idx = tx_ring->reg_idx;
10302 int wait_loop;
10303 u32 txdctl;
10304
10305 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
10306
10307 /* delay mechanism from ixgbe_disable_tx */
10308 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10309
10310 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10311 wait_delay = delay_interval;
10312
10313 while (wait_loop--) {
10314 usleep_range(wait_delay, wait_delay + 10);
10315 wait_delay += delay_interval * 2;
10316 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
10317
10318 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
10319 return;
10320 }
10321
10322 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n");
10323 }
10324
ixgbe_disable_txr(struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring)10325 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter,
10326 struct ixgbe_ring *tx_ring)
10327 {
10328 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10329 ixgbe_disable_txr_hw(adapter, tx_ring);
10330 }
10331
ixgbe_disable_rxr_hw(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring)10332 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter,
10333 struct ixgbe_ring *rx_ring)
10334 {
10335 unsigned long wait_delay, delay_interval;
10336 struct ixgbe_hw *hw = &adapter->hw;
10337 u8 reg_idx = rx_ring->reg_idx;
10338 int wait_loop;
10339 u32 rxdctl;
10340
10341 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10342 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
10343 rxdctl |= IXGBE_RXDCTL_SWFLSH;
10344
10345 /* write value back with RXDCTL.ENABLE bit cleared */
10346 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
10347
10348 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
10349 if (hw->mac.type == ixgbe_mac_82598EB &&
10350 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
10351 return;
10352
10353 /* delay mechanism from ixgbe_disable_rx */
10354 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10355
10356 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10357 wait_delay = delay_interval;
10358
10359 while (wait_loop--) {
10360 usleep_range(wait_delay, wait_delay + 10);
10361 wait_delay += delay_interval * 2;
10362 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10363
10364 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
10365 return;
10366 }
10367
10368 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n");
10369 }
10370
ixgbe_reset_txr_stats(struct ixgbe_ring * tx_ring)10371 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring)
10372 {
10373 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats));
10374 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats));
10375 }
10376
ixgbe_reset_rxr_stats(struct ixgbe_ring * rx_ring)10377 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring)
10378 {
10379 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats));
10380 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats));
10381 }
10382
10383 /**
10384 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings
10385 * @adapter: adapter structure
10386 * @ring: ring index
10387 *
10388 * This function disables a certain Rx/Tx/XDP Tx ring. The function
10389 * assumes that the netdev is running.
10390 **/
ixgbe_txrx_ring_disable(struct ixgbe_adapter * adapter,int ring)10391 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring)
10392 {
10393 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10394
10395 rx_ring = adapter->rx_ring[ring];
10396 tx_ring = adapter->tx_ring[ring];
10397 xdp_ring = adapter->xdp_ring[ring];
10398
10399 ixgbe_disable_txr(adapter, tx_ring);
10400 if (xdp_ring)
10401 ixgbe_disable_txr(adapter, xdp_ring);
10402 ixgbe_disable_rxr_hw(adapter, rx_ring);
10403
10404 if (xdp_ring)
10405 synchronize_rcu();
10406
10407 /* Rx/Tx/XDP Tx share the same napi context. */
10408 napi_disable(&rx_ring->q_vector->napi);
10409
10410 ixgbe_clean_tx_ring(tx_ring);
10411 if (xdp_ring)
10412 ixgbe_clean_tx_ring(xdp_ring);
10413 ixgbe_clean_rx_ring(rx_ring);
10414
10415 ixgbe_reset_txr_stats(tx_ring);
10416 if (xdp_ring)
10417 ixgbe_reset_txr_stats(xdp_ring);
10418 ixgbe_reset_rxr_stats(rx_ring);
10419 }
10420
10421 /**
10422 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings
10423 * @adapter: adapter structure
10424 * @ring: ring index
10425 *
10426 * This function enables a certain Rx/Tx/XDP Tx ring. The function
10427 * assumes that the netdev is running.
10428 **/
ixgbe_txrx_ring_enable(struct ixgbe_adapter * adapter,int ring)10429 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring)
10430 {
10431 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10432
10433 rx_ring = adapter->rx_ring[ring];
10434 tx_ring = adapter->tx_ring[ring];
10435 xdp_ring = adapter->xdp_ring[ring];
10436
10437 /* Rx/Tx/XDP Tx share the same napi context. */
10438 napi_enable(&rx_ring->q_vector->napi);
10439
10440 ixgbe_configure_tx_ring(adapter, tx_ring);
10441 if (xdp_ring)
10442 ixgbe_configure_tx_ring(adapter, xdp_ring);
10443 ixgbe_configure_rx_ring(adapter, rx_ring);
10444
10445 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10446 if (xdp_ring)
10447 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state);
10448 }
10449
10450 /**
10451 * ixgbe_enumerate_functions - Get the number of ports this device has
10452 * @adapter: adapter structure
10453 *
10454 * This function enumerates the phsyical functions co-located on a single slot,
10455 * in order to determine how many ports a device has. This is most useful in
10456 * determining the required GT/s of PCIe bandwidth necessary for optimal
10457 * performance.
10458 **/
ixgbe_enumerate_functions(struct ixgbe_adapter * adapter)10459 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
10460 {
10461 struct pci_dev *entry, *pdev = adapter->pdev;
10462 int physfns = 0;
10463
10464 /* Some cards can not use the generic count PCIe functions method,
10465 * because they are behind a parent switch, so we hardcode these with
10466 * the correct number of functions.
10467 */
10468 if (ixgbe_pcie_from_parent(&adapter->hw))
10469 physfns = 4;
10470
10471 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
10472 /* don't count virtual functions */
10473 if (entry->is_virtfn)
10474 continue;
10475
10476 /* When the devices on the bus don't all match our device ID,
10477 * we can't reliably determine the correct number of
10478 * functions. This can occur if a function has been direct
10479 * attached to a virtual machine using VT-d, for example. In
10480 * this case, simply return -1 to indicate this.
10481 */
10482 if ((entry->vendor != pdev->vendor) ||
10483 (entry->device != pdev->device))
10484 return -1;
10485
10486 physfns++;
10487 }
10488
10489 return physfns;
10490 }
10491
10492 /**
10493 * ixgbe_wol_supported - Check whether device supports WoL
10494 * @adapter: the adapter private structure
10495 * @device_id: the device ID
10496 * @subdevice_id: the subsystem device ID
10497 *
10498 * This function is used by probe and ethtool to determine
10499 * which devices have WoL support
10500 *
10501 **/
ixgbe_wol_supported(struct ixgbe_adapter * adapter,u16 device_id,u16 subdevice_id)10502 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
10503 u16 subdevice_id)
10504 {
10505 struct ixgbe_hw *hw = &adapter->hw;
10506 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
10507
10508 /* WOL not supported on 82598 */
10509 if (hw->mac.type == ixgbe_mac_82598EB)
10510 return false;
10511
10512 /* check eeprom to see if WOL is enabled for X540 and newer */
10513 if (hw->mac.type >= ixgbe_mac_X540) {
10514 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
10515 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
10516 (hw->bus.func == 0)))
10517 return true;
10518 }
10519
10520 /* WOL is determined based on device IDs for 82599 MACs */
10521 switch (device_id) {
10522 case IXGBE_DEV_ID_82599_SFP:
10523 /* Only these subdevices could supports WOL */
10524 switch (subdevice_id) {
10525 case IXGBE_SUBDEV_ID_82599_560FLR:
10526 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
10527 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
10528 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
10529 /* only support first port */
10530 if (hw->bus.func != 0)
10531 break;
10532 fallthrough;
10533 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
10534 case IXGBE_SUBDEV_ID_82599_SFP:
10535 case IXGBE_SUBDEV_ID_82599_RNDC:
10536 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
10537 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
10538 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
10539 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
10540 return true;
10541 }
10542 break;
10543 case IXGBE_DEV_ID_82599EN_SFP:
10544 /* Only these subdevices support WOL */
10545 switch (subdevice_id) {
10546 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
10547 return true;
10548 }
10549 break;
10550 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
10551 /* All except this subdevice support WOL */
10552 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
10553 return true;
10554 break;
10555 case IXGBE_DEV_ID_82599_KX4:
10556 return true;
10557 default:
10558 break;
10559 }
10560
10561 return false;
10562 }
10563
10564 /**
10565 * ixgbe_set_fw_version - Set FW version
10566 * @adapter: the adapter private structure
10567 *
10568 * This function is used by probe and ethtool to determine the FW version to
10569 * format to display. The FW version is taken from the EEPROM/NVM.
10570 */
ixgbe_set_fw_version(struct ixgbe_adapter * adapter)10571 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter)
10572 {
10573 struct ixgbe_hw *hw = &adapter->hw;
10574 struct ixgbe_nvm_version nvm_ver;
10575
10576 ixgbe_get_oem_prod_version(hw, &nvm_ver);
10577 if (nvm_ver.oem_valid) {
10578 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10579 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor,
10580 nvm_ver.oem_release);
10581 return;
10582 }
10583
10584 ixgbe_get_etk_id(hw, &nvm_ver);
10585 ixgbe_get_orom_version(hw, &nvm_ver);
10586
10587 if (nvm_ver.or_valid) {
10588 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10589 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major,
10590 nvm_ver.or_build, nvm_ver.or_patch);
10591 return;
10592 }
10593
10594 /* Set ETrack ID format */
10595 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10596 "0x%08x", nvm_ver.etk_id);
10597 }
10598
10599 /**
10600 * ixgbe_probe - Device Initialization Routine
10601 * @pdev: PCI device information struct
10602 * @ent: entry in ixgbe_pci_tbl
10603 *
10604 * Returns 0 on success, negative on failure
10605 *
10606 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
10607 * The OS initialization, configuring of the adapter private structure,
10608 * and a hardware reset occur.
10609 **/
ixgbe_probe(struct pci_dev * pdev,const struct pci_device_id * ent)10610 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10611 {
10612 struct net_device *netdev;
10613 struct ixgbe_adapter *adapter = NULL;
10614 struct ixgbe_hw *hw;
10615 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
10616 int i, err, pci_using_dac, expected_gts;
10617 unsigned int indices = MAX_TX_QUEUES;
10618 u8 part_str[IXGBE_PBANUM_LENGTH];
10619 bool disable_dev = false;
10620 #ifdef IXGBE_FCOE
10621 u16 device_caps;
10622 #endif
10623 u32 eec;
10624
10625 /* Catch broken hardware that put the wrong VF device ID in
10626 * the PCIe SR-IOV capability.
10627 */
10628 if (pdev->is_virtfn) {
10629 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
10630 pci_name(pdev), pdev->vendor, pdev->device);
10631 return -EINVAL;
10632 }
10633
10634 err = pci_enable_device_mem(pdev);
10635 if (err)
10636 return err;
10637
10638 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
10639 pci_using_dac = 1;
10640 } else {
10641 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10642 if (err) {
10643 dev_err(&pdev->dev,
10644 "No usable DMA configuration, aborting\n");
10645 goto err_dma;
10646 }
10647 pci_using_dac = 0;
10648 }
10649
10650 err = pci_request_mem_regions(pdev, ixgbe_driver_name);
10651 if (err) {
10652 dev_err(&pdev->dev,
10653 "pci_request_selected_regions failed 0x%x\n", err);
10654 goto err_pci_reg;
10655 }
10656
10657 pci_enable_pcie_error_reporting(pdev);
10658
10659 pci_set_master(pdev);
10660 pci_save_state(pdev);
10661
10662 if (ii->mac == ixgbe_mac_82598EB) {
10663 #ifdef CONFIG_IXGBE_DCB
10664 /* 8 TC w/ 4 queues per TC */
10665 indices = 4 * MAX_TRAFFIC_CLASS;
10666 #else
10667 indices = IXGBE_MAX_RSS_INDICES;
10668 #endif
10669 }
10670
10671 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
10672 if (!netdev) {
10673 err = -ENOMEM;
10674 goto err_alloc_etherdev;
10675 }
10676
10677 SET_NETDEV_DEV(netdev, &pdev->dev);
10678
10679 adapter = netdev_priv(netdev);
10680
10681 adapter->netdev = netdev;
10682 adapter->pdev = pdev;
10683 hw = &adapter->hw;
10684 hw->back = adapter;
10685 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
10686
10687 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
10688 pci_resource_len(pdev, 0));
10689 adapter->io_addr = hw->hw_addr;
10690 if (!hw->hw_addr) {
10691 err = -EIO;
10692 goto err_ioremap;
10693 }
10694
10695 netdev->netdev_ops = &ixgbe_netdev_ops;
10696 ixgbe_set_ethtool_ops(netdev);
10697 netdev->watchdog_timeo = 5 * HZ;
10698 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
10699
10700 /* Setup hw api */
10701 hw->mac.ops = *ii->mac_ops;
10702 hw->mac.type = ii->mac;
10703 hw->mvals = ii->mvals;
10704 if (ii->link_ops)
10705 hw->link.ops = *ii->link_ops;
10706
10707 /* EEPROM */
10708 hw->eeprom.ops = *ii->eeprom_ops;
10709 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
10710 if (ixgbe_removed(hw->hw_addr)) {
10711 err = -EIO;
10712 goto err_ioremap;
10713 }
10714 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
10715 if (!(eec & BIT(8)))
10716 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
10717
10718 /* PHY */
10719 hw->phy.ops = *ii->phy_ops;
10720 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
10721 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
10722 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
10723 hw->phy.mdio.mmds = 0;
10724 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10725 hw->phy.mdio.dev = netdev;
10726 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
10727 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
10728
10729 /* setup the private structure */
10730 err = ixgbe_sw_init(adapter, ii);
10731 if (err)
10732 goto err_sw_init;
10733
10734 switch (adapter->hw.mac.type) {
10735 case ixgbe_mac_X550:
10736 case ixgbe_mac_X550EM_x:
10737 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550;
10738 break;
10739 case ixgbe_mac_x550em_a:
10740 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a;
10741 break;
10742 default:
10743 break;
10744 }
10745
10746 /* Make sure the SWFW semaphore is in a valid state */
10747 if (hw->mac.ops.init_swfw_sync)
10748 hw->mac.ops.init_swfw_sync(hw);
10749
10750 /* Make it possible the adapter to be woken up via WOL */
10751 switch (adapter->hw.mac.type) {
10752 case ixgbe_mac_82599EB:
10753 case ixgbe_mac_X540:
10754 case ixgbe_mac_X550:
10755 case ixgbe_mac_X550EM_x:
10756 case ixgbe_mac_x550em_a:
10757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
10758 break;
10759 default:
10760 break;
10761 }
10762
10763 /*
10764 * If there is a fan on this device and it has failed log the
10765 * failure.
10766 */
10767 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
10768 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
10769 if (esdp & IXGBE_ESDP_SDP1)
10770 e_crit(probe, "Fan has stopped, replace the adapter\n");
10771 }
10772
10773 if (allow_unsupported_sfp)
10774 hw->allow_unsupported_sfp = allow_unsupported_sfp;
10775
10776 /* reset_hw fills in the perm_addr as well */
10777 hw->phy.reset_if_overtemp = true;
10778 err = hw->mac.ops.reset_hw(hw);
10779 hw->phy.reset_if_overtemp = false;
10780 ixgbe_set_eee_capable(adapter);
10781 if (err == -ENOENT) {
10782 err = 0;
10783 } else if (err == -EOPNOTSUPP) {
10784 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
10785 e_dev_err("Reload the driver after installing a supported module.\n");
10786 goto err_sw_init;
10787 } else if (err) {
10788 e_dev_err("HW Init failed: %d\n", err);
10789 goto err_sw_init;
10790 }
10791
10792 #ifdef CONFIG_PCI_IOV
10793 /* SR-IOV not supported on the 82598 */
10794 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
10795 goto skip_sriov;
10796 /* Mailbox */
10797 ixgbe_init_mbx_params_pf(hw);
10798 hw->mbx.ops = ii->mbx_ops;
10799 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
10800 ixgbe_enable_sriov(adapter, max_vfs);
10801 skip_sriov:
10802
10803 #endif
10804 netdev->features = NETIF_F_SG |
10805 NETIF_F_TSO |
10806 NETIF_F_TSO6 |
10807 NETIF_F_RXHASH |
10808 NETIF_F_RXCSUM |
10809 NETIF_F_HW_CSUM;
10810
10811 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
10812 NETIF_F_GSO_GRE_CSUM | \
10813 NETIF_F_GSO_IPXIP4 | \
10814 NETIF_F_GSO_IPXIP6 | \
10815 NETIF_F_GSO_UDP_TUNNEL | \
10816 NETIF_F_GSO_UDP_TUNNEL_CSUM)
10817
10818 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
10819 netdev->features |= NETIF_F_GSO_PARTIAL |
10820 IXGBE_GSO_PARTIAL_FEATURES;
10821
10822 if (hw->mac.type >= ixgbe_mac_82599EB)
10823 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
10824
10825 #ifdef CONFIG_IXGBE_IPSEC
10826 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \
10827 NETIF_F_HW_ESP_TX_CSUM | \
10828 NETIF_F_GSO_ESP)
10829
10830 if (adapter->ipsec)
10831 netdev->features |= IXGBE_ESP_FEATURES;
10832 #endif
10833 /* copy netdev features into list of user selectable features */
10834 netdev->hw_features |= netdev->features |
10835 NETIF_F_HW_VLAN_CTAG_FILTER |
10836 NETIF_F_HW_VLAN_CTAG_RX |
10837 NETIF_F_HW_VLAN_CTAG_TX |
10838 NETIF_F_RXALL |
10839 NETIF_F_HW_L2FW_DOFFLOAD;
10840
10841 if (hw->mac.type >= ixgbe_mac_82599EB)
10842 netdev->hw_features |= NETIF_F_NTUPLE |
10843 NETIF_F_HW_TC;
10844
10845 if (pci_using_dac)
10846 netdev->features |= NETIF_F_HIGHDMA;
10847
10848 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
10849 netdev->hw_enc_features |= netdev->vlan_features;
10850 netdev->mpls_features |= NETIF_F_SG |
10851 NETIF_F_TSO |
10852 NETIF_F_TSO6 |
10853 NETIF_F_HW_CSUM;
10854 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES;
10855
10856 /* set this bit last since it cannot be part of vlan_features */
10857 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
10858 NETIF_F_HW_VLAN_CTAG_RX |
10859 NETIF_F_HW_VLAN_CTAG_TX;
10860
10861 netdev->priv_flags |= IFF_UNICAST_FLT;
10862 netdev->priv_flags |= IFF_SUPP_NOFCS;
10863
10864 /* MTU range: 68 - 9710 */
10865 netdev->min_mtu = ETH_MIN_MTU;
10866 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
10867
10868 #ifdef CONFIG_IXGBE_DCB
10869 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
10870 netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
10871 #endif
10872
10873 #ifdef IXGBE_FCOE
10874 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
10875 unsigned int fcoe_l;
10876
10877 if (hw->mac.ops.get_device_caps) {
10878 hw->mac.ops.get_device_caps(hw, &device_caps);
10879 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
10880 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
10881 }
10882
10883
10884 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
10885 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
10886
10887 netdev->features |= NETIF_F_FSO |
10888 NETIF_F_FCOE_CRC;
10889
10890 netdev->vlan_features |= NETIF_F_FSO |
10891 NETIF_F_FCOE_CRC |
10892 NETIF_F_FCOE_MTU;
10893 }
10894 #endif /* IXGBE_FCOE */
10895 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
10896 netdev->hw_features |= NETIF_F_LRO;
10897 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
10898 netdev->features |= NETIF_F_LRO;
10899
10900 if (ixgbe_check_fw_error(adapter)) {
10901 err = -EIO;
10902 goto err_sw_init;
10903 }
10904
10905 /* make sure the EEPROM is good */
10906 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
10907 e_dev_err("The EEPROM Checksum Is Not Valid\n");
10908 err = -EIO;
10909 goto err_sw_init;
10910 }
10911
10912 eth_platform_get_mac_address(&adapter->pdev->dev,
10913 adapter->hw.mac.perm_addr);
10914
10915 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
10916
10917 if (!is_valid_ether_addr(netdev->dev_addr)) {
10918 e_dev_err("invalid MAC address\n");
10919 err = -EIO;
10920 goto err_sw_init;
10921 }
10922
10923 /* Set hw->mac.addr to permanent MAC address */
10924 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
10925 ixgbe_mac_set_default_filter(adapter);
10926
10927 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0);
10928
10929 if (ixgbe_removed(hw->hw_addr)) {
10930 err = -EIO;
10931 goto err_sw_init;
10932 }
10933 INIT_WORK(&adapter->service_task, ixgbe_service_task);
10934 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
10935 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
10936
10937 err = ixgbe_init_interrupt_scheme(adapter);
10938 if (err)
10939 goto err_sw_init;
10940
10941 for (i = 0; i < adapter->num_rx_queues; i++)
10942 u64_stats_init(&adapter->rx_ring[i]->syncp);
10943 for (i = 0; i < adapter->num_tx_queues; i++)
10944 u64_stats_init(&adapter->tx_ring[i]->syncp);
10945 for (i = 0; i < adapter->num_xdp_queues; i++)
10946 u64_stats_init(&adapter->xdp_ring[i]->syncp);
10947
10948 /* WOL not supported for all devices */
10949 adapter->wol = 0;
10950 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
10951 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
10952 pdev->subsystem_device);
10953 if (hw->wol_enabled)
10954 adapter->wol = IXGBE_WUFC_MAG;
10955
10956 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
10957
10958 /* save off EEPROM version number */
10959 ixgbe_set_fw_version(adapter);
10960
10961 /* pick up the PCI bus settings for reporting later */
10962 if (ixgbe_pcie_from_parent(hw))
10963 ixgbe_get_parent_bus_info(adapter);
10964 else
10965 hw->mac.ops.get_bus_info(hw);
10966
10967 /* calculate the expected PCIe bandwidth required for optimal
10968 * performance. Note that some older parts will never have enough
10969 * bandwidth due to being older generation PCIe parts. We clamp these
10970 * parts to ensure no warning is displayed if it can't be fixed.
10971 */
10972 switch (hw->mac.type) {
10973 case ixgbe_mac_82598EB:
10974 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
10975 break;
10976 default:
10977 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
10978 break;
10979 }
10980
10981 /* don't check link if we failed to enumerate functions */
10982 if (expected_gts > 0)
10983 ixgbe_check_minimum_link(adapter, expected_gts);
10984
10985 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
10986 if (err)
10987 strlcpy(part_str, "Unknown", sizeof(part_str));
10988 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
10989 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
10990 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
10991 part_str);
10992 else
10993 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
10994 hw->mac.type, hw->phy.type, part_str);
10995
10996 e_dev_info("%pM\n", netdev->dev_addr);
10997
10998 /* reset the hardware with the new settings */
10999 err = hw->mac.ops.start_hw(hw);
11000 if (err == -EACCES) {
11001 /* We are running on a pre-production device, log a warning */
11002 e_dev_warn("This device is a pre-production adapter/LOM. "
11003 "Please be aware there may be issues associated "
11004 "with your hardware. If you are experiencing "
11005 "problems please contact your Intel or hardware "
11006 "representative who provided you with this "
11007 "hardware.\n");
11008 }
11009 strcpy(netdev->name, "eth%d");
11010 pci_set_drvdata(pdev, adapter);
11011 err = register_netdev(netdev);
11012 if (err)
11013 goto err_register;
11014
11015
11016 /* power down the optics for 82599 SFP+ fiber */
11017 if (hw->mac.ops.disable_tx_laser)
11018 hw->mac.ops.disable_tx_laser(hw);
11019
11020 /* carrier off reporting is important to ethtool even BEFORE open */
11021 netif_carrier_off(netdev);
11022
11023 #ifdef CONFIG_IXGBE_DCA
11024 if (dca_add_requester(&pdev->dev) == 0) {
11025 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
11026 ixgbe_setup_dca(adapter);
11027 }
11028 #endif
11029 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
11030 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
11031 for (i = 0; i < adapter->num_vfs; i++)
11032 ixgbe_vf_configuration(pdev, (i | 0x10000000));
11033 }
11034
11035 /* firmware requires driver version to be 0xFFFFFFFF
11036 * since os does not support feature
11037 */
11038 if (hw->mac.ops.set_fw_drv_ver)
11039 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
11040 sizeof(UTS_RELEASE) - 1,
11041 UTS_RELEASE);
11042
11043 /* add san mac addr to netdev */
11044 ixgbe_add_sanmac_netdev(netdev);
11045
11046 e_dev_info("%s\n", ixgbe_default_device_descr);
11047
11048 #ifdef CONFIG_IXGBE_HWMON
11049 if (ixgbe_sysfs_init(adapter))
11050 e_err(probe, "failed to allocate sysfs resources\n");
11051 #endif /* CONFIG_IXGBE_HWMON */
11052
11053 ixgbe_dbg_adapter_init(adapter);
11054
11055 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
11056 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
11057 hw->mac.ops.setup_link(hw,
11058 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
11059 true);
11060
11061 err = ixgbe_mii_bus_init(hw);
11062 if (err)
11063 goto err_netdev;
11064
11065 return 0;
11066
11067 err_netdev:
11068 unregister_netdev(netdev);
11069 err_register:
11070 ixgbe_release_hw_control(adapter);
11071 ixgbe_clear_interrupt_scheme(adapter);
11072 err_sw_init:
11073 ixgbe_disable_sriov(adapter);
11074 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
11075 iounmap(adapter->io_addr);
11076 kfree(adapter->jump_tables[0]);
11077 kfree(adapter->mac_table);
11078 kfree(adapter->rss_key);
11079 bitmap_free(adapter->af_xdp_zc_qps);
11080 err_ioremap:
11081 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11082 free_netdev(netdev);
11083 err_alloc_etherdev:
11084 pci_disable_pcie_error_reporting(pdev);
11085 pci_release_mem_regions(pdev);
11086 err_pci_reg:
11087 err_dma:
11088 if (!adapter || disable_dev)
11089 pci_disable_device(pdev);
11090 return err;
11091 }
11092
11093 /**
11094 * ixgbe_remove - Device Removal Routine
11095 * @pdev: PCI device information struct
11096 *
11097 * ixgbe_remove is called by the PCI subsystem to alert the driver
11098 * that it should release a PCI device. The could be caused by a
11099 * Hot-Plug event, or because the driver is going to be removed from
11100 * memory.
11101 **/
ixgbe_remove(struct pci_dev * pdev)11102 static void ixgbe_remove(struct pci_dev *pdev)
11103 {
11104 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11105 struct net_device *netdev;
11106 bool disable_dev;
11107 int i;
11108
11109 /* if !adapter then we already cleaned up in probe */
11110 if (!adapter)
11111 return;
11112
11113 netdev = adapter->netdev;
11114 ixgbe_dbg_adapter_exit(adapter);
11115
11116 set_bit(__IXGBE_REMOVING, &adapter->state);
11117 cancel_work_sync(&adapter->service_task);
11118
11119 if (adapter->mii_bus)
11120 mdiobus_unregister(adapter->mii_bus);
11121
11122 #ifdef CONFIG_IXGBE_DCA
11123 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
11124 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
11125 dca_remove_requester(&pdev->dev);
11126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
11127 IXGBE_DCA_CTRL_DCA_DISABLE);
11128 }
11129
11130 #endif
11131 #ifdef CONFIG_IXGBE_HWMON
11132 ixgbe_sysfs_exit(adapter);
11133 #endif /* CONFIG_IXGBE_HWMON */
11134
11135 /* remove the added san mac */
11136 ixgbe_del_sanmac_netdev(netdev);
11137
11138 #ifdef CONFIG_PCI_IOV
11139 ixgbe_disable_sriov(adapter);
11140 #endif
11141 if (netdev->reg_state == NETREG_REGISTERED)
11142 unregister_netdev(netdev);
11143
11144 ixgbe_stop_ipsec_offload(adapter);
11145 ixgbe_clear_interrupt_scheme(adapter);
11146
11147 ixgbe_release_hw_control(adapter);
11148
11149 #ifdef CONFIG_DCB
11150 kfree(adapter->ixgbe_ieee_pfc);
11151 kfree(adapter->ixgbe_ieee_ets);
11152
11153 #endif
11154 iounmap(adapter->io_addr);
11155 pci_release_mem_regions(pdev);
11156
11157 e_dev_info("complete\n");
11158
11159 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
11160 if (adapter->jump_tables[i]) {
11161 kfree(adapter->jump_tables[i]->input);
11162 kfree(adapter->jump_tables[i]->mask);
11163 }
11164 kfree(adapter->jump_tables[i]);
11165 }
11166
11167 kfree(adapter->mac_table);
11168 kfree(adapter->rss_key);
11169 bitmap_free(adapter->af_xdp_zc_qps);
11170 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11171 free_netdev(netdev);
11172
11173 pci_disable_pcie_error_reporting(pdev);
11174
11175 if (disable_dev)
11176 pci_disable_device(pdev);
11177 }
11178
11179 /**
11180 * ixgbe_io_error_detected - called when PCI error is detected
11181 * @pdev: Pointer to PCI device
11182 * @state: The current pci connection state
11183 *
11184 * This function is called after a PCI bus error affecting
11185 * this device has been detected.
11186 */
ixgbe_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)11187 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
11188 pci_channel_state_t state)
11189 {
11190 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11191 struct net_device *netdev = adapter->netdev;
11192
11193 #ifdef CONFIG_PCI_IOV
11194 struct ixgbe_hw *hw = &adapter->hw;
11195 struct pci_dev *bdev, *vfdev;
11196 u32 dw0, dw1, dw2, dw3;
11197 int vf, pos;
11198 u16 req_id, pf_func;
11199
11200 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
11201 adapter->num_vfs == 0)
11202 goto skip_bad_vf_detection;
11203
11204 bdev = pdev->bus->self;
11205 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
11206 bdev = bdev->bus->self;
11207
11208 if (!bdev)
11209 goto skip_bad_vf_detection;
11210
11211 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
11212 if (!pos)
11213 goto skip_bad_vf_detection;
11214
11215 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
11216 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
11217 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
11218 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
11219 if (ixgbe_removed(hw->hw_addr))
11220 goto skip_bad_vf_detection;
11221
11222 req_id = dw1 >> 16;
11223 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
11224 if (!(req_id & 0x0080))
11225 goto skip_bad_vf_detection;
11226
11227 pf_func = req_id & 0x01;
11228 if ((pf_func & 1) == (pdev->devfn & 1)) {
11229 unsigned int device_id;
11230
11231 vf = (req_id & 0x7F) >> 1;
11232 e_dev_err("VF %d has caused a PCIe error\n", vf);
11233 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
11234 "%8.8x\tdw3: %8.8x\n",
11235 dw0, dw1, dw2, dw3);
11236 switch (adapter->hw.mac.type) {
11237 case ixgbe_mac_82599EB:
11238 device_id = IXGBE_82599_VF_DEVICE_ID;
11239 break;
11240 case ixgbe_mac_X540:
11241 device_id = IXGBE_X540_VF_DEVICE_ID;
11242 break;
11243 case ixgbe_mac_X550:
11244 device_id = IXGBE_DEV_ID_X550_VF;
11245 break;
11246 case ixgbe_mac_X550EM_x:
11247 device_id = IXGBE_DEV_ID_X550EM_X_VF;
11248 break;
11249 case ixgbe_mac_x550em_a:
11250 device_id = IXGBE_DEV_ID_X550EM_A_VF;
11251 break;
11252 default:
11253 device_id = 0;
11254 break;
11255 }
11256
11257 /* Find the pci device of the offending VF */
11258 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
11259 while (vfdev) {
11260 if (vfdev->devfn == (req_id & 0xFF))
11261 break;
11262 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
11263 device_id, vfdev);
11264 }
11265 /*
11266 * There's a slim chance the VF could have been hot plugged,
11267 * so if it is no longer present we don't need to issue the
11268 * VFLR. Just clean up the AER in that case.
11269 */
11270 if (vfdev) {
11271 pcie_flr(vfdev);
11272 /* Free device reference count */
11273 pci_dev_put(vfdev);
11274 }
11275 }
11276
11277 /*
11278 * Even though the error may have occurred on the other port
11279 * we still need to increment the vf error reference count for
11280 * both ports because the I/O resume function will be called
11281 * for both of them.
11282 */
11283 adapter->vferr_refcount++;
11284
11285 return PCI_ERS_RESULT_RECOVERED;
11286
11287 skip_bad_vf_detection:
11288 #endif /* CONFIG_PCI_IOV */
11289 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
11290 return PCI_ERS_RESULT_DISCONNECT;
11291
11292 if (!netif_device_present(netdev))
11293 return PCI_ERS_RESULT_DISCONNECT;
11294
11295 rtnl_lock();
11296 netif_device_detach(netdev);
11297
11298 if (netif_running(netdev))
11299 ixgbe_close_suspend(adapter);
11300
11301 if (state == pci_channel_io_perm_failure) {
11302 rtnl_unlock();
11303 return PCI_ERS_RESULT_DISCONNECT;
11304 }
11305
11306 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
11307 pci_disable_device(pdev);
11308 rtnl_unlock();
11309
11310 /* Request a slot reset. */
11311 return PCI_ERS_RESULT_NEED_RESET;
11312 }
11313
11314 /**
11315 * ixgbe_io_slot_reset - called after the pci bus has been reset.
11316 * @pdev: Pointer to PCI device
11317 *
11318 * Restart the card from scratch, as if from a cold-boot.
11319 */
ixgbe_io_slot_reset(struct pci_dev * pdev)11320 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
11321 {
11322 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11323 pci_ers_result_t result;
11324
11325 if (pci_enable_device_mem(pdev)) {
11326 e_err(probe, "Cannot re-enable PCI device after reset.\n");
11327 result = PCI_ERS_RESULT_DISCONNECT;
11328 } else {
11329 smp_mb__before_atomic();
11330 clear_bit(__IXGBE_DISABLED, &adapter->state);
11331 adapter->hw.hw_addr = adapter->io_addr;
11332 pci_set_master(pdev);
11333 pci_restore_state(pdev);
11334 pci_save_state(pdev);
11335
11336 pci_wake_from_d3(pdev, false);
11337
11338 ixgbe_reset(adapter);
11339 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
11340 result = PCI_ERS_RESULT_RECOVERED;
11341 }
11342
11343 return result;
11344 }
11345
11346 /**
11347 * ixgbe_io_resume - called when traffic can start flowing again.
11348 * @pdev: Pointer to PCI device
11349 *
11350 * This callback is called when the error recovery driver tells us that
11351 * its OK to resume normal operation.
11352 */
ixgbe_io_resume(struct pci_dev * pdev)11353 static void ixgbe_io_resume(struct pci_dev *pdev)
11354 {
11355 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11356 struct net_device *netdev = adapter->netdev;
11357
11358 #ifdef CONFIG_PCI_IOV
11359 if (adapter->vferr_refcount) {
11360 e_info(drv, "Resuming after VF err\n");
11361 adapter->vferr_refcount--;
11362 return;
11363 }
11364
11365 #endif
11366 rtnl_lock();
11367 if (netif_running(netdev))
11368 ixgbe_open(netdev);
11369
11370 netif_device_attach(netdev);
11371 rtnl_unlock();
11372 }
11373
11374 static const struct pci_error_handlers ixgbe_err_handler = {
11375 .error_detected = ixgbe_io_error_detected,
11376 .slot_reset = ixgbe_io_slot_reset,
11377 .resume = ixgbe_io_resume,
11378 };
11379
11380 static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume);
11381
11382 static struct pci_driver ixgbe_driver = {
11383 .name = ixgbe_driver_name,
11384 .id_table = ixgbe_pci_tbl,
11385 .probe = ixgbe_probe,
11386 .remove = ixgbe_remove,
11387 .driver.pm = &ixgbe_pm_ops,
11388 .shutdown = ixgbe_shutdown,
11389 .sriov_configure = ixgbe_pci_sriov_configure,
11390 .err_handler = &ixgbe_err_handler
11391 };
11392
11393 /**
11394 * ixgbe_init_module - Driver Registration Routine
11395 *
11396 * ixgbe_init_module is the first routine called when the driver is
11397 * loaded. All it does is register with the PCI subsystem.
11398 **/
ixgbe_init_module(void)11399 static int __init ixgbe_init_module(void)
11400 {
11401 int ret;
11402 pr_info("%s\n", ixgbe_driver_string);
11403 pr_info("%s\n", ixgbe_copyright);
11404
11405 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
11406 if (!ixgbe_wq) {
11407 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
11408 return -ENOMEM;
11409 }
11410
11411 ixgbe_dbg_init();
11412
11413 ret = pci_register_driver(&ixgbe_driver);
11414 if (ret) {
11415 destroy_workqueue(ixgbe_wq);
11416 ixgbe_dbg_exit();
11417 return ret;
11418 }
11419
11420 #ifdef CONFIG_IXGBE_DCA
11421 dca_register_notify(&dca_notifier);
11422 #endif
11423
11424 return 0;
11425 }
11426
11427 module_init(ixgbe_init_module);
11428
11429 /**
11430 * ixgbe_exit_module - Driver Exit Cleanup Routine
11431 *
11432 * ixgbe_exit_module is called just before the driver is removed
11433 * from memory.
11434 **/
ixgbe_exit_module(void)11435 static void __exit ixgbe_exit_module(void)
11436 {
11437 #ifdef CONFIG_IXGBE_DCA
11438 dca_unregister_notify(&dca_notifier);
11439 #endif
11440 pci_unregister_driver(&ixgbe_driver);
11441
11442 ixgbe_dbg_exit();
11443 if (ixgbe_wq) {
11444 destroy_workqueue(ixgbe_wq);
11445 ixgbe_wq = NULL;
11446 }
11447 }
11448
11449 #ifdef CONFIG_IXGBE_DCA
ixgbe_notify_dca(struct notifier_block * nb,unsigned long event,void * p)11450 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
11451 void *p)
11452 {
11453 int ret_val;
11454
11455 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
11456 __ixgbe_notify_dca);
11457
11458 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
11459 }
11460
11461 #endif /* CONFIG_IXGBE_DCA */
11462
11463 module_exit(ixgbe_exit_module);
11464
11465 /* ixgbe_main.c */
11466