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1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #include <linux/pci.h>
5 #include <linux/delay.h>
6 #include <linux/iopoll.h>
7 #include <linux/sched.h>
8 
9 #include "ixgbe.h"
10 #include "ixgbe_phy.h"
11 
12 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27 
28 /**
29  *  ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30  *  @hw: pointer to the hardware structure
31  *  @byte: byte to send
32  *
33  *  Returns an error code on error.
34  **/
ixgbe_out_i2c_byte_ack(struct ixgbe_hw * hw,u8 byte)35 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36 {
37 	s32 status;
38 
39 	status = ixgbe_clock_out_i2c_byte(hw, byte);
40 	if (status)
41 		return status;
42 	return ixgbe_get_i2c_ack(hw);
43 }
44 
45 /**
46  *  ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47  *  @hw: pointer to the hardware structure
48  *  @byte: pointer to a u8 to receive the byte
49  *
50  *  Returns an error code on error.
51  **/
ixgbe_in_i2c_byte_ack(struct ixgbe_hw * hw,u8 * byte)52 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53 {
54 	s32 status;
55 
56 	status = ixgbe_clock_in_i2c_byte(hw, byte);
57 	if (status)
58 		return status;
59 	/* ACK */
60 	return ixgbe_clock_out_i2c_bit(hw, false);
61 }
62 
63 /**
64  *  ixgbe_ones_comp_byte_add - Perform one's complement addition
65  *  @add1: addend 1
66  *  @add2: addend 2
67  *
68  *  Returns one's complement 8-bit sum.
69  **/
ixgbe_ones_comp_byte_add(u8 add1,u8 add2)70 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71 {
72 	u16 sum = add1 + add2;
73 
74 	sum = (sum & 0xFF) + (sum >> 8);
75 	return sum & 0xFF;
76 }
77 
78 /**
79  *  ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80  *  @hw: pointer to the hardware structure
81  *  @addr: I2C bus address to read from
82  *  @reg: I2C device register to read from
83  *  @val: pointer to location to receive read value
84  *  @lock: true if to take and release semaphore
85  *
86  *  Returns an error code on error.
87  */
ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val,bool lock)88 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 					u16 reg, u16 *val, bool lock)
90 {
91 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
92 	int max_retry = 3;
93 	int retry = 0;
94 	u8 csum_byte;
95 	u8 high_bits;
96 	u8 low_bits;
97 	u8 reg_high;
98 	u8 csum;
99 
100 	reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
101 	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
102 	csum = ~csum;
103 	do {
104 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 			return -EBUSY;
106 		ixgbe_i2c_start(hw);
107 		/* Device Address and write indication */
108 		if (ixgbe_out_i2c_byte_ack(hw, addr))
109 			goto fail;
110 		/* Write bits 14:8 */
111 		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
112 			goto fail;
113 		/* Write bits 7:0 */
114 		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
115 			goto fail;
116 		/* Write csum */
117 		if (ixgbe_out_i2c_byte_ack(hw, csum))
118 			goto fail;
119 		/* Re-start condition */
120 		ixgbe_i2c_start(hw);
121 		/* Device Address and read indication */
122 		if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
123 			goto fail;
124 		/* Get upper bits */
125 		if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
126 			goto fail;
127 		/* Get low bits */
128 		if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
129 			goto fail;
130 		/* Get csum */
131 		if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
132 			goto fail;
133 		/* NACK */
134 		if (ixgbe_clock_out_i2c_bit(hw, false))
135 			goto fail;
136 		ixgbe_i2c_stop(hw);
137 		if (lock)
138 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 		*val = (high_bits << 8) | low_bits;
140 		return 0;
141 
142 fail:
143 		ixgbe_i2c_bus_clear(hw);
144 		if (lock)
145 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 		retry++;
147 		if (retry < max_retry)
148 			hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149 		else
150 			hw_dbg(hw, "I2C byte read combined error.\n");
151 	} while (retry < max_retry);
152 
153 	return -EIO;
154 }
155 
156 /**
157  *  ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158  *  @hw: pointer to the hardware structure
159  *  @addr: I2C bus address to write to
160  *  @reg: I2C device register to write to
161  *  @val: value to write
162  *  @lock: true if to take and release semaphore
163  *
164  *  Returns an error code on error.
165  */
ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val,bool lock)166 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 					 u16 reg, u16 val, bool lock)
168 {
169 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 	int max_retry = 1;
171 	int retry = 0;
172 	u8 reg_high;
173 	u8 csum;
174 
175 	reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
176 	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 	csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 	csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
179 	csum = ~csum;
180 	do {
181 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 			return -EBUSY;
183 		ixgbe_i2c_start(hw);
184 		/* Device Address and write indication */
185 		if (ixgbe_out_i2c_byte_ack(hw, addr))
186 			goto fail;
187 		/* Write bits 14:8 */
188 		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
189 			goto fail;
190 		/* Write bits 7:0 */
191 		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
192 			goto fail;
193 		/* Write data 15:8 */
194 		if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
195 			goto fail;
196 		/* Write data 7:0 */
197 		if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
198 			goto fail;
199 		/* Write csum */
200 		if (ixgbe_out_i2c_byte_ack(hw, csum))
201 			goto fail;
202 		ixgbe_i2c_stop(hw);
203 		if (lock)
204 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205 		return 0;
206 
207 fail:
208 		ixgbe_i2c_bus_clear(hw);
209 		if (lock)
210 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 		retry++;
212 		if (retry < max_retry)
213 			hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214 		else
215 			hw_dbg(hw, "I2C byte write combined error.\n");
216 	} while (retry < max_retry);
217 
218 	return -EIO;
219 }
220 
221 /**
222  *  ixgbe_probe_phy - Probe a single address for a PHY
223  *  @hw: pointer to hardware structure
224  *  @phy_addr: PHY address to probe
225  *
226  *  Returns true if PHY found
227  **/
ixgbe_probe_phy(struct ixgbe_hw * hw,u16 phy_addr)228 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229 {
230 	u16 ext_ability = 0;
231 
232 	hw->phy.mdio.prtad = phy_addr;
233 	if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
234 		return false;
235 
236 	if (ixgbe_get_phy_id(hw))
237 		return false;
238 
239 	hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
240 
241 	if (hw->phy.type == ixgbe_phy_unknown) {
242 		hw->phy.ops.read_reg(hw,
243 				     MDIO_PMA_EXTABLE,
244 				     MDIO_MMD_PMAPMD,
245 				     &ext_ability);
246 		if (ext_ability &
247 		    (MDIO_PMA_EXTABLE_10GBT |
248 		     MDIO_PMA_EXTABLE_1000BT))
249 			hw->phy.type = ixgbe_phy_cu_unknown;
250 		else
251 			hw->phy.type = ixgbe_phy_generic;
252 	}
253 
254 	return true;
255 }
256 
257 /**
258  *  ixgbe_identify_phy_generic - Get physical layer module
259  *  @hw: pointer to hardware structure
260  *
261  *  Determines the physical layer module found on the current adapter.
262  **/
ixgbe_identify_phy_generic(struct ixgbe_hw * hw)263 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264 {
265 	u32 status = -EFAULT;
266 	u32 phy_addr;
267 
268 	if (!hw->phy.phy_semaphore_mask) {
269 		if (hw->bus.lan_id)
270 			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271 		else
272 			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273 	}
274 
275 	if (hw->phy.type != ixgbe_phy_unknown)
276 		return 0;
277 
278 	if (hw->phy.nw_mng_if_sel) {
279 		phy_addr = (hw->phy.nw_mng_if_sel &
280 			    IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
281 			   IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
282 		if (ixgbe_probe_phy(hw, phy_addr))
283 			return 0;
284 		else
285 			return -EFAULT;
286 	}
287 
288 	for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
289 		if (ixgbe_probe_phy(hw, phy_addr)) {
290 			status = 0;
291 			break;
292 		}
293 	}
294 
295 	/* Certain media types do not have a phy so an address will not
296 	 * be found and the code will take this path.  Caller has to
297 	 * decide if it is an error or not.
298 	 */
299 	if (status)
300 		hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
301 
302 	return status;
303 }
304 
305 /**
306  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
307  * @hw: pointer to the hardware structure
308  *
309  * This function checks the MMNGC.MNG_VETO bit to see if there are
310  * any constraints on link from manageability.  For MAC's that don't
311  * have this bit just return false since the link can not be blocked
312  * via this method.
313  **/
ixgbe_check_reset_blocked(struct ixgbe_hw * hw)314 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
315 {
316 	u32 mmngc;
317 
318 	/* If we don't have this bit, it can't be blocking */
319 	if (hw->mac.type == ixgbe_mac_82598EB)
320 		return false;
321 
322 	mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
323 	if (mmngc & IXGBE_MMNGC_MNG_VETO) {
324 		hw_dbg(hw, "MNG_VETO bit detected.\n");
325 		return true;
326 	}
327 
328 	return false;
329 }
330 
331 /**
332  *  ixgbe_get_phy_id - Get the phy type
333  *  @hw: pointer to hardware structure
334  *
335  **/
ixgbe_get_phy_id(struct ixgbe_hw * hw)336 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
337 {
338 	s32 status;
339 	u16 phy_id_high = 0;
340 	u16 phy_id_low = 0;
341 
342 	status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
343 				      &phy_id_high);
344 
345 	if (!status) {
346 		hw->phy.id = (u32)(phy_id_high << 16);
347 		status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
348 					      &phy_id_low);
349 		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
350 		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
351 	}
352 	return status;
353 }
354 
355 /**
356  *  ixgbe_get_phy_type_from_id - Get the phy type
357  *  @phy_id: hardware phy id
358  *
359  **/
ixgbe_get_phy_type_from_id(u32 phy_id)360 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
361 {
362 	enum ixgbe_phy_type phy_type;
363 
364 	switch (phy_id) {
365 	case TN1010_PHY_ID:
366 		phy_type = ixgbe_phy_tn;
367 		break;
368 	case X550_PHY_ID2:
369 	case X550_PHY_ID3:
370 	case X540_PHY_ID:
371 		phy_type = ixgbe_phy_aq;
372 		break;
373 	case QT2022_PHY_ID:
374 		phy_type = ixgbe_phy_qt;
375 		break;
376 	case ATH_PHY_ID:
377 		phy_type = ixgbe_phy_nl;
378 		break;
379 	case X557_PHY_ID:
380 	case X557_PHY_ID2:
381 		phy_type = ixgbe_phy_x550em_ext_t;
382 		break;
383 	case BCM54616S_E_PHY_ID:
384 		phy_type = ixgbe_phy_ext_1g_t;
385 		break;
386 	default:
387 		phy_type = ixgbe_phy_unknown;
388 		break;
389 	}
390 
391 	return phy_type;
392 }
393 
394 /**
395  *  ixgbe_reset_phy_generic - Performs a PHY reset
396  *  @hw: pointer to hardware structure
397  **/
ixgbe_reset_phy_generic(struct ixgbe_hw * hw)398 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
399 {
400 	u32 i;
401 	u16 ctrl = 0;
402 	s32 status = 0;
403 
404 	if (hw->phy.type == ixgbe_phy_unknown)
405 		status = ixgbe_identify_phy_generic(hw);
406 
407 	if (status != 0 || hw->phy.type == ixgbe_phy_none)
408 		return status;
409 
410 	/* Don't reset PHY if it's shut down due to overtemp. */
411 	if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw))
412 		return 0;
413 
414 	/* Blocked by MNG FW so bail */
415 	if (ixgbe_check_reset_blocked(hw))
416 		return 0;
417 
418 	/*
419 	 * Perform soft PHY reset to the PHY_XS.
420 	 * This will cause a soft reset to the PHY
421 	 */
422 	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
423 			      MDIO_MMD_PHYXS,
424 			      MDIO_CTRL1_RESET);
425 
426 	/*
427 	 * Poll for reset bit to self-clear indicating reset is complete.
428 	 * Some PHYs could take up to 3 seconds to complete and need about
429 	 * 1.7 usec delay after the reset is complete.
430 	 */
431 	for (i = 0; i < 30; i++) {
432 		msleep(100);
433 		if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
434 			status = hw->phy.ops.read_reg(hw,
435 						  IXGBE_MDIO_TX_VENDOR_ALARMS_3,
436 						  MDIO_MMD_PMAPMD, &ctrl);
437 			if (status)
438 				return status;
439 
440 			if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
441 				udelay(2);
442 				break;
443 			}
444 		} else {
445 			status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
446 						      MDIO_MMD_PHYXS, &ctrl);
447 			if (status)
448 				return status;
449 
450 			if (!(ctrl & MDIO_CTRL1_RESET)) {
451 				udelay(2);
452 				break;
453 			}
454 		}
455 	}
456 
457 	if (ctrl & MDIO_CTRL1_RESET) {
458 		hw_dbg(hw, "PHY reset polling failed to complete.\n");
459 		return -EIO;
460 	}
461 
462 	return 0;
463 }
464 
465 /**
466  *  ixgbe_read_phy_reg_mdi - read PHY register
467  *  @hw: pointer to hardware structure
468  *  @reg_addr: 32 bit address of PHY register to read
469  *  @device_type: 5 bit device type
470  *  @phy_data: Pointer to read data from PHY register
471  *
472  *  Reads a value from a specified PHY register without the SWFW lock
473  **/
ixgbe_read_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)474 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
475 		       u16 *phy_data)
476 {
477 	u32 i, data, command;
478 
479 	/* Setup and write the address cycle command */
480 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
481 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
482 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
483 		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
484 
485 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
486 
487 	/* Check every 10 usec to see if the address cycle completed.
488 	 * The MDI Command bit will clear when the operation is
489 	 * complete
490 	 */
491 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
492 		udelay(10);
493 
494 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
495 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
496 				break;
497 	}
498 
499 
500 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
501 		hw_dbg(hw, "PHY address command did not complete.\n");
502 		return -EIO;
503 	}
504 
505 	/* Address cycle complete, setup and write the read
506 	 * command
507 	 */
508 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
509 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
510 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
511 		   (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
512 
513 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
514 
515 	/* Check every 10 usec to see if the address cycle
516 	 * completed. The MDI Command bit will clear when the
517 	 * operation is complete
518 	 */
519 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
520 		udelay(10);
521 
522 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
523 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
524 			break;
525 	}
526 
527 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
528 		hw_dbg(hw, "PHY read command didn't complete\n");
529 		return -EIO;
530 	}
531 
532 	/* Read operation is complete.  Get the data
533 	 * from MSRWD
534 	 */
535 	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
536 	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
537 	*phy_data = (u16)(data);
538 
539 	return 0;
540 }
541 
542 /**
543  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
544  *  using the SWFW lock - this function is needed in most cases
545  *  @hw: pointer to hardware structure
546  *  @reg_addr: 32 bit address of PHY register to read
547  *  @device_type: 5 bit device type
548  *  @phy_data: Pointer to read data from PHY register
549  **/
ixgbe_read_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)550 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
551 			       u32 device_type, u16 *phy_data)
552 {
553 	s32 status;
554 	u32 gssr = hw->phy.phy_semaphore_mask;
555 
556 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
557 		status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
558 						phy_data);
559 		hw->mac.ops.release_swfw_sync(hw, gssr);
560 	} else {
561 		return -EBUSY;
562 	}
563 
564 	return status;
565 }
566 
567 /**
568  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
569  *  without SWFW lock
570  *  @hw: pointer to hardware structure
571  *  @reg_addr: 32 bit PHY register to write
572  *  @device_type: 5 bit device type
573  *  @phy_data: Data to write to the PHY register
574  **/
ixgbe_write_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)575 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
576 				u32 device_type, u16 phy_data)
577 {
578 	u32 i, command;
579 
580 	/* Put the data in the MDI single read and write data register*/
581 	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
582 
583 	/* Setup and write the address cycle command */
584 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
585 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
586 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
587 		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
588 
589 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
590 
591 	/*
592 	 * Check every 10 usec to see if the address cycle completed.
593 	 * The MDI Command bit will clear when the operation is
594 	 * complete
595 	 */
596 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
597 		udelay(10);
598 
599 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
600 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
601 			break;
602 	}
603 
604 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
605 		hw_dbg(hw, "PHY address cmd didn't complete\n");
606 		return -EIO;
607 	}
608 
609 	/*
610 	 * Address cycle complete, setup and write the write
611 	 * command
612 	 */
613 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
614 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
615 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
616 		   (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
617 
618 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
619 
620 	/* Check every 10 usec to see if the address cycle
621 	 * completed. The MDI Command bit will clear when the
622 	 * operation is complete
623 	 */
624 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
625 		udelay(10);
626 
627 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
628 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
629 			break;
630 	}
631 
632 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
633 		hw_dbg(hw, "PHY write cmd didn't complete\n");
634 		return -EIO;
635 	}
636 
637 	return 0;
638 }
639 
640 /**
641  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
642  *  using SWFW lock- this function is needed in most cases
643  *  @hw: pointer to hardware structure
644  *  @reg_addr: 32 bit PHY register to write
645  *  @device_type: 5 bit device type
646  *  @phy_data: Data to write to the PHY register
647  **/
ixgbe_write_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)648 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
649 				u32 device_type, u16 phy_data)
650 {
651 	s32 status;
652 	u32 gssr = hw->phy.phy_semaphore_mask;
653 
654 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
655 		status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
656 						 phy_data);
657 		hw->mac.ops.release_swfw_sync(hw, gssr);
658 	} else {
659 		return -EBUSY;
660 	}
661 
662 	return status;
663 }
664 
665 #define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
666 
667 /**
668  *  ixgbe_msca_cmd - Write the command register and poll for completion/timeout
669  *  @hw: pointer to hardware structure
670  *  @cmd: command register value to write
671  **/
ixgbe_msca_cmd(struct ixgbe_hw * hw,u32 cmd)672 static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
673 {
674 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
675 
676 	return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
677 				  !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
678 				  10 * IXGBE_MDIO_COMMAND_TIMEOUT);
679 }
680 
681 /**
682  *  ixgbe_mii_bus_read_generic - Read a clause 22/45 register with gssr flags
683  *  @hw: pointer to hardware structure
684  *  @addr: address
685  *  @regnum: register number
686  *  @gssr: semaphore flags to acquire
687  **/
ixgbe_mii_bus_read_generic(struct ixgbe_hw * hw,int addr,int regnum,u32 gssr)688 static s32 ixgbe_mii_bus_read_generic(struct ixgbe_hw *hw, int addr,
689 				      int regnum, u32 gssr)
690 {
691 	u32 hwaddr, cmd;
692 	s32 data;
693 
694 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
695 		return -EBUSY;
696 
697 	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
698 	if (regnum & MII_ADDR_C45) {
699 		hwaddr |= regnum & GENMASK(21, 0);
700 		cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
701 	} else {
702 		hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
703 		cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
704 			IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
705 	}
706 
707 	data = ixgbe_msca_cmd(hw, cmd);
708 	if (data < 0)
709 		goto mii_bus_read_done;
710 
711 	/* For a clause 45 access the address cycle just completed, we still
712 	 * need to do the read command, otherwise just get the data
713 	 */
714 	if (!(regnum & MII_ADDR_C45))
715 		goto do_mii_bus_read;
716 
717 	cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
718 	data = ixgbe_msca_cmd(hw, cmd);
719 	if (data < 0)
720 		goto mii_bus_read_done;
721 
722 do_mii_bus_read:
723 	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
724 	data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
725 
726 mii_bus_read_done:
727 	hw->mac.ops.release_swfw_sync(hw, gssr);
728 	return data;
729 }
730 
731 /**
732  *  ixgbe_mii_bus_write_generic - Write a clause 22/45 register with gssr flags
733  *  @hw: pointer to hardware structure
734  *  @addr: address
735  *  @regnum: register number
736  *  @val: value to write
737  *  @gssr: semaphore flags to acquire
738  **/
ixgbe_mii_bus_write_generic(struct ixgbe_hw * hw,int addr,int regnum,u16 val,u32 gssr)739 static s32 ixgbe_mii_bus_write_generic(struct ixgbe_hw *hw, int addr,
740 				       int regnum, u16 val, u32 gssr)
741 {
742 	u32 hwaddr, cmd;
743 	s32 err;
744 
745 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
746 		return -EBUSY;
747 
748 	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
749 
750 	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
751 	if (regnum & MII_ADDR_C45) {
752 		hwaddr |= regnum & GENMASK(21, 0);
753 		cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
754 	} else {
755 		hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
756 		cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
757 			IXGBE_MSCA_MDI_COMMAND;
758 	}
759 
760 	/* For clause 45 this is an address cycle, for clause 22 this is the
761 	 * entire transaction
762 	 */
763 	err = ixgbe_msca_cmd(hw, cmd);
764 	if (err < 0 || !(regnum & MII_ADDR_C45))
765 		goto mii_bus_write_done;
766 
767 	cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
768 	err = ixgbe_msca_cmd(hw, cmd);
769 
770 mii_bus_write_done:
771 	hw->mac.ops.release_swfw_sync(hw, gssr);
772 	return err;
773 }
774 
775 /**
776  *  ixgbe_mii_bus_read - Read a clause 22/45 register
777  *  @bus: pointer to mii_bus structure which points to our driver private
778  *  @addr: address
779  *  @regnum: register number
780  **/
ixgbe_mii_bus_read(struct mii_bus * bus,int addr,int regnum)781 static s32 ixgbe_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
782 {
783 	struct ixgbe_adapter *adapter = bus->priv;
784 	struct ixgbe_hw *hw = &adapter->hw;
785 	u32 gssr = hw->phy.phy_semaphore_mask;
786 
787 	return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
788 }
789 
790 /**
791  *  ixgbe_mii_bus_write - Write a clause 22/45 register
792  *  @bus: pointer to mii_bus structure which points to our driver private
793  *  @addr: address
794  *  @regnum: register number
795  *  @val: value to write
796  **/
ixgbe_mii_bus_write(struct mii_bus * bus,int addr,int regnum,u16 val)797 static s32 ixgbe_mii_bus_write(struct mii_bus *bus, int addr, int regnum,
798 			       u16 val)
799 {
800 	struct ixgbe_adapter *adapter = bus->priv;
801 	struct ixgbe_hw *hw = &adapter->hw;
802 	u32 gssr = hw->phy.phy_semaphore_mask;
803 
804 	return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
805 }
806 
807 /**
808  *  ixgbe_x550em_a_mii_bus_read - Read a clause 22/45 register on x550em_a
809  *  @bus: pointer to mii_bus structure which points to our driver private
810  *  @addr: address
811  *  @regnum: register number
812  **/
ixgbe_x550em_a_mii_bus_read(struct mii_bus * bus,int addr,int regnum)813 static s32 ixgbe_x550em_a_mii_bus_read(struct mii_bus *bus, int addr,
814 				       int regnum)
815 {
816 	struct ixgbe_adapter *adapter = bus->priv;
817 	struct ixgbe_hw *hw = &adapter->hw;
818 	u32 gssr = hw->phy.phy_semaphore_mask;
819 
820 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
821 	return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
822 }
823 
824 /**
825  *  ixgbe_x550em_a_mii_bus_write - Write a clause 22/45 register on x550em_a
826  *  @bus: pointer to mii_bus structure which points to our driver private
827  *  @addr: address
828  *  @regnum: register number
829  *  @val: value to write
830  **/
ixgbe_x550em_a_mii_bus_write(struct mii_bus * bus,int addr,int regnum,u16 val)831 static s32 ixgbe_x550em_a_mii_bus_write(struct mii_bus *bus, int addr,
832 					int regnum, u16 val)
833 {
834 	struct ixgbe_adapter *adapter = bus->priv;
835 	struct ixgbe_hw *hw = &adapter->hw;
836 	u32 gssr = hw->phy.phy_semaphore_mask;
837 
838 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
839 	return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
840 }
841 
842 /**
843  * ixgbe_get_first_secondary_devfn - get first device downstream of root port
844  * @devfn: PCI_DEVFN of root port on domain 0, bus 0
845  *
846  * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
847  * on domain 0, bus 0, devfn = 'devfn'
848  **/
ixgbe_get_first_secondary_devfn(unsigned int devfn)849 static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
850 {
851 	struct pci_dev *rp_pdev;
852 	int bus;
853 
854 	rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
855 	if (rp_pdev && rp_pdev->subordinate) {
856 		bus = rp_pdev->subordinate->number;
857 		pci_dev_put(rp_pdev);
858 		return pci_get_domain_bus_and_slot(0, bus, 0);
859 	}
860 
861 	pci_dev_put(rp_pdev);
862 	return NULL;
863 }
864 
865 /**
866  * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
867  * @hw: pointer to hardware structure
868  *
869  * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
870  * the SoC.  There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
871  * but we only want to register one MDIO bus.
872  **/
ixgbe_x550em_a_has_mii(struct ixgbe_hw * hw)873 static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
874 {
875 	struct ixgbe_adapter *adapter = hw->back;
876 	struct pci_dev *pdev = adapter->pdev;
877 	struct pci_dev *func0_pdev;
878 	bool has_mii = false;
879 
880 	/* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
881 	 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
882 	 * It's not valid for function 0 to be disabled and function 1 is up,
883 	 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
884 	 * of those two root ports
885 	 */
886 	func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
887 	if (func0_pdev) {
888 		if (func0_pdev == pdev)
889 			has_mii = true;
890 		goto out;
891 	}
892 	func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
893 	if (func0_pdev == pdev)
894 		has_mii = true;
895 
896 out:
897 	pci_dev_put(func0_pdev);
898 	return has_mii;
899 }
900 
901 /**
902  * ixgbe_mii_bus_init - mii_bus structure setup
903  * @hw: pointer to hardware structure
904  *
905  * Returns 0 on success, negative on failure
906  *
907  * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
908  **/
ixgbe_mii_bus_init(struct ixgbe_hw * hw)909 s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
910 {
911 	s32 (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
912 	s32 (*read)(struct mii_bus *bus, int addr, int regnum);
913 	struct ixgbe_adapter *adapter = hw->back;
914 	struct pci_dev *pdev = adapter->pdev;
915 	struct device *dev = &adapter->netdev->dev;
916 	struct mii_bus *bus;
917 
918 	switch (hw->device_id) {
919 	/* C3000 SoCs */
920 	case IXGBE_DEV_ID_X550EM_A_KR:
921 	case IXGBE_DEV_ID_X550EM_A_KR_L:
922 	case IXGBE_DEV_ID_X550EM_A_SFP_N:
923 	case IXGBE_DEV_ID_X550EM_A_SGMII:
924 	case IXGBE_DEV_ID_X550EM_A_SGMII_L:
925 	case IXGBE_DEV_ID_X550EM_A_10G_T:
926 	case IXGBE_DEV_ID_X550EM_A_SFP:
927 	case IXGBE_DEV_ID_X550EM_A_1G_T:
928 	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
929 		if (!ixgbe_x550em_a_has_mii(hw))
930 			return 0;
931 		read = &ixgbe_x550em_a_mii_bus_read;
932 		write = &ixgbe_x550em_a_mii_bus_write;
933 		break;
934 	default:
935 		read = &ixgbe_mii_bus_read;
936 		write = &ixgbe_mii_bus_write;
937 		break;
938 	}
939 
940 	bus = devm_mdiobus_alloc(dev);
941 	if (!bus)
942 		return -ENOMEM;
943 
944 	bus->read = read;
945 	bus->write = write;
946 
947 	/* Use the position of the device in the PCI hierarchy as the id */
948 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
949 		 pci_name(pdev));
950 
951 	bus->name = "ixgbe-mdio";
952 	bus->priv = adapter;
953 	bus->parent = dev;
954 	bus->phy_mask = GENMASK(31, 0);
955 
956 	/* Support clause 22/45 natively.  ixgbe_probe() sets MDIO_EMULATE_C22
957 	 * unfortunately that causes some clause 22 frames to be sent with
958 	 * clause 45 addressing.  We don't want that.
959 	 */
960 	hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
961 
962 	adapter->mii_bus = bus;
963 	return mdiobus_register(bus);
964 }
965 
966 /**
967  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
968  *  @hw: pointer to hardware structure
969  *
970  *  Restart autonegotiation and PHY and waits for completion.
971  **/
ixgbe_setup_phy_link_generic(struct ixgbe_hw * hw)972 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
973 {
974 	s32 status = 0;
975 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
976 	bool autoneg = false;
977 	ixgbe_link_speed speed;
978 
979 	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
980 
981 	/* Set or unset auto-negotiation 10G advertisement */
982 	hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
983 
984 	autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
985 	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
986 	    (speed & IXGBE_LINK_SPEED_10GB_FULL))
987 		autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
988 
989 	hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
990 
991 	hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
992 			     MDIO_MMD_AN, &autoneg_reg);
993 
994 	if (hw->mac.type == ixgbe_mac_X550) {
995 		/* Set or unset auto-negotiation 5G advertisement */
996 		autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
997 		if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
998 		    (speed & IXGBE_LINK_SPEED_5GB_FULL))
999 			autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
1000 
1001 		/* Set or unset auto-negotiation 2.5G advertisement */
1002 		autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
1003 		if ((hw->phy.autoneg_advertised &
1004 		     IXGBE_LINK_SPEED_2_5GB_FULL) &&
1005 		    (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1006 			autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1007 	}
1008 
1009 	/* Set or unset auto-negotiation 1G advertisement */
1010 	autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1011 	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1012 	    (speed & IXGBE_LINK_SPEED_1GB_FULL))
1013 		autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1014 
1015 	hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1016 			      MDIO_MMD_AN, autoneg_reg);
1017 
1018 	/* Set or unset auto-negotiation 100M advertisement */
1019 	hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1020 
1021 	autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1022 	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1023 	    (speed & IXGBE_LINK_SPEED_100_FULL))
1024 		autoneg_reg |= ADVERTISE_100FULL;
1025 
1026 	hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1027 
1028 	/* Blocked by MNG FW so don't reset PHY */
1029 	if (ixgbe_check_reset_blocked(hw))
1030 		return 0;
1031 
1032 	/* Restart PHY autonegotiation and wait for completion */
1033 	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1034 			     MDIO_MMD_AN, &autoneg_reg);
1035 
1036 	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1037 
1038 	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1039 			      MDIO_MMD_AN, autoneg_reg);
1040 
1041 	return status;
1042 }
1043 
1044 /**
1045  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1046  *  @hw: pointer to hardware structure
1047  *  @speed: new link speed
1048  *  @autoneg_wait_to_complete: unused
1049  **/
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)1050 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1051 				       ixgbe_link_speed speed,
1052 				       bool autoneg_wait_to_complete)
1053 {
1054 	/* Clear autoneg_advertised and set new values based on input link
1055 	 * speed.
1056 	 */
1057 	hw->phy.autoneg_advertised = 0;
1058 
1059 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1060 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1061 
1062 	if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1063 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1064 
1065 	if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1066 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1067 
1068 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1069 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1070 
1071 	if (speed & IXGBE_LINK_SPEED_100_FULL)
1072 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1073 
1074 	if (speed & IXGBE_LINK_SPEED_10_FULL)
1075 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1076 
1077 	/* Setup link based on the new speed settings */
1078 	if (hw->phy.ops.setup_link)
1079 		hw->phy.ops.setup_link(hw);
1080 
1081 	return 0;
1082 }
1083 
1084 /**
1085  * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1086  * @hw: pointer to hardware structure
1087  *
1088  * Determines the supported link capabilities by reading the PHY auto
1089  * negotiation register.
1090  */
ixgbe_get_copper_speeds_supported(struct ixgbe_hw * hw)1091 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1092 {
1093 	u16 speed_ability;
1094 	s32 status;
1095 
1096 	status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1097 				      &speed_ability);
1098 	if (status)
1099 		return status;
1100 
1101 	if (speed_ability & MDIO_SPEED_10G)
1102 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1103 	if (speed_ability & MDIO_PMA_SPEED_1000)
1104 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1105 	if (speed_ability & MDIO_PMA_SPEED_100)
1106 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1107 
1108 	switch (hw->mac.type) {
1109 	case ixgbe_mac_X550:
1110 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1111 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1112 		break;
1113 	case ixgbe_mac_X550EM_x:
1114 	case ixgbe_mac_x550em_a:
1115 		hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1116 		break;
1117 	default:
1118 		break;
1119 	}
1120 
1121 	return 0;
1122 }
1123 
1124 /**
1125  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1126  * @hw: pointer to hardware structure
1127  * @speed: pointer to link speed
1128  * @autoneg: boolean auto-negotiation value
1129  */
ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)1130 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1131 					       ixgbe_link_speed *speed,
1132 					       bool *autoneg)
1133 {
1134 	s32 status = 0;
1135 
1136 	*autoneg = true;
1137 	if (!hw->phy.speeds_supported)
1138 		status = ixgbe_get_copper_speeds_supported(hw);
1139 
1140 	*speed = hw->phy.speeds_supported;
1141 	return status;
1142 }
1143 
1144 /**
1145  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1146  *  @hw: pointer to hardware structure
1147  *  @speed: link speed
1148  *  @link_up: status of link
1149  *
1150  *  Reads the VS1 register to determine if link is up and the current speed for
1151  *  the PHY.
1152  **/
ixgbe_check_phy_link_tnx(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up)1153 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1154 			     bool *link_up)
1155 {
1156 	s32 status;
1157 	u32 time_out;
1158 	u32 max_time_out = 10;
1159 	u16 phy_link = 0;
1160 	u16 phy_speed = 0;
1161 	u16 phy_data = 0;
1162 
1163 	/* Initialize speed and link to default case */
1164 	*link_up = false;
1165 	*speed = IXGBE_LINK_SPEED_10GB_FULL;
1166 
1167 	/*
1168 	 * Check current speed and link status of the PHY register.
1169 	 * This is a vendor specific register and may have to
1170 	 * be changed for other copper PHYs.
1171 	 */
1172 	for (time_out = 0; time_out < max_time_out; time_out++) {
1173 		udelay(10);
1174 		status = hw->phy.ops.read_reg(hw,
1175 					      MDIO_STAT1,
1176 					      MDIO_MMD_VEND1,
1177 					      &phy_data);
1178 		phy_link = phy_data &
1179 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1180 		phy_speed = phy_data &
1181 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1182 		if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1183 			*link_up = true;
1184 			if (phy_speed ==
1185 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1186 				*speed = IXGBE_LINK_SPEED_1GB_FULL;
1187 			break;
1188 		}
1189 	}
1190 
1191 	return status;
1192 }
1193 
1194 /**
1195  *	ixgbe_setup_phy_link_tnx - Set and restart autoneg
1196  *	@hw: pointer to hardware structure
1197  *
1198  *	Restart autonegotiation and PHY and waits for completion.
1199  *      This function always returns success, this is nessary since
1200  *	it is called via a function pointer that could call other
1201  *	functions that could return an error.
1202  **/
ixgbe_setup_phy_link_tnx(struct ixgbe_hw * hw)1203 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1204 {
1205 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1206 	bool autoneg = false;
1207 	ixgbe_link_speed speed;
1208 
1209 	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1210 
1211 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1212 		/* Set or unset auto-negotiation 10G advertisement */
1213 		hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1214 				     MDIO_MMD_AN,
1215 				     &autoneg_reg);
1216 
1217 		autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1218 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1219 			autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1220 
1221 		hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1222 				      MDIO_MMD_AN,
1223 				      autoneg_reg);
1224 	}
1225 
1226 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1227 		/* Set or unset auto-negotiation 1G advertisement */
1228 		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1229 				     MDIO_MMD_AN,
1230 				     &autoneg_reg);
1231 
1232 		autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1233 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1234 			autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1235 
1236 		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1237 				      MDIO_MMD_AN,
1238 				      autoneg_reg);
1239 	}
1240 
1241 	if (speed & IXGBE_LINK_SPEED_100_FULL) {
1242 		/* Set or unset auto-negotiation 100M advertisement */
1243 		hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1244 				     MDIO_MMD_AN,
1245 				     &autoneg_reg);
1246 
1247 		autoneg_reg &= ~(ADVERTISE_100FULL |
1248 				 ADVERTISE_100HALF);
1249 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1250 			autoneg_reg |= ADVERTISE_100FULL;
1251 
1252 		hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1253 				      MDIO_MMD_AN,
1254 				      autoneg_reg);
1255 	}
1256 
1257 	/* Blocked by MNG FW so don't reset PHY */
1258 	if (ixgbe_check_reset_blocked(hw))
1259 		return 0;
1260 
1261 	/* Restart PHY autonegotiation and wait for completion */
1262 	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1263 			     MDIO_MMD_AN, &autoneg_reg);
1264 
1265 	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1266 
1267 	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1268 			      MDIO_MMD_AN, autoneg_reg);
1269 	return 0;
1270 }
1271 
1272 /**
1273  *  ixgbe_reset_phy_nl - Performs a PHY reset
1274  *  @hw: pointer to hardware structure
1275  **/
ixgbe_reset_phy_nl(struct ixgbe_hw * hw)1276 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1277 {
1278 	u16 phy_offset, control, eword, edata, block_crc;
1279 	bool end_data = false;
1280 	u16 list_offset, data_offset;
1281 	u16 phy_data = 0;
1282 	s32 ret_val;
1283 	u32 i;
1284 
1285 	/* Blocked by MNG FW so bail */
1286 	if (ixgbe_check_reset_blocked(hw))
1287 		return 0;
1288 
1289 	hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1290 
1291 	/* reset the PHY and poll for completion */
1292 	hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1293 			      (phy_data | MDIO_CTRL1_RESET));
1294 
1295 	for (i = 0; i < 100; i++) {
1296 		hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1297 				     &phy_data);
1298 		if ((phy_data & MDIO_CTRL1_RESET) == 0)
1299 			break;
1300 		usleep_range(10000, 20000);
1301 	}
1302 
1303 	if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1304 		hw_dbg(hw, "PHY reset did not complete.\n");
1305 		return -EIO;
1306 	}
1307 
1308 	/* Get init offsets */
1309 	ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1310 						      &data_offset);
1311 	if (ret_val)
1312 		return ret_val;
1313 
1314 	ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1315 	data_offset++;
1316 	while (!end_data) {
1317 		/*
1318 		 * Read control word from PHY init contents offset
1319 		 */
1320 		ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1321 		if (ret_val)
1322 			goto err_eeprom;
1323 		control = (eword & IXGBE_CONTROL_MASK_NL) >>
1324 			   IXGBE_CONTROL_SHIFT_NL;
1325 		edata = eword & IXGBE_DATA_MASK_NL;
1326 		switch (control) {
1327 		case IXGBE_DELAY_NL:
1328 			data_offset++;
1329 			hw_dbg(hw, "DELAY: %d MS\n", edata);
1330 			usleep_range(edata * 1000, edata * 2000);
1331 			break;
1332 		case IXGBE_DATA_NL:
1333 			hw_dbg(hw, "DATA:\n");
1334 			data_offset++;
1335 			ret_val = hw->eeprom.ops.read(hw, data_offset++,
1336 						      &phy_offset);
1337 			if (ret_val)
1338 				goto err_eeprom;
1339 			for (i = 0; i < edata; i++) {
1340 				ret_val = hw->eeprom.ops.read(hw, data_offset,
1341 							      &eword);
1342 				if (ret_val)
1343 					goto err_eeprom;
1344 				hw->phy.ops.write_reg(hw, phy_offset,
1345 						      MDIO_MMD_PMAPMD, eword);
1346 				hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1347 				       phy_offset);
1348 				data_offset++;
1349 				phy_offset++;
1350 			}
1351 			break;
1352 		case IXGBE_CONTROL_NL:
1353 			data_offset++;
1354 			hw_dbg(hw, "CONTROL:\n");
1355 			if (edata == IXGBE_CONTROL_EOL_NL) {
1356 				hw_dbg(hw, "EOL\n");
1357 				end_data = true;
1358 			} else if (edata == IXGBE_CONTROL_SOL_NL) {
1359 				hw_dbg(hw, "SOL\n");
1360 			} else {
1361 				hw_dbg(hw, "Bad control value\n");
1362 				return -EIO;
1363 			}
1364 			break;
1365 		default:
1366 			hw_dbg(hw, "Bad control type\n");
1367 			return -EIO;
1368 		}
1369 	}
1370 
1371 	return ret_val;
1372 
1373 err_eeprom:
1374 	hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1375 	return -EIO;
1376 }
1377 
1378 /**
1379  *  ixgbe_identify_module_generic - Identifies module type
1380  *  @hw: pointer to hardware structure
1381  *
1382  *  Determines HW type and calls appropriate function.
1383  **/
ixgbe_identify_module_generic(struct ixgbe_hw * hw)1384 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1385 {
1386 	switch (hw->mac.ops.get_media_type(hw)) {
1387 	case ixgbe_media_type_fiber:
1388 		return ixgbe_identify_sfp_module_generic(hw);
1389 	case ixgbe_media_type_fiber_qsfp:
1390 		return ixgbe_identify_qsfp_module_generic(hw);
1391 	default:
1392 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1393 		return -ENOENT;
1394 	}
1395 
1396 	return -ENOENT;
1397 }
1398 
1399 /**
1400  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1401  *  @hw: pointer to hardware structure
1402  *
1403  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1404  **/
ixgbe_identify_sfp_module_generic(struct ixgbe_hw * hw)1405 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1406 {
1407 	struct ixgbe_adapter *adapter = hw->back;
1408 	s32 status;
1409 	u32 vendor_oui = 0;
1410 	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1411 	u8 identifier = 0;
1412 	u8 comp_codes_1g = 0;
1413 	u8 comp_codes_10g = 0;
1414 	u8 oui_bytes[3] = {0, 0, 0};
1415 	u8 cable_tech = 0;
1416 	u8 cable_spec = 0;
1417 	u16 enforce_sfp = 0;
1418 
1419 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1420 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1421 		return -ENOENT;
1422 	}
1423 
1424 	/* LAN ID is needed for sfp_type determination */
1425 	hw->mac.ops.set_lan_id(hw);
1426 
1427 	status = hw->phy.ops.read_i2c_eeprom(hw,
1428 					     IXGBE_SFF_IDENTIFIER,
1429 					     &identifier);
1430 
1431 	if (status)
1432 		goto err_read_i2c_eeprom;
1433 
1434 	if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1435 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1436 		return -EOPNOTSUPP;
1437 	}
1438 	status = hw->phy.ops.read_i2c_eeprom(hw,
1439 					     IXGBE_SFF_1GBE_COMP_CODES,
1440 					     &comp_codes_1g);
1441 
1442 	if (status)
1443 		goto err_read_i2c_eeprom;
1444 
1445 	status = hw->phy.ops.read_i2c_eeprom(hw,
1446 					     IXGBE_SFF_10GBE_COMP_CODES,
1447 					     &comp_codes_10g);
1448 
1449 	if (status)
1450 		goto err_read_i2c_eeprom;
1451 	status = hw->phy.ops.read_i2c_eeprom(hw,
1452 					     IXGBE_SFF_CABLE_TECHNOLOGY,
1453 					     &cable_tech);
1454 
1455 	if (status)
1456 		goto err_read_i2c_eeprom;
1457 
1458 	 /* ID Module
1459 	  * =========
1460 	  * 0   SFP_DA_CU
1461 	  * 1   SFP_SR
1462 	  * 2   SFP_LR
1463 	  * 3   SFP_DA_CORE0 - 82599-specific
1464 	  * 4   SFP_DA_CORE1 - 82599-specific
1465 	  * 5   SFP_SR/LR_CORE0 - 82599-specific
1466 	  * 6   SFP_SR/LR_CORE1 - 82599-specific
1467 	  * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1468 	  * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1469 	  * 9   SFP_1g_cu_CORE0 - 82599-specific
1470 	  * 10  SFP_1g_cu_CORE1 - 82599-specific
1471 	  * 11  SFP_1g_sx_CORE0 - 82599-specific
1472 	  * 12  SFP_1g_sx_CORE1 - 82599-specific
1473 	  */
1474 	if (hw->mac.type == ixgbe_mac_82598EB) {
1475 		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1476 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1477 		else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1478 			hw->phy.sfp_type = ixgbe_sfp_type_sr;
1479 		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1480 			hw->phy.sfp_type = ixgbe_sfp_type_lr;
1481 		else
1482 			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1483 	} else {
1484 		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1485 			if (hw->bus.lan_id == 0)
1486 				hw->phy.sfp_type =
1487 					     ixgbe_sfp_type_da_cu_core0;
1488 			else
1489 				hw->phy.sfp_type =
1490 					     ixgbe_sfp_type_da_cu_core1;
1491 		} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1492 			hw->phy.ops.read_i2c_eeprom(
1493 					hw, IXGBE_SFF_CABLE_SPEC_COMP,
1494 					&cable_spec);
1495 			if (cable_spec &
1496 			    IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1497 				if (hw->bus.lan_id == 0)
1498 					hw->phy.sfp_type =
1499 					ixgbe_sfp_type_da_act_lmt_core0;
1500 				else
1501 					hw->phy.sfp_type =
1502 					ixgbe_sfp_type_da_act_lmt_core1;
1503 			} else {
1504 				hw->phy.sfp_type =
1505 						ixgbe_sfp_type_unknown;
1506 			}
1507 		} else if (comp_codes_10g &
1508 			   (IXGBE_SFF_10GBASESR_CAPABLE |
1509 			    IXGBE_SFF_10GBASELR_CAPABLE)) {
1510 			if (hw->bus.lan_id == 0)
1511 				hw->phy.sfp_type =
1512 					      ixgbe_sfp_type_srlr_core0;
1513 			else
1514 				hw->phy.sfp_type =
1515 					      ixgbe_sfp_type_srlr_core1;
1516 		} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1517 			if (hw->bus.lan_id == 0)
1518 				hw->phy.sfp_type =
1519 					ixgbe_sfp_type_1g_cu_core0;
1520 			else
1521 				hw->phy.sfp_type =
1522 					ixgbe_sfp_type_1g_cu_core1;
1523 		} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1524 			if (hw->bus.lan_id == 0)
1525 				hw->phy.sfp_type =
1526 					ixgbe_sfp_type_1g_sx_core0;
1527 			else
1528 				hw->phy.sfp_type =
1529 					ixgbe_sfp_type_1g_sx_core1;
1530 		} else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1531 			if (hw->bus.lan_id == 0)
1532 				hw->phy.sfp_type =
1533 					ixgbe_sfp_type_1g_lx_core0;
1534 			else
1535 				hw->phy.sfp_type =
1536 					ixgbe_sfp_type_1g_lx_core1;
1537 		} else {
1538 			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1539 		}
1540 	}
1541 
1542 	if (hw->phy.sfp_type != stored_sfp_type)
1543 		hw->phy.sfp_setup_needed = true;
1544 
1545 	/* Determine if the SFP+ PHY is dual speed or not. */
1546 	hw->phy.multispeed_fiber = false;
1547 	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1548 	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1549 	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1550 	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1551 		hw->phy.multispeed_fiber = true;
1552 
1553 	/* Determine PHY vendor */
1554 	if (hw->phy.type != ixgbe_phy_nl) {
1555 		hw->phy.id = identifier;
1556 		status = hw->phy.ops.read_i2c_eeprom(hw,
1557 					    IXGBE_SFF_VENDOR_OUI_BYTE0,
1558 					    &oui_bytes[0]);
1559 
1560 		if (status != 0)
1561 			goto err_read_i2c_eeprom;
1562 
1563 		status = hw->phy.ops.read_i2c_eeprom(hw,
1564 					    IXGBE_SFF_VENDOR_OUI_BYTE1,
1565 					    &oui_bytes[1]);
1566 
1567 		if (status != 0)
1568 			goto err_read_i2c_eeprom;
1569 
1570 		status = hw->phy.ops.read_i2c_eeprom(hw,
1571 					    IXGBE_SFF_VENDOR_OUI_BYTE2,
1572 					    &oui_bytes[2]);
1573 
1574 		if (status != 0)
1575 			goto err_read_i2c_eeprom;
1576 
1577 		vendor_oui =
1578 		  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1579 		   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1580 		   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1581 
1582 		switch (vendor_oui) {
1583 		case IXGBE_SFF_VENDOR_OUI_TYCO:
1584 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1585 				hw->phy.type =
1586 					    ixgbe_phy_sfp_passive_tyco;
1587 			break;
1588 		case IXGBE_SFF_VENDOR_OUI_FTL:
1589 			if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1590 				hw->phy.type = ixgbe_phy_sfp_ftl_active;
1591 			else
1592 				hw->phy.type = ixgbe_phy_sfp_ftl;
1593 			break;
1594 		case IXGBE_SFF_VENDOR_OUI_AVAGO:
1595 			hw->phy.type = ixgbe_phy_sfp_avago;
1596 			break;
1597 		case IXGBE_SFF_VENDOR_OUI_INTEL:
1598 			hw->phy.type = ixgbe_phy_sfp_intel;
1599 			break;
1600 		default:
1601 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1602 				hw->phy.type =
1603 					 ixgbe_phy_sfp_passive_unknown;
1604 			else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1605 				hw->phy.type =
1606 					ixgbe_phy_sfp_active_unknown;
1607 			else
1608 				hw->phy.type = ixgbe_phy_sfp_unknown;
1609 			break;
1610 		}
1611 	}
1612 
1613 	/* Allow any DA cable vendor */
1614 	if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1615 	    IXGBE_SFF_DA_ACTIVE_CABLE))
1616 		return 0;
1617 
1618 	/* Verify supported 1G SFP modules */
1619 	if (comp_codes_10g == 0 &&
1620 	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1621 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1622 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1623 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1624 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1625 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1626 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1627 		return -EOPNOTSUPP;
1628 	}
1629 
1630 	/* Anything else 82598-based is supported */
1631 	if (hw->mac.type == ixgbe_mac_82598EB)
1632 		return 0;
1633 
1634 	hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1635 	if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1636 	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1637 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1638 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1639 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1640 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1641 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1642 		/* Make sure we're a supported PHY type */
1643 		if (hw->phy.type == ixgbe_phy_sfp_intel)
1644 			return 0;
1645 		if (hw->allow_unsupported_sfp) {
1646 			e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1647 			return 0;
1648 		}
1649 		hw_dbg(hw, "SFP+ module not supported\n");
1650 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1651 		return -EOPNOTSUPP;
1652 	}
1653 	return 0;
1654 
1655 err_read_i2c_eeprom:
1656 	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1657 	if (hw->phy.type != ixgbe_phy_nl) {
1658 		hw->phy.id = 0;
1659 		hw->phy.type = ixgbe_phy_unknown;
1660 	}
1661 	return -ENOENT;
1662 }
1663 
1664 /**
1665  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1666  * @hw: pointer to hardware structure
1667  *
1668  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1669  **/
ixgbe_identify_qsfp_module_generic(struct ixgbe_hw * hw)1670 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1671 {
1672 	struct ixgbe_adapter *adapter = hw->back;
1673 	s32 status;
1674 	u32 vendor_oui = 0;
1675 	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1676 	u8 identifier = 0;
1677 	u8 comp_codes_1g = 0;
1678 	u8 comp_codes_10g = 0;
1679 	u8 oui_bytes[3] = {0, 0, 0};
1680 	u16 enforce_sfp = 0;
1681 	u8 connector = 0;
1682 	u8 cable_length = 0;
1683 	u8 device_tech = 0;
1684 	bool active_cable = false;
1685 
1686 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1687 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1688 		return -ENOENT;
1689 	}
1690 
1691 	/* LAN ID is needed for sfp_type determination */
1692 	hw->mac.ops.set_lan_id(hw);
1693 
1694 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1695 					     &identifier);
1696 
1697 	if (status != 0)
1698 		goto err_read_i2c_eeprom;
1699 
1700 	if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1701 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1702 		return -EOPNOTSUPP;
1703 	}
1704 
1705 	hw->phy.id = identifier;
1706 
1707 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1708 					     &comp_codes_10g);
1709 
1710 	if (status != 0)
1711 		goto err_read_i2c_eeprom;
1712 
1713 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1714 					     &comp_codes_1g);
1715 
1716 	if (status != 0)
1717 		goto err_read_i2c_eeprom;
1718 
1719 	if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1720 		hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1721 		if (hw->bus.lan_id == 0)
1722 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1723 		else
1724 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1725 	} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1726 				     IXGBE_SFF_10GBASELR_CAPABLE)) {
1727 		if (hw->bus.lan_id == 0)
1728 			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1729 		else
1730 			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1731 	} else {
1732 		if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1733 			active_cable = true;
1734 
1735 		if (!active_cable) {
1736 			/* check for active DA cables that pre-date
1737 			 * SFF-8436 v3.6
1738 			 */
1739 			hw->phy.ops.read_i2c_eeprom(hw,
1740 					IXGBE_SFF_QSFP_CONNECTOR,
1741 					&connector);
1742 
1743 			hw->phy.ops.read_i2c_eeprom(hw,
1744 					IXGBE_SFF_QSFP_CABLE_LENGTH,
1745 					&cable_length);
1746 
1747 			hw->phy.ops.read_i2c_eeprom(hw,
1748 					IXGBE_SFF_QSFP_DEVICE_TECH,
1749 					&device_tech);
1750 
1751 			if ((connector ==
1752 				     IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1753 			    (cable_length > 0) &&
1754 			    ((device_tech >> 4) ==
1755 				     IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1756 				active_cable = true;
1757 		}
1758 
1759 		if (active_cable) {
1760 			hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1761 			if (hw->bus.lan_id == 0)
1762 				hw->phy.sfp_type =
1763 						ixgbe_sfp_type_da_act_lmt_core0;
1764 			else
1765 				hw->phy.sfp_type =
1766 						ixgbe_sfp_type_da_act_lmt_core1;
1767 		} else {
1768 			/* unsupported module type */
1769 			hw->phy.type = ixgbe_phy_sfp_unsupported;
1770 			return -EOPNOTSUPP;
1771 		}
1772 	}
1773 
1774 	if (hw->phy.sfp_type != stored_sfp_type)
1775 		hw->phy.sfp_setup_needed = true;
1776 
1777 	/* Determine if the QSFP+ PHY is dual speed or not. */
1778 	hw->phy.multispeed_fiber = false;
1779 	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1780 	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1781 	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1782 	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1783 		hw->phy.multispeed_fiber = true;
1784 
1785 	/* Determine PHY vendor for optical modules */
1786 	if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1787 			      IXGBE_SFF_10GBASELR_CAPABLE)) {
1788 		status = hw->phy.ops.read_i2c_eeprom(hw,
1789 					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1790 					&oui_bytes[0]);
1791 
1792 		if (status != 0)
1793 			goto err_read_i2c_eeprom;
1794 
1795 		status = hw->phy.ops.read_i2c_eeprom(hw,
1796 					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1797 					&oui_bytes[1]);
1798 
1799 		if (status != 0)
1800 			goto err_read_i2c_eeprom;
1801 
1802 		status = hw->phy.ops.read_i2c_eeprom(hw,
1803 					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1804 					&oui_bytes[2]);
1805 
1806 		if (status != 0)
1807 			goto err_read_i2c_eeprom;
1808 
1809 		vendor_oui =
1810 			((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1811 			 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1812 			 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1813 
1814 		if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1815 			hw->phy.type = ixgbe_phy_qsfp_intel;
1816 		else
1817 			hw->phy.type = ixgbe_phy_qsfp_unknown;
1818 
1819 		hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1820 		if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1821 			/* Make sure we're a supported PHY type */
1822 			if (hw->phy.type == ixgbe_phy_qsfp_intel)
1823 				return 0;
1824 			if (hw->allow_unsupported_sfp) {
1825 				e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1826 				return 0;
1827 			}
1828 			hw_dbg(hw, "QSFP module not supported\n");
1829 			hw->phy.type = ixgbe_phy_sfp_unsupported;
1830 			return -EOPNOTSUPP;
1831 		}
1832 		return 0;
1833 	}
1834 	return 0;
1835 
1836 err_read_i2c_eeprom:
1837 	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1838 	hw->phy.id = 0;
1839 	hw->phy.type = ixgbe_phy_unknown;
1840 
1841 	return -ENOENT;
1842 }
1843 
1844 /**
1845  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1846  *  @hw: pointer to hardware structure
1847  *  @list_offset: offset to the SFP ID list
1848  *  @data_offset: offset to the SFP data block
1849  *
1850  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1851  *  so it returns the offsets to the phy init sequence block.
1852  **/
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw * hw,u16 * list_offset,u16 * data_offset)1853 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1854 					u16 *list_offset,
1855 					u16 *data_offset)
1856 {
1857 	u16 sfp_id;
1858 	u16 sfp_type = hw->phy.sfp_type;
1859 
1860 	if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1861 		return -EOPNOTSUPP;
1862 
1863 	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1864 		return -ENOENT;
1865 
1866 	if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1867 	    (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1868 		return -EOPNOTSUPP;
1869 
1870 	/*
1871 	 * Limiting active cables and 1G Phys must be initialized as
1872 	 * SR modules
1873 	 */
1874 	if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1875 	    sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1876 	    sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1877 	    sfp_type == ixgbe_sfp_type_1g_sx_core0)
1878 		sfp_type = ixgbe_sfp_type_srlr_core0;
1879 	else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1880 		 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1881 		 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1882 		 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1883 		sfp_type = ixgbe_sfp_type_srlr_core1;
1884 
1885 	/* Read offset to PHY init contents */
1886 	if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1887 		hw_err(hw, "eeprom read at %d failed\n",
1888 		       IXGBE_PHY_INIT_OFFSET_NL);
1889 		return -EIO;
1890 	}
1891 
1892 	if ((!*list_offset) || (*list_offset == 0xFFFF))
1893 		return -EIO;
1894 
1895 	/* Shift offset to first ID word */
1896 	(*list_offset)++;
1897 
1898 	/*
1899 	 * Find the matching SFP ID in the EEPROM
1900 	 * and program the init sequence
1901 	 */
1902 	if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1903 		goto err_phy;
1904 
1905 	while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1906 		if (sfp_id == sfp_type) {
1907 			(*list_offset)++;
1908 			if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1909 				goto err_phy;
1910 			if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1911 				hw_dbg(hw, "SFP+ module not supported\n");
1912 				return -EOPNOTSUPP;
1913 			} else {
1914 				break;
1915 			}
1916 		} else {
1917 			(*list_offset) += 2;
1918 			if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1919 				goto err_phy;
1920 		}
1921 	}
1922 
1923 	if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1924 		hw_dbg(hw, "No matching SFP+ module found\n");
1925 		return -EOPNOTSUPP;
1926 	}
1927 
1928 	return 0;
1929 
1930 err_phy:
1931 	hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1932 	return -EIO;
1933 }
1934 
1935 /**
1936  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1937  *  @hw: pointer to hardware structure
1938  *  @byte_offset: EEPROM byte offset to read
1939  *  @eeprom_data: value read
1940  *
1941  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1942  **/
ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)1943 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1944 				  u8 *eeprom_data)
1945 {
1946 	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1947 					 IXGBE_I2C_EEPROM_DEV_ADDR,
1948 					 eeprom_data);
1949 }
1950 
1951 /**
1952  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1953  *  @hw: pointer to hardware structure
1954  *  @byte_offset: byte offset at address 0xA2
1955  *  @sff8472_data: value read
1956  *
1957  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1958  **/
ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)1959 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1960 				   u8 *sff8472_data)
1961 {
1962 	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1963 					 IXGBE_I2C_EEPROM_DEV_ADDR2,
1964 					 sff8472_data);
1965 }
1966 
1967 /**
1968  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1969  *  @hw: pointer to hardware structure
1970  *  @byte_offset: EEPROM byte offset to write
1971  *  @eeprom_data: value to write
1972  *
1973  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1974  **/
ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 eeprom_data)1975 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1976 				   u8 eeprom_data)
1977 {
1978 	return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1979 					  IXGBE_I2C_EEPROM_DEV_ADDR,
1980 					  eeprom_data);
1981 }
1982 
1983 /**
1984  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1985  * @hw: pointer to hardware structure
1986  * @offset: eeprom offset to be read
1987  * @addr: I2C address to be read
1988  */
ixgbe_is_sfp_probe(struct ixgbe_hw * hw,u8 offset,u8 addr)1989 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1990 {
1991 	if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1992 	    offset == IXGBE_SFF_IDENTIFIER &&
1993 	    hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1994 		return true;
1995 	return false;
1996 }
1997 
1998 /**
1999  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2000  *  @hw: pointer to hardware structure
2001  *  @byte_offset: byte offset to read
2002  *  @dev_addr: device address
2003  *  @data: value read
2004  *  @lock: true if to take and release semaphore
2005  *
2006  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2007  *  a specified device address.
2008  */
ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data,bool lock)2009 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2010 					   u8 dev_addr, u8 *data, bool lock)
2011 {
2012 	s32 status;
2013 	u32 max_retry = 10;
2014 	u32 retry = 0;
2015 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
2016 	bool nack = true;
2017 
2018 	if (hw->mac.type >= ixgbe_mac_X550)
2019 		max_retry = 3;
2020 	if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2021 		max_retry = IXGBE_SFP_DETECT_RETRIES;
2022 
2023 	*data = 0;
2024 
2025 	do {
2026 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2027 			return -EBUSY;
2028 
2029 		ixgbe_i2c_start(hw);
2030 
2031 		/* Device Address and write indication */
2032 		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2033 		if (status != 0)
2034 			goto fail;
2035 
2036 		status = ixgbe_get_i2c_ack(hw);
2037 		if (status != 0)
2038 			goto fail;
2039 
2040 		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2041 		if (status != 0)
2042 			goto fail;
2043 
2044 		status = ixgbe_get_i2c_ack(hw);
2045 		if (status != 0)
2046 			goto fail;
2047 
2048 		ixgbe_i2c_start(hw);
2049 
2050 		/* Device Address and read indication */
2051 		status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2052 		if (status != 0)
2053 			goto fail;
2054 
2055 		status = ixgbe_get_i2c_ack(hw);
2056 		if (status != 0)
2057 			goto fail;
2058 
2059 		status = ixgbe_clock_in_i2c_byte(hw, data);
2060 		if (status != 0)
2061 			goto fail;
2062 
2063 		status = ixgbe_clock_out_i2c_bit(hw, nack);
2064 		if (status != 0)
2065 			goto fail;
2066 
2067 		ixgbe_i2c_stop(hw);
2068 		if (lock)
2069 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2070 		return 0;
2071 
2072 fail:
2073 		ixgbe_i2c_bus_clear(hw);
2074 		if (lock) {
2075 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2076 			msleep(100);
2077 		}
2078 		retry++;
2079 		if (retry < max_retry)
2080 			hw_dbg(hw, "I2C byte read error - Retrying.\n");
2081 		else
2082 			hw_dbg(hw, "I2C byte read error.\n");
2083 
2084 	} while (retry < max_retry);
2085 
2086 	return status;
2087 }
2088 
2089 /**
2090  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2091  *  @hw: pointer to hardware structure
2092  *  @byte_offset: byte offset to read
2093  *  @dev_addr: device address
2094  *  @data: value read
2095  *
2096  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2097  *  a specified device address.
2098  */
ixgbe_read_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2099 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2100 				u8 dev_addr, u8 *data)
2101 {
2102 	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2103 					       data, true);
2104 }
2105 
2106 /**
2107  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2108  *  @hw: pointer to hardware structure
2109  *  @byte_offset: byte offset to read
2110  *  @dev_addr: device address
2111  *  @data: value read
2112  *
2113  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2114  *  a specified device address.
2115  */
ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2116 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2117 					 u8 dev_addr, u8 *data)
2118 {
2119 	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2120 					       data, false);
2121 }
2122 
2123 /**
2124  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2125  *  @hw: pointer to hardware structure
2126  *  @byte_offset: byte offset to write
2127  *  @dev_addr: device address
2128  *  @data: value to write
2129  *  @lock: true if to take and release semaphore
2130  *
2131  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2132  *  a specified device address.
2133  */
ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data,bool lock)2134 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2135 					    u8 dev_addr, u8 data, bool lock)
2136 {
2137 	s32 status;
2138 	u32 max_retry = 1;
2139 	u32 retry = 0;
2140 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
2141 
2142 	if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2143 		return -EBUSY;
2144 
2145 	do {
2146 		ixgbe_i2c_start(hw);
2147 
2148 		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2149 		if (status != 0)
2150 			goto fail;
2151 
2152 		status = ixgbe_get_i2c_ack(hw);
2153 		if (status != 0)
2154 			goto fail;
2155 
2156 		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2157 		if (status != 0)
2158 			goto fail;
2159 
2160 		status = ixgbe_get_i2c_ack(hw);
2161 		if (status != 0)
2162 			goto fail;
2163 
2164 		status = ixgbe_clock_out_i2c_byte(hw, data);
2165 		if (status != 0)
2166 			goto fail;
2167 
2168 		status = ixgbe_get_i2c_ack(hw);
2169 		if (status != 0)
2170 			goto fail;
2171 
2172 		ixgbe_i2c_stop(hw);
2173 		if (lock)
2174 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2175 		return 0;
2176 
2177 fail:
2178 		ixgbe_i2c_bus_clear(hw);
2179 		retry++;
2180 		if (retry < max_retry)
2181 			hw_dbg(hw, "I2C byte write error - Retrying.\n");
2182 		else
2183 			hw_dbg(hw, "I2C byte write error.\n");
2184 	} while (retry < max_retry);
2185 
2186 	if (lock)
2187 		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2188 
2189 	return status;
2190 }
2191 
2192 /**
2193  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2194  *  @hw: pointer to hardware structure
2195  *  @byte_offset: byte offset to write
2196  *  @dev_addr: device address
2197  *  @data: value to write
2198  *
2199  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2200  *  a specified device address.
2201  */
ixgbe_write_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2202 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2203 				 u8 dev_addr, u8 data)
2204 {
2205 	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2206 						data, true);
2207 }
2208 
2209 /**
2210  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2211  *  @hw: pointer to hardware structure
2212  *  @byte_offset: byte offset to write
2213  *  @dev_addr: device address
2214  *  @data: value to write
2215  *
2216  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2217  *  a specified device address.
2218  */
ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2219 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2220 					  u8 dev_addr, u8 data)
2221 {
2222 	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2223 						data, false);
2224 }
2225 
2226 /**
2227  *  ixgbe_i2c_start - Sets I2C start condition
2228  *  @hw: pointer to hardware structure
2229  *
2230  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2231  *  Set bit-bang mode on X550 hardware.
2232  **/
ixgbe_i2c_start(struct ixgbe_hw * hw)2233 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2234 {
2235 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2236 
2237 	i2cctl |= IXGBE_I2C_BB_EN(hw);
2238 
2239 	/* Start condition must begin with data and clock high */
2240 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2241 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2242 
2243 	/* Setup time for start condition (4.7us) */
2244 	udelay(IXGBE_I2C_T_SU_STA);
2245 
2246 	ixgbe_set_i2c_data(hw, &i2cctl, 0);
2247 
2248 	/* Hold time for start condition (4us) */
2249 	udelay(IXGBE_I2C_T_HD_STA);
2250 
2251 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2252 
2253 	/* Minimum low period of clock is 4.7 us */
2254 	udelay(IXGBE_I2C_T_LOW);
2255 
2256 }
2257 
2258 /**
2259  *  ixgbe_i2c_stop - Sets I2C stop condition
2260  *  @hw: pointer to hardware structure
2261  *
2262  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2263  *  Disables bit-bang mode and negates data output enable on X550
2264  *  hardware.
2265  **/
ixgbe_i2c_stop(struct ixgbe_hw * hw)2266 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2267 {
2268 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2269 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2270 	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2271 	u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2272 
2273 	/* Stop condition must begin with data low and clock high */
2274 	ixgbe_set_i2c_data(hw, &i2cctl, 0);
2275 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2276 
2277 	/* Setup time for stop condition (4us) */
2278 	udelay(IXGBE_I2C_T_SU_STO);
2279 
2280 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2281 
2282 	/* bus free time between stop and start (4.7us)*/
2283 	udelay(IXGBE_I2C_T_BUF);
2284 
2285 	if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2286 		i2cctl &= ~bb_en_bit;
2287 		i2cctl |= data_oe_bit | clk_oe_bit;
2288 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2289 		IXGBE_WRITE_FLUSH(hw);
2290 	}
2291 }
2292 
2293 /**
2294  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2295  *  @hw: pointer to hardware structure
2296  *  @data: data byte to clock in
2297  *
2298  *  Clocks in one byte data via I2C data/clock
2299  **/
ixgbe_clock_in_i2c_byte(struct ixgbe_hw * hw,u8 * data)2300 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2301 {
2302 	s32 i;
2303 	bool bit = false;
2304 
2305 	*data = 0;
2306 	for (i = 7; i >= 0; i--) {
2307 		ixgbe_clock_in_i2c_bit(hw, &bit);
2308 		*data |= bit << i;
2309 	}
2310 
2311 	return 0;
2312 }
2313 
2314 /**
2315  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2316  *  @hw: pointer to hardware structure
2317  *  @data: data byte clocked out
2318  *
2319  *  Clocks out one byte data via I2C data/clock
2320  **/
ixgbe_clock_out_i2c_byte(struct ixgbe_hw * hw,u8 data)2321 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2322 {
2323 	s32 status;
2324 	s32 i;
2325 	u32 i2cctl;
2326 	bool bit = false;
2327 
2328 	for (i = 7; i >= 0; i--) {
2329 		bit = (data >> i) & 0x1;
2330 		status = ixgbe_clock_out_i2c_bit(hw, bit);
2331 
2332 		if (status != 0)
2333 			break;
2334 	}
2335 
2336 	/* Release SDA line (set high) */
2337 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2338 	i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2339 	i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2340 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2341 	IXGBE_WRITE_FLUSH(hw);
2342 
2343 	return status;
2344 }
2345 
2346 /**
2347  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2348  *  @hw: pointer to hardware structure
2349  *
2350  *  Clocks in/out one bit via I2C data/clock
2351  **/
ixgbe_get_i2c_ack(struct ixgbe_hw * hw)2352 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2353 {
2354 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2355 	s32 status = 0;
2356 	u32 i = 0;
2357 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2358 	u32 timeout = 10;
2359 	bool ack = true;
2360 
2361 	if (data_oe_bit) {
2362 		i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2363 		i2cctl |= data_oe_bit;
2364 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2365 		IXGBE_WRITE_FLUSH(hw);
2366 	}
2367 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2368 
2369 	/* Minimum high period of clock is 4us */
2370 	udelay(IXGBE_I2C_T_HIGH);
2371 
2372 	/* Poll for ACK.  Note that ACK in I2C spec is
2373 	 * transition from 1 to 0 */
2374 	for (i = 0; i < timeout; i++) {
2375 		i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2376 		ack = ixgbe_get_i2c_data(hw, &i2cctl);
2377 
2378 		udelay(1);
2379 		if (ack == 0)
2380 			break;
2381 	}
2382 
2383 	if (ack == 1) {
2384 		hw_dbg(hw, "I2C ack was not received.\n");
2385 		status = -EIO;
2386 	}
2387 
2388 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2389 
2390 	/* Minimum low period of clock is 4.7 us */
2391 	udelay(IXGBE_I2C_T_LOW);
2392 
2393 	return status;
2394 }
2395 
2396 /**
2397  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2398  *  @hw: pointer to hardware structure
2399  *  @data: read data value
2400  *
2401  *  Clocks in one bit via I2C data/clock
2402  **/
ixgbe_clock_in_i2c_bit(struct ixgbe_hw * hw,bool * data)2403 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2404 {
2405 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2406 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2407 
2408 	if (data_oe_bit) {
2409 		i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2410 		i2cctl |= data_oe_bit;
2411 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2412 		IXGBE_WRITE_FLUSH(hw);
2413 	}
2414 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2415 
2416 	/* Minimum high period of clock is 4us */
2417 	udelay(IXGBE_I2C_T_HIGH);
2418 
2419 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2420 	*data = ixgbe_get_i2c_data(hw, &i2cctl);
2421 
2422 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2423 
2424 	/* Minimum low period of clock is 4.7 us */
2425 	udelay(IXGBE_I2C_T_LOW);
2426 
2427 	return 0;
2428 }
2429 
2430 /**
2431  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2432  *  @hw: pointer to hardware structure
2433  *  @data: data value to write
2434  *
2435  *  Clocks out one bit via I2C data/clock
2436  **/
ixgbe_clock_out_i2c_bit(struct ixgbe_hw * hw,bool data)2437 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2438 {
2439 	s32 status;
2440 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2441 
2442 	status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2443 	if (status == 0) {
2444 		ixgbe_raise_i2c_clk(hw, &i2cctl);
2445 
2446 		/* Minimum high period of clock is 4us */
2447 		udelay(IXGBE_I2C_T_HIGH);
2448 
2449 		ixgbe_lower_i2c_clk(hw, &i2cctl);
2450 
2451 		/* Minimum low period of clock is 4.7 us.
2452 		 * This also takes care of the data hold time.
2453 		 */
2454 		udelay(IXGBE_I2C_T_LOW);
2455 	} else {
2456 		hw_dbg(hw, "I2C data was not set to %X\n", data);
2457 		return -EIO;
2458 	}
2459 
2460 	return 0;
2461 }
2462 /**
2463  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2464  *  @hw: pointer to hardware structure
2465  *  @i2cctl: Current value of I2CCTL register
2466  *
2467  *  Raises the I2C clock line '0'->'1'
2468  *  Negates the I2C clock output enable on X550 hardware.
2469  **/
ixgbe_raise_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2470 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2471 {
2472 	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2473 	u32 i = 0;
2474 	u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2475 	u32 i2cctl_r = 0;
2476 
2477 	if (clk_oe_bit) {
2478 		*i2cctl |= clk_oe_bit;
2479 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2480 	}
2481 
2482 	for (i = 0; i < timeout; i++) {
2483 		*i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2484 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2485 		IXGBE_WRITE_FLUSH(hw);
2486 		/* SCL rise time (1000ns) */
2487 		udelay(IXGBE_I2C_T_RISE);
2488 
2489 		i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2490 		if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2491 			break;
2492 	}
2493 }
2494 
2495 /**
2496  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2497  *  @hw: pointer to hardware structure
2498  *  @i2cctl: Current value of I2CCTL register
2499  *
2500  *  Lowers the I2C clock line '1'->'0'
2501  *  Asserts the I2C clock output enable on X550 hardware.
2502  **/
ixgbe_lower_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2503 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2504 {
2505 
2506 	*i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2507 	*i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2508 
2509 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2510 	IXGBE_WRITE_FLUSH(hw);
2511 
2512 	/* SCL fall time (300ns) */
2513 	udelay(IXGBE_I2C_T_FALL);
2514 }
2515 
2516 /**
2517  *  ixgbe_set_i2c_data - Sets the I2C data bit
2518  *  @hw: pointer to hardware structure
2519  *  @i2cctl: Current value of I2CCTL register
2520  *  @data: I2C data value (0 or 1) to set
2521  *
2522  *  Sets the I2C data bit
2523  *  Asserts the I2C data output enable on X550 hardware.
2524  **/
ixgbe_set_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl,bool data)2525 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2526 {
2527 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2528 
2529 	if (data)
2530 		*i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2531 	else
2532 		*i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2533 	*i2cctl &= ~data_oe_bit;
2534 
2535 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2536 	IXGBE_WRITE_FLUSH(hw);
2537 
2538 	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2539 	udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2540 
2541 	if (!data)	/* Can't verify data in this case */
2542 		return 0;
2543 	if (data_oe_bit) {
2544 		*i2cctl |= data_oe_bit;
2545 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2546 		IXGBE_WRITE_FLUSH(hw);
2547 	}
2548 
2549 	/* Verify data was set correctly */
2550 	*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2551 	if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2552 		hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2553 		return -EIO;
2554 	}
2555 
2556 	return 0;
2557 }
2558 
2559 /**
2560  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2561  *  @hw: pointer to hardware structure
2562  *  @i2cctl: Current value of I2CCTL register
2563  *
2564  *  Returns the I2C data bit value
2565  *  Negates the I2C data output enable on X550 hardware.
2566  **/
ixgbe_get_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl)2567 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2568 {
2569 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2570 
2571 	if (data_oe_bit) {
2572 		*i2cctl |= data_oe_bit;
2573 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2574 		IXGBE_WRITE_FLUSH(hw);
2575 		udelay(IXGBE_I2C_T_FALL);
2576 	}
2577 
2578 	if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2579 		return true;
2580 	return false;
2581 }
2582 
2583 /**
2584  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2585  *  @hw: pointer to hardware structure
2586  *
2587  *  Clears the I2C bus by sending nine clock pulses.
2588  *  Used when data line is stuck low.
2589  **/
ixgbe_i2c_bus_clear(struct ixgbe_hw * hw)2590 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2591 {
2592 	u32 i2cctl;
2593 	u32 i;
2594 
2595 	ixgbe_i2c_start(hw);
2596 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2597 
2598 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2599 
2600 	for (i = 0; i < 9; i++) {
2601 		ixgbe_raise_i2c_clk(hw, &i2cctl);
2602 
2603 		/* Min high period of clock is 4us */
2604 		udelay(IXGBE_I2C_T_HIGH);
2605 
2606 		ixgbe_lower_i2c_clk(hw, &i2cctl);
2607 
2608 		/* Min low period of clock is 4.7us*/
2609 		udelay(IXGBE_I2C_T_LOW);
2610 	}
2611 
2612 	ixgbe_i2c_start(hw);
2613 
2614 	/* Put the i2c bus back to default state */
2615 	ixgbe_i2c_stop(hw);
2616 }
2617 
2618 /**
2619  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2620  *  @hw: pointer to hardware structure
2621  *
2622  *  Checks if the LASI temp alarm status was triggered due to overtemp
2623  *
2624  *  Return true when an overtemp event detected, otherwise false.
2625  **/
ixgbe_tn_check_overtemp(struct ixgbe_hw * hw)2626 bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2627 {
2628 	u16 phy_data = 0;
2629 	u32 status;
2630 
2631 	if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2632 		return false;
2633 
2634 	/* Check that the LASI temp alarm status was triggered */
2635 	status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2636 				      MDIO_MMD_PMAPMD, &phy_data);
2637 	if (status)
2638 		return false;
2639 
2640 	return !!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM);
2641 }
2642 
2643 /** ixgbe_set_copper_phy_power - Control power for copper phy
2644  *  @hw: pointer to hardware structure
2645  *  @on: true for on, false for off
2646  **/
ixgbe_set_copper_phy_power(struct ixgbe_hw * hw,bool on)2647 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2648 {
2649 	u32 status;
2650 	u16 reg;
2651 
2652 	/* Bail if we don't have copper phy */
2653 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2654 		return 0;
2655 
2656 	if (!on && ixgbe_mng_present(hw))
2657 		return 0;
2658 
2659 	status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg);
2660 	if (status)
2661 		return status;
2662 
2663 	if (on) {
2664 		reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2665 	} else {
2666 		if (ixgbe_check_reset_blocked(hw))
2667 			return 0;
2668 		reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2669 	}
2670 
2671 	status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2672 	return status;
2673 }
2674