1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #ifndef OTX2_COMMON_H
9 #define OTX2_COMMON_H
10
11 #include <linux/ethtool.h>
12 #include <linux/pci.h>
13 #include <linux/iommu.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/ptp_clock_kernel.h>
16 #include <linux/timecounter.h>
17 #include <linux/soc/marvell/octeontx2/asm.h>
18 #include <net/pkt_cls.h>
19 #include <net/devlink.h>
20
21 #include <mbox.h>
22 #include <npc.h>
23 #include "otx2_reg.h"
24 #include "otx2_txrx.h"
25 #include "otx2_devlink.h"
26 #include <rvu_trace.h>
27
28 /* PCI device IDs */
29 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
30 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
31 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8
32
33 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200
34
35 /* PCI BAR nos */
36 #define PCI_CFG_REG_BAR_NUM 2
37 #define PCI_MBOX_BAR_NUM 4
38
39 #define NAME_SIZE 32
40
41 enum arua_mapped_qtypes {
42 AURA_NIX_RQ,
43 AURA_NIX_SQ,
44 };
45
46 /* NIX LF interrupts range*/
47 #define NIX_LF_QINT_VEC_START 0x00
48 #define NIX_LF_CINT_VEC_START 0x40
49 #define NIX_LF_GINT_VEC 0x80
50 #define NIX_LF_ERR_VEC 0x81
51 #define NIX_LF_POISON_VEC 0x82
52
53 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */
54 #define SEND_CQ_SKID 2000
55
56 struct otx2_lmt_info {
57 u64 lmt_addr;
58 u16 lmt_id;
59 };
60 /* RSS configuration */
61 struct otx2_rss_ctx {
62 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE];
63 };
64
65 struct otx2_rss_info {
66 u8 enable;
67 u32 flowkey_cfg;
68 u16 rss_size;
69 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */
70 u8 key[RSS_HASH_KEY_SIZE];
71 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS];
72 };
73
74 /* NIX (or NPC) RX errors */
75 enum otx2_errlvl {
76 NPC_ERRLVL_RE,
77 NPC_ERRLVL_LID_LA,
78 NPC_ERRLVL_LID_LB,
79 NPC_ERRLVL_LID_LC,
80 NPC_ERRLVL_LID_LD,
81 NPC_ERRLVL_LID_LE,
82 NPC_ERRLVL_LID_LF,
83 NPC_ERRLVL_LID_LG,
84 NPC_ERRLVL_LID_LH,
85 NPC_ERRLVL_NIX = 0x0F,
86 };
87
88 enum otx2_errcodes_re {
89 /* NPC_ERRLVL_RE errcodes */
90 ERRCODE_FCS = 0x7,
91 ERRCODE_FCS_RCV = 0x8,
92 ERRCODE_UNDERSIZE = 0x10,
93 ERRCODE_OVERSIZE = 0x11,
94 ERRCODE_OL2_LEN_MISMATCH = 0x12,
95 /* NPC_ERRLVL_NIX errcodes */
96 ERRCODE_OL3_LEN = 0x10,
97 ERRCODE_OL4_LEN = 0x11,
98 ERRCODE_OL4_CSUM = 0x12,
99 ERRCODE_IL3_LEN = 0x20,
100 ERRCODE_IL4_LEN = 0x21,
101 ERRCODE_IL4_CSUM = 0x22,
102 };
103
104 /* NIX TX stats */
105 enum nix_stat_lf_tx {
106 TX_UCAST = 0x0,
107 TX_BCAST = 0x1,
108 TX_MCAST = 0x2,
109 TX_DROP = 0x3,
110 TX_OCTS = 0x4,
111 TX_STATS_ENUM_LAST,
112 };
113
114 /* NIX RX stats */
115 enum nix_stat_lf_rx {
116 RX_OCTS = 0x0,
117 RX_UCAST = 0x1,
118 RX_BCAST = 0x2,
119 RX_MCAST = 0x3,
120 RX_DROP = 0x4,
121 RX_DROP_OCTS = 0x5,
122 RX_FCS = 0x6,
123 RX_ERR = 0x7,
124 RX_DRP_BCAST = 0x8,
125 RX_DRP_MCAST = 0x9,
126 RX_DRP_L3BCAST = 0xa,
127 RX_DRP_L3MCAST = 0xb,
128 RX_STATS_ENUM_LAST,
129 };
130
131 struct otx2_dev_stats {
132 u64 rx_bytes;
133 u64 rx_frames;
134 u64 rx_ucast_frames;
135 u64 rx_bcast_frames;
136 u64 rx_mcast_frames;
137 u64 rx_drops;
138
139 u64 tx_bytes;
140 u64 tx_frames;
141 u64 tx_ucast_frames;
142 u64 tx_bcast_frames;
143 u64 tx_mcast_frames;
144 u64 tx_drops;
145 };
146
147 /* Driver counted stats */
148 struct otx2_drv_stats {
149 atomic_t rx_fcs_errs;
150 atomic_t rx_oversize_errs;
151 atomic_t rx_undersize_errs;
152 atomic_t rx_csum_errs;
153 atomic_t rx_len_errs;
154 atomic_t rx_other_errs;
155 };
156
157 struct mbox {
158 struct otx2_mbox mbox;
159 struct work_struct mbox_wrk;
160 struct otx2_mbox mbox_up;
161 struct work_struct mbox_up_wrk;
162 struct otx2_nic *pfvf;
163 void *bbuf_base; /* Bounce buffer for mbox memory */
164 struct mutex lock; /* serialize mailbox access */
165 int num_msgs; /* mbox number of messages */
166 int up_num_msgs; /* mbox_up number of messages */
167 };
168
169 struct otx2_hw {
170 struct pci_dev *pdev;
171 struct otx2_rss_info rss_info;
172 u16 rx_queues;
173 u16 tx_queues;
174 u16 max_queues;
175 u16 pool_cnt;
176 u16 rqpool_cnt;
177 u16 sqpool_cnt;
178
179 /* NPA */
180 u32 stack_pg_ptrs; /* No of ptrs per stack page */
181 u32 stack_pg_bytes; /* Size of stack page */
182 u16 sqb_size;
183
184 /* NIX */
185 u8 txschq_link_cfg_lvl;
186 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
187 u16 matchall_ipolicer;
188 u32 dwrr_mtu;
189
190 /* HW settings, coalescing etc */
191 u16 rx_chan_base;
192 u16 tx_chan_base;
193 u16 cq_qcount_wait;
194 u16 cq_ecount_wait;
195 u16 rq_skid;
196 u8 cq_time_wait;
197
198 /* Segmentation */
199 u8 lso_tsov4_idx;
200 u8 lso_tsov6_idx;
201 u8 lso_udpv4_idx;
202 u8 lso_udpv6_idx;
203
204 /* RSS */
205 u8 flowkey_alg_idx;
206
207 /* MSI-X */
208 u8 cint_cnt; /* CQ interrupt count */
209 u16 npa_msixoff; /* Offset of NPA vectors */
210 u16 nix_msixoff; /* Offset of NIX vectors */
211 char *irq_name;
212 cpumask_var_t *affinity_mask;
213
214 /* Stats */
215 struct otx2_dev_stats dev_stats;
216 struct otx2_drv_stats drv_stats;
217 u64 cgx_rx_stats[CGX_RX_STATS_COUNT];
218 u64 cgx_tx_stats[CGX_TX_STATS_COUNT];
219 u64 cgx_fec_corr_blks;
220 u64 cgx_fec_uncorr_blks;
221 u8 cgx_links; /* No. of CGX links present in HW */
222 u8 lbk_links; /* No. of LBK links present in HW */
223 u8 tx_link; /* Transmit channel link number */
224 #define HW_TSO 0
225 #define CN10K_MBOX 1
226 #define CN10K_LMTST 2
227 unsigned long cap_flag;
228
229 #define LMT_LINE_SIZE 128
230 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */
231 u64 *lmt_base;
232 struct otx2_lmt_info __percpu *lmt_info;
233 };
234
235 enum vfperm {
236 OTX2_RESET_VF_PERM,
237 OTX2_TRUSTED_VF,
238 };
239
240 struct otx2_vf_config {
241 struct otx2_nic *pf;
242 struct delayed_work link_event_work;
243 bool intf_down; /* interface was either configured or not */
244 u8 mac[ETH_ALEN];
245 u16 vlan;
246 int tx_vtag_idx;
247 bool trusted;
248 };
249
250 struct flr_work {
251 struct work_struct work;
252 struct otx2_nic *pf;
253 };
254
255 struct refill_work {
256 struct delayed_work pool_refill_work;
257 struct otx2_nic *pf;
258 };
259
260 struct otx2_ptp {
261 struct ptp_clock_info ptp_info;
262 struct ptp_clock *ptp_clock;
263 struct otx2_nic *nic;
264
265 struct cyclecounter cycle_counter;
266 struct timecounter time_counter;
267 };
268
269 #define OTX2_HW_TIMESTAMP_LEN 8
270
271 struct otx2_mac_table {
272 u8 addr[ETH_ALEN];
273 u16 mcam_entry;
274 bool inuse;
275 };
276
277 struct otx2_flow_config {
278 u16 *flow_ent;
279 u16 *def_ent;
280 u16 nr_flows;
281 #define OTX2_DEFAULT_FLOWCOUNT 16
282 #define OTX2_MAX_UNICAST_FLOWS 8
283 #define OTX2_MAX_VLAN_FLOWS 1
284 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT
285 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \
286 OTX2_MAX_UNICAST_FLOWS + \
287 OTX2_MAX_VLAN_FLOWS)
288 u16 unicast_offset;
289 u16 rx_vlan_offset;
290 u16 vf_vlan_offset;
291 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */
292 #define OTX2_VF_VLAN_RX_INDEX 0
293 #define OTX2_VF_VLAN_TX_INDEX 1
294 u16 max_flows;
295 u8 dmacflt_max_flows;
296 u8 *bmap_to_dmacindex;
297 unsigned long dmacflt_bmap;
298 struct list_head flow_list;
299 };
300
301 struct otx2_tc_info {
302 /* hash table to store TC offloaded flows */
303 struct rhashtable flow_table;
304 struct rhashtable_params flow_ht_params;
305 unsigned long *tc_entries_bitmap;
306 };
307
308 struct dev_hw_ops {
309 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura);
310 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq,
311 int size, int qidx);
312 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq);
313 void (*aura_freeptr)(void *dev, int aura, u64 buf);
314 };
315
316 struct otx2_nic {
317 void __iomem *reg_base;
318 struct net_device *netdev;
319 struct dev_hw_ops *hw_ops;
320 void *iommu_domain;
321 u16 max_frs;
322 u16 rbsize; /* Receive buffer size */
323
324 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0)
325 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1)
326 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2)
327 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3)
328 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4)
329 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5)
330 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6)
331 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7)
332 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8)
333 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9)
334 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10)
335 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11)
336 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12)
337 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13)
338 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14)
339 u64 flags;
340 u64 *cq_op_addr;
341
342 struct otx2_qset qset;
343 struct otx2_hw hw;
344 struct pci_dev *pdev;
345 struct device *dev;
346
347 /* Mbox */
348 struct mbox mbox;
349 struct mbox *mbox_pfvf;
350 struct workqueue_struct *mbox_wq;
351 struct workqueue_struct *mbox_pfvf_wq;
352
353 u8 total_vfs;
354 u16 pcifunc; /* RVU PF_FUNC */
355 u16 bpid[NIX_MAX_BPID_CHAN];
356 struct otx2_vf_config *vf_configs;
357 struct cgx_link_user_info linfo;
358
359 /* NPC MCAM */
360 struct otx2_flow_config *flow_cfg;
361 struct otx2_mac_table *mac_table;
362 struct otx2_tc_info tc_info;
363
364 u64 reset_count;
365 struct work_struct reset_task;
366 struct workqueue_struct *flr_wq;
367 struct flr_work *flr_wrk;
368 struct refill_work *refill_wrk;
369 struct workqueue_struct *otx2_wq;
370 struct work_struct rx_mode_work;
371
372 /* Ethtool stuff */
373 u32 msg_enable;
374
375 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */
376 int nix_blkaddr;
377 /* LMTST Lines info */
378 struct qmem *dync_lmt;
379 u16 tot_lmt_lines;
380 u16 npa_lmt_lines;
381 u32 nix_lmt_size;
382
383 struct otx2_ptp *ptp;
384 struct hwtstamp_config tstamp;
385
386 unsigned long rq_bmap;
387
388 /* Devlink */
389 struct otx2_devlink *dl;
390 };
391
is_otx2_lbkvf(struct pci_dev * pdev)392 static inline bool is_otx2_lbkvf(struct pci_dev *pdev)
393 {
394 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF;
395 }
396
is_96xx_A0(struct pci_dev * pdev)397 static inline bool is_96xx_A0(struct pci_dev *pdev)
398 {
399 return (pdev->revision == 0x00) &&
400 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
401 }
402
is_96xx_B0(struct pci_dev * pdev)403 static inline bool is_96xx_B0(struct pci_dev *pdev)
404 {
405 return (pdev->revision == 0x01) &&
406 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
407 }
408
409 /* REVID for PCIe devices.
410 * Bits 0..1: minor pass, bit 3..2: major pass
411 * bits 7..4: midr id
412 */
413 #define PCI_REVISION_ID_96XX 0x00
414 #define PCI_REVISION_ID_95XX 0x10
415 #define PCI_REVISION_ID_95XXN 0x20
416 #define PCI_REVISION_ID_98XX 0x30
417 #define PCI_REVISION_ID_95XXMM 0x40
418 #define PCI_REVISION_ID_95XXO 0xE0
419
is_dev_otx2(struct pci_dev * pdev)420 static inline bool is_dev_otx2(struct pci_dev *pdev)
421 {
422 u8 midr = pdev->revision & 0xF0;
423
424 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
425 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
426 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
427 }
428
otx2_setup_dev_hw_settings(struct otx2_nic * pfvf)429 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
430 {
431 struct otx2_hw *hw = &pfvf->hw;
432
433 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT;
434 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT;
435 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT;
436
437 __set_bit(HW_TSO, &hw->cap_flag);
438
439 if (is_96xx_A0(pfvf->pdev)) {
440 __clear_bit(HW_TSO, &hw->cap_flag);
441
442 /* Time based irq coalescing is not supported */
443 pfvf->hw.cq_qcount_wait = 0x0;
444
445 /* Due to HW issue previous silicons required minimum
446 * 600 unused CQE to avoid CQ overflow.
447 */
448 pfvf->hw.rq_skid = 600;
449 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K);
450 }
451 if (is_96xx_B0(pfvf->pdev))
452 __clear_bit(HW_TSO, &hw->cap_flag);
453
454 if (!is_dev_otx2(pfvf->pdev)) {
455 __set_bit(CN10K_MBOX, &hw->cap_flag);
456 __set_bit(CN10K_LMTST, &hw->cap_flag);
457 }
458 }
459
460 /* Register read/write APIs */
otx2_get_regaddr(struct otx2_nic * nic,u64 offset)461 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset)
462 {
463 u64 blkaddr;
464
465 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) {
466 case BLKTYPE_NIX:
467 blkaddr = nic->nix_blkaddr;
468 break;
469 case BLKTYPE_NPA:
470 blkaddr = BLKADDR_NPA;
471 break;
472 default:
473 blkaddr = BLKADDR_RVUM;
474 break;
475 }
476
477 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT);
478 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT);
479
480 return nic->reg_base + offset;
481 }
482
otx2_write64(struct otx2_nic * nic,u64 offset,u64 val)483 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val)
484 {
485 void __iomem *addr = otx2_get_regaddr(nic, offset);
486
487 writeq(val, addr);
488 }
489
otx2_read64(struct otx2_nic * nic,u64 offset)490 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset)
491 {
492 void __iomem *addr = otx2_get_regaddr(nic, offset);
493
494 return readq(addr);
495 }
496
497 /* Mbox bounce buffer APIs */
otx2_mbox_bbuf_init(struct mbox * mbox,struct pci_dev * pdev)498 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev)
499 {
500 struct otx2_mbox *otx2_mbox;
501 struct otx2_mbox_dev *mdev;
502
503 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL);
504 if (!mbox->bbuf_base)
505 return -ENOMEM;
506
507 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF
508 * prepare all mbox messages in bounce buffer instead of directly
509 * in hw mbox memory.
510 */
511 otx2_mbox = &mbox->mbox;
512 mdev = &otx2_mbox->dev[0];
513 mdev->mbase = mbox->bbuf_base;
514
515 otx2_mbox = &mbox->mbox_up;
516 mdev = &otx2_mbox->dev[0];
517 mdev->mbase = mbox->bbuf_base;
518 return 0;
519 }
520
otx2_sync_mbox_bbuf(struct otx2_mbox * mbox,int devid)521 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid)
522 {
523 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
524 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE);
525 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
526 struct mbox_hdr *hdr;
527 u64 msg_size;
528
529 if (mdev->mbase == hw_mbase)
530 return;
531
532 hdr = hw_mbase + mbox->rx_start;
533 msg_size = hdr->msg_size;
534
535 if (msg_size > mbox->rx_size - msgs_offset)
536 msg_size = mbox->rx_size - msgs_offset;
537
538 /* Copy mbox messages from mbox memory to bounce buffer */
539 memcpy(mdev->mbase + mbox->rx_start,
540 hw_mbase + mbox->rx_start, msg_size + msgs_offset);
541 }
542
543 /* With the absence of API for 128-bit IO memory access for arm64,
544 * implement required operations at place.
545 */
546 #if defined(CONFIG_ARM64)
otx2_write128(u64 lo,u64 hi,void __iomem * addr)547 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr)
548 {
549 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!"
550 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr));
551 }
552
otx2_atomic64_add(u64 incr,u64 * ptr)553 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr)
554 {
555 u64 result;
556
557 __asm__ volatile(".cpu generic+lse\n"
558 "ldadd %x[i], %x[r], [%[b]]"
559 : [r]"=r"(result), "+m"(*ptr)
560 : [i]"r"(incr), [b]"r"(ptr)
561 : "memory");
562 return result;
563 }
564
565 #else
566 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr)
567 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; })
568 #endif
569
__cn10k_aura_freeptr(struct otx2_nic * pfvf,u64 aura,u64 * ptrs,u64 num_ptrs)570 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura,
571 u64 *ptrs, u64 num_ptrs)
572 {
573 struct otx2_lmt_info *lmt_info;
574 u64 size = 0, count_eot = 0;
575 u64 tar_addr, val = 0;
576
577 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id());
578 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0);
579 /* LMTID is same as AURA Id */
580 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63);
581 /* Set if [127:64] of last 128bit word has a valid pointer */
582 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL;
583 /* Set AURA ID to free pointer */
584 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF);
585 /* Target address for LMTST flush tells HW how many 128bit
586 * words are valid from NPA_LF_AURA_BATCH_FREE0.
587 *
588 * tar_addr[6:4] is LMTST size-1 in units of 128b.
589 */
590 if (num_ptrs > 2) {
591 size = (sizeof(u64) * num_ptrs) / 16;
592 if (!count_eot)
593 size++;
594 tar_addr |= ((size - 1) & 0x7) << 4;
595 }
596 dma_wmb();
597 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs);
598 /* Perform LMTST flush */
599 cn10k_lmt_flush(val, tar_addr);
600 }
601
cn10k_aura_freeptr(void * dev,int aura,u64 buf)602 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf)
603 {
604 struct otx2_nic *pfvf = dev;
605 u64 ptrs[2];
606
607 ptrs[1] = buf;
608 get_cpu();
609 /* Free only one buffer at time during init and teardown */
610 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2);
611 put_cpu();
612 }
613
614 /* Alloc pointer from pool/aura */
otx2_aura_allocptr(struct otx2_nic * pfvf,int aura)615 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura)
616 {
617 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf,
618 NPA_LF_AURA_OP_ALLOCX(0));
619 u64 incr = (u64)aura | BIT_ULL(63);
620
621 return otx2_atomic64_add(incr, ptr);
622 }
623
624 /* Free pointer to a pool/aura */
otx2_aura_freeptr(void * dev,int aura,u64 buf)625 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf)
626 {
627 struct otx2_nic *pfvf = dev;
628 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0);
629
630 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr);
631 }
632
otx2_get_pool_idx(struct otx2_nic * pfvf,int type,int idx)633 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx)
634 {
635 if (type == AURA_NIX_SQ)
636 return pfvf->hw.rqpool_cnt + idx;
637
638 /* AURA_NIX_RQ */
639 return idx;
640 }
641
642 /* Mbox APIs */
otx2_sync_mbox_msg(struct mbox * mbox)643 static inline int otx2_sync_mbox_msg(struct mbox *mbox)
644 {
645 int err;
646
647 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
648 return 0;
649 otx2_mbox_msg_send(&mbox->mbox, 0);
650 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0);
651 if (err)
652 return err;
653
654 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
655 }
656
otx2_sync_mbox_up_msg(struct mbox * mbox,int devid)657 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid)
658 {
659 int err;
660
661 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid))
662 return 0;
663 otx2_mbox_msg_send(&mbox->mbox_up, devid);
664 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid);
665 if (err)
666 return err;
667
668 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid);
669 }
670
671 /* Use this API to send mbox msgs in atomic context
672 * where sleeping is not allowed
673 */
otx2_sync_mbox_msg_busy_poll(struct mbox * mbox)674 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox)
675 {
676 int err;
677
678 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
679 return 0;
680 otx2_mbox_msg_send(&mbox->mbox, 0);
681 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0);
682 if (err)
683 return err;
684
685 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
686 }
687
688 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
689 static struct _req_type __maybe_unused \
690 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \
691 { \
692 struct _req_type *req; \
693 \
694 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
695 &mbox->mbox, 0, sizeof(struct _req_type), \
696 sizeof(struct _rsp_type)); \
697 if (!req) \
698 return NULL; \
699 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
700 req->hdr.id = _id; \
701 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \
702 return req; \
703 }
704
705 MBOX_MESSAGES
706 #undef M
707
708 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
709 int \
710 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \
711 struct _req_type *req, \
712 struct _rsp_type *rsp); \
713
714 MBOX_UP_CGX_MESSAGES
715 #undef M
716
717 /* Time to wait before watchdog kicks off */
718 #define OTX2_TX_TIMEOUT (100 * HZ)
719
720 #define RVU_PFVF_PF_SHIFT 10
721 #define RVU_PFVF_PF_MASK 0x3F
722 #define RVU_PFVF_FUNC_SHIFT 0
723 #define RVU_PFVF_FUNC_MASK 0x3FF
724
is_otx2_vf(u16 pcifunc)725 static inline bool is_otx2_vf(u16 pcifunc)
726 {
727 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
728 }
729
rvu_get_pf(u16 pcifunc)730 static inline int rvu_get_pf(u16 pcifunc)
731 {
732 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
733 }
734
otx2_dma_map_page(struct otx2_nic * pfvf,struct page * page,size_t offset,size_t size,enum dma_data_direction dir)735 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf,
736 struct page *page,
737 size_t offset, size_t size,
738 enum dma_data_direction dir)
739 {
740 dma_addr_t iova;
741
742 iova = dma_map_page_attrs(pfvf->dev, page,
743 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC);
744 if (unlikely(dma_mapping_error(pfvf->dev, iova)))
745 return (dma_addr_t)NULL;
746 return iova;
747 }
748
otx2_dma_unmap_page(struct otx2_nic * pfvf,dma_addr_t addr,size_t size,enum dma_data_direction dir)749 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf,
750 dma_addr_t addr, size_t size,
751 enum dma_data_direction dir)
752 {
753 dma_unmap_page_attrs(pfvf->dev, addr, size,
754 dir, DMA_ATTR_SKIP_CPU_SYNC);
755 }
756
757 /* MSI-X APIs */
758 void otx2_free_cints(struct otx2_nic *pfvf, int n);
759 void otx2_set_cints_affinity(struct otx2_nic *pfvf);
760 int otx2_set_mac_address(struct net_device *netdev, void *p);
761 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu);
762 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq);
763 void otx2_get_mac_from_af(struct net_device *netdev);
764 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx);
765 int otx2_config_pause_frm(struct otx2_nic *pfvf);
766 void otx2_setup_segmentation(struct otx2_nic *pfvf);
767
768 /* RVU block related APIs */
769 int otx2_attach_npa_nix(struct otx2_nic *pfvf);
770 int otx2_detach_resources(struct mbox *mbox);
771 int otx2_config_npa(struct otx2_nic *pfvf);
772 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf);
773 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf);
774 void otx2_aura_pool_free(struct otx2_nic *pfvf);
775 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type);
776 void otx2_sq_free_sqbs(struct otx2_nic *pfvf);
777 int otx2_config_nix(struct otx2_nic *pfvf);
778 int otx2_config_nix_queues(struct otx2_nic *pfvf);
779 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl);
780 int otx2_txsch_alloc(struct otx2_nic *pfvf);
781 int otx2_txschq_stop(struct otx2_nic *pfvf);
782 void otx2_sqb_flush(struct otx2_nic *pfvf);
783 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
784 dma_addr_t *dma);
785 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable);
786 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
787 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable);
788 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
789 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
790 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
791 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
792 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
793 dma_addr_t *dma);
794
795 /* RSS configuration APIs*/
796 int otx2_rss_init(struct otx2_nic *pfvf);
797 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf);
798 void otx2_set_rss_key(struct otx2_nic *pfvf);
799 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id);
800
801 /* Mbox handlers */
802 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
803 struct msix_offset_rsp *rsp);
804 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
805 struct npa_lf_alloc_rsp *rsp);
806 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
807 struct nix_lf_alloc_rsp *rsp);
808 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
809 struct nix_txsch_alloc_rsp *rsp);
810 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
811 struct cgx_stats_rsp *rsp);
812 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
813 struct cgx_fec_stats_rsp *rsp);
814 void otx2_set_fec_stats_count(struct otx2_nic *pfvf);
815 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
816 struct nix_bp_cfg_rsp *rsp);
817
818 /* Device stats APIs */
819 void otx2_get_dev_stats(struct otx2_nic *pfvf);
820 void otx2_get_stats64(struct net_device *netdev,
821 struct rtnl_link_stats64 *stats);
822 void otx2_update_lmac_stats(struct otx2_nic *pfvf);
823 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf);
824 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx);
825 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx);
826 void otx2_set_ethtool_ops(struct net_device *netdev);
827 void otx2vf_set_ethtool_ops(struct net_device *netdev);
828
829 int otx2_open(struct net_device *netdev);
830 int otx2_stop(struct net_device *netdev);
831 int otx2_set_real_num_queues(struct net_device *netdev,
832 int tx_queues, int rx_queues);
833 /* MCAM filter related APIs */
834 int otx2_mcam_flow_init(struct otx2_nic *pf);
835 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf);
836 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count);
837 void otx2_mcam_flow_del(struct otx2_nic *pf);
838 int otx2_destroy_ntuple_flows(struct otx2_nic *pf);
839 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf);
840 int otx2_get_flow(struct otx2_nic *pfvf,
841 struct ethtool_rxnfc *nfc, u32 location);
842 int otx2_get_all_flows(struct otx2_nic *pfvf,
843 struct ethtool_rxnfc *nfc, u32 *rule_locs);
844 int otx2_add_flow(struct otx2_nic *pfvf,
845 struct ethtool_rxnfc *nfc);
846 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location);
847 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg);
848 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id);
849 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac);
850 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac);
851 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable);
852 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf);
853 u16 otx2_get_max_mtu(struct otx2_nic *pfvf);
854 /* tc support */
855 int otx2_init_tc(struct otx2_nic *nic);
856 void otx2_shutdown_tc(struct otx2_nic *nic);
857 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type,
858 void *type_data);
859 int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic);
860 /* CGX/RPM DMAC filters support */
861 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf);
862 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u8 bit_pos);
863 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u8 bit_pos);
864 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u8 bit_pos);
865 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf);
866 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf);
867 #endif /* OTX2_COMMON_H */
868