1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
3 *
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 *
8 * Based on the SuperH Ethernet driver
9 */
10
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/sys_soc.h>
32 #include <linux/reset.h>
33 #include <linux/math64.h>
34
35 #include "ravb.h"
36
37 #define RAVB_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR)
42
43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
44 "ch0", /* RAVB_BE */
45 "ch1", /* RAVB_NC */
46 };
47
48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
49 "ch18", /* RAVB_BE */
50 "ch19", /* RAVB_NC */
51 };
52
ravb_modify(struct net_device * ndev,enum ravb_reg reg,u32 clear,u32 set)53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
54 u32 set)
55 {
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
57 }
58
ravb_wait(struct net_device * ndev,enum ravb_reg reg,u32 mask,u32 value)59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
60 {
61 int i;
62
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
65 return 0;
66 udelay(10);
67 }
68 return -ETIMEDOUT;
69 }
70
ravb_config(struct net_device * ndev)71 static int ravb_config(struct net_device *ndev)
72 {
73 int error;
74
75 /* Set config mode */
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
79 if (error)
80 netdev_err(ndev, "failed to switch device to config mode\n");
81
82 return error;
83 }
84
ravb_set_rate(struct net_device * ndev)85 static void ravb_set_rate(struct net_device *ndev)
86 {
87 struct ravb_private *priv = netdev_priv(ndev);
88
89 switch (priv->speed) {
90 case 100: /* 100BASE */
91 ravb_write(ndev, GECMR_SPEED_100, GECMR);
92 break;
93 case 1000: /* 1000BASE */
94 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
95 break;
96 }
97 }
98
ravb_set_buffer_align(struct sk_buff * skb)99 static void ravb_set_buffer_align(struct sk_buff *skb)
100 {
101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
102
103 if (reserve)
104 skb_reserve(skb, RAVB_ALIGN - reserve);
105 }
106
107 /* Get MAC address from the MAC address registers
108 *
109 * Ethernet AVB device doesn't have ROM for MAC address.
110 * This function gets the MAC address that was used by a bootloader.
111 */
ravb_read_mac_address(struct device_node * np,struct net_device * ndev)112 static void ravb_read_mac_address(struct device_node *np,
113 struct net_device *ndev)
114 {
115 int ret;
116
117 ret = of_get_ethdev_address(np, ndev);
118 if (ret) {
119 u32 mahr = ravb_read(ndev, MAHR);
120 u32 malr = ravb_read(ndev, MALR);
121
122 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
123 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
124 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
125 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
126 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
127 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
128 }
129 }
130
ravb_mdio_ctrl(struct mdiobb_ctrl * ctrl,u32 mask,int set)131 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
132 {
133 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
134 mdiobb);
135
136 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
137 }
138
139 /* MDC pin control */
ravb_set_mdc(struct mdiobb_ctrl * ctrl,int level)140 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
141 {
142 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
143 }
144
145 /* Data I/O pin control */
ravb_set_mdio_dir(struct mdiobb_ctrl * ctrl,int output)146 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
147 {
148 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
149 }
150
151 /* Set data bit */
ravb_set_mdio_data(struct mdiobb_ctrl * ctrl,int value)152 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
153 {
154 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
155 }
156
157 /* Get data bit */
ravb_get_mdio_data(struct mdiobb_ctrl * ctrl)158 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
159 {
160 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
161 mdiobb);
162
163 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
164 }
165
166 /* MDIO bus control struct */
167 static const struct mdiobb_ops bb_ops = {
168 .owner = THIS_MODULE,
169 .set_mdc = ravb_set_mdc,
170 .set_mdio_dir = ravb_set_mdio_dir,
171 .set_mdio_data = ravb_set_mdio_data,
172 .get_mdio_data = ravb_get_mdio_data,
173 };
174
175 /* Free TX skb function for AVB-IP */
ravb_tx_free(struct net_device * ndev,int q,bool free_txed_only)176 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
177 {
178 struct ravb_private *priv = netdev_priv(ndev);
179 struct net_device_stats *stats = &priv->stats[q];
180 unsigned int num_tx_desc = priv->num_tx_desc;
181 struct ravb_tx_desc *desc;
182 unsigned int entry;
183 int free_num = 0;
184 u32 size;
185
186 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
187 bool txed;
188
189 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
190 num_tx_desc);
191 desc = &priv->tx_ring[q][entry];
192 txed = desc->die_dt == DT_FEMPTY;
193 if (free_txed_only && !txed)
194 break;
195 /* Descriptor type must be checked before all other reads */
196 dma_rmb();
197 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
198 /* Free the original skb. */
199 if (priv->tx_skb[q][entry / num_tx_desc]) {
200 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
201 size, DMA_TO_DEVICE);
202 /* Last packet descriptor? */
203 if (entry % num_tx_desc == num_tx_desc - 1) {
204 entry /= num_tx_desc;
205 dev_kfree_skb_any(priv->tx_skb[q][entry]);
206 priv->tx_skb[q][entry] = NULL;
207 if (txed)
208 stats->tx_packets++;
209 }
210 free_num++;
211 }
212 if (txed)
213 stats->tx_bytes += size;
214 desc->die_dt = DT_EEMPTY;
215 }
216 return free_num;
217 }
218
ravb_rx_ring_free(struct net_device * ndev,int q)219 static void ravb_rx_ring_free(struct net_device *ndev, int q)
220 {
221 struct ravb_private *priv = netdev_priv(ndev);
222 unsigned int ring_size;
223 unsigned int i;
224
225 if (!priv->rx_ring[q])
226 return;
227
228 for (i = 0; i < priv->num_rx_ring[q]; i++) {
229 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
230
231 if (!dma_mapping_error(ndev->dev.parent,
232 le32_to_cpu(desc->dptr)))
233 dma_unmap_single(ndev->dev.parent,
234 le32_to_cpu(desc->dptr),
235 RX_BUF_SZ,
236 DMA_FROM_DEVICE);
237 }
238 ring_size = sizeof(struct ravb_ex_rx_desc) *
239 (priv->num_rx_ring[q] + 1);
240 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
241 priv->rx_desc_dma[q]);
242 priv->rx_ring[q] = NULL;
243 }
244
245 /* Free skb's and DMA buffers for Ethernet AVB */
ravb_ring_free(struct net_device * ndev,int q)246 static void ravb_ring_free(struct net_device *ndev, int q)
247 {
248 struct ravb_private *priv = netdev_priv(ndev);
249 const struct ravb_hw_info *info = priv->info;
250 unsigned int num_tx_desc = priv->num_tx_desc;
251 unsigned int ring_size;
252 unsigned int i;
253
254 info->rx_ring_free(ndev, q);
255
256 if (priv->tx_ring[q]) {
257 ravb_tx_free(ndev, q, false);
258
259 ring_size = sizeof(struct ravb_tx_desc) *
260 (priv->num_tx_ring[q] * num_tx_desc + 1);
261 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
262 priv->tx_desc_dma[q]);
263 priv->tx_ring[q] = NULL;
264 }
265
266 /* Free RX skb ringbuffer */
267 if (priv->rx_skb[q]) {
268 for (i = 0; i < priv->num_rx_ring[q]; i++)
269 dev_kfree_skb(priv->rx_skb[q][i]);
270 }
271 kfree(priv->rx_skb[q]);
272 priv->rx_skb[q] = NULL;
273
274 /* Free aligned TX buffers */
275 kfree(priv->tx_align[q]);
276 priv->tx_align[q] = NULL;
277
278 /* Free TX skb ringbuffer.
279 * SKBs are freed by ravb_tx_free() call above.
280 */
281 kfree(priv->tx_skb[q]);
282 priv->tx_skb[q] = NULL;
283 }
284
ravb_rx_ring_format(struct net_device * ndev,int q)285 static void ravb_rx_ring_format(struct net_device *ndev, int q)
286 {
287 struct ravb_private *priv = netdev_priv(ndev);
288 struct ravb_ex_rx_desc *rx_desc;
289 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
290 dma_addr_t dma_addr;
291 unsigned int i;
292
293 memset(priv->rx_ring[q], 0, rx_ring_size);
294 /* Build RX ring buffer */
295 for (i = 0; i < priv->num_rx_ring[q]; i++) {
296 /* RX descriptor */
297 rx_desc = &priv->rx_ring[q][i];
298 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
299 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
300 RX_BUF_SZ,
301 DMA_FROM_DEVICE);
302 /* We just set the data size to 0 for a failed mapping which
303 * should prevent DMA from happening...
304 */
305 if (dma_mapping_error(ndev->dev.parent, dma_addr))
306 rx_desc->ds_cc = cpu_to_le16(0);
307 rx_desc->dptr = cpu_to_le32(dma_addr);
308 rx_desc->die_dt = DT_FEMPTY;
309 }
310 rx_desc = &priv->rx_ring[q][i];
311 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
312 rx_desc->die_dt = DT_LINKFIX; /* type */
313 }
314
315 /* Format skb and descriptor buffer for Ethernet AVB */
ravb_ring_format(struct net_device * ndev,int q)316 static void ravb_ring_format(struct net_device *ndev, int q)
317 {
318 struct ravb_private *priv = netdev_priv(ndev);
319 const struct ravb_hw_info *info = priv->info;
320 unsigned int num_tx_desc = priv->num_tx_desc;
321 struct ravb_tx_desc *tx_desc;
322 struct ravb_desc *desc;
323 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
324 num_tx_desc;
325 unsigned int i;
326
327 priv->cur_rx[q] = 0;
328 priv->cur_tx[q] = 0;
329 priv->dirty_rx[q] = 0;
330 priv->dirty_tx[q] = 0;
331
332 info->rx_ring_format(ndev, q);
333
334 memset(priv->tx_ring[q], 0, tx_ring_size);
335 /* Build TX ring buffer */
336 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
337 i++, tx_desc++) {
338 tx_desc->die_dt = DT_EEMPTY;
339 if (num_tx_desc > 1) {
340 tx_desc++;
341 tx_desc->die_dt = DT_EEMPTY;
342 }
343 }
344 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
345 tx_desc->die_dt = DT_LINKFIX; /* type */
346
347 /* RX descriptor base address for best effort */
348 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
349 desc->die_dt = DT_LINKFIX; /* type */
350 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
351
352 /* TX descriptor base address for best effort */
353 desc = &priv->desc_bat[q];
354 desc->die_dt = DT_LINKFIX; /* type */
355 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
356 }
357
ravb_alloc_rx_desc(struct net_device * ndev,int q)358 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q)
359 {
360 struct ravb_private *priv = netdev_priv(ndev);
361 unsigned int ring_size;
362
363 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
364
365 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
366 &priv->rx_desc_dma[q],
367 GFP_KERNEL);
368 return priv->rx_ring[q];
369 }
370
371 /* Init skb and descriptor buffer for Ethernet AVB */
ravb_ring_init(struct net_device * ndev,int q)372 static int ravb_ring_init(struct net_device *ndev, int q)
373 {
374 struct ravb_private *priv = netdev_priv(ndev);
375 const struct ravb_hw_info *info = priv->info;
376 unsigned int num_tx_desc = priv->num_tx_desc;
377 unsigned int ring_size;
378 struct sk_buff *skb;
379 unsigned int i;
380
381 /* Allocate RX and TX skb rings */
382 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
383 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
384 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
385 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
386 if (!priv->rx_skb[q] || !priv->tx_skb[q])
387 goto error;
388
389 for (i = 0; i < priv->num_rx_ring[q]; i++) {
390 skb = netdev_alloc_skb(ndev, info->max_rx_len);
391 if (!skb)
392 goto error;
393 ravb_set_buffer_align(skb);
394 priv->rx_skb[q][i] = skb;
395 }
396
397 if (num_tx_desc > 1) {
398 /* Allocate rings for the aligned buffers */
399 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
400 DPTR_ALIGN - 1, GFP_KERNEL);
401 if (!priv->tx_align[q])
402 goto error;
403 }
404
405 /* Allocate all RX descriptors. */
406 if (!info->alloc_rx_desc(ndev, q))
407 goto error;
408
409 priv->dirty_rx[q] = 0;
410
411 /* Allocate all TX descriptors. */
412 ring_size = sizeof(struct ravb_tx_desc) *
413 (priv->num_tx_ring[q] * num_tx_desc + 1);
414 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
415 &priv->tx_desc_dma[q],
416 GFP_KERNEL);
417 if (!priv->tx_ring[q])
418 goto error;
419
420 return 0;
421
422 error:
423 ravb_ring_free(ndev, q);
424
425 return -ENOMEM;
426 }
427
ravb_rcar_emac_init(struct net_device * ndev)428 static void ravb_rcar_emac_init(struct net_device *ndev)
429 {
430 /* Receive frame limit set register */
431 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
432
433 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
434 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
435 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
436 ECMR_TE | ECMR_RE, ECMR);
437
438 ravb_set_rate(ndev);
439
440 /* Set MAC address */
441 ravb_write(ndev,
442 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
443 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
444 ravb_write(ndev,
445 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
446
447 /* E-MAC status register clear */
448 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
449
450 /* E-MAC interrupt enable register */
451 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
452 }
453
454 /* E-MAC init function */
ravb_emac_init(struct net_device * ndev)455 static void ravb_emac_init(struct net_device *ndev)
456 {
457 struct ravb_private *priv = netdev_priv(ndev);
458 const struct ravb_hw_info *info = priv->info;
459
460 info->emac_init(ndev);
461 }
462
ravb_rcar_dmac_init(struct net_device * ndev)463 static void ravb_rcar_dmac_init(struct net_device *ndev)
464 {
465 struct ravb_private *priv = netdev_priv(ndev);
466 const struct ravb_hw_info *info = priv->info;
467
468 /* Set AVB RX */
469 ravb_write(ndev,
470 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
471
472 /* Set FIFO size */
473 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
474
475 /* Timestamp enable */
476 ravb_write(ndev, TCCR_TFEN, TCCR);
477
478 /* Interrupt init: */
479 if (info->multi_irqs) {
480 /* Clear DIL.DPLx */
481 ravb_write(ndev, 0, DIL);
482 /* Set queue specific interrupt */
483 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
484 }
485 /* Frame receive */
486 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
487 /* Disable FIFO full warning */
488 ravb_write(ndev, 0, RIC1);
489 /* Receive FIFO full error, descriptor empty */
490 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
491 /* Frame transmitted, timestamp FIFO updated */
492 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
493 }
494
495 /* Device init function for Ethernet AVB */
ravb_dmac_init(struct net_device * ndev)496 static int ravb_dmac_init(struct net_device *ndev)
497 {
498 struct ravb_private *priv = netdev_priv(ndev);
499 const struct ravb_hw_info *info = priv->info;
500 int error;
501
502 /* Set CONFIG mode */
503 error = ravb_config(ndev);
504 if (error)
505 return error;
506
507 error = ravb_ring_init(ndev, RAVB_BE);
508 if (error)
509 return error;
510 error = ravb_ring_init(ndev, RAVB_NC);
511 if (error) {
512 ravb_ring_free(ndev, RAVB_BE);
513 return error;
514 }
515
516 /* Descriptor format */
517 ravb_ring_format(ndev, RAVB_BE);
518 ravb_ring_format(ndev, RAVB_NC);
519
520 info->dmac_init(ndev);
521
522 /* Setting the control will start the AVB-DMAC process. */
523 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
524
525 return 0;
526 }
527
ravb_get_tx_tstamp(struct net_device * ndev)528 static void ravb_get_tx_tstamp(struct net_device *ndev)
529 {
530 struct ravb_private *priv = netdev_priv(ndev);
531 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
532 struct skb_shared_hwtstamps shhwtstamps;
533 struct sk_buff *skb;
534 struct timespec64 ts;
535 u16 tag, tfa_tag;
536 int count;
537 u32 tfa2;
538
539 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
540 while (count--) {
541 tfa2 = ravb_read(ndev, TFA2);
542 tfa_tag = (tfa2 & TFA2_TST) >> 16;
543 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
544 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
545 ravb_read(ndev, TFA1);
546 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
547 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
548 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
549 list) {
550 skb = ts_skb->skb;
551 tag = ts_skb->tag;
552 list_del(&ts_skb->list);
553 kfree(ts_skb);
554 if (tag == tfa_tag) {
555 skb_tstamp_tx(skb, &shhwtstamps);
556 dev_consume_skb_any(skb);
557 break;
558 } else {
559 dev_kfree_skb_any(skb);
560 }
561 }
562 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
563 }
564 }
565
ravb_rx_csum(struct sk_buff * skb)566 static void ravb_rx_csum(struct sk_buff *skb)
567 {
568 u8 *hw_csum;
569
570 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
571 * appended to packet data
572 */
573 if (unlikely(skb->len < sizeof(__sum16)))
574 return;
575 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
576 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
577 skb->ip_summed = CHECKSUM_COMPLETE;
578 skb_trim(skb, skb->len - sizeof(__sum16));
579 }
580
ravb_rcar_rx(struct net_device * ndev,int * quota,int q)581 static bool ravb_rcar_rx(struct net_device *ndev, int *quota, int q)
582 {
583 struct ravb_private *priv = netdev_priv(ndev);
584 const struct ravb_hw_info *info = priv->info;
585 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
586 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
587 priv->cur_rx[q];
588 struct net_device_stats *stats = &priv->stats[q];
589 struct ravb_ex_rx_desc *desc;
590 struct sk_buff *skb;
591 dma_addr_t dma_addr;
592 struct timespec64 ts;
593 u8 desc_status;
594 u16 pkt_len;
595 int limit;
596
597 boguscnt = min(boguscnt, *quota);
598 limit = boguscnt;
599 desc = &priv->rx_ring[q][entry];
600 while (desc->die_dt != DT_FEMPTY) {
601 /* Descriptor type must be checked before all other reads */
602 dma_rmb();
603 desc_status = desc->msc;
604 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
605
606 if (--boguscnt < 0)
607 break;
608
609 /* We use 0-byte descriptors to mark the DMA mapping errors */
610 if (!pkt_len)
611 continue;
612
613 if (desc_status & MSC_MC)
614 stats->multicast++;
615
616 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
617 MSC_CEEF)) {
618 stats->rx_errors++;
619 if (desc_status & MSC_CRC)
620 stats->rx_crc_errors++;
621 if (desc_status & MSC_RFE)
622 stats->rx_frame_errors++;
623 if (desc_status & (MSC_RTLF | MSC_RTSF))
624 stats->rx_length_errors++;
625 if (desc_status & MSC_CEEF)
626 stats->rx_missed_errors++;
627 } else {
628 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
629
630 skb = priv->rx_skb[q][entry];
631 priv->rx_skb[q][entry] = NULL;
632 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
633 RX_BUF_SZ,
634 DMA_FROM_DEVICE);
635 get_ts &= (q == RAVB_NC) ?
636 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
637 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
638 if (get_ts) {
639 struct skb_shared_hwtstamps *shhwtstamps;
640
641 shhwtstamps = skb_hwtstamps(skb);
642 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
643 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
644 32) | le32_to_cpu(desc->ts_sl);
645 ts.tv_nsec = le32_to_cpu(desc->ts_n);
646 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
647 }
648
649 skb_put(skb, pkt_len);
650 skb->protocol = eth_type_trans(skb, ndev);
651 if (ndev->features & NETIF_F_RXCSUM)
652 ravb_rx_csum(skb);
653 napi_gro_receive(&priv->napi[q], skb);
654 stats->rx_packets++;
655 stats->rx_bytes += pkt_len;
656 }
657
658 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
659 desc = &priv->rx_ring[q][entry];
660 }
661
662 /* Refill the RX ring buffers. */
663 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
664 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
665 desc = &priv->rx_ring[q][entry];
666 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
667
668 if (!priv->rx_skb[q][entry]) {
669 skb = netdev_alloc_skb(ndev, info->max_rx_len);
670 if (!skb)
671 break; /* Better luck next round. */
672 ravb_set_buffer_align(skb);
673 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
674 le16_to_cpu(desc->ds_cc),
675 DMA_FROM_DEVICE);
676 skb_checksum_none_assert(skb);
677 /* We just set the data size to 0 for a failed mapping
678 * which should prevent DMA from happening...
679 */
680 if (dma_mapping_error(ndev->dev.parent, dma_addr))
681 desc->ds_cc = cpu_to_le16(0);
682 desc->dptr = cpu_to_le32(dma_addr);
683 priv->rx_skb[q][entry] = skb;
684 }
685 /* Descriptor type must be set after all the above writes */
686 dma_wmb();
687 desc->die_dt = DT_FEMPTY;
688 }
689
690 *quota -= limit - (++boguscnt);
691
692 return boguscnt <= 0;
693 }
694
695 /* Packet receive function for Ethernet AVB */
ravb_rx(struct net_device * ndev,int * quota,int q)696 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
697 {
698 struct ravb_private *priv = netdev_priv(ndev);
699 const struct ravb_hw_info *info = priv->info;
700
701 return info->receive(ndev, quota, q);
702 }
703
ravb_rcv_snd_disable(struct net_device * ndev)704 static void ravb_rcv_snd_disable(struct net_device *ndev)
705 {
706 /* Disable TX and RX */
707 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
708 }
709
ravb_rcv_snd_enable(struct net_device * ndev)710 static void ravb_rcv_snd_enable(struct net_device *ndev)
711 {
712 /* Enable TX and RX */
713 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
714 }
715
716 /* function for waiting dma process finished */
ravb_stop_dma(struct net_device * ndev)717 static int ravb_stop_dma(struct net_device *ndev)
718 {
719 int error;
720
721 /* Wait for stopping the hardware TX process */
722 error = ravb_wait(ndev, TCCR,
723 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
724 if (error)
725 return error;
726
727 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
728 0);
729 if (error)
730 return error;
731
732 /* Stop the E-MAC's RX/TX processes. */
733 ravb_rcv_snd_disable(ndev);
734
735 /* Wait for stopping the RX DMA process */
736 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
737 if (error)
738 return error;
739
740 /* Stop AVB-DMAC process */
741 return ravb_config(ndev);
742 }
743
744 /* E-MAC interrupt handler */
ravb_emac_interrupt_unlocked(struct net_device * ndev)745 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
746 {
747 struct ravb_private *priv = netdev_priv(ndev);
748 u32 ecsr, psr;
749
750 ecsr = ravb_read(ndev, ECSR);
751 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
752
753 if (ecsr & ECSR_MPD)
754 pm_wakeup_event(&priv->pdev->dev, 0);
755 if (ecsr & ECSR_ICD)
756 ndev->stats.tx_carrier_errors++;
757 if (ecsr & ECSR_LCHNG) {
758 /* Link changed */
759 if (priv->no_avb_link)
760 return;
761 psr = ravb_read(ndev, PSR);
762 if (priv->avb_link_active_low)
763 psr ^= PSR_LMON;
764 if (!(psr & PSR_LMON)) {
765 /* DIsable RX and TX */
766 ravb_rcv_snd_disable(ndev);
767 } else {
768 /* Enable RX and TX */
769 ravb_rcv_snd_enable(ndev);
770 }
771 }
772 }
773
ravb_emac_interrupt(int irq,void * dev_id)774 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
775 {
776 struct net_device *ndev = dev_id;
777 struct ravb_private *priv = netdev_priv(ndev);
778
779 spin_lock(&priv->lock);
780 ravb_emac_interrupt_unlocked(ndev);
781 spin_unlock(&priv->lock);
782 return IRQ_HANDLED;
783 }
784
785 /* Error interrupt handler */
ravb_error_interrupt(struct net_device * ndev)786 static void ravb_error_interrupt(struct net_device *ndev)
787 {
788 struct ravb_private *priv = netdev_priv(ndev);
789 u32 eis, ris2;
790
791 eis = ravb_read(ndev, EIS);
792 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
793 if (eis & EIS_QFS) {
794 ris2 = ravb_read(ndev, RIS2);
795 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),
796 RIS2);
797
798 /* Receive Descriptor Empty int */
799 if (ris2 & RIS2_QFF0)
800 priv->stats[RAVB_BE].rx_over_errors++;
801
802 /* Receive Descriptor Empty int */
803 if (ris2 & RIS2_QFF1)
804 priv->stats[RAVB_NC].rx_over_errors++;
805
806 /* Receive FIFO Overflow int */
807 if (ris2 & RIS2_RFFF)
808 priv->rx_fifo_errors++;
809 }
810 }
811
ravb_queue_interrupt(struct net_device * ndev,int q)812 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
813 {
814 struct ravb_private *priv = netdev_priv(ndev);
815 const struct ravb_hw_info *info = priv->info;
816 u32 ris0 = ravb_read(ndev, RIS0);
817 u32 ric0 = ravb_read(ndev, RIC0);
818 u32 tis = ravb_read(ndev, TIS);
819 u32 tic = ravb_read(ndev, TIC);
820
821 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
822 if (napi_schedule_prep(&priv->napi[q])) {
823 /* Mask RX and TX interrupts */
824 if (!info->multi_irqs) {
825 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
826 ravb_write(ndev, tic & ~BIT(q), TIC);
827 } else {
828 ravb_write(ndev, BIT(q), RID0);
829 ravb_write(ndev, BIT(q), TID);
830 }
831 __napi_schedule(&priv->napi[q]);
832 } else {
833 netdev_warn(ndev,
834 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
835 ris0, ric0);
836 netdev_warn(ndev,
837 " tx status 0x%08x, tx mask 0x%08x.\n",
838 tis, tic);
839 }
840 return true;
841 }
842 return false;
843 }
844
ravb_timestamp_interrupt(struct net_device * ndev)845 static bool ravb_timestamp_interrupt(struct net_device *ndev)
846 {
847 u32 tis = ravb_read(ndev, TIS);
848
849 if (tis & TIS_TFUF) {
850 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
851 ravb_get_tx_tstamp(ndev);
852 return true;
853 }
854 return false;
855 }
856
ravb_interrupt(int irq,void * dev_id)857 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
858 {
859 struct net_device *ndev = dev_id;
860 struct ravb_private *priv = netdev_priv(ndev);
861 irqreturn_t result = IRQ_NONE;
862 u32 iss;
863
864 spin_lock(&priv->lock);
865 /* Get interrupt status */
866 iss = ravb_read(ndev, ISS);
867
868 /* Received and transmitted interrupts */
869 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
870 int q;
871
872 /* Timestamp updated */
873 if (ravb_timestamp_interrupt(ndev))
874 result = IRQ_HANDLED;
875
876 /* Network control and best effort queue RX/TX */
877 for (q = RAVB_NC; q >= RAVB_BE; q--) {
878 if (ravb_queue_interrupt(ndev, q))
879 result = IRQ_HANDLED;
880 }
881 }
882
883 /* E-MAC status summary */
884 if (iss & ISS_MS) {
885 ravb_emac_interrupt_unlocked(ndev);
886 result = IRQ_HANDLED;
887 }
888
889 /* Error status summary */
890 if (iss & ISS_ES) {
891 ravb_error_interrupt(ndev);
892 result = IRQ_HANDLED;
893 }
894
895 /* gPTP interrupt status summary */
896 if (iss & ISS_CGIS) {
897 ravb_ptp_interrupt(ndev);
898 result = IRQ_HANDLED;
899 }
900
901 spin_unlock(&priv->lock);
902 return result;
903 }
904
905 /* Timestamp/Error/gPTP interrupt handler */
ravb_multi_interrupt(int irq,void * dev_id)906 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
907 {
908 struct net_device *ndev = dev_id;
909 struct ravb_private *priv = netdev_priv(ndev);
910 irqreturn_t result = IRQ_NONE;
911 u32 iss;
912
913 spin_lock(&priv->lock);
914 /* Get interrupt status */
915 iss = ravb_read(ndev, ISS);
916
917 /* Timestamp updated */
918 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
919 result = IRQ_HANDLED;
920
921 /* Error status summary */
922 if (iss & ISS_ES) {
923 ravb_error_interrupt(ndev);
924 result = IRQ_HANDLED;
925 }
926
927 /* gPTP interrupt status summary */
928 if (iss & ISS_CGIS) {
929 ravb_ptp_interrupt(ndev);
930 result = IRQ_HANDLED;
931 }
932
933 spin_unlock(&priv->lock);
934 return result;
935 }
936
ravb_dma_interrupt(int irq,void * dev_id,int q)937 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
938 {
939 struct net_device *ndev = dev_id;
940 struct ravb_private *priv = netdev_priv(ndev);
941 irqreturn_t result = IRQ_NONE;
942
943 spin_lock(&priv->lock);
944
945 /* Network control/Best effort queue RX/TX */
946 if (ravb_queue_interrupt(ndev, q))
947 result = IRQ_HANDLED;
948
949 spin_unlock(&priv->lock);
950 return result;
951 }
952
ravb_be_interrupt(int irq,void * dev_id)953 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
954 {
955 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
956 }
957
ravb_nc_interrupt(int irq,void * dev_id)958 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
959 {
960 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
961 }
962
ravb_poll(struct napi_struct * napi,int budget)963 static int ravb_poll(struct napi_struct *napi, int budget)
964 {
965 struct net_device *ndev = napi->dev;
966 struct ravb_private *priv = netdev_priv(ndev);
967 const struct ravb_hw_info *info = priv->info;
968 unsigned long flags;
969 int q = napi - priv->napi;
970 int mask = BIT(q);
971 int quota = budget;
972
973 /* Processing RX Descriptor Ring */
974 /* Clear RX interrupt */
975 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
976 if (ravb_rx(ndev, "a, q))
977 goto out;
978
979 /* Processing TX Descriptor Ring */
980 spin_lock_irqsave(&priv->lock, flags);
981 /* Clear TX interrupt */
982 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
983 ravb_tx_free(ndev, q, true);
984 netif_wake_subqueue(ndev, q);
985 spin_unlock_irqrestore(&priv->lock, flags);
986
987 napi_complete(napi);
988
989 /* Re-enable RX/TX interrupts */
990 spin_lock_irqsave(&priv->lock, flags);
991 if (!info->multi_irqs) {
992 ravb_modify(ndev, RIC0, mask, mask);
993 ravb_modify(ndev, TIC, mask, mask);
994 } else {
995 ravb_write(ndev, mask, RIE0);
996 ravb_write(ndev, mask, TIE);
997 }
998 spin_unlock_irqrestore(&priv->lock, flags);
999
1000 /* Receive error message handling */
1001 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
1002 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
1003 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
1004 ndev->stats.rx_over_errors = priv->rx_over_errors;
1005 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
1006 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
1007 out:
1008 return budget - quota;
1009 }
1010
1011 /* PHY state control function */
ravb_adjust_link(struct net_device * ndev)1012 static void ravb_adjust_link(struct net_device *ndev)
1013 {
1014 struct ravb_private *priv = netdev_priv(ndev);
1015 const struct ravb_hw_info *info = priv->info;
1016 struct phy_device *phydev = ndev->phydev;
1017 bool new_state = false;
1018 unsigned long flags;
1019
1020 spin_lock_irqsave(&priv->lock, flags);
1021
1022 /* Disable TX and RX right over here, if E-MAC change is ignored */
1023 if (priv->no_avb_link)
1024 ravb_rcv_snd_disable(ndev);
1025
1026 if (phydev->link) {
1027 if (phydev->speed != priv->speed) {
1028 new_state = true;
1029 priv->speed = phydev->speed;
1030 info->set_rate(ndev);
1031 }
1032 if (!priv->link) {
1033 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
1034 new_state = true;
1035 priv->link = phydev->link;
1036 }
1037 } else if (priv->link) {
1038 new_state = true;
1039 priv->link = 0;
1040 priv->speed = 0;
1041 }
1042
1043 /* Enable TX and RX right over here, if E-MAC change is ignored */
1044 if (priv->no_avb_link && phydev->link)
1045 ravb_rcv_snd_enable(ndev);
1046
1047 spin_unlock_irqrestore(&priv->lock, flags);
1048
1049 if (new_state && netif_msg_link(priv))
1050 phy_print_status(phydev);
1051 }
1052
1053 static const struct soc_device_attribute r8a7795es10[] = {
1054 { .soc_id = "r8a7795", .revision = "ES1.0", },
1055 { /* sentinel */ }
1056 };
1057
1058 /* PHY init function */
ravb_phy_init(struct net_device * ndev)1059 static int ravb_phy_init(struct net_device *ndev)
1060 {
1061 struct device_node *np = ndev->dev.parent->of_node;
1062 struct ravb_private *priv = netdev_priv(ndev);
1063 struct phy_device *phydev;
1064 struct device_node *pn;
1065 phy_interface_t iface;
1066 int err;
1067
1068 priv->link = 0;
1069 priv->speed = 0;
1070
1071 /* Try connecting to PHY */
1072 pn = of_parse_phandle(np, "phy-handle", 0);
1073 if (!pn) {
1074 /* In the case of a fixed PHY, the DT node associated
1075 * to the PHY is the Ethernet MAC DT node.
1076 */
1077 if (of_phy_is_fixed_link(np)) {
1078 err = of_phy_register_fixed_link(np);
1079 if (err)
1080 return err;
1081 }
1082 pn = of_node_get(np);
1083 }
1084
1085 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1086 : priv->phy_interface;
1087 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1088 of_node_put(pn);
1089 if (!phydev) {
1090 netdev_err(ndev, "failed to connect PHY\n");
1091 err = -ENOENT;
1092 goto err_deregister_fixed_link;
1093 }
1094
1095 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1096 * at this time.
1097 */
1098 if (soc_device_match(r8a7795es10)) {
1099 err = phy_set_max_speed(phydev, SPEED_100);
1100 if (err) {
1101 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1102 goto err_phy_disconnect;
1103 }
1104
1105 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1106 }
1107
1108 /* 10BASE, Pause and Asym Pause is not supported */
1109 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1110 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1111 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1112 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1113
1114 /* Half Duplex is not supported */
1115 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1116 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1117
1118 phy_attached_info(phydev);
1119
1120 return 0;
1121
1122 err_phy_disconnect:
1123 phy_disconnect(phydev);
1124 err_deregister_fixed_link:
1125 if (of_phy_is_fixed_link(np))
1126 of_phy_deregister_fixed_link(np);
1127
1128 return err;
1129 }
1130
1131 /* PHY control start function */
ravb_phy_start(struct net_device * ndev)1132 static int ravb_phy_start(struct net_device *ndev)
1133 {
1134 int error;
1135
1136 error = ravb_phy_init(ndev);
1137 if (error)
1138 return error;
1139
1140 phy_start(ndev->phydev);
1141
1142 return 0;
1143 }
1144
ravb_get_msglevel(struct net_device * ndev)1145 static u32 ravb_get_msglevel(struct net_device *ndev)
1146 {
1147 struct ravb_private *priv = netdev_priv(ndev);
1148
1149 return priv->msg_enable;
1150 }
1151
ravb_set_msglevel(struct net_device * ndev,u32 value)1152 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1153 {
1154 struct ravb_private *priv = netdev_priv(ndev);
1155
1156 priv->msg_enable = value;
1157 }
1158
1159 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1160 "rx_queue_0_current",
1161 "tx_queue_0_current",
1162 "rx_queue_0_dirty",
1163 "tx_queue_0_dirty",
1164 "rx_queue_0_packets",
1165 "tx_queue_0_packets",
1166 "rx_queue_0_bytes",
1167 "tx_queue_0_bytes",
1168 "rx_queue_0_mcast_packets",
1169 "rx_queue_0_errors",
1170 "rx_queue_0_crc_errors",
1171 "rx_queue_0_frame_errors",
1172 "rx_queue_0_length_errors",
1173 "rx_queue_0_missed_errors",
1174 "rx_queue_0_over_errors",
1175
1176 "rx_queue_1_current",
1177 "tx_queue_1_current",
1178 "rx_queue_1_dirty",
1179 "tx_queue_1_dirty",
1180 "rx_queue_1_packets",
1181 "tx_queue_1_packets",
1182 "rx_queue_1_bytes",
1183 "tx_queue_1_bytes",
1184 "rx_queue_1_mcast_packets",
1185 "rx_queue_1_errors",
1186 "rx_queue_1_crc_errors",
1187 "rx_queue_1_frame_errors",
1188 "rx_queue_1_length_errors",
1189 "rx_queue_1_missed_errors",
1190 "rx_queue_1_over_errors",
1191 };
1192
ravb_get_sset_count(struct net_device * netdev,int sset)1193 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1194 {
1195 struct ravb_private *priv = netdev_priv(netdev);
1196 const struct ravb_hw_info *info = priv->info;
1197
1198 switch (sset) {
1199 case ETH_SS_STATS:
1200 return info->stats_len;
1201 default:
1202 return -EOPNOTSUPP;
1203 }
1204 }
1205
ravb_get_ethtool_stats(struct net_device * ndev,struct ethtool_stats * estats,u64 * data)1206 static void ravb_get_ethtool_stats(struct net_device *ndev,
1207 struct ethtool_stats *estats, u64 *data)
1208 {
1209 struct ravb_private *priv = netdev_priv(ndev);
1210 int i = 0;
1211 int q;
1212
1213 /* Device-specific stats */
1214 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1215 struct net_device_stats *stats = &priv->stats[q];
1216
1217 data[i++] = priv->cur_rx[q];
1218 data[i++] = priv->cur_tx[q];
1219 data[i++] = priv->dirty_rx[q];
1220 data[i++] = priv->dirty_tx[q];
1221 data[i++] = stats->rx_packets;
1222 data[i++] = stats->tx_packets;
1223 data[i++] = stats->rx_bytes;
1224 data[i++] = stats->tx_bytes;
1225 data[i++] = stats->multicast;
1226 data[i++] = stats->rx_errors;
1227 data[i++] = stats->rx_crc_errors;
1228 data[i++] = stats->rx_frame_errors;
1229 data[i++] = stats->rx_length_errors;
1230 data[i++] = stats->rx_missed_errors;
1231 data[i++] = stats->rx_over_errors;
1232 }
1233 }
1234
ravb_get_strings(struct net_device * ndev,u32 stringset,u8 * data)1235 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1236 {
1237 struct ravb_private *priv = netdev_priv(ndev);
1238 const struct ravb_hw_info *info = priv->info;
1239
1240 switch (stringset) {
1241 case ETH_SS_STATS:
1242 memcpy(data, info->gstrings_stats, info->gstrings_size);
1243 break;
1244 }
1245 }
1246
ravb_get_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)1247 static void ravb_get_ringparam(struct net_device *ndev,
1248 struct ethtool_ringparam *ring)
1249 {
1250 struct ravb_private *priv = netdev_priv(ndev);
1251
1252 ring->rx_max_pending = BE_RX_RING_MAX;
1253 ring->tx_max_pending = BE_TX_RING_MAX;
1254 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1255 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1256 }
1257
ravb_set_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)1258 static int ravb_set_ringparam(struct net_device *ndev,
1259 struct ethtool_ringparam *ring)
1260 {
1261 struct ravb_private *priv = netdev_priv(ndev);
1262 const struct ravb_hw_info *info = priv->info;
1263 int error;
1264
1265 if (ring->tx_pending > BE_TX_RING_MAX ||
1266 ring->rx_pending > BE_RX_RING_MAX ||
1267 ring->tx_pending < BE_TX_RING_MIN ||
1268 ring->rx_pending < BE_RX_RING_MIN)
1269 return -EINVAL;
1270 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1271 return -EINVAL;
1272
1273 if (netif_running(ndev)) {
1274 netif_device_detach(ndev);
1275 /* Stop PTP Clock driver */
1276 if (info->gptp)
1277 ravb_ptp_stop(ndev);
1278 /* Wait for DMA stopping */
1279 error = ravb_stop_dma(ndev);
1280 if (error) {
1281 netdev_err(ndev,
1282 "cannot set ringparam! Any AVB processes are still running?\n");
1283 return error;
1284 }
1285 synchronize_irq(ndev->irq);
1286
1287 /* Free all the skb's in the RX queue and the DMA buffers. */
1288 ravb_ring_free(ndev, RAVB_BE);
1289 ravb_ring_free(ndev, RAVB_NC);
1290 }
1291
1292 /* Set new parameters */
1293 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1294 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1295
1296 if (netif_running(ndev)) {
1297 error = ravb_dmac_init(ndev);
1298 if (error) {
1299 netdev_err(ndev,
1300 "%s: ravb_dmac_init() failed, error %d\n",
1301 __func__, error);
1302 return error;
1303 }
1304
1305 ravb_emac_init(ndev);
1306
1307 /* Initialise PTP Clock driver */
1308 if (info->gptp)
1309 ravb_ptp_init(ndev, priv->pdev);
1310
1311 netif_device_attach(ndev);
1312 }
1313
1314 return 0;
1315 }
1316
ravb_get_ts_info(struct net_device * ndev,struct ethtool_ts_info * info)1317 static int ravb_get_ts_info(struct net_device *ndev,
1318 struct ethtool_ts_info *info)
1319 {
1320 struct ravb_private *priv = netdev_priv(ndev);
1321
1322 info->so_timestamping =
1323 SOF_TIMESTAMPING_TX_SOFTWARE |
1324 SOF_TIMESTAMPING_RX_SOFTWARE |
1325 SOF_TIMESTAMPING_SOFTWARE |
1326 SOF_TIMESTAMPING_TX_HARDWARE |
1327 SOF_TIMESTAMPING_RX_HARDWARE |
1328 SOF_TIMESTAMPING_RAW_HARDWARE;
1329 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1330 info->rx_filters =
1331 (1 << HWTSTAMP_FILTER_NONE) |
1332 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1333 (1 << HWTSTAMP_FILTER_ALL);
1334 info->phc_index = ptp_clock_index(priv->ptp.clock);
1335
1336 return 0;
1337 }
1338
ravb_get_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)1339 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1340 {
1341 struct ravb_private *priv = netdev_priv(ndev);
1342
1343 wol->supported = WAKE_MAGIC;
1344 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1345 }
1346
ravb_set_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)1347 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1348 {
1349 struct ravb_private *priv = netdev_priv(ndev);
1350
1351 if (wol->wolopts & ~WAKE_MAGIC)
1352 return -EOPNOTSUPP;
1353
1354 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1355
1356 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1357
1358 return 0;
1359 }
1360
1361 static const struct ethtool_ops ravb_ethtool_ops = {
1362 .nway_reset = phy_ethtool_nway_reset,
1363 .get_msglevel = ravb_get_msglevel,
1364 .set_msglevel = ravb_set_msglevel,
1365 .get_link = ethtool_op_get_link,
1366 .get_strings = ravb_get_strings,
1367 .get_ethtool_stats = ravb_get_ethtool_stats,
1368 .get_sset_count = ravb_get_sset_count,
1369 .get_ringparam = ravb_get_ringparam,
1370 .set_ringparam = ravb_set_ringparam,
1371 .get_ts_info = ravb_get_ts_info,
1372 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1373 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1374 .get_wol = ravb_get_wol,
1375 .set_wol = ravb_set_wol,
1376 };
1377
ravb_hook_irq(unsigned int irq,irq_handler_t handler,struct net_device * ndev,struct device * dev,const char * ch)1378 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1379 struct net_device *ndev, struct device *dev,
1380 const char *ch)
1381 {
1382 char *name;
1383 int error;
1384
1385 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1386 if (!name)
1387 return -ENOMEM;
1388 error = request_irq(irq, handler, 0, name, ndev);
1389 if (error)
1390 netdev_err(ndev, "cannot request IRQ %s\n", name);
1391
1392 return error;
1393 }
1394
1395 /* Network device open function for Ethernet AVB */
ravb_open(struct net_device * ndev)1396 static int ravb_open(struct net_device *ndev)
1397 {
1398 struct ravb_private *priv = netdev_priv(ndev);
1399 const struct ravb_hw_info *info = priv->info;
1400 struct platform_device *pdev = priv->pdev;
1401 struct device *dev = &pdev->dev;
1402 int error;
1403
1404 napi_enable(&priv->napi[RAVB_BE]);
1405 napi_enable(&priv->napi[RAVB_NC]);
1406
1407 if (!info->multi_irqs) {
1408 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1409 ndev->name, ndev);
1410 if (error) {
1411 netdev_err(ndev, "cannot request IRQ\n");
1412 goto out_napi_off;
1413 }
1414 } else {
1415 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1416 dev, "ch22:multi");
1417 if (error)
1418 goto out_napi_off;
1419 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1420 dev, "ch24:emac");
1421 if (error)
1422 goto out_free_irq;
1423 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1424 ndev, dev, "ch0:rx_be");
1425 if (error)
1426 goto out_free_irq_emac;
1427 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1428 ndev, dev, "ch18:tx_be");
1429 if (error)
1430 goto out_free_irq_be_rx;
1431 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1432 ndev, dev, "ch1:rx_nc");
1433 if (error)
1434 goto out_free_irq_be_tx;
1435 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1436 ndev, dev, "ch19:tx_nc");
1437 if (error)
1438 goto out_free_irq_nc_rx;
1439 }
1440
1441 /* Device init */
1442 error = ravb_dmac_init(ndev);
1443 if (error)
1444 goto out_free_irq_nc_tx;
1445 ravb_emac_init(ndev);
1446
1447 /* Initialise PTP Clock driver */
1448 if (info->gptp)
1449 ravb_ptp_init(ndev, priv->pdev);
1450
1451 /* PHY control start */
1452 error = ravb_phy_start(ndev);
1453 if (error)
1454 goto out_ptp_stop;
1455
1456 netif_tx_start_all_queues(ndev);
1457
1458 return 0;
1459
1460 out_ptp_stop:
1461 /* Stop PTP Clock driver */
1462 if (info->gptp)
1463 ravb_ptp_stop(ndev);
1464 ravb_stop_dma(ndev);
1465 out_free_irq_nc_tx:
1466 if (!info->multi_irqs)
1467 goto out_free_irq;
1468 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1469 out_free_irq_nc_rx:
1470 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1471 out_free_irq_be_tx:
1472 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1473 out_free_irq_be_rx:
1474 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1475 out_free_irq_emac:
1476 free_irq(priv->emac_irq, ndev);
1477 out_free_irq:
1478 free_irq(ndev->irq, ndev);
1479 out_napi_off:
1480 napi_disable(&priv->napi[RAVB_NC]);
1481 napi_disable(&priv->napi[RAVB_BE]);
1482 return error;
1483 }
1484
1485 /* Timeout function for Ethernet AVB */
ravb_tx_timeout(struct net_device * ndev,unsigned int txqueue)1486 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1487 {
1488 struct ravb_private *priv = netdev_priv(ndev);
1489
1490 netif_err(priv, tx_err, ndev,
1491 "transmit timed out, status %08x, resetting...\n",
1492 ravb_read(ndev, ISS));
1493
1494 /* tx_errors count up */
1495 ndev->stats.tx_errors++;
1496
1497 schedule_work(&priv->work);
1498 }
1499
ravb_tx_timeout_work(struct work_struct * work)1500 static void ravb_tx_timeout_work(struct work_struct *work)
1501 {
1502 struct ravb_private *priv = container_of(work, struct ravb_private,
1503 work);
1504 const struct ravb_hw_info *info = priv->info;
1505 struct net_device *ndev = priv->ndev;
1506 int error;
1507
1508 if (!rtnl_trylock()) {
1509 usleep_range(1000, 2000);
1510 schedule_work(&priv->work);
1511 return;
1512 }
1513
1514 netif_tx_stop_all_queues(ndev);
1515
1516 /* Stop PTP Clock driver */
1517 if (info->gptp)
1518 ravb_ptp_stop(ndev);
1519
1520 /* Wait for DMA stopping */
1521 if (ravb_stop_dma(ndev)) {
1522 /* If ravb_stop_dma() fails, the hardware is still operating
1523 * for TX and/or RX. So, this should not call the following
1524 * functions because ravb_dmac_init() is possible to fail too.
1525 * Also, this should not retry ravb_stop_dma() again and again
1526 * here because it's possible to wait forever. So, this just
1527 * re-enables the TX and RX and skip the following
1528 * re-initialization procedure.
1529 */
1530 ravb_rcv_snd_enable(ndev);
1531 goto out;
1532 }
1533
1534 ravb_ring_free(ndev, RAVB_BE);
1535 ravb_ring_free(ndev, RAVB_NC);
1536
1537 /* Device init */
1538 error = ravb_dmac_init(ndev);
1539 if (error) {
1540 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1541 * should return here to avoid re-enabling the TX and RX in
1542 * ravb_emac_init().
1543 */
1544 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1545 __func__, error);
1546 goto out_unlock;
1547 }
1548 ravb_emac_init(ndev);
1549
1550 out:
1551 /* Initialise PTP Clock driver */
1552 if (info->gptp)
1553 ravb_ptp_init(ndev, priv->pdev);
1554
1555 netif_tx_start_all_queues(ndev);
1556
1557 out_unlock:
1558 rtnl_unlock();
1559 }
1560
1561 /* Packet transmit function for Ethernet AVB */
ravb_start_xmit(struct sk_buff * skb,struct net_device * ndev)1562 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1563 {
1564 struct ravb_private *priv = netdev_priv(ndev);
1565 unsigned int num_tx_desc = priv->num_tx_desc;
1566 u16 q = skb_get_queue_mapping(skb);
1567 struct ravb_tstamp_skb *ts_skb;
1568 struct ravb_tx_desc *desc;
1569 unsigned long flags;
1570 dma_addr_t dma_addr;
1571 void *buffer;
1572 u32 entry;
1573 u32 len;
1574
1575 spin_lock_irqsave(&priv->lock, flags);
1576 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1577 num_tx_desc) {
1578 netif_err(priv, tx_queued, ndev,
1579 "still transmitting with the full ring!\n");
1580 netif_stop_subqueue(ndev, q);
1581 spin_unlock_irqrestore(&priv->lock, flags);
1582 return NETDEV_TX_BUSY;
1583 }
1584
1585 if (skb_put_padto(skb, ETH_ZLEN))
1586 goto exit;
1587
1588 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1589 priv->tx_skb[q][entry / num_tx_desc] = skb;
1590
1591 if (num_tx_desc > 1) {
1592 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1593 entry / num_tx_desc * DPTR_ALIGN;
1594 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1595
1596 /* Zero length DMA descriptors are problematic as they seem
1597 * to terminate DMA transfers. Avoid them by simply using a
1598 * length of DPTR_ALIGN (4) when skb data is aligned to
1599 * DPTR_ALIGN.
1600 *
1601 * As skb is guaranteed to have at least ETH_ZLEN (60)
1602 * bytes of data by the call to skb_put_padto() above this
1603 * is safe with respect to both the length of the first DMA
1604 * descriptor (len) overflowing the available data and the
1605 * length of the second DMA descriptor (skb->len - len)
1606 * being negative.
1607 */
1608 if (len == 0)
1609 len = DPTR_ALIGN;
1610
1611 memcpy(buffer, skb->data, len);
1612 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1613 DMA_TO_DEVICE);
1614 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1615 goto drop;
1616
1617 desc = &priv->tx_ring[q][entry];
1618 desc->ds_tagl = cpu_to_le16(len);
1619 desc->dptr = cpu_to_le32(dma_addr);
1620
1621 buffer = skb->data + len;
1622 len = skb->len - len;
1623 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1624 DMA_TO_DEVICE);
1625 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1626 goto unmap;
1627
1628 desc++;
1629 } else {
1630 desc = &priv->tx_ring[q][entry];
1631 len = skb->len;
1632 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
1633 DMA_TO_DEVICE);
1634 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1635 goto drop;
1636 }
1637 desc->ds_tagl = cpu_to_le16(len);
1638 desc->dptr = cpu_to_le32(dma_addr);
1639
1640 /* TX timestamp required */
1641 if (q == RAVB_NC) {
1642 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1643 if (!ts_skb) {
1644 if (num_tx_desc > 1) {
1645 desc--;
1646 dma_unmap_single(ndev->dev.parent, dma_addr,
1647 len, DMA_TO_DEVICE);
1648 }
1649 goto unmap;
1650 }
1651 ts_skb->skb = skb_get(skb);
1652 ts_skb->tag = priv->ts_skb_tag++;
1653 priv->ts_skb_tag &= 0x3ff;
1654 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1655
1656 /* TAG and timestamp required flag */
1657 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1658 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1659 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
1660 }
1661
1662 skb_tx_timestamp(skb);
1663 /* Descriptor type must be set after all the above writes */
1664 dma_wmb();
1665 if (num_tx_desc > 1) {
1666 desc->die_dt = DT_FEND;
1667 desc--;
1668 desc->die_dt = DT_FSTART;
1669 } else {
1670 desc->die_dt = DT_FSINGLE;
1671 }
1672 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1673
1674 priv->cur_tx[q] += num_tx_desc;
1675 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1676 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
1677 !ravb_tx_free(ndev, q, true))
1678 netif_stop_subqueue(ndev, q);
1679
1680 exit:
1681 spin_unlock_irqrestore(&priv->lock, flags);
1682 return NETDEV_TX_OK;
1683
1684 unmap:
1685 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1686 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1687 drop:
1688 dev_kfree_skb_any(skb);
1689 priv->tx_skb[q][entry / num_tx_desc] = NULL;
1690 goto exit;
1691 }
1692
ravb_select_queue(struct net_device * ndev,struct sk_buff * skb,struct net_device * sb_dev)1693 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1694 struct net_device *sb_dev)
1695 {
1696 /* If skb needs TX timestamp, it is handled in network control queue */
1697 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1698 RAVB_BE;
1699
1700 }
1701
ravb_get_stats(struct net_device * ndev)1702 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1703 {
1704 struct ravb_private *priv = netdev_priv(ndev);
1705 const struct ravb_hw_info *info = priv->info;
1706 struct net_device_stats *nstats, *stats0, *stats1;
1707
1708 nstats = &ndev->stats;
1709 stats0 = &priv->stats[RAVB_BE];
1710 stats1 = &priv->stats[RAVB_NC];
1711
1712 if (info->tx_counters) {
1713 nstats->tx_dropped += ravb_read(ndev, TROCR);
1714 ravb_write(ndev, 0, TROCR); /* (write clear) */
1715 }
1716
1717 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1718 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1719 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1720 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1721 nstats->multicast = stats0->multicast + stats1->multicast;
1722 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1723 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1724 nstats->rx_frame_errors =
1725 stats0->rx_frame_errors + stats1->rx_frame_errors;
1726 nstats->rx_length_errors =
1727 stats0->rx_length_errors + stats1->rx_length_errors;
1728 nstats->rx_missed_errors =
1729 stats0->rx_missed_errors + stats1->rx_missed_errors;
1730 nstats->rx_over_errors =
1731 stats0->rx_over_errors + stats1->rx_over_errors;
1732
1733 return nstats;
1734 }
1735
1736 /* Update promiscuous bit */
ravb_set_rx_mode(struct net_device * ndev)1737 static void ravb_set_rx_mode(struct net_device *ndev)
1738 {
1739 struct ravb_private *priv = netdev_priv(ndev);
1740 unsigned long flags;
1741
1742 spin_lock_irqsave(&priv->lock, flags);
1743 ravb_modify(ndev, ECMR, ECMR_PRM,
1744 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1745 spin_unlock_irqrestore(&priv->lock, flags);
1746 }
1747
1748 /* Device close function for Ethernet AVB */
ravb_close(struct net_device * ndev)1749 static int ravb_close(struct net_device *ndev)
1750 {
1751 struct device_node *np = ndev->dev.parent->of_node;
1752 struct ravb_private *priv = netdev_priv(ndev);
1753 const struct ravb_hw_info *info = priv->info;
1754 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1755
1756 netif_tx_stop_all_queues(ndev);
1757
1758 /* Disable interrupts by clearing the interrupt masks. */
1759 ravb_write(ndev, 0, RIC0);
1760 ravb_write(ndev, 0, RIC2);
1761 ravb_write(ndev, 0, TIC);
1762
1763 /* Stop PTP Clock driver */
1764 if (info->gptp)
1765 ravb_ptp_stop(ndev);
1766
1767 /* Set the config mode to stop the AVB-DMAC's processes */
1768 if (ravb_stop_dma(ndev) < 0)
1769 netdev_err(ndev,
1770 "device will be stopped after h/w processes are done.\n");
1771
1772 /* Clear the timestamp list */
1773 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1774 list_del(&ts_skb->list);
1775 kfree_skb(ts_skb->skb);
1776 kfree(ts_skb);
1777 }
1778
1779 /* PHY disconnect */
1780 if (ndev->phydev) {
1781 phy_stop(ndev->phydev);
1782 phy_disconnect(ndev->phydev);
1783 if (of_phy_is_fixed_link(np))
1784 of_phy_deregister_fixed_link(np);
1785 }
1786
1787 cancel_work_sync(&priv->work);
1788
1789 if (info->multi_irqs) {
1790 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1791 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1792 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1793 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1794 free_irq(priv->emac_irq, ndev);
1795 }
1796 free_irq(ndev->irq, ndev);
1797
1798 napi_disable(&priv->napi[RAVB_NC]);
1799 napi_disable(&priv->napi[RAVB_BE]);
1800
1801 /* Free all the skb's in the RX queue and the DMA buffers. */
1802 ravb_ring_free(ndev, RAVB_BE);
1803 ravb_ring_free(ndev, RAVB_NC);
1804
1805 return 0;
1806 }
1807
ravb_hwtstamp_get(struct net_device * ndev,struct ifreq * req)1808 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1809 {
1810 struct ravb_private *priv = netdev_priv(ndev);
1811 struct hwtstamp_config config;
1812
1813 config.flags = 0;
1814 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1815 HWTSTAMP_TX_OFF;
1816 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
1817 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
1818 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1819 break;
1820 case RAVB_RXTSTAMP_TYPE_ALL:
1821 config.rx_filter = HWTSTAMP_FILTER_ALL;
1822 break;
1823 default:
1824 config.rx_filter = HWTSTAMP_FILTER_NONE;
1825 }
1826
1827 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1828 -EFAULT : 0;
1829 }
1830
1831 /* Control hardware time stamping */
ravb_hwtstamp_set(struct net_device * ndev,struct ifreq * req)1832 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1833 {
1834 struct ravb_private *priv = netdev_priv(ndev);
1835 struct hwtstamp_config config;
1836 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1837 u32 tstamp_tx_ctrl;
1838
1839 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1840 return -EFAULT;
1841
1842 /* Reserved for future extensions */
1843 if (config.flags)
1844 return -EINVAL;
1845
1846 switch (config.tx_type) {
1847 case HWTSTAMP_TX_OFF:
1848 tstamp_tx_ctrl = 0;
1849 break;
1850 case HWTSTAMP_TX_ON:
1851 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1852 break;
1853 default:
1854 return -ERANGE;
1855 }
1856
1857 switch (config.rx_filter) {
1858 case HWTSTAMP_FILTER_NONE:
1859 tstamp_rx_ctrl = 0;
1860 break;
1861 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1862 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1863 break;
1864 default:
1865 config.rx_filter = HWTSTAMP_FILTER_ALL;
1866 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1867 }
1868
1869 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1870 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1871
1872 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1873 -EFAULT : 0;
1874 }
1875
1876 /* ioctl to device function */
ravb_do_ioctl(struct net_device * ndev,struct ifreq * req,int cmd)1877 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1878 {
1879 struct phy_device *phydev = ndev->phydev;
1880
1881 if (!netif_running(ndev))
1882 return -EINVAL;
1883
1884 if (!phydev)
1885 return -ENODEV;
1886
1887 switch (cmd) {
1888 case SIOCGHWTSTAMP:
1889 return ravb_hwtstamp_get(ndev, req);
1890 case SIOCSHWTSTAMP:
1891 return ravb_hwtstamp_set(ndev, req);
1892 }
1893
1894 return phy_mii_ioctl(phydev, req, cmd);
1895 }
1896
ravb_change_mtu(struct net_device * ndev,int new_mtu)1897 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
1898 {
1899 struct ravb_private *priv = netdev_priv(ndev);
1900
1901 ndev->mtu = new_mtu;
1902
1903 if (netif_running(ndev)) {
1904 synchronize_irq(priv->emac_irq);
1905 ravb_emac_init(ndev);
1906 }
1907
1908 netdev_update_features(ndev);
1909
1910 return 0;
1911 }
1912
ravb_set_rx_csum(struct net_device * ndev,bool enable)1913 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1914 {
1915 struct ravb_private *priv = netdev_priv(ndev);
1916 unsigned long flags;
1917
1918 spin_lock_irqsave(&priv->lock, flags);
1919
1920 /* Disable TX and RX */
1921 ravb_rcv_snd_disable(ndev);
1922
1923 /* Modify RX Checksum setting */
1924 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1925
1926 /* Enable TX and RX */
1927 ravb_rcv_snd_enable(ndev);
1928
1929 spin_unlock_irqrestore(&priv->lock, flags);
1930 }
1931
ravb_set_features_rx_csum(struct net_device * ndev,netdev_features_t features)1932 static int ravb_set_features_rx_csum(struct net_device *ndev,
1933 netdev_features_t features)
1934 {
1935 netdev_features_t changed = ndev->features ^ features;
1936
1937 if (changed & NETIF_F_RXCSUM)
1938 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1939
1940 ndev->features = features;
1941
1942 return 0;
1943 }
1944
ravb_set_features(struct net_device * ndev,netdev_features_t features)1945 static int ravb_set_features(struct net_device *ndev,
1946 netdev_features_t features)
1947 {
1948 struct ravb_private *priv = netdev_priv(ndev);
1949 const struct ravb_hw_info *info = priv->info;
1950
1951 return info->set_rx_csum_feature(ndev, features);
1952 }
1953
1954 static const struct net_device_ops ravb_netdev_ops = {
1955 .ndo_open = ravb_open,
1956 .ndo_stop = ravb_close,
1957 .ndo_start_xmit = ravb_start_xmit,
1958 .ndo_select_queue = ravb_select_queue,
1959 .ndo_get_stats = ravb_get_stats,
1960 .ndo_set_rx_mode = ravb_set_rx_mode,
1961 .ndo_tx_timeout = ravb_tx_timeout,
1962 .ndo_eth_ioctl = ravb_do_ioctl,
1963 .ndo_change_mtu = ravb_change_mtu,
1964 .ndo_validate_addr = eth_validate_addr,
1965 .ndo_set_mac_address = eth_mac_addr,
1966 .ndo_set_features = ravb_set_features,
1967 };
1968
1969 /* MDIO bus init function */
ravb_mdio_init(struct ravb_private * priv)1970 static int ravb_mdio_init(struct ravb_private *priv)
1971 {
1972 struct platform_device *pdev = priv->pdev;
1973 struct device *dev = &pdev->dev;
1974 struct phy_device *phydev;
1975 struct device_node *pn;
1976 int error;
1977
1978 /* Bitbang init */
1979 priv->mdiobb.ops = &bb_ops;
1980
1981 /* MII controller setting */
1982 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1983 if (!priv->mii_bus)
1984 return -ENOMEM;
1985
1986 /* Hook up MII support for ethtool */
1987 priv->mii_bus->name = "ravb_mii";
1988 priv->mii_bus->parent = dev;
1989 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1990 pdev->name, pdev->id);
1991
1992 /* Register MDIO bus */
1993 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1994 if (error)
1995 goto out_free_bus;
1996
1997 pn = of_parse_phandle(dev->of_node, "phy-handle", 0);
1998 phydev = of_phy_find_device(pn);
1999 if (phydev) {
2000 phydev->mac_managed_pm = true;
2001 put_device(&phydev->mdio.dev);
2002 }
2003 of_node_put(pn);
2004
2005 return 0;
2006
2007 out_free_bus:
2008 free_mdio_bitbang(priv->mii_bus);
2009 return error;
2010 }
2011
2012 /* MDIO bus release function */
ravb_mdio_release(struct ravb_private * priv)2013 static int ravb_mdio_release(struct ravb_private *priv)
2014 {
2015 /* Unregister mdio bus */
2016 mdiobus_unregister(priv->mii_bus);
2017
2018 /* Free bitbang info */
2019 free_mdio_bitbang(priv->mii_bus);
2020
2021 return 0;
2022 }
2023
2024 static const struct ravb_hw_info ravb_gen3_hw_info = {
2025 .rx_ring_free = ravb_rx_ring_free,
2026 .rx_ring_format = ravb_rx_ring_format,
2027 .alloc_rx_desc = ravb_alloc_rx_desc,
2028 .receive = ravb_rcar_rx,
2029 .set_rate = ravb_set_rate,
2030 .set_rx_csum_feature = ravb_set_features_rx_csum,
2031 .dmac_init = ravb_rcar_dmac_init,
2032 .emac_init = ravb_rcar_emac_init,
2033 .gstrings_stats = ravb_gstrings_stats,
2034 .gstrings_size = sizeof(ravb_gstrings_stats),
2035 .net_hw_features = NETIF_F_RXCSUM,
2036 .net_features = NETIF_F_RXCSUM,
2037 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2038 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2039 .internal_delay = 1,
2040 .tx_counters = 1,
2041 .multi_irqs = 1,
2042 .ccc_gac = 1,
2043 };
2044
2045 static const struct ravb_hw_info ravb_gen2_hw_info = {
2046 .rx_ring_free = ravb_rx_ring_free,
2047 .rx_ring_format = ravb_rx_ring_format,
2048 .alloc_rx_desc = ravb_alloc_rx_desc,
2049 .receive = ravb_rcar_rx,
2050 .set_rate = ravb_set_rate,
2051 .set_rx_csum_feature = ravb_set_features_rx_csum,
2052 .dmac_init = ravb_rcar_dmac_init,
2053 .emac_init = ravb_rcar_emac_init,
2054 .gstrings_stats = ravb_gstrings_stats,
2055 .gstrings_size = sizeof(ravb_gstrings_stats),
2056 .net_hw_features = NETIF_F_RXCSUM,
2057 .net_features = NETIF_F_RXCSUM,
2058 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2059 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2060 .aligned_tx = 1,
2061 .gptp = 1,
2062 };
2063
2064 static const struct of_device_id ravb_match_table[] = {
2065 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info },
2066 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info },
2067 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
2068 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
2069 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
2070 { }
2071 };
2072 MODULE_DEVICE_TABLE(of, ravb_match_table);
2073
ravb_set_gti(struct net_device * ndev)2074 static int ravb_set_gti(struct net_device *ndev)
2075 {
2076 struct ravb_private *priv = netdev_priv(ndev);
2077 struct device *dev = ndev->dev.parent;
2078 unsigned long rate;
2079 uint64_t inc;
2080
2081 rate = clk_get_rate(priv->clk);
2082 if (!rate)
2083 return -EINVAL;
2084
2085 inc = div64_ul(1000000000ULL << 20, rate);
2086
2087 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
2088 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
2089 inc, GTI_TIV_MIN, GTI_TIV_MAX);
2090 return -EINVAL;
2091 }
2092
2093 ravb_write(ndev, inc, GTI);
2094
2095 return 0;
2096 }
2097
ravb_set_config_mode(struct net_device * ndev)2098 static void ravb_set_config_mode(struct net_device *ndev)
2099 {
2100 struct ravb_private *priv = netdev_priv(ndev);
2101 const struct ravb_hw_info *info = priv->info;
2102
2103 if (info->gptp) {
2104 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2105 /* Set CSEL value */
2106 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
2107 } else {
2108 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
2109 CCC_GAC | CCC_CSEL_HPB);
2110 }
2111 }
2112
2113 /* Set tx and rx clock internal delay modes */
ravb_parse_delay_mode(struct device_node * np,struct net_device * ndev)2114 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
2115 {
2116 struct ravb_private *priv = netdev_priv(ndev);
2117 bool explicit_delay = false;
2118 u32 delay;
2119
2120 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
2121 /* Valid values are 0 and 1800, according to DT bindings */
2122 priv->rxcidm = !!delay;
2123 explicit_delay = true;
2124 }
2125 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
2126 /* Valid values are 0 and 2000, according to DT bindings */
2127 priv->txcidm = !!delay;
2128 explicit_delay = true;
2129 }
2130
2131 if (explicit_delay)
2132 return;
2133
2134 /* Fall back to legacy rgmii-*id behavior */
2135 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2136 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
2137 priv->rxcidm = 1;
2138 priv->rgmii_override = 1;
2139 }
2140
2141 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2142 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2143 priv->txcidm = 1;
2144 priv->rgmii_override = 1;
2145 }
2146 }
2147
ravb_set_delay_mode(struct net_device * ndev)2148 static void ravb_set_delay_mode(struct net_device *ndev)
2149 {
2150 struct ravb_private *priv = netdev_priv(ndev);
2151 u32 set = 0;
2152
2153 if (priv->rxcidm)
2154 set |= APSR_RDM;
2155 if (priv->txcidm)
2156 set |= APSR_TDM;
2157 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set);
2158 }
2159
ravb_probe(struct platform_device * pdev)2160 static int ravb_probe(struct platform_device *pdev)
2161 {
2162 struct device_node *np = pdev->dev.of_node;
2163 const struct ravb_hw_info *info;
2164 struct reset_control *rstc;
2165 struct ravb_private *priv;
2166 struct net_device *ndev;
2167 int error, irq, q;
2168 struct resource *res;
2169 int i;
2170
2171 if (!np) {
2172 dev_err(&pdev->dev,
2173 "this driver is required to be instantiated from device tree\n");
2174 return -EINVAL;
2175 }
2176
2177 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
2178 if (IS_ERR(rstc))
2179 return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
2180 "failed to get cpg reset\n");
2181
2182 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2183 NUM_TX_QUEUE, NUM_RX_QUEUE);
2184 if (!ndev)
2185 return -ENOMEM;
2186
2187 info = of_device_get_match_data(&pdev->dev);
2188
2189 ndev->features = info->net_features;
2190 ndev->hw_features = info->net_hw_features;
2191
2192 error = reset_control_deassert(rstc);
2193 if (error)
2194 goto out_free_netdev;
2195
2196 pm_runtime_enable(&pdev->dev);
2197 error = pm_runtime_resume_and_get(&pdev->dev);
2198 if (error < 0)
2199 goto out_rpm_disable;
2200
2201 if (info->multi_irqs)
2202 irq = platform_get_irq_byname(pdev, "ch22");
2203 else
2204 irq = platform_get_irq(pdev, 0);
2205 if (irq < 0) {
2206 error = irq;
2207 goto out_release;
2208 }
2209 ndev->irq = irq;
2210
2211 SET_NETDEV_DEV(ndev, &pdev->dev);
2212
2213 priv = netdev_priv(ndev);
2214 priv->info = info;
2215 priv->rstc = rstc;
2216 priv->ndev = ndev;
2217 priv->pdev = pdev;
2218 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2219 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2220 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2221 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2222 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2223 if (IS_ERR(priv->addr)) {
2224 error = PTR_ERR(priv->addr);
2225 goto out_release;
2226 }
2227
2228 /* The Ether-specific entries in the device structure. */
2229 ndev->base_addr = res->start;
2230
2231 spin_lock_init(&priv->lock);
2232 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2233
2234 error = of_get_phy_mode(np, &priv->phy_interface);
2235 if (error && error != -ENODEV)
2236 goto out_release;
2237
2238 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2239 priv->avb_link_active_low =
2240 of_property_read_bool(np, "renesas,ether-link-active-low");
2241
2242 if (info->multi_irqs) {
2243 irq = platform_get_irq_byname(pdev, "ch24");
2244 if (irq < 0) {
2245 error = irq;
2246 goto out_release;
2247 }
2248 priv->emac_irq = irq;
2249 for (i = 0; i < NUM_RX_QUEUE; i++) {
2250 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2251 if (irq < 0) {
2252 error = irq;
2253 goto out_release;
2254 }
2255 priv->rx_irqs[i] = irq;
2256 }
2257 for (i = 0; i < NUM_TX_QUEUE; i++) {
2258 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2259 if (irq < 0) {
2260 error = irq;
2261 goto out_release;
2262 }
2263 priv->tx_irqs[i] = irq;
2264 }
2265 }
2266
2267 priv->clk = devm_clk_get(&pdev->dev, NULL);
2268 if (IS_ERR(priv->clk)) {
2269 error = PTR_ERR(priv->clk);
2270 goto out_release;
2271 }
2272
2273 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk");
2274 if (IS_ERR(priv->refclk)) {
2275 error = PTR_ERR(priv->refclk);
2276 goto out_release;
2277 }
2278 clk_prepare_enable(priv->refclk);
2279
2280 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2281 ndev->min_mtu = ETH_MIN_MTU;
2282
2283 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer
2284 * Use two descriptor to handle such situation. First descriptor to
2285 * handle aligned data buffer and second descriptor to handle the
2286 * overflow data because of alignment.
2287 */
2288 priv->num_tx_desc = info->aligned_tx ? 2 : 1;
2289
2290 /* Set function */
2291 ndev->netdev_ops = &ravb_netdev_ops;
2292 ndev->ethtool_ops = &ravb_ethtool_ops;
2293
2294 /* Set AVB config mode */
2295 ravb_set_config_mode(ndev);
2296
2297 /* Set GTI value */
2298 error = ravb_set_gti(ndev);
2299 if (error)
2300 goto out_disable_refclk;
2301
2302 /* Request GTI loading */
2303 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2304
2305 if (info->internal_delay) {
2306 ravb_parse_delay_mode(np, ndev);
2307 ravb_set_delay_mode(ndev);
2308 }
2309
2310 /* Allocate descriptor base address table */
2311 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2312 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2313 &priv->desc_bat_dma, GFP_KERNEL);
2314 if (!priv->desc_bat) {
2315 dev_err(&pdev->dev,
2316 "Cannot allocate desc base address table (size %d bytes)\n",
2317 priv->desc_bat_size);
2318 error = -ENOMEM;
2319 goto out_disable_refclk;
2320 }
2321 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2322 priv->desc_bat[q].die_dt = DT_EOS;
2323 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2324
2325 /* Initialise HW timestamp list */
2326 INIT_LIST_HEAD(&priv->ts_skb_list);
2327
2328 /* Initialise PTP Clock driver */
2329 if (info->ccc_gac)
2330 ravb_ptp_init(ndev, pdev);
2331
2332 /* Debug message level */
2333 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2334
2335 /* Read and set MAC address */
2336 ravb_read_mac_address(np, ndev);
2337 if (!is_valid_ether_addr(ndev->dev_addr)) {
2338 dev_warn(&pdev->dev,
2339 "no valid MAC address supplied, using a random one\n");
2340 eth_hw_addr_random(ndev);
2341 }
2342
2343 /* MDIO bus init */
2344 error = ravb_mdio_init(priv);
2345 if (error) {
2346 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2347 goto out_dma_free;
2348 }
2349
2350 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2351 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2352
2353 /* Network device register */
2354 error = register_netdev(ndev);
2355 if (error)
2356 goto out_napi_del;
2357
2358 device_set_wakeup_capable(&pdev->dev, 1);
2359
2360 /* Print device information */
2361 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2362 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2363
2364 platform_set_drvdata(pdev, ndev);
2365
2366 return 0;
2367
2368 out_napi_del:
2369 netif_napi_del(&priv->napi[RAVB_NC]);
2370 netif_napi_del(&priv->napi[RAVB_BE]);
2371 ravb_mdio_release(priv);
2372 out_dma_free:
2373 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2374 priv->desc_bat_dma);
2375
2376 /* Stop PTP Clock driver */
2377 if (info->ccc_gac)
2378 ravb_ptp_stop(ndev);
2379 out_disable_refclk:
2380 clk_disable_unprepare(priv->refclk);
2381 out_release:
2382 pm_runtime_put(&pdev->dev);
2383 out_rpm_disable:
2384 pm_runtime_disable(&pdev->dev);
2385 reset_control_assert(rstc);
2386 out_free_netdev:
2387 free_netdev(ndev);
2388 return error;
2389 }
2390
ravb_remove(struct platform_device * pdev)2391 static int ravb_remove(struct platform_device *pdev)
2392 {
2393 struct net_device *ndev = platform_get_drvdata(pdev);
2394 struct ravb_private *priv = netdev_priv(ndev);
2395 const struct ravb_hw_info *info = priv->info;
2396
2397 /* Stop PTP Clock driver */
2398 if (info->ccc_gac)
2399 ravb_ptp_stop(ndev);
2400
2401 clk_disable_unprepare(priv->refclk);
2402
2403 /* Set reset mode */
2404 ravb_write(ndev, CCC_OPC_RESET, CCC);
2405 unregister_netdev(ndev);
2406 netif_napi_del(&priv->napi[RAVB_NC]);
2407 netif_napi_del(&priv->napi[RAVB_BE]);
2408 ravb_mdio_release(priv);
2409 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2410 priv->desc_bat_dma);
2411 pm_runtime_put_sync(&pdev->dev);
2412 pm_runtime_disable(&pdev->dev);
2413 reset_control_assert(priv->rstc);
2414 free_netdev(ndev);
2415 platform_set_drvdata(pdev, NULL);
2416
2417 return 0;
2418 }
2419
ravb_wol_setup(struct net_device * ndev)2420 static int ravb_wol_setup(struct net_device *ndev)
2421 {
2422 struct ravb_private *priv = netdev_priv(ndev);
2423
2424 /* Disable interrupts by clearing the interrupt masks. */
2425 ravb_write(ndev, 0, RIC0);
2426 ravb_write(ndev, 0, RIC2);
2427 ravb_write(ndev, 0, TIC);
2428
2429 /* Only allow ECI interrupts */
2430 synchronize_irq(priv->emac_irq);
2431 napi_disable(&priv->napi[RAVB_NC]);
2432 napi_disable(&priv->napi[RAVB_BE]);
2433 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2434
2435 /* Enable MagicPacket */
2436 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2437
2438 return enable_irq_wake(priv->emac_irq);
2439 }
2440
ravb_wol_restore(struct net_device * ndev)2441 static int ravb_wol_restore(struct net_device *ndev)
2442 {
2443 struct ravb_private *priv = netdev_priv(ndev);
2444 int ret;
2445
2446 napi_enable(&priv->napi[RAVB_NC]);
2447 napi_enable(&priv->napi[RAVB_BE]);
2448
2449 /* Disable MagicPacket */
2450 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2451
2452 ret = ravb_close(ndev);
2453 if (ret < 0)
2454 return ret;
2455
2456 return disable_irq_wake(priv->emac_irq);
2457 }
2458
ravb_suspend(struct device * dev)2459 static int __maybe_unused ravb_suspend(struct device *dev)
2460 {
2461 struct net_device *ndev = dev_get_drvdata(dev);
2462 struct ravb_private *priv = netdev_priv(ndev);
2463 int ret;
2464
2465 if (!netif_running(ndev))
2466 return 0;
2467
2468 netif_device_detach(ndev);
2469
2470 if (priv->wol_enabled)
2471 ret = ravb_wol_setup(ndev);
2472 else
2473 ret = ravb_close(ndev);
2474
2475 if (priv->info->ccc_gac)
2476 ravb_ptp_stop(ndev);
2477
2478 return ret;
2479 }
2480
ravb_resume(struct device * dev)2481 static int __maybe_unused ravb_resume(struct device *dev)
2482 {
2483 struct net_device *ndev = dev_get_drvdata(dev);
2484 struct ravb_private *priv = netdev_priv(ndev);
2485 const struct ravb_hw_info *info = priv->info;
2486 int ret = 0;
2487
2488 /* If WoL is enabled set reset mode to rearm the WoL logic */
2489 if (priv->wol_enabled)
2490 ravb_write(ndev, CCC_OPC_RESET, CCC);
2491
2492 /* All register have been reset to default values.
2493 * Restore all registers which where setup at probe time and
2494 * reopen device if it was running before system suspended.
2495 */
2496
2497 /* Set AVB config mode */
2498 ravb_set_config_mode(ndev);
2499
2500 /* Set GTI value */
2501 ret = ravb_set_gti(ndev);
2502 if (ret)
2503 return ret;
2504
2505 /* Request GTI loading */
2506 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2507
2508 if (info->internal_delay)
2509 ravb_set_delay_mode(ndev);
2510
2511 /* Restore descriptor base address table */
2512 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2513
2514 if (priv->info->ccc_gac)
2515 ravb_ptp_init(ndev, priv->pdev);
2516
2517 if (netif_running(ndev)) {
2518 if (priv->wol_enabled) {
2519 ret = ravb_wol_restore(ndev);
2520 if (ret)
2521 return ret;
2522 }
2523 ret = ravb_open(ndev);
2524 if (ret < 0)
2525 return ret;
2526 ravb_set_rx_mode(ndev);
2527 netif_device_attach(ndev);
2528 }
2529
2530 return ret;
2531 }
2532
ravb_runtime_nop(struct device * dev)2533 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2534 {
2535 /* Runtime PM callback shared between ->runtime_suspend()
2536 * and ->runtime_resume(). Simply returns success.
2537 *
2538 * This driver re-initializes all registers after
2539 * pm_runtime_get_sync() anyway so there is no need
2540 * to save and restore registers here.
2541 */
2542 return 0;
2543 }
2544
2545 static const struct dev_pm_ops ravb_dev_pm_ops = {
2546 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2547 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2548 };
2549
2550 static struct platform_driver ravb_driver = {
2551 .probe = ravb_probe,
2552 .remove = ravb_remove,
2553 .driver = {
2554 .name = "ravb",
2555 .pm = &ravb_dev_pm_ops,
2556 .of_match_table = ravb_match_table,
2557 },
2558 };
2559
2560 module_platform_driver(ravb_driver);
2561
2562 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2563 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2564 MODULE_LICENSE("GPL v2");
2565