1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Xilinx Axi Ethernet device driver
4 *
5 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
9 * Copyright (c) 2010 - 2011 PetaLogix
10 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
11 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
12 *
13 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
14 * and Spartan6.
15 *
16 * TODO:
17 * - Add Axi Fifo support.
18 * - Factor out Axi DMA code into separate driver.
19 * - Test and fix basic multicast filtering.
20 * - Add support for extended multicast filtering.
21 * - Test basic VLAN support.
22 * - Add support for extended VLAN support.
23 */
24
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/etherdevice.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_address.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/phy.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40
41 #include "xilinx_axienet.h"
42
43 /* Descriptors defines for Tx and Rx DMA */
44 #define TX_BD_NUM_DEFAULT 128
45 #define RX_BD_NUM_DEFAULT 1024
46 #define TX_BD_NUM_MIN (MAX_SKB_FRAGS + 1)
47 #define TX_BD_NUM_MAX 4096
48 #define RX_BD_NUM_MAX 4096
49
50 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */
51 #define DRIVER_NAME "xaxienet"
52 #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
53 #define DRIVER_VERSION "1.00a"
54
55 #define AXIENET_REGS_N 40
56
57 /* Match table for of_platform binding */
58 static const struct of_device_id axienet_of_match[] = {
59 { .compatible = "xlnx,axi-ethernet-1.00.a", },
60 { .compatible = "xlnx,axi-ethernet-1.01.a", },
61 { .compatible = "xlnx,axi-ethernet-2.01.a", },
62 {},
63 };
64
65 MODULE_DEVICE_TABLE(of, axienet_of_match);
66
67 /* Option table for setting up Axi Ethernet hardware options */
68 static struct axienet_option axienet_options[] = {
69 /* Turn on jumbo packet support for both Rx and Tx */
70 {
71 .opt = XAE_OPTION_JUMBO,
72 .reg = XAE_TC_OFFSET,
73 .m_or = XAE_TC_JUM_MASK,
74 }, {
75 .opt = XAE_OPTION_JUMBO,
76 .reg = XAE_RCW1_OFFSET,
77 .m_or = XAE_RCW1_JUM_MASK,
78 }, { /* Turn on VLAN packet support for both Rx and Tx */
79 .opt = XAE_OPTION_VLAN,
80 .reg = XAE_TC_OFFSET,
81 .m_or = XAE_TC_VLAN_MASK,
82 }, {
83 .opt = XAE_OPTION_VLAN,
84 .reg = XAE_RCW1_OFFSET,
85 .m_or = XAE_RCW1_VLAN_MASK,
86 }, { /* Turn on FCS stripping on receive packets */
87 .opt = XAE_OPTION_FCS_STRIP,
88 .reg = XAE_RCW1_OFFSET,
89 .m_or = XAE_RCW1_FCS_MASK,
90 }, { /* Turn on FCS insertion on transmit packets */
91 .opt = XAE_OPTION_FCS_INSERT,
92 .reg = XAE_TC_OFFSET,
93 .m_or = XAE_TC_FCS_MASK,
94 }, { /* Turn off length/type field checking on receive packets */
95 .opt = XAE_OPTION_LENTYPE_ERR,
96 .reg = XAE_RCW1_OFFSET,
97 .m_or = XAE_RCW1_LT_DIS_MASK,
98 }, { /* Turn on Rx flow control */
99 .opt = XAE_OPTION_FLOW_CONTROL,
100 .reg = XAE_FCC_OFFSET,
101 .m_or = XAE_FCC_FCRX_MASK,
102 }, { /* Turn on Tx flow control */
103 .opt = XAE_OPTION_FLOW_CONTROL,
104 .reg = XAE_FCC_OFFSET,
105 .m_or = XAE_FCC_FCTX_MASK,
106 }, { /* Turn on promiscuous frame filtering */
107 .opt = XAE_OPTION_PROMISC,
108 .reg = XAE_FMI_OFFSET,
109 .m_or = XAE_FMI_PM_MASK,
110 }, { /* Enable transmitter */
111 .opt = XAE_OPTION_TXEN,
112 .reg = XAE_TC_OFFSET,
113 .m_or = XAE_TC_TX_MASK,
114 }, { /* Enable receiver */
115 .opt = XAE_OPTION_RXEN,
116 .reg = XAE_RCW1_OFFSET,
117 .m_or = XAE_RCW1_RX_MASK,
118 },
119 {}
120 };
121
122 /**
123 * axienet_dma_in32 - Memory mapped Axi DMA register read
124 * @lp: Pointer to axienet local structure
125 * @reg: Address offset from the base address of the Axi DMA core
126 *
127 * Return: The contents of the Axi DMA register
128 *
129 * This function returns the contents of the corresponding Axi DMA register.
130 */
axienet_dma_in32(struct axienet_local * lp,off_t reg)131 static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
132 {
133 return ioread32(lp->dma_regs + reg);
134 }
135
136 /**
137 * axienet_dma_out32 - Memory mapped Axi DMA register write.
138 * @lp: Pointer to axienet local structure
139 * @reg: Address offset from the base address of the Axi DMA core
140 * @value: Value to be written into the Axi DMA register
141 *
142 * This function writes the desired value into the corresponding Axi DMA
143 * register.
144 */
axienet_dma_out32(struct axienet_local * lp,off_t reg,u32 value)145 static inline void axienet_dma_out32(struct axienet_local *lp,
146 off_t reg, u32 value)
147 {
148 iowrite32(value, lp->dma_regs + reg);
149 }
150
axienet_dma_out_addr(struct axienet_local * lp,off_t reg,dma_addr_t addr)151 static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
152 dma_addr_t addr)
153 {
154 axienet_dma_out32(lp, reg, lower_32_bits(addr));
155
156 if (lp->features & XAE_FEATURE_DMA_64BIT)
157 axienet_dma_out32(lp, reg + 4, upper_32_bits(addr));
158 }
159
desc_set_phys_addr(struct axienet_local * lp,dma_addr_t addr,struct axidma_bd * desc)160 static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr,
161 struct axidma_bd *desc)
162 {
163 desc->phys = lower_32_bits(addr);
164 if (lp->features & XAE_FEATURE_DMA_64BIT)
165 desc->phys_msb = upper_32_bits(addr);
166 }
167
desc_get_phys_addr(struct axienet_local * lp,struct axidma_bd * desc)168 static dma_addr_t desc_get_phys_addr(struct axienet_local *lp,
169 struct axidma_bd *desc)
170 {
171 dma_addr_t ret = desc->phys;
172
173 if (lp->features & XAE_FEATURE_DMA_64BIT)
174 ret |= ((dma_addr_t)desc->phys_msb << 16) << 16;
175
176 return ret;
177 }
178
179 /**
180 * axienet_dma_bd_release - Release buffer descriptor rings
181 * @ndev: Pointer to the net_device structure
182 *
183 * This function is used to release the descriptors allocated in
184 * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
185 * driver stop api is called.
186 */
axienet_dma_bd_release(struct net_device * ndev)187 static void axienet_dma_bd_release(struct net_device *ndev)
188 {
189 int i;
190 struct axienet_local *lp = netdev_priv(ndev);
191
192 /* If we end up here, tx_bd_v must have been DMA allocated. */
193 dma_free_coherent(ndev->dev.parent,
194 sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
195 lp->tx_bd_v,
196 lp->tx_bd_p);
197
198 if (!lp->rx_bd_v)
199 return;
200
201 for (i = 0; i < lp->rx_bd_num; i++) {
202 dma_addr_t phys;
203
204 /* A NULL skb means this descriptor has not been initialised
205 * at all.
206 */
207 if (!lp->rx_bd_v[i].skb)
208 break;
209
210 dev_kfree_skb(lp->rx_bd_v[i].skb);
211
212 /* For each descriptor, we programmed cntrl with the (non-zero)
213 * descriptor size, after it had been successfully allocated.
214 * So a non-zero value in there means we need to unmap it.
215 */
216 if (lp->rx_bd_v[i].cntrl) {
217 phys = desc_get_phys_addr(lp, &lp->rx_bd_v[i]);
218 dma_unmap_single(ndev->dev.parent, phys,
219 lp->max_frm_size, DMA_FROM_DEVICE);
220 }
221 }
222
223 dma_free_coherent(ndev->dev.parent,
224 sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
225 lp->rx_bd_v,
226 lp->rx_bd_p);
227 }
228
229 /**
230 * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
231 * @ndev: Pointer to the net_device structure
232 *
233 * Return: 0, on success -ENOMEM, on failure
234 *
235 * This function is called to initialize the Rx and Tx DMA descriptor
236 * rings. This initializes the descriptors with required default values
237 * and is called when Axi Ethernet driver reset is called.
238 */
axienet_dma_bd_init(struct net_device * ndev)239 static int axienet_dma_bd_init(struct net_device *ndev)
240 {
241 u32 cr;
242 int i;
243 struct sk_buff *skb;
244 struct axienet_local *lp = netdev_priv(ndev);
245
246 /* Reset the indexes which are used for accessing the BDs */
247 lp->tx_bd_ci = 0;
248 lp->tx_bd_tail = 0;
249 lp->rx_bd_ci = 0;
250
251 /* Allocate the Tx and Rx buffer descriptors. */
252 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
253 sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
254 &lp->tx_bd_p, GFP_KERNEL);
255 if (!lp->tx_bd_v)
256 return -ENOMEM;
257
258 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
259 sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
260 &lp->rx_bd_p, GFP_KERNEL);
261 if (!lp->rx_bd_v)
262 goto out;
263
264 for (i = 0; i < lp->tx_bd_num; i++) {
265 dma_addr_t addr = lp->tx_bd_p +
266 sizeof(*lp->tx_bd_v) *
267 ((i + 1) % lp->tx_bd_num);
268
269 lp->tx_bd_v[i].next = lower_32_bits(addr);
270 if (lp->features & XAE_FEATURE_DMA_64BIT)
271 lp->tx_bd_v[i].next_msb = upper_32_bits(addr);
272 }
273
274 for (i = 0; i < lp->rx_bd_num; i++) {
275 dma_addr_t addr;
276
277 addr = lp->rx_bd_p + sizeof(*lp->rx_bd_v) *
278 ((i + 1) % lp->rx_bd_num);
279 lp->rx_bd_v[i].next = lower_32_bits(addr);
280 if (lp->features & XAE_FEATURE_DMA_64BIT)
281 lp->rx_bd_v[i].next_msb = upper_32_bits(addr);
282
283 skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
284 if (!skb)
285 goto out;
286
287 lp->rx_bd_v[i].skb = skb;
288 addr = dma_map_single(ndev->dev.parent, skb->data,
289 lp->max_frm_size, DMA_FROM_DEVICE);
290 if (dma_mapping_error(ndev->dev.parent, addr)) {
291 netdev_err(ndev, "DMA mapping error\n");
292 goto out;
293 }
294 desc_set_phys_addr(lp, addr, &lp->rx_bd_v[i]);
295
296 lp->rx_bd_v[i].cntrl = lp->max_frm_size;
297 }
298
299 /* Start updating the Rx channel control register */
300 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
301 /* Update the interrupt coalesce count */
302 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
303 ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
304 /* Update the delay timer count */
305 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
306 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
307 /* Enable coalesce, delay timer and error interrupts */
308 cr |= XAXIDMA_IRQ_ALL_MASK;
309 /* Write to the Rx channel control register */
310 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
311
312 /* Start updating the Tx channel control register */
313 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
314 /* Update the interrupt coalesce count */
315 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
316 ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
317 /* Update the delay timer count */
318 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
319 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
320 /* Enable coalesce, delay timer and error interrupts */
321 cr |= XAXIDMA_IRQ_ALL_MASK;
322 /* Write to the Tx channel control register */
323 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
324
325 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
326 * halted state. This will make the Rx side ready for reception.
327 */
328 axienet_dma_out_addr(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
329 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
330 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
331 cr | XAXIDMA_CR_RUNSTOP_MASK);
332 axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
333 (sizeof(*lp->rx_bd_v) * (lp->rx_bd_num - 1)));
334
335 /* Write to the RS (Run-stop) bit in the Tx channel control register.
336 * Tx channel is now ready to run. But only after we write to the
337 * tail pointer register that the Tx channel will start transmitting.
338 */
339 axienet_dma_out_addr(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
340 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
341 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
342 cr | XAXIDMA_CR_RUNSTOP_MASK);
343
344 return 0;
345 out:
346 axienet_dma_bd_release(ndev);
347 return -ENOMEM;
348 }
349
350 /**
351 * axienet_set_mac_address - Write the MAC address
352 * @ndev: Pointer to the net_device structure
353 * @address: 6 byte Address to be written as MAC address
354 *
355 * This function is called to initialize the MAC address of the Axi Ethernet
356 * core. It writes to the UAW0 and UAW1 registers of the core.
357 */
axienet_set_mac_address(struct net_device * ndev,const void * address)358 static void axienet_set_mac_address(struct net_device *ndev,
359 const void *address)
360 {
361 struct axienet_local *lp = netdev_priv(ndev);
362
363 if (address)
364 memcpy(ndev->dev_addr, address, ETH_ALEN);
365 if (!is_valid_ether_addr(ndev->dev_addr))
366 eth_hw_addr_random(ndev);
367
368 /* Set up unicast MAC address filter set its mac address */
369 axienet_iow(lp, XAE_UAW0_OFFSET,
370 (ndev->dev_addr[0]) |
371 (ndev->dev_addr[1] << 8) |
372 (ndev->dev_addr[2] << 16) |
373 (ndev->dev_addr[3] << 24));
374 axienet_iow(lp, XAE_UAW1_OFFSET,
375 (((axienet_ior(lp, XAE_UAW1_OFFSET)) &
376 ~XAE_UAW1_UNICASTADDR_MASK) |
377 (ndev->dev_addr[4] |
378 (ndev->dev_addr[5] << 8))));
379 }
380
381 /**
382 * netdev_set_mac_address - Write the MAC address (from outside the driver)
383 * @ndev: Pointer to the net_device structure
384 * @p: 6 byte Address to be written as MAC address
385 *
386 * Return: 0 for all conditions. Presently, there is no failure case.
387 *
388 * This function is called to initialize the MAC address of the Axi Ethernet
389 * core. It calls the core specific axienet_set_mac_address. This is the
390 * function that goes into net_device_ops structure entry ndo_set_mac_address.
391 */
netdev_set_mac_address(struct net_device * ndev,void * p)392 static int netdev_set_mac_address(struct net_device *ndev, void *p)
393 {
394 struct sockaddr *addr = p;
395 axienet_set_mac_address(ndev, addr->sa_data);
396 return 0;
397 }
398
399 /**
400 * axienet_set_multicast_list - Prepare the multicast table
401 * @ndev: Pointer to the net_device structure
402 *
403 * This function is called to initialize the multicast table during
404 * initialization. The Axi Ethernet basic multicast support has a four-entry
405 * multicast table which is initialized here. Additionally this function
406 * goes into the net_device_ops structure entry ndo_set_multicast_list. This
407 * means whenever the multicast table entries need to be updated this
408 * function gets called.
409 */
axienet_set_multicast_list(struct net_device * ndev)410 static void axienet_set_multicast_list(struct net_device *ndev)
411 {
412 int i;
413 u32 reg, af0reg, af1reg;
414 struct axienet_local *lp = netdev_priv(ndev);
415
416 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
417 netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
418 /* We must make the kernel realize we had to move into
419 * promiscuous mode. If it was a promiscuous mode request
420 * the flag is already set. If not we set it.
421 */
422 ndev->flags |= IFF_PROMISC;
423 reg = axienet_ior(lp, XAE_FMI_OFFSET);
424 reg |= XAE_FMI_PM_MASK;
425 axienet_iow(lp, XAE_FMI_OFFSET, reg);
426 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
427 } else if (!netdev_mc_empty(ndev)) {
428 struct netdev_hw_addr *ha;
429
430 i = 0;
431 netdev_for_each_mc_addr(ha, ndev) {
432 if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
433 break;
434
435 af0reg = (ha->addr[0]);
436 af0reg |= (ha->addr[1] << 8);
437 af0reg |= (ha->addr[2] << 16);
438 af0reg |= (ha->addr[3] << 24);
439
440 af1reg = (ha->addr[4]);
441 af1reg |= (ha->addr[5] << 8);
442
443 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
444 reg |= i;
445
446 axienet_iow(lp, XAE_FMI_OFFSET, reg);
447 axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
448 axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
449 i++;
450 }
451 } else {
452 reg = axienet_ior(lp, XAE_FMI_OFFSET);
453 reg &= ~XAE_FMI_PM_MASK;
454
455 axienet_iow(lp, XAE_FMI_OFFSET, reg);
456
457 for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
458 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
459 reg |= i;
460
461 axienet_iow(lp, XAE_FMI_OFFSET, reg);
462 axienet_iow(lp, XAE_AF0_OFFSET, 0);
463 axienet_iow(lp, XAE_AF1_OFFSET, 0);
464 }
465
466 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
467 }
468 }
469
470 /**
471 * axienet_setoptions - Set an Axi Ethernet option
472 * @ndev: Pointer to the net_device structure
473 * @options: Option to be enabled/disabled
474 *
475 * The Axi Ethernet core has multiple features which can be selectively turned
476 * on or off. The typical options could be jumbo frame option, basic VLAN
477 * option, promiscuous mode option etc. This function is used to set or clear
478 * these options in the Axi Ethernet hardware. This is done through
479 * axienet_option structure .
480 */
axienet_setoptions(struct net_device * ndev,u32 options)481 static void axienet_setoptions(struct net_device *ndev, u32 options)
482 {
483 int reg;
484 struct axienet_local *lp = netdev_priv(ndev);
485 struct axienet_option *tp = &axienet_options[0];
486
487 while (tp->opt) {
488 reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
489 if (options & tp->opt)
490 reg |= tp->m_or;
491 axienet_iow(lp, tp->reg, reg);
492 tp++;
493 }
494
495 lp->options |= options;
496 }
497
__axienet_device_reset(struct axienet_local * lp)498 static int __axienet_device_reset(struct axienet_local *lp)
499 {
500 u32 value;
501 int ret;
502
503 /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
504 * process of Axi DMA takes a while to complete as all pending
505 * commands/transfers will be flushed or completed during this
506 * reset process.
507 * Note that even though both TX and RX have their own reset register,
508 * they both reset the entire DMA core, so only one needs to be used.
509 */
510 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK);
511 ret = read_poll_timeout(axienet_dma_in32, value,
512 !(value & XAXIDMA_CR_RESET_MASK),
513 DELAY_OF_ONE_MILLISEC, 50000, false, lp,
514 XAXIDMA_TX_CR_OFFSET);
515 if (ret) {
516 dev_err(lp->dev, "%s: DMA reset timeout!\n", __func__);
517 return ret;
518 }
519
520 /* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */
521 ret = read_poll_timeout(axienet_ior, value,
522 value & XAE_INT_PHYRSTCMPLT_MASK,
523 DELAY_OF_ONE_MILLISEC, 50000, false, lp,
524 XAE_IS_OFFSET);
525 if (ret) {
526 dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", __func__);
527 return ret;
528 }
529
530 return 0;
531 }
532
533 /**
534 * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
535 * @ndev: Pointer to the net_device structure
536 *
537 * This function is called to reset and initialize the Axi Ethernet core. This
538 * is typically called during initialization. It does a reset of the Axi DMA
539 * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
540 * areconnected to Axi Ethernet reset lines, this in turn resets the Axi
541 * Ethernet core. No separate hardware reset is done for the Axi Ethernet
542 * core.
543 * Returns 0 on success or a negative error number otherwise.
544 */
axienet_device_reset(struct net_device * ndev)545 static int axienet_device_reset(struct net_device *ndev)
546 {
547 u32 axienet_status;
548 struct axienet_local *lp = netdev_priv(ndev);
549 int ret;
550
551 ret = __axienet_device_reset(lp);
552 if (ret)
553 return ret;
554
555 lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
556 lp->options |= XAE_OPTION_VLAN;
557 lp->options &= (~XAE_OPTION_JUMBO);
558
559 if ((ndev->mtu > XAE_MTU) &&
560 (ndev->mtu <= XAE_JUMBO_MTU)) {
561 lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN +
562 XAE_TRL_SIZE;
563
564 if (lp->max_frm_size <= lp->rxmem)
565 lp->options |= XAE_OPTION_JUMBO;
566 }
567
568 ret = axienet_dma_bd_init(ndev);
569 if (ret) {
570 netdev_err(ndev, "%s: descriptor allocation failed\n",
571 __func__);
572 return ret;
573 }
574
575 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
576 axienet_status &= ~XAE_RCW1_RX_MASK;
577 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
578
579 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
580 if (axienet_status & XAE_INT_RXRJECT_MASK)
581 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
582 axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ?
583 XAE_INT_RECV_ERROR_MASK : 0);
584
585 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
586
587 /* Sync default options with HW but leave receiver and
588 * transmitter disabled.
589 */
590 axienet_setoptions(ndev, lp->options &
591 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
592 axienet_set_mac_address(ndev, NULL);
593 axienet_set_multicast_list(ndev);
594 axienet_setoptions(ndev, lp->options);
595
596 netif_trans_update(ndev);
597
598 return 0;
599 }
600
601 /**
602 * axienet_free_tx_chain - Clean up a series of linked TX descriptors.
603 * @ndev: Pointer to the net_device structure
604 * @first_bd: Index of first descriptor to clean up
605 * @nr_bds: Number of descriptors to clean up, can be -1 if unknown.
606 * @sizep: Pointer to a u32 filled with the total sum of all bytes
607 * in all cleaned-up descriptors. Ignored if NULL.
608 *
609 * Would either be called after a successful transmit operation, or after
610 * there was an error when setting up the chain.
611 * Returns the number of descriptors handled.
612 */
axienet_free_tx_chain(struct net_device * ndev,u32 first_bd,int nr_bds,u32 * sizep)613 static int axienet_free_tx_chain(struct net_device *ndev, u32 first_bd,
614 int nr_bds, u32 *sizep)
615 {
616 struct axienet_local *lp = netdev_priv(ndev);
617 struct axidma_bd *cur_p;
618 int max_bds = nr_bds;
619 unsigned int status;
620 dma_addr_t phys;
621 int i;
622
623 if (max_bds == -1)
624 max_bds = lp->tx_bd_num;
625
626 for (i = 0; i < max_bds; i++) {
627 cur_p = &lp->tx_bd_v[(first_bd + i) % lp->tx_bd_num];
628 status = cur_p->status;
629
630 /* If no number is given, clean up *all* descriptors that have
631 * been completed by the MAC.
632 */
633 if (nr_bds == -1 && !(status & XAXIDMA_BD_STS_COMPLETE_MASK))
634 break;
635
636 /* Ensure we see complete descriptor update */
637 dma_rmb();
638 phys = desc_get_phys_addr(lp, cur_p);
639 dma_unmap_single(ndev->dev.parent, phys,
640 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
641 DMA_TO_DEVICE);
642
643 if (cur_p->skb && (status & XAXIDMA_BD_STS_COMPLETE_MASK))
644 dev_consume_skb_irq(cur_p->skb);
645
646 cur_p->app0 = 0;
647 cur_p->app1 = 0;
648 cur_p->app2 = 0;
649 cur_p->app4 = 0;
650 cur_p->skb = NULL;
651 /* ensure our transmit path and device don't prematurely see status cleared */
652 wmb();
653 cur_p->cntrl = 0;
654 cur_p->status = 0;
655
656 if (sizep)
657 *sizep += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
658 }
659
660 return i;
661 }
662
663 /**
664 * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
665 * @lp: Pointer to the axienet_local structure
666 * @num_frag: The number of BDs to check for
667 *
668 * Return: 0, on success
669 * NETDEV_TX_BUSY, if any of the descriptors are not free
670 *
671 * This function is invoked before BDs are allocated and transmission starts.
672 * This function returns 0 if a BD or group of BDs can be allocated for
673 * transmission. If the BD or any of the BDs are not free the function
674 * returns a busy status. This is invoked from axienet_start_xmit.
675 */
axienet_check_tx_bd_space(struct axienet_local * lp,int num_frag)676 static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
677 int num_frag)
678 {
679 struct axidma_bd *cur_p;
680
681 /* Ensure we see all descriptor updates from device or TX IRQ path */
682 rmb();
683 cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % lp->tx_bd_num];
684 if (cur_p->cntrl)
685 return NETDEV_TX_BUSY;
686 return 0;
687 }
688
689 /**
690 * axienet_start_xmit_done - Invoked once a transmit is completed by the
691 * Axi DMA Tx channel.
692 * @ndev: Pointer to the net_device structure
693 *
694 * This function is invoked from the Axi DMA Tx isr to notify the completion
695 * of transmit operation. It clears fields in the corresponding Tx BDs and
696 * unmaps the corresponding buffer so that CPU can regain ownership of the
697 * buffer. It finally invokes "netif_wake_queue" to restart transmission if
698 * required.
699 */
axienet_start_xmit_done(struct net_device * ndev)700 static void axienet_start_xmit_done(struct net_device *ndev)
701 {
702 struct axienet_local *lp = netdev_priv(ndev);
703 u32 packets = 0;
704 u32 size = 0;
705
706 packets = axienet_free_tx_chain(ndev, lp->tx_bd_ci, -1, &size);
707
708 lp->tx_bd_ci += packets;
709 if (lp->tx_bd_ci >= lp->tx_bd_num)
710 lp->tx_bd_ci -= lp->tx_bd_num;
711
712 ndev->stats.tx_packets += packets;
713 ndev->stats.tx_bytes += size;
714
715 /* Matches barrier in axienet_start_xmit */
716 smp_mb();
717
718 if (!axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1))
719 netif_wake_queue(ndev);
720 }
721
722 /**
723 * axienet_start_xmit - Starts the transmission.
724 * @skb: sk_buff pointer that contains data to be Txed.
725 * @ndev: Pointer to net_device structure.
726 *
727 * Return: NETDEV_TX_OK, on success
728 * NETDEV_TX_BUSY, if any of the descriptors are not free
729 *
730 * This function is invoked from upper layers to initiate transmission. The
731 * function uses the next available free BDs and populates their fields to
732 * start the transmission. Additionally if checksum offloading is supported,
733 * it populates AXI Stream Control fields with appropriate values.
734 */
735 static netdev_tx_t
axienet_start_xmit(struct sk_buff * skb,struct net_device * ndev)736 axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
737 {
738 u32 ii;
739 u32 num_frag;
740 u32 csum_start_off;
741 u32 csum_index_off;
742 skb_frag_t *frag;
743 dma_addr_t tail_p, phys;
744 struct axienet_local *lp = netdev_priv(ndev);
745 struct axidma_bd *cur_p;
746 u32 orig_tail_ptr = lp->tx_bd_tail;
747
748 num_frag = skb_shinfo(skb)->nr_frags;
749 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
750
751 if (axienet_check_tx_bd_space(lp, num_frag + 1)) {
752 /* Should not happen as last start_xmit call should have
753 * checked for sufficient space and queue should only be
754 * woken when sufficient space is available.
755 */
756 netif_stop_queue(ndev);
757 if (net_ratelimit())
758 netdev_warn(ndev, "TX ring unexpectedly full\n");
759 return NETDEV_TX_BUSY;
760 }
761
762 if (skb->ip_summed == CHECKSUM_PARTIAL) {
763 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
764 /* Tx Full Checksum Offload Enabled */
765 cur_p->app0 |= 2;
766 } else if (lp->features & XAE_FEATURE_PARTIAL_TX_CSUM) {
767 csum_start_off = skb_transport_offset(skb);
768 csum_index_off = csum_start_off + skb->csum_offset;
769 /* Tx Partial Checksum Offload Enabled */
770 cur_p->app0 |= 1;
771 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
772 }
773 } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
774 cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
775 }
776
777 phys = dma_map_single(ndev->dev.parent, skb->data,
778 skb_headlen(skb), DMA_TO_DEVICE);
779 if (unlikely(dma_mapping_error(ndev->dev.parent, phys))) {
780 if (net_ratelimit())
781 netdev_err(ndev, "TX DMA mapping error\n");
782 ndev->stats.tx_dropped++;
783 return NETDEV_TX_OK;
784 }
785 desc_set_phys_addr(lp, phys, cur_p);
786 cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
787
788 for (ii = 0; ii < num_frag; ii++) {
789 if (++lp->tx_bd_tail >= lp->tx_bd_num)
790 lp->tx_bd_tail = 0;
791 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
792 frag = &skb_shinfo(skb)->frags[ii];
793 phys = dma_map_single(ndev->dev.parent,
794 skb_frag_address(frag),
795 skb_frag_size(frag),
796 DMA_TO_DEVICE);
797 if (unlikely(dma_mapping_error(ndev->dev.parent, phys))) {
798 if (net_ratelimit())
799 netdev_err(ndev, "TX DMA mapping error\n");
800 ndev->stats.tx_dropped++;
801 axienet_free_tx_chain(ndev, orig_tail_ptr, ii + 1,
802 NULL);
803 lp->tx_bd_tail = orig_tail_ptr;
804
805 return NETDEV_TX_OK;
806 }
807 desc_set_phys_addr(lp, phys, cur_p);
808 cur_p->cntrl = skb_frag_size(frag);
809 }
810
811 cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
812 cur_p->skb = skb;
813
814 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
815 /* Start the transfer */
816 axienet_dma_out_addr(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
817 if (++lp->tx_bd_tail >= lp->tx_bd_num)
818 lp->tx_bd_tail = 0;
819
820 /* Stop queue if next transmit may not have space */
821 if (axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1)) {
822 netif_stop_queue(ndev);
823
824 /* Matches barrier in axienet_start_xmit_done */
825 smp_mb();
826
827 /* Space might have just been freed - check again */
828 if (!axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1))
829 netif_wake_queue(ndev);
830 }
831
832 return NETDEV_TX_OK;
833 }
834
835 /**
836 * axienet_recv - Is called from Axi DMA Rx Isr to complete the received
837 * BD processing.
838 * @ndev: Pointer to net_device structure.
839 *
840 * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
841 * does minimal processing and invokes "netif_rx" to complete further
842 * processing.
843 */
axienet_recv(struct net_device * ndev)844 static void axienet_recv(struct net_device *ndev)
845 {
846 u32 length;
847 u32 csumstatus;
848 u32 size = 0;
849 u32 packets = 0;
850 dma_addr_t tail_p = 0;
851 struct axienet_local *lp = netdev_priv(ndev);
852 struct sk_buff *skb, *new_skb;
853 struct axidma_bd *cur_p;
854
855 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
856
857 while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
858 dma_addr_t phys;
859
860 /* Ensure we see complete descriptor update */
861 dma_rmb();
862
863 skb = cur_p->skb;
864 cur_p->skb = NULL;
865
866 /* skb could be NULL if a previous pass already received the
867 * packet for this slot in the ring, but failed to refill it
868 * with a newly allocated buffer. In this case, don't try to
869 * receive it again.
870 */
871 if (likely(skb)) {
872 length = cur_p->app4 & 0x0000FFFF;
873
874 phys = desc_get_phys_addr(lp, cur_p);
875 dma_unmap_single(ndev->dev.parent, phys, lp->max_frm_size,
876 DMA_FROM_DEVICE);
877
878 skb_put(skb, length);
879 skb->protocol = eth_type_trans(skb, ndev);
880 /*skb_checksum_none_assert(skb);*/
881 skb->ip_summed = CHECKSUM_NONE;
882
883 /* if we're doing Rx csum offload, set it up */
884 if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
885 csumstatus = (cur_p->app2 &
886 XAE_FULL_CSUM_STATUS_MASK) >> 3;
887 if (csumstatus == XAE_IP_TCP_CSUM_VALIDATED ||
888 csumstatus == XAE_IP_UDP_CSUM_VALIDATED) {
889 skb->ip_summed = CHECKSUM_UNNECESSARY;
890 }
891 } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
892 skb->protocol == htons(ETH_P_IP) &&
893 skb->len > 64) {
894 skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
895 skb->ip_summed = CHECKSUM_COMPLETE;
896 }
897
898 netif_rx(skb);
899
900 size += length;
901 packets++;
902 }
903
904 new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
905 if (!new_skb)
906 break;
907
908 phys = dma_map_single(ndev->dev.parent, new_skb->data,
909 lp->max_frm_size,
910 DMA_FROM_DEVICE);
911 if (unlikely(dma_mapping_error(ndev->dev.parent, phys))) {
912 if (net_ratelimit())
913 netdev_err(ndev, "RX DMA mapping error\n");
914 dev_kfree_skb(new_skb);
915 break;
916 }
917 desc_set_phys_addr(lp, phys, cur_p);
918
919 cur_p->cntrl = lp->max_frm_size;
920 cur_p->status = 0;
921 cur_p->skb = new_skb;
922
923 /* Only update tail_p to mark this slot as usable after it has
924 * been successfully refilled.
925 */
926 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
927
928 if (++lp->rx_bd_ci >= lp->rx_bd_num)
929 lp->rx_bd_ci = 0;
930 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
931 }
932
933 ndev->stats.rx_packets += packets;
934 ndev->stats.rx_bytes += size;
935
936 if (tail_p)
937 axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
938 }
939
940 /**
941 * axienet_tx_irq - Tx Done Isr.
942 * @irq: irq number
943 * @_ndev: net_device pointer
944 *
945 * Return: IRQ_HANDLED if device generated a TX interrupt, IRQ_NONE otherwise.
946 *
947 * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
948 * to complete the BD processing.
949 */
axienet_tx_irq(int irq,void * _ndev)950 static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
951 {
952 u32 cr;
953 unsigned int status;
954 struct net_device *ndev = _ndev;
955 struct axienet_local *lp = netdev_priv(ndev);
956
957 status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
958 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
959 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
960 axienet_start_xmit_done(lp->ndev);
961 goto out;
962 }
963 if (!(status & XAXIDMA_IRQ_ALL_MASK))
964 return IRQ_NONE;
965 if (status & XAXIDMA_IRQ_ERROR_MASK) {
966 dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status);
967 dev_err(&ndev->dev, "Current BD is at: 0x%x%08x\n",
968 (lp->tx_bd_v[lp->tx_bd_ci]).phys_msb,
969 (lp->tx_bd_v[lp->tx_bd_ci]).phys);
970
971 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
972 /* Disable coalesce, delay timer and error interrupts */
973 cr &= (~XAXIDMA_IRQ_ALL_MASK);
974 /* Write to the Tx channel control register */
975 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
976
977 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
978 /* Disable coalesce, delay timer and error interrupts */
979 cr &= (~XAXIDMA_IRQ_ALL_MASK);
980 /* Write to the Rx channel control register */
981 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
982
983 schedule_work(&lp->dma_err_task);
984 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
985 }
986 out:
987 return IRQ_HANDLED;
988 }
989
990 /**
991 * axienet_rx_irq - Rx Isr.
992 * @irq: irq number
993 * @_ndev: net_device pointer
994 *
995 * Return: IRQ_HANDLED if device generated a RX interrupt, IRQ_NONE otherwise.
996 *
997 * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
998 * processing.
999 */
axienet_rx_irq(int irq,void * _ndev)1000 static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
1001 {
1002 u32 cr;
1003 unsigned int status;
1004 struct net_device *ndev = _ndev;
1005 struct axienet_local *lp = netdev_priv(ndev);
1006
1007 status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
1008 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
1009 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
1010 axienet_recv(lp->ndev);
1011 goto out;
1012 }
1013 if (!(status & XAXIDMA_IRQ_ALL_MASK))
1014 return IRQ_NONE;
1015 if (status & XAXIDMA_IRQ_ERROR_MASK) {
1016 dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status);
1017 dev_err(&ndev->dev, "Current BD is at: 0x%x%08x\n",
1018 (lp->rx_bd_v[lp->rx_bd_ci]).phys_msb,
1019 (lp->rx_bd_v[lp->rx_bd_ci]).phys);
1020
1021 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1022 /* Disable coalesce, delay timer and error interrupts */
1023 cr &= (~XAXIDMA_IRQ_ALL_MASK);
1024 /* Finally write to the Tx channel control register */
1025 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1026
1027 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1028 /* Disable coalesce, delay timer and error interrupts */
1029 cr &= (~XAXIDMA_IRQ_ALL_MASK);
1030 /* write to the Rx channel control register */
1031 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1032
1033 schedule_work(&lp->dma_err_task);
1034 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
1035 }
1036 out:
1037 return IRQ_HANDLED;
1038 }
1039
1040 /**
1041 * axienet_eth_irq - Ethernet core Isr.
1042 * @irq: irq number
1043 * @_ndev: net_device pointer
1044 *
1045 * Return: IRQ_HANDLED if device generated a core interrupt, IRQ_NONE otherwise.
1046 *
1047 * Handle miscellaneous conditions indicated by Ethernet core IRQ.
1048 */
axienet_eth_irq(int irq,void * _ndev)1049 static irqreturn_t axienet_eth_irq(int irq, void *_ndev)
1050 {
1051 struct net_device *ndev = _ndev;
1052 struct axienet_local *lp = netdev_priv(ndev);
1053 unsigned int pending;
1054
1055 pending = axienet_ior(lp, XAE_IP_OFFSET);
1056 if (!pending)
1057 return IRQ_NONE;
1058
1059 if (pending & XAE_INT_RXFIFOOVR_MASK)
1060 ndev->stats.rx_missed_errors++;
1061
1062 if (pending & XAE_INT_RXRJECT_MASK)
1063 ndev->stats.rx_frame_errors++;
1064
1065 axienet_iow(lp, XAE_IS_OFFSET, pending);
1066 return IRQ_HANDLED;
1067 }
1068
1069 static void axienet_dma_err_handler(struct work_struct *work);
1070
1071 /**
1072 * axienet_open - Driver open routine.
1073 * @ndev: Pointer to net_device structure
1074 *
1075 * Return: 0, on success.
1076 * non-zero error value on failure
1077 *
1078 * This is the driver open routine. It calls phylink_start to start the
1079 * PHY device.
1080 * It also allocates interrupt service routines, enables the interrupt lines
1081 * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
1082 * descriptors are initialized.
1083 */
axienet_open(struct net_device * ndev)1084 static int axienet_open(struct net_device *ndev)
1085 {
1086 int ret;
1087 struct axienet_local *lp = netdev_priv(ndev);
1088
1089 dev_dbg(&ndev->dev, "axienet_open()\n");
1090
1091 /* When we do an Axi Ethernet reset, it resets the complete core
1092 * including the MDIO. MDIO must be disabled before resetting.
1093 * Hold MDIO bus lock to avoid MDIO accesses during the reset.
1094 */
1095 axienet_lock_mii(lp);
1096 ret = axienet_device_reset(ndev);
1097 axienet_unlock_mii(lp);
1098
1099 ret = phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0);
1100 if (ret) {
1101 dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret);
1102 return ret;
1103 }
1104
1105 phylink_start(lp->phylink);
1106
1107 /* Enable worker thread for Axi DMA error handling */
1108 INIT_WORK(&lp->dma_err_task, axienet_dma_err_handler);
1109
1110 /* Enable interrupts for Axi DMA Tx */
1111 ret = request_irq(lp->tx_irq, axienet_tx_irq, IRQF_SHARED,
1112 ndev->name, ndev);
1113 if (ret)
1114 goto err_tx_irq;
1115 /* Enable interrupts for Axi DMA Rx */
1116 ret = request_irq(lp->rx_irq, axienet_rx_irq, IRQF_SHARED,
1117 ndev->name, ndev);
1118 if (ret)
1119 goto err_rx_irq;
1120 /* Enable interrupts for Axi Ethernet core (if defined) */
1121 if (lp->eth_irq > 0) {
1122 ret = request_irq(lp->eth_irq, axienet_eth_irq, IRQF_SHARED,
1123 ndev->name, ndev);
1124 if (ret)
1125 goto err_eth_irq;
1126 }
1127
1128 return 0;
1129
1130 err_eth_irq:
1131 free_irq(lp->rx_irq, ndev);
1132 err_rx_irq:
1133 free_irq(lp->tx_irq, ndev);
1134 err_tx_irq:
1135 phylink_stop(lp->phylink);
1136 phylink_disconnect_phy(lp->phylink);
1137 cancel_work_sync(&lp->dma_err_task);
1138 dev_err(lp->dev, "request_irq() failed\n");
1139 return ret;
1140 }
1141
1142 /**
1143 * axienet_stop - Driver stop routine.
1144 * @ndev: Pointer to net_device structure
1145 *
1146 * Return: 0, on success.
1147 *
1148 * This is the driver stop routine. It calls phylink_disconnect to stop the PHY
1149 * device. It also removes the interrupt handlers and disables the interrupts.
1150 * The Axi DMA Tx/Rx BDs are released.
1151 */
axienet_stop(struct net_device * ndev)1152 static int axienet_stop(struct net_device *ndev)
1153 {
1154 u32 cr, sr;
1155 int count;
1156 struct axienet_local *lp = netdev_priv(ndev);
1157
1158 dev_dbg(&ndev->dev, "axienet_close()\n");
1159
1160 phylink_stop(lp->phylink);
1161 phylink_disconnect_phy(lp->phylink);
1162
1163 axienet_setoptions(ndev, lp->options &
1164 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1165
1166 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1167 cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK);
1168 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1169
1170 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1171 cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK);
1172 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1173
1174 axienet_iow(lp, XAE_IE_OFFSET, 0);
1175
1176 /* Give DMAs a chance to halt gracefully */
1177 sr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
1178 for (count = 0; !(sr & XAXIDMA_SR_HALT_MASK) && count < 5; ++count) {
1179 msleep(20);
1180 sr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
1181 }
1182
1183 sr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
1184 for (count = 0; !(sr & XAXIDMA_SR_HALT_MASK) && count < 5; ++count) {
1185 msleep(20);
1186 sr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
1187 }
1188
1189 /* Do a reset to ensure DMA is really stopped */
1190 axienet_lock_mii(lp);
1191 __axienet_device_reset(lp);
1192 axienet_unlock_mii(lp);
1193
1194 cancel_work_sync(&lp->dma_err_task);
1195
1196 if (lp->eth_irq > 0)
1197 free_irq(lp->eth_irq, ndev);
1198 free_irq(lp->tx_irq, ndev);
1199 free_irq(lp->rx_irq, ndev);
1200
1201 axienet_dma_bd_release(ndev);
1202 return 0;
1203 }
1204
1205 /**
1206 * axienet_change_mtu - Driver change mtu routine.
1207 * @ndev: Pointer to net_device structure
1208 * @new_mtu: New mtu value to be applied
1209 *
1210 * Return: Always returns 0 (success).
1211 *
1212 * This is the change mtu driver routine. It checks if the Axi Ethernet
1213 * hardware supports jumbo frames before changing the mtu. This can be
1214 * called only when the device is not up.
1215 */
axienet_change_mtu(struct net_device * ndev,int new_mtu)1216 static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
1217 {
1218 struct axienet_local *lp = netdev_priv(ndev);
1219
1220 if (netif_running(ndev))
1221 return -EBUSY;
1222
1223 if ((new_mtu + VLAN_ETH_HLEN +
1224 XAE_TRL_SIZE) > lp->rxmem)
1225 return -EINVAL;
1226
1227 ndev->mtu = new_mtu;
1228
1229 return 0;
1230 }
1231
1232 #ifdef CONFIG_NET_POLL_CONTROLLER
1233 /**
1234 * axienet_poll_controller - Axi Ethernet poll mechanism.
1235 * @ndev: Pointer to net_device structure
1236 *
1237 * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1238 * to polling the ISRs and are enabled back after the polling is done.
1239 */
axienet_poll_controller(struct net_device * ndev)1240 static void axienet_poll_controller(struct net_device *ndev)
1241 {
1242 struct axienet_local *lp = netdev_priv(ndev);
1243 disable_irq(lp->tx_irq);
1244 disable_irq(lp->rx_irq);
1245 axienet_rx_irq(lp->tx_irq, ndev);
1246 axienet_tx_irq(lp->rx_irq, ndev);
1247 enable_irq(lp->tx_irq);
1248 enable_irq(lp->rx_irq);
1249 }
1250 #endif
1251
axienet_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1252 static int axienet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1253 {
1254 struct axienet_local *lp = netdev_priv(dev);
1255
1256 if (!netif_running(dev))
1257 return -EINVAL;
1258
1259 return phylink_mii_ioctl(lp->phylink, rq, cmd);
1260 }
1261
1262 static const struct net_device_ops axienet_netdev_ops = {
1263 .ndo_open = axienet_open,
1264 .ndo_stop = axienet_stop,
1265 .ndo_start_xmit = axienet_start_xmit,
1266 .ndo_change_mtu = axienet_change_mtu,
1267 .ndo_set_mac_address = netdev_set_mac_address,
1268 .ndo_validate_addr = eth_validate_addr,
1269 .ndo_eth_ioctl = axienet_ioctl,
1270 .ndo_set_rx_mode = axienet_set_multicast_list,
1271 #ifdef CONFIG_NET_POLL_CONTROLLER
1272 .ndo_poll_controller = axienet_poll_controller,
1273 #endif
1274 };
1275
1276 /**
1277 * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1278 * @ndev: Pointer to net_device structure
1279 * @ed: Pointer to ethtool_drvinfo structure
1280 *
1281 * This implements ethtool command for getting the driver information.
1282 * Issue "ethtool -i ethX" under linux prompt to execute this function.
1283 */
axienet_ethtools_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * ed)1284 static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
1285 struct ethtool_drvinfo *ed)
1286 {
1287 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1288 strlcpy(ed->version, DRIVER_VERSION, sizeof(ed->version));
1289 }
1290
1291 /**
1292 * axienet_ethtools_get_regs_len - Get the total regs length present in the
1293 * AxiEthernet core.
1294 * @ndev: Pointer to net_device structure
1295 *
1296 * This implements ethtool command for getting the total register length
1297 * information.
1298 *
1299 * Return: the total regs length
1300 */
axienet_ethtools_get_regs_len(struct net_device * ndev)1301 static int axienet_ethtools_get_regs_len(struct net_device *ndev)
1302 {
1303 return sizeof(u32) * AXIENET_REGS_N;
1304 }
1305
1306 /**
1307 * axienet_ethtools_get_regs - Dump the contents of all registers present
1308 * in AxiEthernet core.
1309 * @ndev: Pointer to net_device structure
1310 * @regs: Pointer to ethtool_regs structure
1311 * @ret: Void pointer used to return the contents of the registers.
1312 *
1313 * This implements ethtool command for getting the Axi Ethernet register dump.
1314 * Issue "ethtool -d ethX" to execute this function.
1315 */
axienet_ethtools_get_regs(struct net_device * ndev,struct ethtool_regs * regs,void * ret)1316 static void axienet_ethtools_get_regs(struct net_device *ndev,
1317 struct ethtool_regs *regs, void *ret)
1318 {
1319 u32 *data = (u32 *) ret;
1320 size_t len = sizeof(u32) * AXIENET_REGS_N;
1321 struct axienet_local *lp = netdev_priv(ndev);
1322
1323 regs->version = 0;
1324 regs->len = len;
1325
1326 memset(data, 0, len);
1327 data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
1328 data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
1329 data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
1330 data[3] = axienet_ior(lp, XAE_IS_OFFSET);
1331 data[4] = axienet_ior(lp, XAE_IP_OFFSET);
1332 data[5] = axienet_ior(lp, XAE_IE_OFFSET);
1333 data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
1334 data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
1335 data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
1336 data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
1337 data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
1338 data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
1339 data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
1340 data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
1341 data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
1342 data[15] = axienet_ior(lp, XAE_TC_OFFSET);
1343 data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
1344 data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
1345 data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
1346 data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1347 data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
1348 data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
1349 data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
1350 data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
1351 data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
1352 data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
1353 data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
1354 data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
1355 data[32] = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1356 data[33] = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
1357 data[34] = axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET);
1358 data[35] = axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET);
1359 data[36] = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1360 data[37] = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
1361 data[38] = axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET);
1362 data[39] = axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET);
1363 }
1364
axienet_ethtools_get_ringparam(struct net_device * ndev,struct ethtool_ringparam * ering)1365 static void axienet_ethtools_get_ringparam(struct net_device *ndev,
1366 struct ethtool_ringparam *ering)
1367 {
1368 struct axienet_local *lp = netdev_priv(ndev);
1369
1370 ering->rx_max_pending = RX_BD_NUM_MAX;
1371 ering->rx_mini_max_pending = 0;
1372 ering->rx_jumbo_max_pending = 0;
1373 ering->tx_max_pending = TX_BD_NUM_MAX;
1374 ering->rx_pending = lp->rx_bd_num;
1375 ering->rx_mini_pending = 0;
1376 ering->rx_jumbo_pending = 0;
1377 ering->tx_pending = lp->tx_bd_num;
1378 }
1379
axienet_ethtools_set_ringparam(struct net_device * ndev,struct ethtool_ringparam * ering)1380 static int axienet_ethtools_set_ringparam(struct net_device *ndev,
1381 struct ethtool_ringparam *ering)
1382 {
1383 struct axienet_local *lp = netdev_priv(ndev);
1384
1385 if (ering->rx_pending > RX_BD_NUM_MAX ||
1386 ering->rx_mini_pending ||
1387 ering->rx_jumbo_pending ||
1388 ering->tx_pending < TX_BD_NUM_MIN ||
1389 ering->tx_pending > TX_BD_NUM_MAX)
1390 return -EINVAL;
1391
1392 if (netif_running(ndev))
1393 return -EBUSY;
1394
1395 lp->rx_bd_num = ering->rx_pending;
1396 lp->tx_bd_num = ering->tx_pending;
1397 return 0;
1398 }
1399
1400 /**
1401 * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1402 * Tx and Rx paths.
1403 * @ndev: Pointer to net_device structure
1404 * @epauseparm: Pointer to ethtool_pauseparam structure.
1405 *
1406 * This implements ethtool command for getting axi ethernet pause frame
1407 * setting. Issue "ethtool -a ethX" to execute this function.
1408 */
1409 static void
axienet_ethtools_get_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * epauseparm)1410 axienet_ethtools_get_pauseparam(struct net_device *ndev,
1411 struct ethtool_pauseparam *epauseparm)
1412 {
1413 struct axienet_local *lp = netdev_priv(ndev);
1414
1415 phylink_ethtool_get_pauseparam(lp->phylink, epauseparm);
1416 }
1417
1418 /**
1419 * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1420 * settings.
1421 * @ndev: Pointer to net_device structure
1422 * @epauseparm:Pointer to ethtool_pauseparam structure
1423 *
1424 * This implements ethtool command for enabling flow control on Rx and Tx
1425 * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1426 * function.
1427 *
1428 * Return: 0 on success, -EFAULT if device is running
1429 */
1430 static int
axienet_ethtools_set_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * epauseparm)1431 axienet_ethtools_set_pauseparam(struct net_device *ndev,
1432 struct ethtool_pauseparam *epauseparm)
1433 {
1434 struct axienet_local *lp = netdev_priv(ndev);
1435
1436 return phylink_ethtool_set_pauseparam(lp->phylink, epauseparm);
1437 }
1438
1439 /**
1440 * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1441 * @ndev: Pointer to net_device structure
1442 * @ecoalesce: Pointer to ethtool_coalesce structure
1443 * @kernel_coal: ethtool CQE mode setting structure
1444 * @extack: extack for reporting error messages
1445 *
1446 * This implements ethtool command for getting the DMA interrupt coalescing
1447 * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1448 * execute this function.
1449 *
1450 * Return: 0 always
1451 */
1452 static int
axienet_ethtools_get_coalesce(struct net_device * ndev,struct ethtool_coalesce * ecoalesce,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)1453 axienet_ethtools_get_coalesce(struct net_device *ndev,
1454 struct ethtool_coalesce *ecoalesce,
1455 struct kernel_ethtool_coalesce *kernel_coal,
1456 struct netlink_ext_ack *extack)
1457 {
1458 u32 regval = 0;
1459 struct axienet_local *lp = netdev_priv(ndev);
1460 regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1461 ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1462 >> XAXIDMA_COALESCE_SHIFT;
1463 regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1464 ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1465 >> XAXIDMA_COALESCE_SHIFT;
1466 return 0;
1467 }
1468
1469 /**
1470 * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1471 * @ndev: Pointer to net_device structure
1472 * @ecoalesce: Pointer to ethtool_coalesce structure
1473 * @kernel_coal: ethtool CQE mode setting structure
1474 * @extack: extack for reporting error messages
1475 *
1476 * This implements ethtool command for setting the DMA interrupt coalescing
1477 * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1478 * prompt to execute this function.
1479 *
1480 * Return: 0, on success, Non-zero error value on failure.
1481 */
1482 static int
axienet_ethtools_set_coalesce(struct net_device * ndev,struct ethtool_coalesce * ecoalesce,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)1483 axienet_ethtools_set_coalesce(struct net_device *ndev,
1484 struct ethtool_coalesce *ecoalesce,
1485 struct kernel_ethtool_coalesce *kernel_coal,
1486 struct netlink_ext_ack *extack)
1487 {
1488 struct axienet_local *lp = netdev_priv(ndev);
1489
1490 if (netif_running(ndev)) {
1491 netdev_err(ndev,
1492 "Please stop netif before applying configuration\n");
1493 return -EFAULT;
1494 }
1495
1496 if (ecoalesce->rx_max_coalesced_frames)
1497 lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1498 if (ecoalesce->tx_max_coalesced_frames)
1499 lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1500
1501 return 0;
1502 }
1503
1504 static int
axienet_ethtools_get_link_ksettings(struct net_device * ndev,struct ethtool_link_ksettings * cmd)1505 axienet_ethtools_get_link_ksettings(struct net_device *ndev,
1506 struct ethtool_link_ksettings *cmd)
1507 {
1508 struct axienet_local *lp = netdev_priv(ndev);
1509
1510 return phylink_ethtool_ksettings_get(lp->phylink, cmd);
1511 }
1512
1513 static int
axienet_ethtools_set_link_ksettings(struct net_device * ndev,const struct ethtool_link_ksettings * cmd)1514 axienet_ethtools_set_link_ksettings(struct net_device *ndev,
1515 const struct ethtool_link_ksettings *cmd)
1516 {
1517 struct axienet_local *lp = netdev_priv(ndev);
1518
1519 return phylink_ethtool_ksettings_set(lp->phylink, cmd);
1520 }
1521
axienet_ethtools_nway_reset(struct net_device * dev)1522 static int axienet_ethtools_nway_reset(struct net_device *dev)
1523 {
1524 struct axienet_local *lp = netdev_priv(dev);
1525
1526 return phylink_ethtool_nway_reset(lp->phylink);
1527 }
1528
1529 static const struct ethtool_ops axienet_ethtool_ops = {
1530 .supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES,
1531 .get_drvinfo = axienet_ethtools_get_drvinfo,
1532 .get_regs_len = axienet_ethtools_get_regs_len,
1533 .get_regs = axienet_ethtools_get_regs,
1534 .get_link = ethtool_op_get_link,
1535 .get_ringparam = axienet_ethtools_get_ringparam,
1536 .set_ringparam = axienet_ethtools_set_ringparam,
1537 .get_pauseparam = axienet_ethtools_get_pauseparam,
1538 .set_pauseparam = axienet_ethtools_set_pauseparam,
1539 .get_coalesce = axienet_ethtools_get_coalesce,
1540 .set_coalesce = axienet_ethtools_set_coalesce,
1541 .get_link_ksettings = axienet_ethtools_get_link_ksettings,
1542 .set_link_ksettings = axienet_ethtools_set_link_ksettings,
1543 .nway_reset = axienet_ethtools_nway_reset,
1544 };
1545
axienet_validate(struct phylink_config * config,unsigned long * supported,struct phylink_link_state * state)1546 static void axienet_validate(struct phylink_config *config,
1547 unsigned long *supported,
1548 struct phylink_link_state *state)
1549 {
1550 struct net_device *ndev = to_net_dev(config->dev);
1551 struct axienet_local *lp = netdev_priv(ndev);
1552 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1553
1554 /* Only support the mode we are configured for */
1555 switch (state->interface) {
1556 case PHY_INTERFACE_MODE_NA:
1557 break;
1558 case PHY_INTERFACE_MODE_1000BASEX:
1559 case PHY_INTERFACE_MODE_SGMII:
1560 if (lp->switch_x_sgmii)
1561 break;
1562 fallthrough;
1563 default:
1564 if (state->interface != lp->phy_mode) {
1565 netdev_warn(ndev, "Cannot use PHY mode %s, supported: %s\n",
1566 phy_modes(state->interface),
1567 phy_modes(lp->phy_mode));
1568 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1569 return;
1570 }
1571 }
1572
1573 phylink_set(mask, Autoneg);
1574 phylink_set_port_modes(mask);
1575
1576 phylink_set(mask, Asym_Pause);
1577 phylink_set(mask, Pause);
1578
1579 switch (state->interface) {
1580 case PHY_INTERFACE_MODE_NA:
1581 case PHY_INTERFACE_MODE_1000BASEX:
1582 case PHY_INTERFACE_MODE_SGMII:
1583 case PHY_INTERFACE_MODE_GMII:
1584 case PHY_INTERFACE_MODE_RGMII:
1585 case PHY_INTERFACE_MODE_RGMII_ID:
1586 case PHY_INTERFACE_MODE_RGMII_RXID:
1587 case PHY_INTERFACE_MODE_RGMII_TXID:
1588 phylink_set(mask, 1000baseX_Full);
1589 phylink_set(mask, 1000baseT_Full);
1590 if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
1591 break;
1592 fallthrough;
1593 case PHY_INTERFACE_MODE_MII:
1594 phylink_set(mask, 100baseT_Full);
1595 phylink_set(mask, 10baseT_Full);
1596 fallthrough;
1597 default:
1598 break;
1599 }
1600
1601 bitmap_and(supported, supported, mask,
1602 __ETHTOOL_LINK_MODE_MASK_NBITS);
1603 bitmap_and(state->advertising, state->advertising, mask,
1604 __ETHTOOL_LINK_MODE_MASK_NBITS);
1605 }
1606
axienet_mac_pcs_get_state(struct phylink_config * config,struct phylink_link_state * state)1607 static void axienet_mac_pcs_get_state(struct phylink_config *config,
1608 struct phylink_link_state *state)
1609 {
1610 struct net_device *ndev = to_net_dev(config->dev);
1611 struct axienet_local *lp = netdev_priv(ndev);
1612
1613 switch (state->interface) {
1614 case PHY_INTERFACE_MODE_SGMII:
1615 case PHY_INTERFACE_MODE_1000BASEX:
1616 phylink_mii_c22_pcs_get_state(lp->pcs_phy, state);
1617 break;
1618 default:
1619 break;
1620 }
1621 }
1622
axienet_mac_an_restart(struct phylink_config * config)1623 static void axienet_mac_an_restart(struct phylink_config *config)
1624 {
1625 struct net_device *ndev = to_net_dev(config->dev);
1626 struct axienet_local *lp = netdev_priv(ndev);
1627
1628 phylink_mii_c22_pcs_an_restart(lp->pcs_phy);
1629 }
1630
axienet_mac_prepare(struct phylink_config * config,unsigned int mode,phy_interface_t iface)1631 static int axienet_mac_prepare(struct phylink_config *config, unsigned int mode,
1632 phy_interface_t iface)
1633 {
1634 struct net_device *ndev = to_net_dev(config->dev);
1635 struct axienet_local *lp = netdev_priv(ndev);
1636 int ret;
1637
1638 switch (iface) {
1639 case PHY_INTERFACE_MODE_SGMII:
1640 case PHY_INTERFACE_MODE_1000BASEX:
1641 if (!lp->switch_x_sgmii)
1642 return 0;
1643
1644 ret = mdiobus_write(lp->pcs_phy->bus,
1645 lp->pcs_phy->addr,
1646 XLNX_MII_STD_SELECT_REG,
1647 iface == PHY_INTERFACE_MODE_SGMII ?
1648 XLNX_MII_STD_SELECT_SGMII : 0);
1649 if (ret < 0)
1650 netdev_warn(ndev, "Failed to switch PHY interface: %d\n",
1651 ret);
1652 return ret;
1653 default:
1654 return 0;
1655 }
1656 }
1657
axienet_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)1658 static void axienet_mac_config(struct phylink_config *config, unsigned int mode,
1659 const struct phylink_link_state *state)
1660 {
1661 struct net_device *ndev = to_net_dev(config->dev);
1662 struct axienet_local *lp = netdev_priv(ndev);
1663 int ret;
1664
1665 switch (state->interface) {
1666 case PHY_INTERFACE_MODE_SGMII:
1667 case PHY_INTERFACE_MODE_1000BASEX:
1668 ret = phylink_mii_c22_pcs_config(lp->pcs_phy, mode,
1669 state->interface,
1670 state->advertising);
1671 if (ret < 0)
1672 netdev_warn(ndev, "Failed to configure PCS: %d\n",
1673 ret);
1674 break;
1675
1676 default:
1677 break;
1678 }
1679 }
1680
axienet_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)1681 static void axienet_mac_link_down(struct phylink_config *config,
1682 unsigned int mode,
1683 phy_interface_t interface)
1684 {
1685 /* nothing meaningful to do */
1686 }
1687
axienet_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1688 static void axienet_mac_link_up(struct phylink_config *config,
1689 struct phy_device *phy,
1690 unsigned int mode, phy_interface_t interface,
1691 int speed, int duplex,
1692 bool tx_pause, bool rx_pause)
1693 {
1694 struct net_device *ndev = to_net_dev(config->dev);
1695 struct axienet_local *lp = netdev_priv(ndev);
1696 u32 emmc_reg, fcc_reg;
1697
1698 emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
1699 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
1700
1701 switch (speed) {
1702 case SPEED_1000:
1703 emmc_reg |= XAE_EMMC_LINKSPD_1000;
1704 break;
1705 case SPEED_100:
1706 emmc_reg |= XAE_EMMC_LINKSPD_100;
1707 break;
1708 case SPEED_10:
1709 emmc_reg |= XAE_EMMC_LINKSPD_10;
1710 break;
1711 default:
1712 dev_err(&ndev->dev,
1713 "Speed other than 10, 100 or 1Gbps is not supported\n");
1714 break;
1715 }
1716
1717 axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
1718
1719 fcc_reg = axienet_ior(lp, XAE_FCC_OFFSET);
1720 if (tx_pause)
1721 fcc_reg |= XAE_FCC_FCTX_MASK;
1722 else
1723 fcc_reg &= ~XAE_FCC_FCTX_MASK;
1724 if (rx_pause)
1725 fcc_reg |= XAE_FCC_FCRX_MASK;
1726 else
1727 fcc_reg &= ~XAE_FCC_FCRX_MASK;
1728 axienet_iow(lp, XAE_FCC_OFFSET, fcc_reg);
1729 }
1730
1731 static const struct phylink_mac_ops axienet_phylink_ops = {
1732 .validate = axienet_validate,
1733 .mac_pcs_get_state = axienet_mac_pcs_get_state,
1734 .mac_an_restart = axienet_mac_an_restart,
1735 .mac_prepare = axienet_mac_prepare,
1736 .mac_config = axienet_mac_config,
1737 .mac_link_down = axienet_mac_link_down,
1738 .mac_link_up = axienet_mac_link_up,
1739 };
1740
1741 /**
1742 * axienet_dma_err_handler - Work queue task for Axi DMA Error
1743 * @work: pointer to work_struct
1744 *
1745 * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1746 * Tx/Rx BDs.
1747 */
axienet_dma_err_handler(struct work_struct * work)1748 static void axienet_dma_err_handler(struct work_struct *work)
1749 {
1750 u32 axienet_status;
1751 u32 cr, i;
1752 struct axienet_local *lp = container_of(work, struct axienet_local,
1753 dma_err_task);
1754 struct net_device *ndev = lp->ndev;
1755 struct axidma_bd *cur_p;
1756
1757 axienet_setoptions(ndev, lp->options &
1758 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1759 /* When we do an Axi Ethernet reset, it resets the complete core
1760 * including the MDIO. MDIO must be disabled before resetting.
1761 * Hold MDIO bus lock to avoid MDIO accesses during the reset.
1762 */
1763 axienet_lock_mii(lp);
1764 __axienet_device_reset(lp);
1765 axienet_unlock_mii(lp);
1766
1767 for (i = 0; i < lp->tx_bd_num; i++) {
1768 cur_p = &lp->tx_bd_v[i];
1769 if (cur_p->cntrl) {
1770 dma_addr_t addr = desc_get_phys_addr(lp, cur_p);
1771
1772 dma_unmap_single(ndev->dev.parent, addr,
1773 (cur_p->cntrl &
1774 XAXIDMA_BD_CTRL_LENGTH_MASK),
1775 DMA_TO_DEVICE);
1776 }
1777 if (cur_p->skb)
1778 dev_kfree_skb_irq(cur_p->skb);
1779 cur_p->phys = 0;
1780 cur_p->phys_msb = 0;
1781 cur_p->cntrl = 0;
1782 cur_p->status = 0;
1783 cur_p->app0 = 0;
1784 cur_p->app1 = 0;
1785 cur_p->app2 = 0;
1786 cur_p->app3 = 0;
1787 cur_p->app4 = 0;
1788 cur_p->skb = NULL;
1789 }
1790
1791 for (i = 0; i < lp->rx_bd_num; i++) {
1792 cur_p = &lp->rx_bd_v[i];
1793 cur_p->status = 0;
1794 cur_p->app0 = 0;
1795 cur_p->app1 = 0;
1796 cur_p->app2 = 0;
1797 cur_p->app3 = 0;
1798 cur_p->app4 = 0;
1799 }
1800
1801 lp->tx_bd_ci = 0;
1802 lp->tx_bd_tail = 0;
1803 lp->rx_bd_ci = 0;
1804
1805 /* Start updating the Rx channel control register */
1806 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1807 /* Update the interrupt coalesce count */
1808 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
1809 (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1810 /* Update the delay timer count */
1811 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
1812 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1813 /* Enable coalesce, delay timer and error interrupts */
1814 cr |= XAXIDMA_IRQ_ALL_MASK;
1815 /* Finally write to the Rx channel control register */
1816 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1817
1818 /* Start updating the Tx channel control register */
1819 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1820 /* Update the interrupt coalesce count */
1821 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
1822 (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1823 /* Update the delay timer count */
1824 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
1825 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1826 /* Enable coalesce, delay timer and error interrupts */
1827 cr |= XAXIDMA_IRQ_ALL_MASK;
1828 /* Finally write to the Tx channel control register */
1829 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1830
1831 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
1832 * halted state. This will make the Rx side ready for reception.
1833 */
1834 axienet_dma_out_addr(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
1835 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1836 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1837 cr | XAXIDMA_CR_RUNSTOP_MASK);
1838 axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
1839 (sizeof(*lp->rx_bd_v) * (lp->rx_bd_num - 1)));
1840
1841 /* Write to the RS (Run-stop) bit in the Tx channel control register.
1842 * Tx channel is now ready to run. But only after we write to the
1843 * tail pointer register that the Tx channel will start transmitting
1844 */
1845 axienet_dma_out_addr(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
1846 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1847 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1848 cr | XAXIDMA_CR_RUNSTOP_MASK);
1849
1850 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
1851 axienet_status &= ~XAE_RCW1_RX_MASK;
1852 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
1853
1854 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
1855 if (axienet_status & XAE_INT_RXRJECT_MASK)
1856 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
1857 axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ?
1858 XAE_INT_RECV_ERROR_MASK : 0);
1859 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
1860
1861 /* Sync default options with HW but leave receiver and
1862 * transmitter disabled.
1863 */
1864 axienet_setoptions(ndev, lp->options &
1865 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1866 axienet_set_mac_address(ndev, NULL);
1867 axienet_set_multicast_list(ndev);
1868 axienet_setoptions(ndev, lp->options);
1869 }
1870
1871 /**
1872 * axienet_probe - Axi Ethernet probe function.
1873 * @pdev: Pointer to platform device structure.
1874 *
1875 * Return: 0, on success
1876 * Non-zero error value on failure.
1877 *
1878 * This is the probe routine for Axi Ethernet driver. This is called before
1879 * any other driver routines are invoked. It allocates and sets up the Ethernet
1880 * device. Parses through device tree and populates fields of
1881 * axienet_local. It registers the Ethernet device.
1882 */
axienet_probe(struct platform_device * pdev)1883 static int axienet_probe(struct platform_device *pdev)
1884 {
1885 int ret;
1886 struct device_node *np;
1887 struct axienet_local *lp;
1888 struct net_device *ndev;
1889 struct resource *ethres;
1890 u8 mac_addr[ETH_ALEN];
1891 int addr_width = 32;
1892 u32 value;
1893
1894 ndev = alloc_etherdev(sizeof(*lp));
1895 if (!ndev)
1896 return -ENOMEM;
1897
1898 platform_set_drvdata(pdev, ndev);
1899
1900 SET_NETDEV_DEV(ndev, &pdev->dev);
1901 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1902 ndev->features = NETIF_F_SG;
1903 ndev->netdev_ops = &axienet_netdev_ops;
1904 ndev->ethtool_ops = &axienet_ethtool_ops;
1905
1906 /* MTU range: 64 - 9000 */
1907 ndev->min_mtu = 64;
1908 ndev->max_mtu = XAE_JUMBO_MTU;
1909
1910 lp = netdev_priv(ndev);
1911 lp->ndev = ndev;
1912 lp->dev = &pdev->dev;
1913 lp->options = XAE_OPTION_DEFAULTS;
1914 lp->rx_bd_num = RX_BD_NUM_DEFAULT;
1915 lp->tx_bd_num = TX_BD_NUM_DEFAULT;
1916
1917 lp->axi_clk = devm_clk_get_optional(&pdev->dev, "s_axi_lite_clk");
1918 if (!lp->axi_clk) {
1919 /* For backward compatibility, if named AXI clock is not present,
1920 * treat the first clock specified as the AXI clock.
1921 */
1922 lp->axi_clk = devm_clk_get_optional(&pdev->dev, NULL);
1923 }
1924 if (IS_ERR(lp->axi_clk)) {
1925 ret = PTR_ERR(lp->axi_clk);
1926 goto free_netdev;
1927 }
1928 ret = clk_prepare_enable(lp->axi_clk);
1929 if (ret) {
1930 dev_err(&pdev->dev, "Unable to enable AXI clock: %d\n", ret);
1931 goto free_netdev;
1932 }
1933
1934 lp->misc_clks[0].id = "axis_clk";
1935 lp->misc_clks[1].id = "ref_clk";
1936 lp->misc_clks[2].id = "mgt_clk";
1937
1938 ret = devm_clk_bulk_get_optional(&pdev->dev, XAE_NUM_MISC_CLOCKS, lp->misc_clks);
1939 if (ret)
1940 goto cleanup_clk;
1941
1942 ret = clk_bulk_prepare_enable(XAE_NUM_MISC_CLOCKS, lp->misc_clks);
1943 if (ret)
1944 goto cleanup_clk;
1945
1946 /* Map device registers */
1947 lp->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ðres);
1948 if (IS_ERR(lp->regs)) {
1949 ret = PTR_ERR(lp->regs);
1950 goto cleanup_clk;
1951 }
1952 lp->regs_start = ethres->start;
1953
1954 /* Setup checksum offload, but default to off if not specified */
1955 lp->features = 0;
1956
1957 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
1958 if (!ret) {
1959 switch (value) {
1960 case 1:
1961 lp->csum_offload_on_tx_path =
1962 XAE_FEATURE_PARTIAL_TX_CSUM;
1963 lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
1964 /* Can checksum TCP/UDP over IPv4. */
1965 ndev->features |= NETIF_F_IP_CSUM;
1966 break;
1967 case 2:
1968 lp->csum_offload_on_tx_path =
1969 XAE_FEATURE_FULL_TX_CSUM;
1970 lp->features |= XAE_FEATURE_FULL_TX_CSUM;
1971 /* Can checksum TCP/UDP over IPv4. */
1972 ndev->features |= NETIF_F_IP_CSUM;
1973 break;
1974 default:
1975 lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
1976 }
1977 }
1978 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
1979 if (!ret) {
1980 switch (value) {
1981 case 1:
1982 lp->csum_offload_on_rx_path =
1983 XAE_FEATURE_PARTIAL_RX_CSUM;
1984 lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
1985 break;
1986 case 2:
1987 lp->csum_offload_on_rx_path =
1988 XAE_FEATURE_FULL_RX_CSUM;
1989 lp->features |= XAE_FEATURE_FULL_RX_CSUM;
1990 break;
1991 default:
1992 lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
1993 }
1994 }
1995 /* For supporting jumbo frames, the Axi Ethernet hardware must have
1996 * a larger Rx/Tx Memory. Typically, the size must be large so that
1997 * we can enable jumbo option and start supporting jumbo frames.
1998 * Here we check for memory allocated for Rx/Tx in the hardware from
1999 * the device-tree and accordingly set flags.
2000 */
2001 of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
2002
2003 lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node,
2004 "xlnx,switch-x-sgmii");
2005
2006 /* Start with the proprietary, and broken phy_type */
2007 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value);
2008 if (!ret) {
2009 netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode");
2010 switch (value) {
2011 case XAE_PHY_TYPE_MII:
2012 lp->phy_mode = PHY_INTERFACE_MODE_MII;
2013 break;
2014 case XAE_PHY_TYPE_GMII:
2015 lp->phy_mode = PHY_INTERFACE_MODE_GMII;
2016 break;
2017 case XAE_PHY_TYPE_RGMII_2_0:
2018 lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID;
2019 break;
2020 case XAE_PHY_TYPE_SGMII:
2021 lp->phy_mode = PHY_INTERFACE_MODE_SGMII;
2022 break;
2023 case XAE_PHY_TYPE_1000BASE_X:
2024 lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX;
2025 break;
2026 default:
2027 ret = -EINVAL;
2028 goto cleanup_clk;
2029 }
2030 } else {
2031 ret = of_get_phy_mode(pdev->dev.of_node, &lp->phy_mode);
2032 if (ret)
2033 goto cleanup_clk;
2034 }
2035 if (lp->switch_x_sgmii && lp->phy_mode != PHY_INTERFACE_MODE_SGMII &&
2036 lp->phy_mode != PHY_INTERFACE_MODE_1000BASEX) {
2037 dev_err(&pdev->dev, "xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\n");
2038 ret = -EINVAL;
2039 goto cleanup_clk;
2040 }
2041
2042 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
2043 np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);
2044 if (np) {
2045 struct resource dmares;
2046
2047 ret = of_address_to_resource(np, 0, &dmares);
2048 if (ret) {
2049 dev_err(&pdev->dev,
2050 "unable to get DMA resource\n");
2051 of_node_put(np);
2052 goto cleanup_clk;
2053 }
2054 lp->dma_regs = devm_ioremap_resource(&pdev->dev,
2055 &dmares);
2056 lp->rx_irq = irq_of_parse_and_map(np, 1);
2057 lp->tx_irq = irq_of_parse_and_map(np, 0);
2058 of_node_put(np);
2059 lp->eth_irq = platform_get_irq_optional(pdev, 0);
2060 } else {
2061 /* Check for these resources directly on the Ethernet node. */
2062 lp->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
2063 lp->rx_irq = platform_get_irq(pdev, 1);
2064 lp->tx_irq = platform_get_irq(pdev, 0);
2065 lp->eth_irq = platform_get_irq_optional(pdev, 2);
2066 }
2067 if (IS_ERR(lp->dma_regs)) {
2068 dev_err(&pdev->dev, "could not map DMA regs\n");
2069 ret = PTR_ERR(lp->dma_regs);
2070 goto cleanup_clk;
2071 }
2072 if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
2073 dev_err(&pdev->dev, "could not determine irqs\n");
2074 ret = -ENOMEM;
2075 goto cleanup_clk;
2076 }
2077
2078 /* Reset core now that clocks are enabled, prior to accessing MDIO */
2079 ret = __axienet_device_reset(lp);
2080 if (ret)
2081 goto cleanup_clk;
2082
2083 /* Autodetect the need for 64-bit DMA pointers.
2084 * When the IP is configured for a bus width bigger than 32 bits,
2085 * writing the MSB registers is mandatory, even if they are all 0.
2086 * We can detect this case by writing all 1's to one such register
2087 * and see if that sticks: when the IP is configured for 32 bits
2088 * only, those registers are RES0.
2089 * Those MSB registers were introduced in IP v7.1, which we check first.
2090 */
2091 if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) {
2092 void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4;
2093
2094 iowrite32(0x0, desc);
2095 if (ioread32(desc) == 0) { /* sanity check */
2096 iowrite32(0xffffffff, desc);
2097 if (ioread32(desc) > 0) {
2098 lp->features |= XAE_FEATURE_DMA_64BIT;
2099 addr_width = 64;
2100 dev_info(&pdev->dev,
2101 "autodetected 64-bit DMA range\n");
2102 }
2103 iowrite32(0x0, desc);
2104 }
2105 }
2106
2107 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width));
2108 if (ret) {
2109 dev_err(&pdev->dev, "No suitable DMA available\n");
2110 goto cleanup_clk;
2111 }
2112
2113 /* Check for Ethernet core IRQ (optional) */
2114 if (lp->eth_irq <= 0)
2115 dev_info(&pdev->dev, "Ethernet core IRQ not defined\n");
2116
2117 /* Retrieve the MAC address */
2118 ret = of_get_mac_address(pdev->dev.of_node, mac_addr);
2119 if (!ret) {
2120 axienet_set_mac_address(ndev, mac_addr);
2121 } else {
2122 dev_warn(&pdev->dev, "could not find MAC address property: %d\n",
2123 ret);
2124 axienet_set_mac_address(ndev, NULL);
2125 }
2126
2127 lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
2128 lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
2129
2130 ret = axienet_mdio_setup(lp);
2131 if (ret)
2132 dev_warn(&pdev->dev,
2133 "error registering MDIO bus: %d\n", ret);
2134
2135 if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII ||
2136 lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2137 lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
2138 if (!lp->phy_node) {
2139 dev_err(&pdev->dev, "phy-handle required for 1000BaseX/SGMII\n");
2140 ret = -EINVAL;
2141 goto cleanup_mdio;
2142 }
2143 lp->pcs_phy = of_mdio_find_device(lp->phy_node);
2144 if (!lp->pcs_phy) {
2145 ret = -EPROBE_DEFER;
2146 goto cleanup_mdio;
2147 }
2148 lp->phylink_config.pcs_poll = true;
2149 }
2150
2151 lp->phylink_config.dev = &ndev->dev;
2152 lp->phylink_config.type = PHYLINK_NETDEV;
2153
2154 lp->phylink = phylink_create(&lp->phylink_config, pdev->dev.fwnode,
2155 lp->phy_mode,
2156 &axienet_phylink_ops);
2157 if (IS_ERR(lp->phylink)) {
2158 ret = PTR_ERR(lp->phylink);
2159 dev_err(&pdev->dev, "phylink_create error (%i)\n", ret);
2160 goto cleanup_mdio;
2161 }
2162
2163 ret = register_netdev(lp->ndev);
2164 if (ret) {
2165 dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
2166 goto cleanup_phylink;
2167 }
2168
2169 return 0;
2170
2171 cleanup_phylink:
2172 phylink_destroy(lp->phylink);
2173
2174 cleanup_mdio:
2175 if (lp->pcs_phy)
2176 put_device(&lp->pcs_phy->dev);
2177 if (lp->mii_bus)
2178 axienet_mdio_teardown(lp);
2179 of_node_put(lp->phy_node);
2180
2181 cleanup_clk:
2182 clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks);
2183 clk_disable_unprepare(lp->axi_clk);
2184
2185 free_netdev:
2186 free_netdev(ndev);
2187
2188 return ret;
2189 }
2190
axienet_remove(struct platform_device * pdev)2191 static int axienet_remove(struct platform_device *pdev)
2192 {
2193 struct net_device *ndev = platform_get_drvdata(pdev);
2194 struct axienet_local *lp = netdev_priv(ndev);
2195
2196 unregister_netdev(ndev);
2197
2198 if (lp->phylink)
2199 phylink_destroy(lp->phylink);
2200
2201 if (lp->pcs_phy)
2202 put_device(&lp->pcs_phy->dev);
2203
2204 axienet_mdio_teardown(lp);
2205
2206 clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks);
2207 clk_disable_unprepare(lp->axi_clk);
2208
2209 of_node_put(lp->phy_node);
2210 lp->phy_node = NULL;
2211
2212 free_netdev(ndev);
2213
2214 return 0;
2215 }
2216
axienet_shutdown(struct platform_device * pdev)2217 static void axienet_shutdown(struct platform_device *pdev)
2218 {
2219 struct net_device *ndev = platform_get_drvdata(pdev);
2220
2221 rtnl_lock();
2222 netif_device_detach(ndev);
2223
2224 if (netif_running(ndev))
2225 dev_close(ndev);
2226
2227 rtnl_unlock();
2228 }
2229
2230 static struct platform_driver axienet_driver = {
2231 .probe = axienet_probe,
2232 .remove = axienet_remove,
2233 .shutdown = axienet_shutdown,
2234 .driver = {
2235 .name = "xilinx_axienet",
2236 .of_match_table = axienet_of_match,
2237 },
2238 };
2239
2240 module_platform_driver(axienet_driver);
2241
2242 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
2243 MODULE_AUTHOR("Xilinx");
2244 MODULE_LICENSE("GPL");
2245