1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * drivers/net/phy/broadcom.c
4 *
5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
6 * transceivers.
7 *
8 * Copyright (c) 2006 Maciej W. Rozycki
9 *
10 * Inspired by code written by Amy Fong.
11 */
12
13 #include "bcm-phy-lib.h"
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/phy.h>
17 #include <linux/brcmphy.h>
18 #include <linux/of.h>
19
20 #define BRCM_PHY_MODEL(phydev) \
21 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
22
23 #define BRCM_PHY_REV(phydev) \
24 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
25
26 MODULE_DESCRIPTION("Broadcom PHY driver");
27 MODULE_AUTHOR("Maciej W. Rozycki");
28 MODULE_LICENSE("GPL");
29
bcm54xx_config_clock_delay(struct phy_device * phydev)30 static int bcm54xx_config_clock_delay(struct phy_device *phydev)
31 {
32 int rc, val;
33
34 /* handling PHY's internal RX clock delay */
35 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
36 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
37 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
38 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
39 /* Disable RGMII RXC-RXD skew */
40 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
41 }
42 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
43 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
44 /* Enable RGMII RXC-RXD skew */
45 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
46 }
47 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
48 val);
49 if (rc < 0)
50 return rc;
51
52 /* handling PHY's internal TX clock delay */
53 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
54 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
55 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
56 /* Disable internal TX clock delay */
57 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
58 }
59 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
60 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
61 /* Enable internal TX clock delay */
62 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
63 }
64 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
65 if (rc < 0)
66 return rc;
67
68 return 0;
69 }
70
bcm54210e_config_init(struct phy_device * phydev)71 static int bcm54210e_config_init(struct phy_device *phydev)
72 {
73 int val;
74
75 bcm54xx_config_clock_delay(phydev);
76
77 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
78 val = phy_read(phydev, MII_CTRL1000);
79 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
80 phy_write(phydev, MII_CTRL1000, val);
81 }
82
83 return 0;
84 }
85
bcm54612e_config_init(struct phy_device * phydev)86 static int bcm54612e_config_init(struct phy_device *phydev)
87 {
88 int reg;
89
90 bcm54xx_config_clock_delay(phydev);
91
92 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
93 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
94 int err;
95
96 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
97 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
98 BCM54612E_LED4_CLK125OUT_EN | reg);
99
100 if (err < 0)
101 return err;
102 }
103
104 return 0;
105 }
106
bcm54616s_config_init(struct phy_device * phydev)107 static int bcm54616s_config_init(struct phy_device *phydev)
108 {
109 int rc, val;
110
111 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
112 phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
113 return 0;
114
115 /* Ensure proper interface mode is selected. */
116 /* Disable RGMII mode */
117 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
118 if (val < 0)
119 return val;
120 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN;
121 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
122 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
123 val);
124 if (rc < 0)
125 return rc;
126
127 /* Select 1000BASE-X register set (primary SerDes) */
128 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
129 if (val < 0)
130 return val;
131 val |= BCM54XX_SHD_MODE_1000BX;
132 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
133 if (rc < 0)
134 return rc;
135
136 /* Power down SerDes interface */
137 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
138 if (rc < 0)
139 return rc;
140
141 /* Select proper interface mode */
142 val &= ~BCM54XX_SHD_INTF_SEL_MASK;
143 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
144 BCM54XX_SHD_INTF_SEL_SGMII :
145 BCM54XX_SHD_INTF_SEL_GBIC;
146 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
147 if (rc < 0)
148 return rc;
149
150 /* Power up SerDes interface */
151 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
152 if (rc < 0)
153 return rc;
154
155 /* Select copper register set */
156 val &= ~BCM54XX_SHD_MODE_1000BX;
157 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
158 if (rc < 0)
159 return rc;
160
161 /* Power up copper interface */
162 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
163 }
164
165 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
bcm50610_a0_workaround(struct phy_device * phydev)166 static int bcm50610_a0_workaround(struct phy_device *phydev)
167 {
168 int err;
169
170 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
171 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
172 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
173 if (err < 0)
174 return err;
175
176 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
177 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
178 if (err < 0)
179 return err;
180
181 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
182 MII_BCM54XX_EXP_EXP75_VDACCTRL);
183 if (err < 0)
184 return err;
185
186 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
187 MII_BCM54XX_EXP_EXP96_MYST);
188 if (err < 0)
189 return err;
190
191 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
192 MII_BCM54XX_EXP_EXP97_MYST);
193
194 return err;
195 }
196
bcm54xx_phydsp_config(struct phy_device * phydev)197 static int bcm54xx_phydsp_config(struct phy_device *phydev)
198 {
199 int err, err2;
200
201 /* Enable the SMDSP clock */
202 err = bcm54xx_auxctl_write(phydev,
203 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
204 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
205 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
206 if (err < 0)
207 return err;
208
209 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
210 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
211 /* Clear bit 9 to fix a phy interop issue. */
212 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
213 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
214 if (err < 0)
215 goto error;
216
217 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
218 err = bcm50610_a0_workaround(phydev);
219 if (err < 0)
220 goto error;
221 }
222 }
223
224 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
225 int val;
226
227 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
228 if (val < 0)
229 goto error;
230
231 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
232 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
233 }
234
235 error:
236 /* Disable the SMDSP clock */
237 err2 = bcm54xx_auxctl_write(phydev,
238 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
239 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
240
241 /* Return the first error reported. */
242 return err ? err : err2;
243 }
244
bcm54xx_adjust_rxrefclk(struct phy_device * phydev)245 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
246 {
247 u32 orig;
248 int val;
249 bool clk125en = true;
250
251 /* Abort if we are using an untested phy. */
252 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
253 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
254 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
255 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E &&
256 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
257 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
258 return;
259
260 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
261 if (val < 0)
262 return;
263
264 orig = val;
265
266 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
267 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
268 BRCM_PHY_REV(phydev) >= 0x3) {
269 /*
270 * Here, bit 0 _disables_ CLK125 when set.
271 * This bit is set by default.
272 */
273 clk125en = false;
274 } else {
275 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
276 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
277 /* Here, bit 0 _enables_ CLK125 when set */
278 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
279 }
280 clk125en = false;
281 }
282 }
283
284 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
285 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
286 else
287 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
288
289 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
290 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E ||
291 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
292 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
293 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS;
294 else
295 val |= BCM54XX_SHD_SCR3_TRDDAPD;
296 }
297
298 if (orig != val)
299 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
300
301 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
302 if (val < 0)
303 return;
304
305 orig = val;
306
307 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
308 val |= BCM54XX_SHD_APD_EN;
309 else
310 val &= ~BCM54XX_SHD_APD_EN;
311
312 if (orig != val)
313 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
314 }
315
bcm54xx_config_init(struct phy_device * phydev)316 static int bcm54xx_config_init(struct phy_device *phydev)
317 {
318 int reg, err, val;
319
320 reg = phy_read(phydev, MII_BCM54XX_ECR);
321 if (reg < 0)
322 return reg;
323
324 /* Mask interrupts globally. */
325 reg |= MII_BCM54XX_ECR_IM;
326 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
327 if (err < 0)
328 return err;
329
330 /* Unmask events we are interested in. */
331 reg = ~(MII_BCM54XX_INT_DUPLEX |
332 MII_BCM54XX_INT_SPEED |
333 MII_BCM54XX_INT_LINK);
334 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
335 if (err < 0)
336 return err;
337
338 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
339 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
340 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
341 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
342
343 bcm54xx_adjust_rxrefclk(phydev);
344
345 switch (BRCM_PHY_MODEL(phydev)) {
346 case PHY_ID_BCM50610:
347 case PHY_ID_BCM50610M:
348 err = bcm54xx_config_clock_delay(phydev);
349 break;
350 case PHY_ID_BCM54210E:
351 err = bcm54210e_config_init(phydev);
352 break;
353 case PHY_ID_BCM54612E:
354 err = bcm54612e_config_init(phydev);
355 break;
356 case PHY_ID_BCM54616S:
357 err = bcm54616s_config_init(phydev);
358 break;
359 case PHY_ID_BCM54810:
360 /* For BCM54810, we need to disable BroadR-Reach function */
361 val = bcm_phy_read_exp(phydev,
362 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
363 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
364 err = bcm_phy_write_exp(phydev,
365 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
366 val);
367 break;
368 }
369 if (err)
370 return err;
371
372 bcm54xx_phydsp_config(phydev);
373
374 /* For non-SFP setups, encode link speed into LED1 and LED3 pair
375 * (green/amber).
376 * Also flash these two LEDs on activity. This means configuring
377 * them for MULTICOLOR and encoding link/activity into them.
378 * Don't do this for devices on an SFP module, since some of these
379 * use the LED outputs to control the SFP LOS signal, and changing
380 * these settings will cause LOS to malfunction.
381 */
382 if (!phy_on_sfp(phydev)) {
383 val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
384 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
385 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
386
387 val = BCM_LED_MULTICOLOR_IN_PHASE |
388 BCM5482_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
389 BCM5482_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
390 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
391 }
392
393 return 0;
394 }
395
bcm54xx_resume(struct phy_device * phydev)396 static int bcm54xx_resume(struct phy_device *phydev)
397 {
398 int ret;
399
400 /* Writes to register other than BMCR would be ignored
401 * unless we clear the PDOWN bit first
402 */
403 ret = genphy_resume(phydev);
404 if (ret < 0)
405 return ret;
406
407 /* Upon exiting power down, the PHY remains in an internal reset state
408 * for 40us
409 */
410 fsleep(40);
411
412 return bcm54xx_config_init(phydev);
413 }
414
bcm54810_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)415 static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
416 {
417 return -EOPNOTSUPP;
418 }
419
bcm54810_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)420 static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
421 u16 val)
422 {
423 return -EOPNOTSUPP;
424 }
425
bcm54811_config_init(struct phy_device * phydev)426 static int bcm54811_config_init(struct phy_device *phydev)
427 {
428 int err, reg;
429
430 /* Disable BroadR-Reach function. */
431 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
432 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
433 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
434 reg);
435 if (err < 0)
436 return err;
437
438 err = bcm54xx_config_init(phydev);
439
440 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
441 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
442 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
443 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
444 BCM54612E_LED4_CLK125OUT_EN | reg);
445 if (err < 0)
446 return err;
447 }
448
449 return err;
450 }
451
bcm5481_config_aneg(struct phy_device * phydev)452 static int bcm5481_config_aneg(struct phy_device *phydev)
453 {
454 struct device_node *np = phydev->mdio.dev.of_node;
455 int ret;
456
457 /* Aneg firstly. */
458 ret = genphy_config_aneg(phydev);
459
460 /* Then we can set up the delay. */
461 bcm54xx_config_clock_delay(phydev);
462
463 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
464 /* Lane Swap - Undocumented register...magic! */
465 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
466 0x11B);
467 if (ret < 0)
468 return ret;
469 }
470
471 return ret;
472 }
473
474 struct bcm54616s_phy_priv {
475 bool mode_1000bx_en;
476 };
477
bcm54616s_probe(struct phy_device * phydev)478 static int bcm54616s_probe(struct phy_device *phydev)
479 {
480 struct bcm54616s_phy_priv *priv;
481 int val;
482
483 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
484 if (!priv)
485 return -ENOMEM;
486
487 phydev->priv = priv;
488
489 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
490 if (val < 0)
491 return val;
492
493 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
494 * is 01b, and the link between PHY and its link partner can be
495 * either 1000Base-X or 100Base-FX.
496 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
497 * support is still missing as of now.
498 */
499 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) {
500 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
501 if (val < 0)
502 return val;
503
504 /* Bit 0 of the SerDes 100-FX Control register, when set
505 * to 1, sets the MII/RGMII -> 100BASE-FX configuration.
506 * When this bit is set to 0, it sets the GMII/RGMII ->
507 * 1000BASE-X configuration.
508 */
509 if (!(val & BCM54616S_100FX_MODE))
510 priv->mode_1000bx_en = true;
511
512 phydev->port = PORT_FIBRE;
513 }
514
515 return 0;
516 }
517
bcm54616s_config_aneg(struct phy_device * phydev)518 static int bcm54616s_config_aneg(struct phy_device *phydev)
519 {
520 struct bcm54616s_phy_priv *priv = phydev->priv;
521 int ret;
522
523 /* Aneg firstly. */
524 if (priv->mode_1000bx_en)
525 ret = genphy_c37_config_aneg(phydev);
526 else
527 ret = genphy_config_aneg(phydev);
528
529 /* Then we can set up the delay. */
530 bcm54xx_config_clock_delay(phydev);
531
532 return ret;
533 }
534
bcm54616s_read_status(struct phy_device * phydev)535 static int bcm54616s_read_status(struct phy_device *phydev)
536 {
537 struct bcm54616s_phy_priv *priv = phydev->priv;
538 int err;
539
540 if (priv->mode_1000bx_en)
541 err = genphy_c37_read_status(phydev);
542 else
543 err = genphy_read_status(phydev);
544
545 return err;
546 }
547
brcm_phy_setbits(struct phy_device * phydev,int reg,int set)548 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
549 {
550 int val;
551
552 val = phy_read(phydev, reg);
553 if (val < 0)
554 return val;
555
556 return phy_write(phydev, reg, val | set);
557 }
558
brcm_fet_config_init(struct phy_device * phydev)559 static int brcm_fet_config_init(struct phy_device *phydev)
560 {
561 int reg, err, err2, brcmtest;
562
563 /* Reset the PHY to bring it to a known state. */
564 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
565 if (err < 0)
566 return err;
567
568 /* The datasheet indicates the PHY needs up to 1us to complete a reset,
569 * build some slack here.
570 */
571 usleep_range(1000, 2000);
572
573 /* The PHY requires 65 MDC clock cycles to complete a write operation
574 * and turnaround the line properly.
575 *
576 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
577 * may flag the lack of turn-around as a read failure. This is
578 * particularly true with this combination since the MDIO controller
579 * only used 64 MDC cycles. This is not a critical failure in this
580 * specific case and it has no functional impact otherwise, so we let
581 * that one go through. If there is a genuine bus error, the next read
582 * of MII_BRCM_FET_INTREG will error out.
583 */
584 err = phy_read(phydev, MII_BMCR);
585 if (err < 0 && err != -EIO)
586 return err;
587
588 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
589 if (reg < 0)
590 return reg;
591
592 /* Unmask events we are interested in and mask interrupts globally. */
593 reg = MII_BRCM_FET_IR_DUPLEX_EN |
594 MII_BRCM_FET_IR_SPEED_EN |
595 MII_BRCM_FET_IR_LINK_EN |
596 MII_BRCM_FET_IR_ENABLE |
597 MII_BRCM_FET_IR_MASK;
598
599 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
600 if (err < 0)
601 return err;
602
603 /* Enable shadow register access */
604 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
605 if (brcmtest < 0)
606 return brcmtest;
607
608 reg = brcmtest | MII_BRCM_FET_BT_SRE;
609
610 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
611 if (err < 0)
612 return err;
613
614 /* Set the LED mode */
615 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
616 if (reg < 0) {
617 err = reg;
618 goto done;
619 }
620
621 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
622 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
623
624 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
625 if (err < 0)
626 goto done;
627
628 /* Enable auto MDIX */
629 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
630 MII_BRCM_FET_SHDW_MC_FAME);
631 if (err < 0)
632 goto done;
633
634 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
635 /* Enable auto power down */
636 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
637 MII_BRCM_FET_SHDW_AS2_APDE);
638 }
639
640 done:
641 /* Disable shadow register access */
642 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
643 if (!err)
644 err = err2;
645
646 return err;
647 }
648
brcm_fet_ack_interrupt(struct phy_device * phydev)649 static int brcm_fet_ack_interrupt(struct phy_device *phydev)
650 {
651 int reg;
652
653 /* Clear pending interrupts. */
654 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
655 if (reg < 0)
656 return reg;
657
658 return 0;
659 }
660
brcm_fet_config_intr(struct phy_device * phydev)661 static int brcm_fet_config_intr(struct phy_device *phydev)
662 {
663 int reg, err;
664
665 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
666 if (reg < 0)
667 return reg;
668
669 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
670 err = brcm_fet_ack_interrupt(phydev);
671 if (err)
672 return err;
673
674 reg &= ~MII_BRCM_FET_IR_MASK;
675 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
676 } else {
677 reg |= MII_BRCM_FET_IR_MASK;
678 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
679 if (err)
680 return err;
681
682 err = brcm_fet_ack_interrupt(phydev);
683 }
684
685 return err;
686 }
687
brcm_fet_handle_interrupt(struct phy_device * phydev)688 static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev)
689 {
690 int irq_status;
691
692 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG);
693 if (irq_status < 0) {
694 phy_error(phydev);
695 return IRQ_NONE;
696 }
697
698 if (irq_status == 0)
699 return IRQ_NONE;
700
701 phy_trigger_machine(phydev);
702
703 return IRQ_HANDLED;
704 }
705
706 struct bcm54xx_phy_priv {
707 u64 *stats;
708 };
709
bcm54xx_phy_probe(struct phy_device * phydev)710 static int bcm54xx_phy_probe(struct phy_device *phydev)
711 {
712 struct bcm54xx_phy_priv *priv;
713
714 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
715 if (!priv)
716 return -ENOMEM;
717
718 phydev->priv = priv;
719
720 priv->stats = devm_kcalloc(&phydev->mdio.dev,
721 bcm_phy_get_sset_count(phydev), sizeof(u64),
722 GFP_KERNEL);
723 if (!priv->stats)
724 return -ENOMEM;
725
726 return 0;
727 }
728
bcm54xx_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)729 static void bcm54xx_get_stats(struct phy_device *phydev,
730 struct ethtool_stats *stats, u64 *data)
731 {
732 struct bcm54xx_phy_priv *priv = phydev->priv;
733
734 bcm_phy_get_stats(phydev, priv->stats, stats, data);
735 }
736
737 static struct phy_driver broadcom_drivers[] = {
738 {
739 .phy_id = PHY_ID_BCM5411,
740 .phy_id_mask = 0xfffffff0,
741 .name = "Broadcom BCM5411",
742 /* PHY_GBIT_FEATURES */
743 .get_sset_count = bcm_phy_get_sset_count,
744 .get_strings = bcm_phy_get_strings,
745 .get_stats = bcm54xx_get_stats,
746 .probe = bcm54xx_phy_probe,
747 .config_init = bcm54xx_config_init,
748 .config_intr = bcm_phy_config_intr,
749 .handle_interrupt = bcm_phy_handle_interrupt,
750 }, {
751 .phy_id = PHY_ID_BCM5421,
752 .phy_id_mask = 0xfffffff0,
753 .name = "Broadcom BCM5421",
754 /* PHY_GBIT_FEATURES */
755 .get_sset_count = bcm_phy_get_sset_count,
756 .get_strings = bcm_phy_get_strings,
757 .get_stats = bcm54xx_get_stats,
758 .probe = bcm54xx_phy_probe,
759 .config_init = bcm54xx_config_init,
760 .config_intr = bcm_phy_config_intr,
761 .handle_interrupt = bcm_phy_handle_interrupt,
762 }, {
763 .phy_id = PHY_ID_BCM54210E,
764 .phy_id_mask = 0xfffffff0,
765 .name = "Broadcom BCM54210E",
766 /* PHY_GBIT_FEATURES */
767 .get_sset_count = bcm_phy_get_sset_count,
768 .get_strings = bcm_phy_get_strings,
769 .get_stats = bcm54xx_get_stats,
770 .probe = bcm54xx_phy_probe,
771 .config_init = bcm54xx_config_init,
772 .config_intr = bcm_phy_config_intr,
773 .handle_interrupt = bcm_phy_handle_interrupt,
774 }, {
775 .phy_id = PHY_ID_BCM5461,
776 .phy_id_mask = 0xfffffff0,
777 .name = "Broadcom BCM5461",
778 /* PHY_GBIT_FEATURES */
779 .get_sset_count = bcm_phy_get_sset_count,
780 .get_strings = bcm_phy_get_strings,
781 .get_stats = bcm54xx_get_stats,
782 .probe = bcm54xx_phy_probe,
783 .config_init = bcm54xx_config_init,
784 .config_intr = bcm_phy_config_intr,
785 .handle_interrupt = bcm_phy_handle_interrupt,
786 }, {
787 .phy_id = PHY_ID_BCM54612E,
788 .phy_id_mask = 0xfffffff0,
789 .name = "Broadcom BCM54612E",
790 /* PHY_GBIT_FEATURES */
791 .get_sset_count = bcm_phy_get_sset_count,
792 .get_strings = bcm_phy_get_strings,
793 .get_stats = bcm54xx_get_stats,
794 .probe = bcm54xx_phy_probe,
795 .config_init = bcm54xx_config_init,
796 .config_intr = bcm_phy_config_intr,
797 .handle_interrupt = bcm_phy_handle_interrupt,
798 }, {
799 .phy_id = PHY_ID_BCM54616S,
800 .phy_id_mask = 0xfffffff0,
801 .name = "Broadcom BCM54616S",
802 /* PHY_GBIT_FEATURES */
803 .soft_reset = genphy_soft_reset,
804 .config_init = bcm54xx_config_init,
805 .config_aneg = bcm54616s_config_aneg,
806 .config_intr = bcm_phy_config_intr,
807 .handle_interrupt = bcm_phy_handle_interrupt,
808 .read_status = bcm54616s_read_status,
809 .probe = bcm54616s_probe,
810 }, {
811 .phy_id = PHY_ID_BCM5464,
812 .phy_id_mask = 0xfffffff0,
813 .name = "Broadcom BCM5464",
814 /* PHY_GBIT_FEATURES */
815 .get_sset_count = bcm_phy_get_sset_count,
816 .get_strings = bcm_phy_get_strings,
817 .get_stats = bcm54xx_get_stats,
818 .probe = bcm54xx_phy_probe,
819 .config_init = bcm54xx_config_init,
820 .config_intr = bcm_phy_config_intr,
821 .handle_interrupt = bcm_phy_handle_interrupt,
822 .suspend = genphy_suspend,
823 .resume = genphy_resume,
824 }, {
825 .phy_id = PHY_ID_BCM5481,
826 .phy_id_mask = 0xfffffff0,
827 .name = "Broadcom BCM5481",
828 /* PHY_GBIT_FEATURES */
829 .get_sset_count = bcm_phy_get_sset_count,
830 .get_strings = bcm_phy_get_strings,
831 .get_stats = bcm54xx_get_stats,
832 .probe = bcm54xx_phy_probe,
833 .config_init = bcm54xx_config_init,
834 .config_aneg = bcm5481_config_aneg,
835 .config_intr = bcm_phy_config_intr,
836 .handle_interrupt = bcm_phy_handle_interrupt,
837 }, {
838 .phy_id = PHY_ID_BCM54810,
839 .phy_id_mask = 0xfffffff0,
840 .name = "Broadcom BCM54810",
841 /* PHY_GBIT_FEATURES */
842 .get_sset_count = bcm_phy_get_sset_count,
843 .get_strings = bcm_phy_get_strings,
844 .get_stats = bcm54xx_get_stats,
845 .probe = bcm54xx_phy_probe,
846 .read_mmd = bcm54810_read_mmd,
847 .write_mmd = bcm54810_write_mmd,
848 .config_init = bcm54xx_config_init,
849 .config_aneg = bcm5481_config_aneg,
850 .config_intr = bcm_phy_config_intr,
851 .handle_interrupt = bcm_phy_handle_interrupt,
852 .suspend = genphy_suspend,
853 .resume = bcm54xx_resume,
854 }, {
855 .phy_id = PHY_ID_BCM54811,
856 .phy_id_mask = 0xfffffff0,
857 .name = "Broadcom BCM54811",
858 /* PHY_GBIT_FEATURES */
859 .get_sset_count = bcm_phy_get_sset_count,
860 .get_strings = bcm_phy_get_strings,
861 .get_stats = bcm54xx_get_stats,
862 .probe = bcm54xx_phy_probe,
863 .config_init = bcm54811_config_init,
864 .config_aneg = bcm5481_config_aneg,
865 .config_intr = bcm_phy_config_intr,
866 .handle_interrupt = bcm_phy_handle_interrupt,
867 .suspend = genphy_suspend,
868 .resume = bcm54xx_resume,
869 }, {
870 .phy_id = PHY_ID_BCM5482,
871 .phy_id_mask = 0xfffffff0,
872 .name = "Broadcom BCM5482",
873 /* PHY_GBIT_FEATURES */
874 .get_sset_count = bcm_phy_get_sset_count,
875 .get_strings = bcm_phy_get_strings,
876 .get_stats = bcm54xx_get_stats,
877 .probe = bcm54xx_phy_probe,
878 .config_init = bcm54xx_config_init,
879 .config_intr = bcm_phy_config_intr,
880 .handle_interrupt = bcm_phy_handle_interrupt,
881 }, {
882 .phy_id = PHY_ID_BCM50610,
883 .phy_id_mask = 0xfffffff0,
884 .name = "Broadcom BCM50610",
885 /* PHY_GBIT_FEATURES */
886 .get_sset_count = bcm_phy_get_sset_count,
887 .get_strings = bcm_phy_get_strings,
888 .get_stats = bcm54xx_get_stats,
889 .probe = bcm54xx_phy_probe,
890 .config_init = bcm54xx_config_init,
891 .config_intr = bcm_phy_config_intr,
892 .handle_interrupt = bcm_phy_handle_interrupt,
893 }, {
894 .phy_id = PHY_ID_BCM50610M,
895 .phy_id_mask = 0xfffffff0,
896 .name = "Broadcom BCM50610M",
897 /* PHY_GBIT_FEATURES */
898 .get_sset_count = bcm_phy_get_sset_count,
899 .get_strings = bcm_phy_get_strings,
900 .get_stats = bcm54xx_get_stats,
901 .probe = bcm54xx_phy_probe,
902 .config_init = bcm54xx_config_init,
903 .config_intr = bcm_phy_config_intr,
904 .handle_interrupt = bcm_phy_handle_interrupt,
905 }, {
906 .phy_id = PHY_ID_BCM57780,
907 .phy_id_mask = 0xfffffff0,
908 .name = "Broadcom BCM57780",
909 /* PHY_GBIT_FEATURES */
910 .get_sset_count = bcm_phy_get_sset_count,
911 .get_strings = bcm_phy_get_strings,
912 .get_stats = bcm54xx_get_stats,
913 .probe = bcm54xx_phy_probe,
914 .config_init = bcm54xx_config_init,
915 .config_intr = bcm_phy_config_intr,
916 .handle_interrupt = bcm_phy_handle_interrupt,
917 }, {
918 .phy_id = PHY_ID_BCMAC131,
919 .phy_id_mask = 0xfffffff0,
920 .name = "Broadcom BCMAC131",
921 /* PHY_BASIC_FEATURES */
922 .config_init = brcm_fet_config_init,
923 .config_intr = brcm_fet_config_intr,
924 .handle_interrupt = brcm_fet_handle_interrupt,
925 }, {
926 .phy_id = PHY_ID_BCM5241,
927 .phy_id_mask = 0xfffffff0,
928 .name = "Broadcom BCM5241",
929 /* PHY_BASIC_FEATURES */
930 .config_init = brcm_fet_config_init,
931 .config_intr = brcm_fet_config_intr,
932 .handle_interrupt = brcm_fet_handle_interrupt,
933 }, {
934 .phy_id = PHY_ID_BCM5395,
935 .phy_id_mask = 0xfffffff0,
936 .name = "Broadcom BCM5395",
937 .flags = PHY_IS_INTERNAL,
938 /* PHY_GBIT_FEATURES */
939 .get_sset_count = bcm_phy_get_sset_count,
940 .get_strings = bcm_phy_get_strings,
941 .get_stats = bcm54xx_get_stats,
942 .probe = bcm54xx_phy_probe,
943 }, {
944 .phy_id = PHY_ID_BCM53125,
945 .phy_id_mask = 0xfffffff0,
946 .name = "Broadcom BCM53125",
947 .flags = PHY_IS_INTERNAL,
948 /* PHY_GBIT_FEATURES */
949 .get_sset_count = bcm_phy_get_sset_count,
950 .get_strings = bcm_phy_get_strings,
951 .get_stats = bcm54xx_get_stats,
952 .probe = bcm54xx_phy_probe,
953 .config_init = bcm54xx_config_init,
954 .config_intr = bcm_phy_config_intr,
955 .handle_interrupt = bcm_phy_handle_interrupt,
956 }, {
957 .phy_id = PHY_ID_BCM89610,
958 .phy_id_mask = 0xfffffff0,
959 .name = "Broadcom BCM89610",
960 /* PHY_GBIT_FEATURES */
961 .get_sset_count = bcm_phy_get_sset_count,
962 .get_strings = bcm_phy_get_strings,
963 .get_stats = bcm54xx_get_stats,
964 .probe = bcm54xx_phy_probe,
965 .config_init = bcm54xx_config_init,
966 .config_intr = bcm_phy_config_intr,
967 .handle_interrupt = bcm_phy_handle_interrupt,
968 } };
969
970 module_phy_driver(broadcom_drivers);
971
972 static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
973 { PHY_ID_BCM5411, 0xfffffff0 },
974 { PHY_ID_BCM5421, 0xfffffff0 },
975 { PHY_ID_BCM54210E, 0xfffffff0 },
976 { PHY_ID_BCM5461, 0xfffffff0 },
977 { PHY_ID_BCM54612E, 0xfffffff0 },
978 { PHY_ID_BCM54616S, 0xfffffff0 },
979 { PHY_ID_BCM5464, 0xfffffff0 },
980 { PHY_ID_BCM5481, 0xfffffff0 },
981 { PHY_ID_BCM54810, 0xfffffff0 },
982 { PHY_ID_BCM54811, 0xfffffff0 },
983 { PHY_ID_BCM5482, 0xfffffff0 },
984 { PHY_ID_BCM50610, 0xfffffff0 },
985 { PHY_ID_BCM50610M, 0xfffffff0 },
986 { PHY_ID_BCM57780, 0xfffffff0 },
987 { PHY_ID_BCMAC131, 0xfffffff0 },
988 { PHY_ID_BCM5241, 0xfffffff0 },
989 { PHY_ID_BCM5395, 0xfffffff0 },
990 { PHY_ID_BCM53125, 0xfffffff0 },
991 { PHY_ID_BCM89610, 0xfffffff0 },
992 { }
993 };
994
995 MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
996