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1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/ieee80211.h>
7 #include <linux/kernel.h>
8 #include <linux/skbuff.h>
9 #include <crypto/hash.h>
10 #include "core.h"
11 #include "debug.h"
12 #include "debugfs_htt_stats.h"
13 #include "debugfs_sta.h"
14 #include "hal_desc.h"
15 #include "hw.h"
16 #include "dp_rx.h"
17 #include "hal_rx.h"
18 #include "dp_tx.h"
19 #include "peer.h"
20 
21 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
22 
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)23 static u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
24 {
25 	return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
26 }
27 
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)28 static enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
29 							       struct hal_rx_desc *desc)
30 {
31 	if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
32 		return HAL_ENCRYPT_TYPE_OPEN;
33 
34 	return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
35 }
36 
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)37 static u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
38 					       struct hal_rx_desc *desc)
39 {
40 	return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
41 }
42 
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)43 static u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
44 						     struct hal_rx_desc *desc)
45 {
46 	return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
47 }
48 
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)49 static bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
50 						     struct hal_rx_desc *desc)
51 {
52 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
53 }
54 
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)55 static bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
56 					       struct hal_rx_desc *desc)
57 {
58 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
59 }
60 
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)61 static bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
62 						 struct sk_buff *skb)
63 {
64 	struct ieee80211_hdr *hdr;
65 
66 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
67 	return ieee80211_has_morefrags(hdr->frame_control);
68 }
69 
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)70 static u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
71 					     struct sk_buff *skb)
72 {
73 	struct ieee80211_hdr *hdr;
74 
75 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
76 	return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
77 }
78 
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)79 static u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
80 					    struct hal_rx_desc *desc)
81 {
82 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
83 }
84 
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)85 static void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
86 					struct hal_rx_desc *desc)
87 {
88 	return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
89 }
90 
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)91 static bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
92 {
93 	return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
94 			   __le32_to_cpu(attn->info2));
95 }
96 
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)97 static bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
98 {
99 	return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
100 			   __le32_to_cpu(attn->info1));
101 }
102 
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)103 static bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
104 {
105 	return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
106 			   __le32_to_cpu(attn->info1));
107 }
108 
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)109 static bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
110 {
111 	return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
112 			  __le32_to_cpu(attn->info2)) ==
113 		RX_DESC_DECRYPT_STATUS_CODE_OK);
114 }
115 
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)116 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
117 {
118 	u32 info = __le32_to_cpu(attn->info1);
119 	u32 errmap = 0;
120 
121 	if (info & RX_ATTENTION_INFO1_FCS_ERR)
122 		errmap |= DP_RX_MPDU_ERR_FCS;
123 
124 	if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
125 		errmap |= DP_RX_MPDU_ERR_DECRYPT;
126 
127 	if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
128 		errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
129 
130 	if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
131 		errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
132 
133 	if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
134 		errmap |= DP_RX_MPDU_ERR_OVERFLOW;
135 
136 	if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
137 		errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
138 
139 	if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
140 		errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
141 
142 	return errmap;
143 }
144 
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)145 static u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
146 					      struct hal_rx_desc *desc)
147 {
148 	return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
149 }
150 
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)151 static u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
152 					struct hal_rx_desc *desc)
153 {
154 	return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
155 }
156 
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
158 					     struct hal_rx_desc *desc)
159 {
160 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
161 }
162 
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)163 static u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
164 					  struct hal_rx_desc *desc)
165 {
166 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
167 }
168 
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
170 					  struct hal_rx_desc *desc)
171 {
172 	return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
173 }
174 
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
176 					     struct hal_rx_desc *desc)
177 {
178 	return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
179 }
180 
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
182 					struct hal_rx_desc *desc)
183 {
184 	return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
185 }
186 
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
188 					struct hal_rx_desc *desc)
189 {
190 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
191 }
192 
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
194 					     struct hal_rx_desc *desc)
195 {
196 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
197 }
198 
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
200 					struct hal_rx_desc *desc)
201 {
202 	return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
203 }
204 
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
206 					       struct hal_rx_desc *desc)
207 {
208 	return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
209 }
210 
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
212 					      struct hal_rx_desc *desc)
213 {
214 	return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
215 }
216 
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)217 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
218 					   struct hal_rx_desc *fdesc,
219 					   struct hal_rx_desc *ldesc)
220 {
221 	ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
222 }
223 
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)224 static u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
225 {
226 	return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
227 			 __le32_to_cpu(attn->info1));
228 }
229 
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)230 static u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
231 					 struct hal_rx_desc *rx_desc)
232 {
233 	u8 *rx_pkt_hdr;
234 
235 	rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
236 
237 	return rx_pkt_hdr;
238 }
239 
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)240 static bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
241 					struct hal_rx_desc *rx_desc)
242 {
243 	u32 tlv_tag;
244 
245 	tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
246 
247 	return tlv_tag == HAL_RX_MPDU_START;
248 }
249 
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)250 static u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
251 				       struct hal_rx_desc *rx_desc)
252 {
253 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
254 }
255 
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)256 static void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
257 					  struct hal_rx_desc *desc,
258 					  u16 len)
259 {
260 	ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
261 }
262 
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)263 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
264 					struct hal_rx_desc *desc)
265 {
266 	struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
267 
268 	return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
269 		(!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
270 		 __le32_to_cpu(attn->info1)));
271 }
272 
ath11k_dp_service_mon_ring(struct timer_list * t)273 static void ath11k_dp_service_mon_ring(struct timer_list *t)
274 {
275 	struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
276 	int i;
277 
278 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
279 		ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
280 
281 	mod_timer(&ab->mon_reap_timer, jiffies +
282 		  msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
283 }
284 
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)285 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
286 {
287 	int i, reaped = 0;
288 	unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
289 
290 	do {
291 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
292 			reaped += ath11k_dp_rx_process_mon_rings(ab, i,
293 								 NULL,
294 								 DP_MON_SERVICE_BUDGET);
295 
296 		/* nothing more to reap */
297 		if (reaped < DP_MON_SERVICE_BUDGET)
298 			return 0;
299 
300 	} while (time_before(jiffies, timeout));
301 
302 	ath11k_warn(ab, "dp mon ring purge timeout");
303 
304 	return -ETIMEDOUT;
305 }
306 
307 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)308 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
309 			       struct dp_rxdma_ring *rx_ring,
310 			       int req_entries,
311 			       enum hal_rx_buf_return_buf_manager mgr)
312 {
313 	struct hal_srng *srng;
314 	u32 *desc;
315 	struct sk_buff *skb;
316 	int num_free;
317 	int num_remain;
318 	int buf_id;
319 	u32 cookie;
320 	dma_addr_t paddr;
321 
322 	req_entries = min(req_entries, rx_ring->bufs_max);
323 
324 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
325 
326 	spin_lock_bh(&srng->lock);
327 
328 	ath11k_hal_srng_access_begin(ab, srng);
329 
330 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
331 	if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
332 		req_entries = num_free;
333 
334 	req_entries = min(num_free, req_entries);
335 	num_remain = req_entries;
336 
337 	while (num_remain > 0) {
338 		skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
339 				    DP_RX_BUFFER_ALIGN_SIZE);
340 		if (!skb)
341 			break;
342 
343 		if (!IS_ALIGNED((unsigned long)skb->data,
344 				DP_RX_BUFFER_ALIGN_SIZE)) {
345 			skb_pull(skb,
346 				 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
347 				 skb->data);
348 		}
349 
350 		paddr = dma_map_single(ab->dev, skb->data,
351 				       skb->len + skb_tailroom(skb),
352 				       DMA_FROM_DEVICE);
353 		if (dma_mapping_error(ab->dev, paddr))
354 			goto fail_free_skb;
355 
356 		spin_lock_bh(&rx_ring->idr_lock);
357 		buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
358 				   (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
359 		spin_unlock_bh(&rx_ring->idr_lock);
360 		if (buf_id <= 0)
361 			goto fail_dma_unmap;
362 
363 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
364 		if (!desc)
365 			goto fail_idr_remove;
366 
367 		ATH11K_SKB_RXCB(skb)->paddr = paddr;
368 
369 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
370 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
371 
372 		num_remain--;
373 
374 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
375 	}
376 
377 	ath11k_hal_srng_access_end(ab, srng);
378 
379 	spin_unlock_bh(&srng->lock);
380 
381 	return req_entries - num_remain;
382 
383 fail_idr_remove:
384 	spin_lock_bh(&rx_ring->idr_lock);
385 	idr_remove(&rx_ring->bufs_idr, buf_id);
386 	spin_unlock_bh(&rx_ring->idr_lock);
387 fail_dma_unmap:
388 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
389 			 DMA_FROM_DEVICE);
390 fail_free_skb:
391 	dev_kfree_skb_any(skb);
392 
393 	ath11k_hal_srng_access_end(ab, srng);
394 
395 	spin_unlock_bh(&srng->lock);
396 
397 	return req_entries - num_remain;
398 }
399 
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)400 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
401 					 struct dp_rxdma_ring *rx_ring)
402 {
403 	struct ath11k_pdev_dp *dp = &ar->dp;
404 	struct sk_buff *skb;
405 	int buf_id;
406 
407 	spin_lock_bh(&rx_ring->idr_lock);
408 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
409 		idr_remove(&rx_ring->bufs_idr, buf_id);
410 		/* TODO: Understand where internal driver does this dma_unmap
411 		 * of rxdma_buffer.
412 		 */
413 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
414 				 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
415 		dev_kfree_skb_any(skb);
416 	}
417 
418 	idr_destroy(&rx_ring->bufs_idr);
419 	spin_unlock_bh(&rx_ring->idr_lock);
420 
421 	/* if rxdma1_enable is false, mon_status_refill_ring
422 	 * isn't setup, so don't clean.
423 	 */
424 	if (!ar->ab->hw_params.rxdma1_enable)
425 		return 0;
426 
427 	rx_ring = &dp->rx_mon_status_refill_ring[0];
428 
429 	spin_lock_bh(&rx_ring->idr_lock);
430 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
431 		idr_remove(&rx_ring->bufs_idr, buf_id);
432 		/* XXX: Understand where internal driver does this dma_unmap
433 		 * of rxdma_buffer.
434 		 */
435 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
436 				 skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL);
437 		dev_kfree_skb_any(skb);
438 	}
439 
440 	idr_destroy(&rx_ring->bufs_idr);
441 	spin_unlock_bh(&rx_ring->idr_lock);
442 
443 	return 0;
444 }
445 
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)446 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
447 {
448 	struct ath11k_pdev_dp *dp = &ar->dp;
449 	struct ath11k_base *ab = ar->ab;
450 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
451 	int i;
452 
453 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
454 
455 	rx_ring = &dp->rxdma_mon_buf_ring;
456 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
457 
458 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
459 		rx_ring = &dp->rx_mon_status_refill_ring[i];
460 		ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
461 	}
462 
463 	return 0;
464 }
465 
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)466 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
467 					  struct dp_rxdma_ring *rx_ring,
468 					  u32 ringtype)
469 {
470 	struct ath11k_pdev_dp *dp = &ar->dp;
471 	int num_entries;
472 
473 	num_entries = rx_ring->refill_buf_ring.size /
474 		ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
475 
476 	rx_ring->bufs_max = num_entries;
477 	ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
478 				   HAL_RX_BUF_RBM_SW3_BM);
479 	return 0;
480 }
481 
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)482 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
483 {
484 	struct ath11k_pdev_dp *dp = &ar->dp;
485 	struct ath11k_base *ab = ar->ab;
486 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
487 	int i;
488 
489 	ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
490 
491 	if (ar->ab->hw_params.rxdma1_enable) {
492 		rx_ring = &dp->rxdma_mon_buf_ring;
493 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
494 	}
495 
496 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
497 		rx_ring = &dp->rx_mon_status_refill_ring[i];
498 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
499 	}
500 
501 	return 0;
502 }
503 
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)504 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
505 {
506 	struct ath11k_pdev_dp *dp = &ar->dp;
507 	struct ath11k_base *ab = ar->ab;
508 	int i;
509 
510 	ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
511 
512 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
513 		if (ab->hw_params.rx_mac_buf_ring)
514 			ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
515 
516 		ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
517 		ath11k_dp_srng_cleanup(ab,
518 				       &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
519 	}
520 
521 	ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
522 }
523 
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)524 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
525 {
526 	struct ath11k_dp *dp = &ab->dp;
527 	int i;
528 
529 	for (i = 0; i < DP_REO_DST_RING_MAX; i++)
530 		ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
531 }
532 
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)533 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
534 {
535 	struct ath11k_dp *dp = &ab->dp;
536 	int ret;
537 	int i;
538 
539 	for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
540 		ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
541 					   HAL_REO_DST, i, 0,
542 					   DP_REO_DST_RING_SIZE);
543 		if (ret) {
544 			ath11k_warn(ab, "failed to setup reo_dst_ring\n");
545 			goto err_reo_cleanup;
546 		}
547 	}
548 
549 	return 0;
550 
551 err_reo_cleanup:
552 	ath11k_dp_pdev_reo_cleanup(ab);
553 
554 	return ret;
555 }
556 
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)557 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
558 {
559 	struct ath11k_pdev_dp *dp = &ar->dp;
560 	struct ath11k_base *ab = ar->ab;
561 	struct dp_srng *srng = NULL;
562 	int i;
563 	int ret;
564 
565 	ret = ath11k_dp_srng_setup(ar->ab,
566 				   &dp->rx_refill_buf_ring.refill_buf_ring,
567 				   HAL_RXDMA_BUF, 0,
568 				   dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
569 	if (ret) {
570 		ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
571 		return ret;
572 	}
573 
574 	if (ar->ab->hw_params.rx_mac_buf_ring) {
575 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
576 			ret = ath11k_dp_srng_setup(ar->ab,
577 						   &dp->rx_mac_buf_ring[i],
578 						   HAL_RXDMA_BUF, 1,
579 						   dp->mac_id + i, 1024);
580 			if (ret) {
581 				ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
582 					    i);
583 				return ret;
584 			}
585 		}
586 	}
587 
588 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
589 		ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
590 					   HAL_RXDMA_DST, 0, dp->mac_id + i,
591 					   DP_RXDMA_ERR_DST_RING_SIZE);
592 		if (ret) {
593 			ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
594 			return ret;
595 		}
596 	}
597 
598 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
599 		srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
600 		ret = ath11k_dp_srng_setup(ar->ab,
601 					   srng,
602 					   HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
603 					   DP_RXDMA_MON_STATUS_RING_SIZE);
604 		if (ret) {
605 			ath11k_warn(ar->ab,
606 				    "failed to setup rx_mon_status_refill_ring %d\n", i);
607 			return ret;
608 		}
609 	}
610 
611 	/* if rxdma1_enable is false, then it doesn't need
612 	 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
613 	 * and rxdma_mon_desc_ring.
614 	 * init reap timer for QCA6390.
615 	 */
616 	if (!ar->ab->hw_params.rxdma1_enable) {
617 		//init mon status buffer reap timer
618 		timer_setup(&ar->ab->mon_reap_timer,
619 			    ath11k_dp_service_mon_ring, 0);
620 		return 0;
621 	}
622 
623 	ret = ath11k_dp_srng_setup(ar->ab,
624 				   &dp->rxdma_mon_buf_ring.refill_buf_ring,
625 				   HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
626 				   DP_RXDMA_MONITOR_BUF_RING_SIZE);
627 	if (ret) {
628 		ath11k_warn(ar->ab,
629 			    "failed to setup HAL_RXDMA_MONITOR_BUF\n");
630 		return ret;
631 	}
632 
633 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
634 				   HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
635 				   DP_RXDMA_MONITOR_DST_RING_SIZE);
636 	if (ret) {
637 		ath11k_warn(ar->ab,
638 			    "failed to setup HAL_RXDMA_MONITOR_DST\n");
639 		return ret;
640 	}
641 
642 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
643 				   HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
644 				   DP_RXDMA_MONITOR_DESC_RING_SIZE);
645 	if (ret) {
646 		ath11k_warn(ar->ab,
647 			    "failed to setup HAL_RXDMA_MONITOR_DESC\n");
648 		return ret;
649 	}
650 
651 	return 0;
652 }
653 
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)654 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
655 {
656 	struct ath11k_dp *dp = &ab->dp;
657 	struct dp_reo_cmd *cmd, *tmp;
658 	struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
659 
660 	spin_lock_bh(&dp->reo_cmd_lock);
661 	list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
662 		list_del(&cmd->list);
663 		dma_unmap_single(ab->dev, cmd->data.paddr,
664 				 cmd->data.size, DMA_BIDIRECTIONAL);
665 		kfree(cmd->data.vaddr);
666 		kfree(cmd);
667 	}
668 
669 	list_for_each_entry_safe(cmd_cache, tmp_cache,
670 				 &dp->reo_cmd_cache_flush_list, list) {
671 		list_del(&cmd_cache->list);
672 		dp->reo_cmd_cache_flush_count--;
673 		dma_unmap_single(ab->dev, cmd_cache->data.paddr,
674 				 cmd_cache->data.size, DMA_BIDIRECTIONAL);
675 		kfree(cmd_cache->data.vaddr);
676 		kfree(cmd_cache);
677 	}
678 	spin_unlock_bh(&dp->reo_cmd_lock);
679 }
680 
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)681 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
682 				   enum hal_reo_cmd_status status)
683 {
684 	struct dp_rx_tid *rx_tid = ctx;
685 
686 	if (status != HAL_REO_CMD_SUCCESS)
687 		ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
688 			    rx_tid->tid, status);
689 
690 	dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
691 			 DMA_BIDIRECTIONAL);
692 	kfree(rx_tid->vaddr);
693 }
694 
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)695 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
696 				      struct dp_rx_tid *rx_tid)
697 {
698 	struct ath11k_hal_reo_cmd cmd = {0};
699 	unsigned long tot_desc_sz, desc_sz;
700 	int ret;
701 
702 	tot_desc_sz = rx_tid->size;
703 	desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
704 
705 	while (tot_desc_sz > desc_sz) {
706 		tot_desc_sz -= desc_sz;
707 		cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
708 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
709 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
710 						HAL_REO_CMD_FLUSH_CACHE, &cmd,
711 						NULL);
712 		if (ret)
713 			ath11k_warn(ab,
714 				    "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
715 				    rx_tid->tid, ret);
716 	}
717 
718 	memset(&cmd, 0, sizeof(cmd));
719 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
720 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
721 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
722 	ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
723 					HAL_REO_CMD_FLUSH_CACHE,
724 					&cmd, ath11k_dp_reo_cmd_free);
725 	if (ret) {
726 		ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
727 			   rx_tid->tid, ret);
728 		dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
729 				 DMA_BIDIRECTIONAL);
730 		kfree(rx_tid->vaddr);
731 	}
732 }
733 
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)734 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
735 				      enum hal_reo_cmd_status status)
736 {
737 	struct ath11k_base *ab = dp->ab;
738 	struct dp_rx_tid *rx_tid = ctx;
739 	struct dp_reo_cache_flush_elem *elem, *tmp;
740 
741 	if (status == HAL_REO_CMD_DRAIN) {
742 		goto free_desc;
743 	} else if (status != HAL_REO_CMD_SUCCESS) {
744 		/* Shouldn't happen! Cleanup in case of other failure? */
745 		ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
746 			    rx_tid->tid, status);
747 		return;
748 	}
749 
750 	elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
751 	if (!elem)
752 		goto free_desc;
753 
754 	elem->ts = jiffies;
755 	memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
756 
757 	spin_lock_bh(&dp->reo_cmd_lock);
758 	list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
759 	dp->reo_cmd_cache_flush_count++;
760 
761 	/* Flush and invalidate aged REO desc from HW cache */
762 	list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
763 				 list) {
764 		if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
765 		    time_after(jiffies, elem->ts +
766 			       msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
767 			list_del(&elem->list);
768 			dp->reo_cmd_cache_flush_count--;
769 			spin_unlock_bh(&dp->reo_cmd_lock);
770 
771 			ath11k_dp_reo_cache_flush(ab, &elem->data);
772 			kfree(elem);
773 			spin_lock_bh(&dp->reo_cmd_lock);
774 		}
775 	}
776 	spin_unlock_bh(&dp->reo_cmd_lock);
777 
778 	return;
779 free_desc:
780 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
781 			 DMA_BIDIRECTIONAL);
782 	kfree(rx_tid->vaddr);
783 }
784 
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)785 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
786 			       struct ath11k_peer *peer, u8 tid)
787 {
788 	struct ath11k_hal_reo_cmd cmd = {0};
789 	struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
790 	int ret;
791 
792 	if (!rx_tid->active)
793 		return;
794 
795 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
796 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
797 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
798 	cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
799 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
800 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
801 					ath11k_dp_rx_tid_del_func);
802 	if (ret) {
803 		ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
804 			   tid, ret);
805 		dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
806 				 DMA_BIDIRECTIONAL);
807 		kfree(rx_tid->vaddr);
808 	}
809 
810 	rx_tid->active = false;
811 }
812 
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)813 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
814 					 u32 *link_desc,
815 					 enum hal_wbm_rel_bm_act action)
816 {
817 	struct ath11k_dp *dp = &ab->dp;
818 	struct hal_srng *srng;
819 	u32 *desc;
820 	int ret = 0;
821 
822 	srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
823 
824 	spin_lock_bh(&srng->lock);
825 
826 	ath11k_hal_srng_access_begin(ab, srng);
827 
828 	desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
829 	if (!desc) {
830 		ret = -ENOBUFS;
831 		goto exit;
832 	}
833 
834 	ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
835 					 action);
836 
837 exit:
838 	ath11k_hal_srng_access_end(ab, srng);
839 
840 	spin_unlock_bh(&srng->lock);
841 
842 	return ret;
843 }
844 
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)845 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
846 {
847 	struct ath11k_base *ab = rx_tid->ab;
848 
849 	lockdep_assert_held(&ab->base_lock);
850 
851 	if (rx_tid->dst_ring_desc) {
852 		if (rel_link_desc)
853 			ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
854 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
855 		kfree(rx_tid->dst_ring_desc);
856 		rx_tid->dst_ring_desc = NULL;
857 	}
858 
859 	rx_tid->cur_sn = 0;
860 	rx_tid->last_frag_no = 0;
861 	rx_tid->rx_frag_bitmap = 0;
862 	__skb_queue_purge(&rx_tid->rx_frags);
863 }
864 
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)865 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
866 {
867 	struct dp_rx_tid *rx_tid;
868 	int i;
869 
870 	lockdep_assert_held(&ar->ab->base_lock);
871 
872 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
873 		rx_tid = &peer->rx_tid[i];
874 
875 		spin_unlock_bh(&ar->ab->base_lock);
876 		del_timer_sync(&rx_tid->frag_timer);
877 		spin_lock_bh(&ar->ab->base_lock);
878 
879 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
880 	}
881 }
882 
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)883 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
884 {
885 	struct dp_rx_tid *rx_tid;
886 	int i;
887 
888 	lockdep_assert_held(&ar->ab->base_lock);
889 
890 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
891 		rx_tid = &peer->rx_tid[i];
892 
893 		ath11k_peer_rx_tid_delete(ar, peer, i);
894 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
895 
896 		spin_unlock_bh(&ar->ab->base_lock);
897 		del_timer_sync(&rx_tid->frag_timer);
898 		spin_lock_bh(&ar->ab->base_lock);
899 	}
900 }
901 
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)902 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
903 					 struct ath11k_peer *peer,
904 					 struct dp_rx_tid *rx_tid,
905 					 u32 ba_win_sz, u16 ssn,
906 					 bool update_ssn)
907 {
908 	struct ath11k_hal_reo_cmd cmd = {0};
909 	int ret;
910 
911 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
912 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
913 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
914 	cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
915 	cmd.ba_window_size = ba_win_sz;
916 
917 	if (update_ssn) {
918 		cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
919 		cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
920 	}
921 
922 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
923 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
924 					NULL);
925 	if (ret) {
926 		ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
927 			    rx_tid->tid, ret);
928 		return ret;
929 	}
930 
931 	rx_tid->ba_win_sz = ba_win_sz;
932 
933 	return 0;
934 }
935 
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)936 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
937 				      const u8 *peer_mac, int vdev_id, u8 tid)
938 {
939 	struct ath11k_peer *peer;
940 	struct dp_rx_tid *rx_tid;
941 
942 	spin_lock_bh(&ab->base_lock);
943 
944 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
945 	if (!peer) {
946 		ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
947 		goto unlock_exit;
948 	}
949 
950 	rx_tid = &peer->rx_tid[tid];
951 	if (!rx_tid->active)
952 		goto unlock_exit;
953 
954 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
955 			 DMA_BIDIRECTIONAL);
956 	kfree(rx_tid->vaddr);
957 
958 	rx_tid->active = false;
959 
960 unlock_exit:
961 	spin_unlock_bh(&ab->base_lock);
962 }
963 
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)964 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
965 			     u8 tid, u32 ba_win_sz, u16 ssn,
966 			     enum hal_pn_type pn_type)
967 {
968 	struct ath11k_base *ab = ar->ab;
969 	struct ath11k_peer *peer;
970 	struct dp_rx_tid *rx_tid;
971 	u32 hw_desc_sz;
972 	u32 *addr_aligned;
973 	void *vaddr;
974 	dma_addr_t paddr;
975 	int ret;
976 
977 	spin_lock_bh(&ab->base_lock);
978 
979 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
980 	if (!peer) {
981 		ath11k_warn(ab, "failed to find the peer to set up rx tid\n");
982 		spin_unlock_bh(&ab->base_lock);
983 		return -ENOENT;
984 	}
985 
986 	rx_tid = &peer->rx_tid[tid];
987 	/* Update the tid queue if it is already setup */
988 	if (rx_tid->active) {
989 		paddr = rx_tid->paddr;
990 		ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
991 						    ba_win_sz, ssn, true);
992 		spin_unlock_bh(&ab->base_lock);
993 		if (ret) {
994 			ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid);
995 			return ret;
996 		}
997 
998 		ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
999 							     peer_mac, paddr,
1000 							     tid, 1, ba_win_sz);
1001 		if (ret)
1002 			ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n",
1003 				    tid, ret);
1004 		return ret;
1005 	}
1006 
1007 	rx_tid->tid = tid;
1008 
1009 	rx_tid->ba_win_sz = ba_win_sz;
1010 
1011 	/* TODO: Optimize the memory allocation for qos tid based on
1012 	 * the actual BA window size in REO tid update path.
1013 	 */
1014 	if (tid == HAL_DESC_REO_NON_QOS_TID)
1015 		hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1016 	else
1017 		hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1018 
1019 	vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
1020 	if (!vaddr) {
1021 		spin_unlock_bh(&ab->base_lock);
1022 		return -ENOMEM;
1023 	}
1024 
1025 	addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
1026 
1027 	ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
1028 				   ssn, pn_type);
1029 
1030 	paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1031 			       DMA_BIDIRECTIONAL);
1032 
1033 	ret = dma_mapping_error(ab->dev, paddr);
1034 	if (ret) {
1035 		spin_unlock_bh(&ab->base_lock);
1036 		goto err_mem_free;
1037 	}
1038 
1039 	rx_tid->vaddr = vaddr;
1040 	rx_tid->paddr = paddr;
1041 	rx_tid->size = hw_desc_sz;
1042 	rx_tid->active = true;
1043 
1044 	spin_unlock_bh(&ab->base_lock);
1045 
1046 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1047 						     paddr, tid, 1, ba_win_sz);
1048 	if (ret) {
1049 		ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n",
1050 			    tid, ret);
1051 		ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1052 	}
1053 
1054 	return ret;
1055 
1056 err_mem_free:
1057 	kfree(vaddr);
1058 
1059 	return ret;
1060 }
1061 
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1062 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1063 			     struct ieee80211_ampdu_params *params)
1064 {
1065 	struct ath11k_base *ab = ar->ab;
1066 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1067 	int vdev_id = arsta->arvif->vdev_id;
1068 	int ret;
1069 
1070 	ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1071 				       params->tid, params->buf_size,
1072 				       params->ssn, arsta->pn_type);
1073 	if (ret)
1074 		ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1075 
1076 	return ret;
1077 }
1078 
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1079 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1080 			    struct ieee80211_ampdu_params *params)
1081 {
1082 	struct ath11k_base *ab = ar->ab;
1083 	struct ath11k_peer *peer;
1084 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1085 	int vdev_id = arsta->arvif->vdev_id;
1086 	dma_addr_t paddr;
1087 	bool active;
1088 	int ret;
1089 
1090 	spin_lock_bh(&ab->base_lock);
1091 
1092 	peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1093 	if (!peer) {
1094 		ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1095 		spin_unlock_bh(&ab->base_lock);
1096 		return -ENOENT;
1097 	}
1098 
1099 	paddr = peer->rx_tid[params->tid].paddr;
1100 	active = peer->rx_tid[params->tid].active;
1101 
1102 	if (!active) {
1103 		spin_unlock_bh(&ab->base_lock);
1104 		return 0;
1105 	}
1106 
1107 	ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1108 	spin_unlock_bh(&ab->base_lock);
1109 	if (ret) {
1110 		ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1111 			    params->tid, ret);
1112 		return ret;
1113 	}
1114 
1115 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1116 						     params->sta->addr, paddr,
1117 						     params->tid, 1, 1);
1118 	if (ret)
1119 		ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1120 			    ret);
1121 
1122 	return ret;
1123 }
1124 
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1125 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1126 				       const u8 *peer_addr,
1127 				       enum set_key_cmd key_cmd,
1128 				       struct ieee80211_key_conf *key)
1129 {
1130 	struct ath11k *ar = arvif->ar;
1131 	struct ath11k_base *ab = ar->ab;
1132 	struct ath11k_hal_reo_cmd cmd = {0};
1133 	struct ath11k_peer *peer;
1134 	struct dp_rx_tid *rx_tid;
1135 	u8 tid;
1136 	int ret = 0;
1137 
1138 	/* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1139 	 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1140 	 * for now.
1141 	 */
1142 	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1143 		return 0;
1144 
1145 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1146 	cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1147 		    HAL_REO_CMD_UPD0_PN_SIZE |
1148 		    HAL_REO_CMD_UPD0_PN_VALID |
1149 		    HAL_REO_CMD_UPD0_PN_CHECK |
1150 		    HAL_REO_CMD_UPD0_SVLD;
1151 
1152 	switch (key->cipher) {
1153 	case WLAN_CIPHER_SUITE_TKIP:
1154 	case WLAN_CIPHER_SUITE_CCMP:
1155 	case WLAN_CIPHER_SUITE_CCMP_256:
1156 	case WLAN_CIPHER_SUITE_GCMP:
1157 	case WLAN_CIPHER_SUITE_GCMP_256:
1158 		if (key_cmd == SET_KEY) {
1159 			cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1160 			cmd.pn_size = 48;
1161 		}
1162 		break;
1163 	default:
1164 		break;
1165 	}
1166 
1167 	spin_lock_bh(&ab->base_lock);
1168 
1169 	peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1170 	if (!peer) {
1171 		ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1172 		spin_unlock_bh(&ab->base_lock);
1173 		return -ENOENT;
1174 	}
1175 
1176 	for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1177 		rx_tid = &peer->rx_tid[tid];
1178 		if (!rx_tid->active)
1179 			continue;
1180 		cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1181 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1182 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1183 						HAL_REO_CMD_UPDATE_RX_QUEUE,
1184 						&cmd, NULL);
1185 		if (ret) {
1186 			ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1187 				    tid, ret);
1188 			break;
1189 		}
1190 	}
1191 
1192 	spin_unlock_bh(&ab->base_lock);
1193 
1194 	return ret;
1195 }
1196 
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1197 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1198 					     u16 peer_id)
1199 {
1200 	int i;
1201 
1202 	for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1203 		if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1204 			if (peer_id == ppdu_stats->user_stats[i].peer_id)
1205 				return i;
1206 		} else {
1207 			return i;
1208 		}
1209 	}
1210 
1211 	return -EINVAL;
1212 }
1213 
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1214 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1215 					   u16 tag, u16 len, const void *ptr,
1216 					   void *data)
1217 {
1218 	struct htt_ppdu_stats_info *ppdu_info;
1219 	struct htt_ppdu_user_stats *user_stats;
1220 	int cur_user;
1221 	u16 peer_id;
1222 
1223 	ppdu_info = (struct htt_ppdu_stats_info *)data;
1224 
1225 	switch (tag) {
1226 	case HTT_PPDU_STATS_TAG_COMMON:
1227 		if (len < sizeof(struct htt_ppdu_stats_common)) {
1228 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1229 				    len, tag);
1230 			return -EINVAL;
1231 		}
1232 		memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1233 		       sizeof(struct htt_ppdu_stats_common));
1234 		break;
1235 	case HTT_PPDU_STATS_TAG_USR_RATE:
1236 		if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1237 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1238 				    len, tag);
1239 			return -EINVAL;
1240 		}
1241 
1242 		peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1243 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1244 						      peer_id);
1245 		if (cur_user < 0)
1246 			return -EINVAL;
1247 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1248 		user_stats->peer_id = peer_id;
1249 		user_stats->is_valid_peer_id = true;
1250 		memcpy((void *)&user_stats->rate, ptr,
1251 		       sizeof(struct htt_ppdu_stats_user_rate));
1252 		user_stats->tlv_flags |= BIT(tag);
1253 		break;
1254 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1255 		if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1256 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1257 				    len, tag);
1258 			return -EINVAL;
1259 		}
1260 
1261 		peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1262 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1263 						      peer_id);
1264 		if (cur_user < 0)
1265 			return -EINVAL;
1266 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1267 		user_stats->peer_id = peer_id;
1268 		user_stats->is_valid_peer_id = true;
1269 		memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1270 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1271 		user_stats->tlv_flags |= BIT(tag);
1272 		break;
1273 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1274 		if (len <
1275 		    sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1276 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1277 				    len, tag);
1278 			return -EINVAL;
1279 		}
1280 
1281 		peer_id =
1282 		((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1283 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1284 						      peer_id);
1285 		if (cur_user < 0)
1286 			return -EINVAL;
1287 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1288 		user_stats->peer_id = peer_id;
1289 		user_stats->is_valid_peer_id = true;
1290 		memcpy((void *)&user_stats->ack_ba, ptr,
1291 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1292 		user_stats->tlv_flags |= BIT(tag);
1293 		break;
1294 	}
1295 	return 0;
1296 }
1297 
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1298 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1299 			   int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1300 				       const void *ptr, void *data),
1301 			   void *data)
1302 {
1303 	const struct htt_tlv *tlv;
1304 	const void *begin = ptr;
1305 	u16 tlv_tag, tlv_len;
1306 	int ret = -EINVAL;
1307 
1308 	while (len > 0) {
1309 		if (len < sizeof(*tlv)) {
1310 			ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1311 				   ptr - begin, len, sizeof(*tlv));
1312 			return -EINVAL;
1313 		}
1314 		tlv = (struct htt_tlv *)ptr;
1315 		tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1316 		tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1317 		ptr += sizeof(*tlv);
1318 		len -= sizeof(*tlv);
1319 
1320 		if (tlv_len > len) {
1321 			ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1322 				   tlv_tag, ptr - begin, len, tlv_len);
1323 			return -EINVAL;
1324 		}
1325 		ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1326 		if (ret == -ENOMEM)
1327 			return ret;
1328 
1329 		ptr += tlv_len;
1330 		len -= tlv_len;
1331 	}
1332 	return 0;
1333 }
1334 
ath11k_he_gi_to_nl80211_he_gi(u8 sgi)1335 static inline u32 ath11k_he_gi_to_nl80211_he_gi(u8 sgi)
1336 {
1337 	u32 ret = 0;
1338 
1339 	switch (sgi) {
1340 	case RX_MSDU_START_SGI_0_8_US:
1341 		ret = NL80211_RATE_INFO_HE_GI_0_8;
1342 		break;
1343 	case RX_MSDU_START_SGI_1_6_US:
1344 		ret = NL80211_RATE_INFO_HE_GI_1_6;
1345 		break;
1346 	case RX_MSDU_START_SGI_3_2_US:
1347 		ret = NL80211_RATE_INFO_HE_GI_3_2;
1348 		break;
1349 	}
1350 
1351 	return ret;
1352 }
1353 
1354 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1355 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1356 				struct htt_ppdu_stats *ppdu_stats, u8 user)
1357 {
1358 	struct ath11k_base *ab = ar->ab;
1359 	struct ath11k_peer *peer;
1360 	struct ieee80211_sta *sta;
1361 	struct ath11k_sta *arsta;
1362 	struct htt_ppdu_stats_user_rate *user_rate;
1363 	struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1364 	struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1365 	struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1366 	int ret;
1367 	u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1368 	u32 succ_bytes = 0;
1369 	u16 rate = 0, succ_pkts = 0;
1370 	u32 tx_duration = 0;
1371 	u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1372 	bool is_ampdu = false;
1373 
1374 	if (!usr_stats)
1375 		return;
1376 
1377 	if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1378 		return;
1379 
1380 	if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1381 		is_ampdu =
1382 			HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1383 
1384 	if (usr_stats->tlv_flags &
1385 	    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1386 		succ_bytes = usr_stats->ack_ba.success_bytes;
1387 		succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1388 				      usr_stats->ack_ba.info);
1389 		tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1390 				usr_stats->ack_ba.info);
1391 	}
1392 
1393 	if (common->fes_duration_us)
1394 		tx_duration = common->fes_duration_us;
1395 
1396 	user_rate = &usr_stats->rate;
1397 	flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1398 	bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1399 	nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1400 	mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1401 	sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1402 	dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1403 
1404 	/* Note: If host configured fixed rates and in some other special
1405 	 * cases, the broadcast/management frames are sent in different rates.
1406 	 * Firmware rate's control to be skipped for this?
1407 	 */
1408 
1409 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1410 		ath11k_warn(ab, "Invalid HE mcs %d peer stats",  mcs);
1411 		return;
1412 	}
1413 
1414 	if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1415 		ath11k_warn(ab, "Invalid VHT mcs %d peer stats",  mcs);
1416 		return;
1417 	}
1418 
1419 	if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1420 		ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1421 			    mcs, nss);
1422 		return;
1423 	}
1424 
1425 	if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1426 		ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1427 							    flags,
1428 							    &rate_idx,
1429 							    &rate);
1430 		if (ret < 0)
1431 			return;
1432 	}
1433 
1434 	rcu_read_lock();
1435 	spin_lock_bh(&ab->base_lock);
1436 	peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1437 
1438 	if (!peer || !peer->sta) {
1439 		spin_unlock_bh(&ab->base_lock);
1440 		rcu_read_unlock();
1441 		return;
1442 	}
1443 
1444 	sta = peer->sta;
1445 	arsta = (struct ath11k_sta *)sta->drv_priv;
1446 
1447 	memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1448 
1449 	switch (flags) {
1450 	case WMI_RATE_PREAMBLE_OFDM:
1451 		arsta->txrate.legacy = rate;
1452 		break;
1453 	case WMI_RATE_PREAMBLE_CCK:
1454 		arsta->txrate.legacy = rate;
1455 		break;
1456 	case WMI_RATE_PREAMBLE_HT:
1457 		arsta->txrate.mcs = mcs + 8 * (nss - 1);
1458 		arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1459 		if (sgi)
1460 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1461 		break;
1462 	case WMI_RATE_PREAMBLE_VHT:
1463 		arsta->txrate.mcs = mcs;
1464 		arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1465 		if (sgi)
1466 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1467 		break;
1468 	case WMI_RATE_PREAMBLE_HE:
1469 		arsta->txrate.mcs = mcs;
1470 		arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1471 		arsta->txrate.he_dcm = dcm;
1472 		arsta->txrate.he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
1473 		arsta->txrate.he_ru_alloc = ath11k_he_ru_tones_to_nl80211_he_ru_alloc(
1474 						(user_rate->ru_end -
1475 						 user_rate->ru_start) + 1);
1476 		break;
1477 	}
1478 
1479 	arsta->txrate.nss = nss;
1480 	arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1481 	arsta->tx_duration += tx_duration;
1482 	memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1483 
1484 	/* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1485 	 * So skip peer stats update for mgmt packets.
1486 	 */
1487 	if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1488 		memset(peer_stats, 0, sizeof(*peer_stats));
1489 		peer_stats->succ_pkts = succ_pkts;
1490 		peer_stats->succ_bytes = succ_bytes;
1491 		peer_stats->is_ampdu = is_ampdu;
1492 		peer_stats->duration = tx_duration;
1493 		peer_stats->ba_fails =
1494 			HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1495 			HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1496 
1497 		if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1498 			ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1499 	}
1500 
1501 	spin_unlock_bh(&ab->base_lock);
1502 	rcu_read_unlock();
1503 }
1504 
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1505 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1506 					 struct htt_ppdu_stats *ppdu_stats)
1507 {
1508 	u8 user;
1509 
1510 	for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1511 		ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1512 }
1513 
1514 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1515 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1516 							u32 ppdu_id)
1517 {
1518 	struct htt_ppdu_stats_info *ppdu_info;
1519 
1520 	spin_lock_bh(&ar->data_lock);
1521 	if (!list_empty(&ar->ppdu_stats_info)) {
1522 		list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1523 			if (ppdu_info->ppdu_id == ppdu_id) {
1524 				spin_unlock_bh(&ar->data_lock);
1525 				return ppdu_info;
1526 			}
1527 		}
1528 
1529 		if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1530 			ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1531 						     typeof(*ppdu_info), list);
1532 			list_del(&ppdu_info->list);
1533 			ar->ppdu_stat_list_depth--;
1534 			ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1535 			kfree(ppdu_info);
1536 		}
1537 	}
1538 	spin_unlock_bh(&ar->data_lock);
1539 
1540 	ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1541 	if (!ppdu_info)
1542 		return NULL;
1543 
1544 	spin_lock_bh(&ar->data_lock);
1545 	list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1546 	ar->ppdu_stat_list_depth++;
1547 	spin_unlock_bh(&ar->data_lock);
1548 
1549 	return ppdu_info;
1550 }
1551 
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1552 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1553 				      struct sk_buff *skb)
1554 {
1555 	struct ath11k_htt_ppdu_stats_msg *msg;
1556 	struct htt_ppdu_stats_info *ppdu_info;
1557 	struct ath11k *ar;
1558 	int ret;
1559 	u8 pdev_id;
1560 	u32 ppdu_id, len;
1561 
1562 	msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1563 	len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1564 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1565 	ppdu_id = msg->ppdu_id;
1566 
1567 	rcu_read_lock();
1568 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1569 	if (!ar) {
1570 		ret = -EINVAL;
1571 		goto exit;
1572 	}
1573 
1574 	if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1575 		trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1576 
1577 	ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1578 	if (!ppdu_info) {
1579 		ret = -EINVAL;
1580 		goto exit;
1581 	}
1582 
1583 	ppdu_info->ppdu_id = ppdu_id;
1584 	ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1585 				     ath11k_htt_tlv_ppdu_stats_parse,
1586 				     (void *)ppdu_info);
1587 	if (ret) {
1588 		ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1589 		goto exit;
1590 	}
1591 
1592 exit:
1593 	rcu_read_unlock();
1594 
1595 	return ret;
1596 }
1597 
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1598 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1599 {
1600 	struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1601 	struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1602 	struct ath11k *ar;
1603 	u8 pdev_id;
1604 
1605 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1606 
1607 	rcu_read_lock();
1608 
1609 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1610 	if (!ar) {
1611 		ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1612 		goto out;
1613 	}
1614 
1615 	trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1616 				ar->ab->pktlog_defs_checksum);
1617 
1618 out:
1619 	rcu_read_unlock();
1620 }
1621 
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1622 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1623 						  struct sk_buff *skb)
1624 {
1625 	u32 *data = (u32 *)skb->data;
1626 	u8 pdev_id, ring_type, ring_id, pdev_idx;
1627 	u16 hp, tp;
1628 	u32 backpressure_time;
1629 	struct ath11k_bp_stats *bp_stats;
1630 
1631 	pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1632 	ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1633 	ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1634 	++data;
1635 
1636 	hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1637 	tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1638 	++data;
1639 
1640 	backpressure_time = *data;
1641 
1642 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1643 		   pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1644 
1645 	if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1646 		if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1647 			return;
1648 
1649 		bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1650 	} else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1651 		pdev_idx = DP_HW2SW_MACID(pdev_id);
1652 
1653 		if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1654 			return;
1655 
1656 		bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1657 	} else {
1658 		ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1659 			    ring_type);
1660 		return;
1661 	}
1662 
1663 	spin_lock_bh(&ab->base_lock);
1664 	bp_stats->hp = hp;
1665 	bp_stats->tp = tp;
1666 	bp_stats->count++;
1667 	bp_stats->jiffies = jiffies;
1668 	spin_unlock_bh(&ab->base_lock);
1669 }
1670 
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1671 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1672 				       struct sk_buff *skb)
1673 {
1674 	struct ath11k_dp *dp = &ab->dp;
1675 	struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1676 	enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1677 	u16 peer_id;
1678 	u8 vdev_id;
1679 	u8 mac_addr[ETH_ALEN];
1680 	u16 peer_mac_h16;
1681 	u16 ast_hash;
1682 	u16 hw_peer_id;
1683 
1684 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1685 
1686 	switch (type) {
1687 	case HTT_T2H_MSG_TYPE_VERSION_CONF:
1688 		dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1689 						  resp->version_msg.version);
1690 		dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1691 						  resp->version_msg.version);
1692 		complete(&dp->htt_tgt_version_received);
1693 		break;
1694 	case HTT_T2H_MSG_TYPE_PEER_MAP:
1695 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1696 				    resp->peer_map_ev.info);
1697 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1698 				    resp->peer_map_ev.info);
1699 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1700 					 resp->peer_map_ev.info1);
1701 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1702 				       peer_mac_h16, mac_addr);
1703 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1704 		break;
1705 	case HTT_T2H_MSG_TYPE_PEER_MAP2:
1706 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1707 				    resp->peer_map_ev.info);
1708 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1709 				    resp->peer_map_ev.info);
1710 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1711 					 resp->peer_map_ev.info1);
1712 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1713 				       peer_mac_h16, mac_addr);
1714 		ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1715 				     resp->peer_map_ev.info2);
1716 		hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1717 				       resp->peer_map_ev.info1);
1718 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1719 				      hw_peer_id);
1720 		break;
1721 	case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1722 	case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1723 		peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1724 				    resp->peer_unmap_ev.info);
1725 		ath11k_peer_unmap_event(ab, peer_id);
1726 		break;
1727 	case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1728 		ath11k_htt_pull_ppdu_stats(ab, skb);
1729 		break;
1730 	case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1731 		ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1732 		break;
1733 	case HTT_T2H_MSG_TYPE_PKTLOG:
1734 		ath11k_htt_pktlog(ab, skb);
1735 		break;
1736 	case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1737 		ath11k_htt_backpressure_event_handler(ab, skb);
1738 		break;
1739 	default:
1740 		ath11k_warn(ab, "htt event %d not handled\n", type);
1741 		break;
1742 	}
1743 
1744 	dev_kfree_skb_any(skb);
1745 }
1746 
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1747 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1748 				      struct sk_buff_head *msdu_list,
1749 				      struct sk_buff *first, struct sk_buff *last,
1750 				      u8 l3pad_bytes, int msdu_len)
1751 {
1752 	struct ath11k_base *ab = ar->ab;
1753 	struct sk_buff *skb;
1754 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1755 	int buf_first_hdr_len, buf_first_len;
1756 	struct hal_rx_desc *ldesc;
1757 	int space_extra, rem_len, buf_len;
1758 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1759 
1760 	/* As the msdu is spread across multiple rx buffers,
1761 	 * find the offset to the start of msdu for computing
1762 	 * the length of the msdu in the first buffer.
1763 	 */
1764 	buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1765 	buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1766 
1767 	if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1768 		skb_put(first, buf_first_hdr_len + msdu_len);
1769 		skb_pull(first, buf_first_hdr_len);
1770 		return 0;
1771 	}
1772 
1773 	ldesc = (struct hal_rx_desc *)last->data;
1774 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1775 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1776 
1777 	/* MSDU spans over multiple buffers because the length of the MSDU
1778 	 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1779 	 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1780 	 */
1781 	skb_put(first, DP_RX_BUFFER_SIZE);
1782 	skb_pull(first, buf_first_hdr_len);
1783 
1784 	/* When an MSDU spread over multiple buffers attention, MSDU_END and
1785 	 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1786 	 */
1787 	ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1788 
1789 	space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1790 	if (space_extra > 0 &&
1791 	    (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1792 		/* Free up all buffers of the MSDU */
1793 		while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1794 			rxcb = ATH11K_SKB_RXCB(skb);
1795 			if (!rxcb->is_continuation) {
1796 				dev_kfree_skb_any(skb);
1797 				break;
1798 			}
1799 			dev_kfree_skb_any(skb);
1800 		}
1801 		return -ENOMEM;
1802 	}
1803 
1804 	rem_len = msdu_len - buf_first_len;
1805 	while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1806 		rxcb = ATH11K_SKB_RXCB(skb);
1807 		if (rxcb->is_continuation)
1808 			buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1809 		else
1810 			buf_len = rem_len;
1811 
1812 		if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1813 			WARN_ON_ONCE(1);
1814 			dev_kfree_skb_any(skb);
1815 			return -EINVAL;
1816 		}
1817 
1818 		skb_put(skb, buf_len + hal_rx_desc_sz);
1819 		skb_pull(skb, hal_rx_desc_sz);
1820 		skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1821 					  buf_len);
1822 		dev_kfree_skb_any(skb);
1823 
1824 		rem_len -= buf_len;
1825 		if (!rxcb->is_continuation)
1826 			break;
1827 	}
1828 
1829 	return 0;
1830 }
1831 
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1832 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1833 						      struct sk_buff *first)
1834 {
1835 	struct sk_buff *skb;
1836 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1837 
1838 	if (!rxcb->is_continuation)
1839 		return first;
1840 
1841 	skb_queue_walk(msdu_list, skb) {
1842 		rxcb = ATH11K_SKB_RXCB(skb);
1843 		if (!rxcb->is_continuation)
1844 			return skb;
1845 	}
1846 
1847 	return NULL;
1848 }
1849 
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1850 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1851 {
1852 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1853 	struct rx_attention *rx_attention;
1854 	bool ip_csum_fail, l4_csum_fail;
1855 
1856 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1857 	ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1858 	l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1859 
1860 	msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1861 			  CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1862 }
1863 
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1864 static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar,
1865 				       enum hal_encrypt_type enctype)
1866 {
1867 	switch (enctype) {
1868 	case HAL_ENCRYPT_TYPE_OPEN:
1869 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1870 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1871 		return 0;
1872 	case HAL_ENCRYPT_TYPE_CCMP_128:
1873 		return IEEE80211_CCMP_MIC_LEN;
1874 	case HAL_ENCRYPT_TYPE_CCMP_256:
1875 		return IEEE80211_CCMP_256_MIC_LEN;
1876 	case HAL_ENCRYPT_TYPE_GCMP_128:
1877 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1878 		return IEEE80211_GCMP_MIC_LEN;
1879 	case HAL_ENCRYPT_TYPE_WEP_40:
1880 	case HAL_ENCRYPT_TYPE_WEP_104:
1881 	case HAL_ENCRYPT_TYPE_WEP_128:
1882 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1883 	case HAL_ENCRYPT_TYPE_WAPI:
1884 		break;
1885 	}
1886 
1887 	ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1888 	return 0;
1889 }
1890 
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1891 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1892 					 enum hal_encrypt_type enctype)
1893 {
1894 	switch (enctype) {
1895 	case HAL_ENCRYPT_TYPE_OPEN:
1896 		return 0;
1897 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1898 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1899 		return IEEE80211_TKIP_IV_LEN;
1900 	case HAL_ENCRYPT_TYPE_CCMP_128:
1901 		return IEEE80211_CCMP_HDR_LEN;
1902 	case HAL_ENCRYPT_TYPE_CCMP_256:
1903 		return IEEE80211_CCMP_256_HDR_LEN;
1904 	case HAL_ENCRYPT_TYPE_GCMP_128:
1905 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1906 		return IEEE80211_GCMP_HDR_LEN;
1907 	case HAL_ENCRYPT_TYPE_WEP_40:
1908 	case HAL_ENCRYPT_TYPE_WEP_104:
1909 	case HAL_ENCRYPT_TYPE_WEP_128:
1910 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1911 	case HAL_ENCRYPT_TYPE_WAPI:
1912 		break;
1913 	}
1914 
1915 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1916 	return 0;
1917 }
1918 
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1919 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1920 				       enum hal_encrypt_type enctype)
1921 {
1922 	switch (enctype) {
1923 	case HAL_ENCRYPT_TYPE_OPEN:
1924 	case HAL_ENCRYPT_TYPE_CCMP_128:
1925 	case HAL_ENCRYPT_TYPE_CCMP_256:
1926 	case HAL_ENCRYPT_TYPE_GCMP_128:
1927 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1928 		return 0;
1929 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1930 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1931 		return IEEE80211_TKIP_ICV_LEN;
1932 	case HAL_ENCRYPT_TYPE_WEP_40:
1933 	case HAL_ENCRYPT_TYPE_WEP_104:
1934 	case HAL_ENCRYPT_TYPE_WEP_128:
1935 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1936 	case HAL_ENCRYPT_TYPE_WAPI:
1937 		break;
1938 	}
1939 
1940 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1941 	return 0;
1942 }
1943 
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1944 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1945 					 struct sk_buff *msdu,
1946 					 u8 *first_hdr,
1947 					 enum hal_encrypt_type enctype,
1948 					 struct ieee80211_rx_status *status)
1949 {
1950 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1951 	u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1952 	struct ieee80211_hdr *hdr;
1953 	size_t hdr_len;
1954 	u8 da[ETH_ALEN];
1955 	u8 sa[ETH_ALEN];
1956 	u16 qos_ctl = 0;
1957 	u8 *qos;
1958 
1959 	/* copy SA & DA and pull decapped header */
1960 	hdr = (struct ieee80211_hdr *)msdu->data;
1961 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
1962 	ether_addr_copy(da, ieee80211_get_DA(hdr));
1963 	ether_addr_copy(sa, ieee80211_get_SA(hdr));
1964 	skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1965 
1966 	if (rxcb->is_first_msdu) {
1967 		/* original 802.11 header is valid for the first msdu
1968 		 * hence we can reuse the same header
1969 		 */
1970 		hdr = (struct ieee80211_hdr *)first_hdr;
1971 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
1972 
1973 		/* Each A-MSDU subframe will be reported as a separate MSDU,
1974 		 * so strip the A-MSDU bit from QoS Ctl.
1975 		 */
1976 		if (ieee80211_is_data_qos(hdr->frame_control)) {
1977 			qos = ieee80211_get_qos_ctl(hdr);
1978 			qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1979 		}
1980 	} else {
1981 		/*  Rebuild qos header if this is a middle/last msdu */
1982 		hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1983 
1984 		/* Reset the order bit as the HT_Control header is stripped */
1985 		hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1986 
1987 		qos_ctl = rxcb->tid;
1988 
1989 		if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
1990 			qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1991 
1992 		/* TODO Add other QoS ctl fields when required */
1993 
1994 		/* copy decap header before overwriting for reuse below */
1995 		memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
1996 	}
1997 
1998 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
1999 		memcpy(skb_push(msdu,
2000 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2001 		       (void *)hdr + hdr_len,
2002 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2003 	}
2004 
2005 	if (!rxcb->is_first_msdu) {
2006 		memcpy(skb_push(msdu,
2007 				IEEE80211_QOS_CTL_LEN), &qos_ctl,
2008 				IEEE80211_QOS_CTL_LEN);
2009 		memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2010 		return;
2011 	}
2012 
2013 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2014 
2015 	/* original 802.11 header has a different DA and in
2016 	 * case of 4addr it may also have different SA
2017 	 */
2018 	hdr = (struct ieee80211_hdr *)msdu->data;
2019 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2020 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2021 }
2022 
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2023 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2024 				       enum hal_encrypt_type enctype,
2025 				       struct ieee80211_rx_status *status,
2026 				       bool decrypted)
2027 {
2028 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2029 	struct ieee80211_hdr *hdr;
2030 	size_t hdr_len;
2031 	size_t crypto_len;
2032 
2033 	if (!rxcb->is_first_msdu ||
2034 	    !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2035 		WARN_ON_ONCE(1);
2036 		return;
2037 	}
2038 
2039 	skb_trim(msdu, msdu->len - FCS_LEN);
2040 
2041 	if (!decrypted)
2042 		return;
2043 
2044 	hdr = (void *)msdu->data;
2045 
2046 	/* Tail */
2047 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2048 		skb_trim(msdu, msdu->len -
2049 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2050 
2051 		skb_trim(msdu, msdu->len -
2052 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2053 	} else {
2054 		/* MIC */
2055 		if (status->flag & RX_FLAG_MIC_STRIPPED)
2056 			skb_trim(msdu, msdu->len -
2057 				 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2058 
2059 		/* ICV */
2060 		if (status->flag & RX_FLAG_ICV_STRIPPED)
2061 			skb_trim(msdu, msdu->len -
2062 				 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2063 	}
2064 
2065 	/* MMIC */
2066 	if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2067 	    !ieee80211_has_morefrags(hdr->frame_control) &&
2068 	    enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2069 		skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2070 
2071 	/* Head */
2072 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2073 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2074 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2075 
2076 		memmove((void *)msdu->data + crypto_len,
2077 			(void *)msdu->data, hdr_len);
2078 		skb_pull(msdu, crypto_len);
2079 	}
2080 }
2081 
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2082 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2083 					 struct sk_buff *msdu,
2084 					 enum hal_encrypt_type enctype)
2085 {
2086 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2087 	struct ieee80211_hdr *hdr;
2088 	size_t hdr_len, crypto_len;
2089 	void *rfc1042;
2090 	bool is_amsdu;
2091 
2092 	is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2093 	hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2094 	rfc1042 = hdr;
2095 
2096 	if (rxcb->is_first_msdu) {
2097 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2098 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2099 
2100 		rfc1042 += hdr_len + crypto_len;
2101 	}
2102 
2103 	if (is_amsdu)
2104 		rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2105 
2106 	return rfc1042;
2107 }
2108 
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2109 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2110 				       struct sk_buff *msdu,
2111 				       u8 *first_hdr,
2112 				       enum hal_encrypt_type enctype,
2113 				       struct ieee80211_rx_status *status)
2114 {
2115 	struct ieee80211_hdr *hdr;
2116 	struct ethhdr *eth;
2117 	size_t hdr_len;
2118 	u8 da[ETH_ALEN];
2119 	u8 sa[ETH_ALEN];
2120 	void *rfc1042;
2121 
2122 	rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2123 	if (WARN_ON_ONCE(!rfc1042))
2124 		return;
2125 
2126 	/* pull decapped header and copy SA & DA */
2127 	eth = (struct ethhdr *)msdu->data;
2128 	ether_addr_copy(da, eth->h_dest);
2129 	ether_addr_copy(sa, eth->h_source);
2130 	skb_pull(msdu, sizeof(struct ethhdr));
2131 
2132 	/* push rfc1042/llc/snap */
2133 	memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2134 	       sizeof(struct ath11k_dp_rfc1042_hdr));
2135 
2136 	/* push original 802.11 header */
2137 	hdr = (struct ieee80211_hdr *)first_hdr;
2138 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2139 
2140 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2141 		memcpy(skb_push(msdu,
2142 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2143 		       (void *)hdr + hdr_len,
2144 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2145 	}
2146 
2147 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2148 
2149 	/* original 802.11 header has a different DA and in
2150 	 * case of 4addr it may also have different SA
2151 	 */
2152 	hdr = (struct ieee80211_hdr *)msdu->data;
2153 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2154 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2155 }
2156 
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2157 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2158 				   struct hal_rx_desc *rx_desc,
2159 				   enum hal_encrypt_type enctype,
2160 				   struct ieee80211_rx_status *status,
2161 				   bool decrypted)
2162 {
2163 	u8 *first_hdr;
2164 	u8 decap;
2165 
2166 	first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2167 	decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2168 
2169 	switch (decap) {
2170 	case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2171 		ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2172 					     enctype, status);
2173 		break;
2174 	case DP_RX_DECAP_TYPE_RAW:
2175 		ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2176 					   decrypted);
2177 		break;
2178 	case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2179 		/* TODO undecap support for middle/last msdu's of amsdu */
2180 		ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2181 					   enctype, status);
2182 		break;
2183 	case DP_RX_DECAP_TYPE_8023:
2184 		/* TODO: Handle undecap for these formats */
2185 		break;
2186 	}
2187 }
2188 
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2189 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2190 				struct sk_buff *msdu,
2191 				struct hal_rx_desc *rx_desc,
2192 				struct ieee80211_rx_status *rx_status)
2193 {
2194 	bool  fill_crypto_hdr, mcast;
2195 	enum hal_encrypt_type enctype;
2196 	bool is_decrypted = false;
2197 	struct ieee80211_hdr *hdr;
2198 	struct ath11k_peer *peer;
2199 	struct rx_attention *rx_attention;
2200 	u32 err_bitmap;
2201 
2202 	hdr = (struct ieee80211_hdr *)msdu->data;
2203 
2204 	/* PN for multicast packets will be checked in mac80211 */
2205 
2206 	mcast = is_multicast_ether_addr(hdr->addr1);
2207 	fill_crypto_hdr = mcast;
2208 
2209 	spin_lock_bh(&ar->ab->base_lock);
2210 	peer = ath11k_peer_find_by_addr(ar->ab, hdr->addr2);
2211 	if (peer) {
2212 		if (mcast)
2213 			enctype = peer->sec_type_grp;
2214 		else
2215 			enctype = peer->sec_type;
2216 	} else {
2217 		enctype = HAL_ENCRYPT_TYPE_OPEN;
2218 	}
2219 	spin_unlock_bh(&ar->ab->base_lock);
2220 
2221 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2222 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2223 	if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2224 		is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2225 
2226 	/* Clear per-MPDU flags while leaving per-PPDU flags intact */
2227 	rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2228 			     RX_FLAG_MMIC_ERROR |
2229 			     RX_FLAG_DECRYPTED |
2230 			     RX_FLAG_IV_STRIPPED |
2231 			     RX_FLAG_MMIC_STRIPPED);
2232 
2233 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2234 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2235 	if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2236 		rx_status->flag |= RX_FLAG_MMIC_ERROR;
2237 
2238 	if (is_decrypted) {
2239 		rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2240 
2241 		if (fill_crypto_hdr)
2242 			rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2243 					RX_FLAG_ICV_STRIPPED;
2244 		else
2245 			rx_status->flag |= RX_FLAG_IV_STRIPPED |
2246 					   RX_FLAG_PN_VALIDATED;
2247 	}
2248 
2249 	ath11k_dp_rx_h_csum_offload(ar, msdu);
2250 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2251 			       enctype, rx_status, is_decrypted);
2252 
2253 	if (!is_decrypted || fill_crypto_hdr)
2254 		return;
2255 
2256 	hdr = (void *)msdu->data;
2257 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2258 }
2259 
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2260 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2261 				struct ieee80211_rx_status *rx_status)
2262 {
2263 	struct ieee80211_supported_band *sband;
2264 	enum rx_msdu_start_pkt_type pkt_type;
2265 	u8 bw;
2266 	u8 rate_mcs, nss;
2267 	u8 sgi;
2268 	bool is_cck;
2269 
2270 	pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2271 	bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2272 	rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2273 	nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2274 	sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2275 
2276 	switch (pkt_type) {
2277 	case RX_MSDU_START_PKT_TYPE_11A:
2278 	case RX_MSDU_START_PKT_TYPE_11B:
2279 		is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2280 		sband = &ar->mac.sbands[rx_status->band];
2281 		rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2282 								is_cck);
2283 		break;
2284 	case RX_MSDU_START_PKT_TYPE_11N:
2285 		rx_status->encoding = RX_ENC_HT;
2286 		if (rate_mcs > ATH11K_HT_MCS_MAX) {
2287 			ath11k_warn(ar->ab,
2288 				    "Received with invalid mcs in HT mode %d\n",
2289 				     rate_mcs);
2290 			break;
2291 		}
2292 		rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2293 		if (sgi)
2294 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2295 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2296 		break;
2297 	case RX_MSDU_START_PKT_TYPE_11AC:
2298 		rx_status->encoding = RX_ENC_VHT;
2299 		rx_status->rate_idx = rate_mcs;
2300 		if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2301 			ath11k_warn(ar->ab,
2302 				    "Received with invalid mcs in VHT mode %d\n",
2303 				     rate_mcs);
2304 			break;
2305 		}
2306 		rx_status->nss = nss;
2307 		if (sgi)
2308 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2309 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2310 		break;
2311 	case RX_MSDU_START_PKT_TYPE_11AX:
2312 		rx_status->rate_idx = rate_mcs;
2313 		if (rate_mcs > ATH11K_HE_MCS_MAX) {
2314 			ath11k_warn(ar->ab,
2315 				    "Received with invalid mcs in HE mode %d\n",
2316 				    rate_mcs);
2317 			break;
2318 		}
2319 		rx_status->encoding = RX_ENC_HE;
2320 		rx_status->nss = nss;
2321 		rx_status->he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
2322 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2323 		break;
2324 	}
2325 }
2326 
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2327 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2328 				struct ieee80211_rx_status *rx_status)
2329 {
2330 	u8 channel_num;
2331 	u32 center_freq, meta_data;
2332 	struct ieee80211_channel *channel;
2333 
2334 	rx_status->freq = 0;
2335 	rx_status->rate_idx = 0;
2336 	rx_status->nss = 0;
2337 	rx_status->encoding = RX_ENC_LEGACY;
2338 	rx_status->bw = RATE_INFO_BW_20;
2339 
2340 	rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2341 
2342 	meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2343 	channel_num = meta_data;
2344 	center_freq = meta_data >> 16;
2345 
2346 	if (center_freq >= ATH11K_MIN_6G_FREQ &&
2347 	    center_freq <= ATH11K_MAX_6G_FREQ) {
2348 		rx_status->band = NL80211_BAND_6GHZ;
2349 		rx_status->freq = center_freq;
2350 	} else if (channel_num >= 1 && channel_num <= 14) {
2351 		rx_status->band = NL80211_BAND_2GHZ;
2352 	} else if (channel_num >= 36 && channel_num <= 173) {
2353 		rx_status->band = NL80211_BAND_5GHZ;
2354 	} else {
2355 		spin_lock_bh(&ar->data_lock);
2356 		channel = ar->rx_channel;
2357 		if (channel) {
2358 			rx_status->band = channel->band;
2359 			channel_num =
2360 				ieee80211_frequency_to_channel(channel->center_freq);
2361 		}
2362 		spin_unlock_bh(&ar->data_lock);
2363 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2364 				rx_desc, sizeof(struct hal_rx_desc));
2365 	}
2366 
2367 	if (rx_status->band != NL80211_BAND_6GHZ)
2368 		rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2369 								 rx_status->band);
2370 
2371 	ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2372 }
2373 
ath11k_print_get_tid(struct ieee80211_hdr * hdr,char * out,size_t size)2374 static char *ath11k_print_get_tid(struct ieee80211_hdr *hdr, char *out,
2375 				  size_t size)
2376 {
2377 	u8 *qc;
2378 	int tid;
2379 
2380 	if (!ieee80211_is_data_qos(hdr->frame_control))
2381 		return "";
2382 
2383 	qc = ieee80211_get_qos_ctl(hdr);
2384 	tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
2385 	snprintf(out, size, "tid %d", tid);
2386 
2387 	return out;
2388 }
2389 
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu)2390 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2391 				      struct sk_buff *msdu)
2392 {
2393 	static const struct ieee80211_radiotap_he known = {
2394 		.data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2395 				     IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2396 		.data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2397 	};
2398 	struct ieee80211_rx_status *status;
2399 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
2400 	struct ieee80211_radiotap_he *he = NULL;
2401 	char tid[32];
2402 
2403 	status = IEEE80211_SKB_RXCB(msdu);
2404 	if (status->encoding == RX_ENC_HE) {
2405 		he = skb_push(msdu, sizeof(known));
2406 		memcpy(he, &known, sizeof(known));
2407 		status->flag |= RX_FLAG_RADIOTAP_HE;
2408 	}
2409 
2410 	ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2411 		   "rx skb %pK len %u peer %pM %s %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2412 		   msdu,
2413 		   msdu->len,
2414 		   ieee80211_get_SA(hdr),
2415 		   ath11k_print_get_tid(hdr, tid, sizeof(tid)),
2416 		   is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
2417 							"mcast" : "ucast",
2418 		   (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
2419 		   (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2420 		   (status->encoding == RX_ENC_HT) ? "ht" : "",
2421 		   (status->encoding == RX_ENC_VHT) ? "vht" : "",
2422 		   (status->encoding == RX_ENC_HE) ? "he" : "",
2423 		   (status->bw == RATE_INFO_BW_40) ? "40" : "",
2424 		   (status->bw == RATE_INFO_BW_80) ? "80" : "",
2425 		   (status->bw == RATE_INFO_BW_160) ? "160" : "",
2426 		   status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2427 		   status->rate_idx,
2428 		   status->nss,
2429 		   status->freq,
2430 		   status->band, status->flag,
2431 		   !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2432 		   !!(status->flag & RX_FLAG_MMIC_ERROR),
2433 		   !!(status->flag & RX_FLAG_AMSDU_MORE));
2434 
2435 	ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2436 			msdu->data, msdu->len);
2437 
2438 	/* TODO: trace rx packet */
2439 
2440 	ieee80211_rx_napi(ar->hw, NULL, msdu, napi);
2441 }
2442 
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list)2443 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2444 				     struct sk_buff *msdu,
2445 				     struct sk_buff_head *msdu_list)
2446 {
2447 	struct ath11k_base *ab = ar->ab;
2448 	struct hal_rx_desc *rx_desc, *lrx_desc;
2449 	struct rx_attention *rx_attention;
2450 	struct ieee80211_rx_status rx_status = {0};
2451 	struct ieee80211_rx_status *status;
2452 	struct ath11k_skb_rxcb *rxcb;
2453 	struct ieee80211_hdr *hdr;
2454 	struct sk_buff *last_buf;
2455 	u8 l3_pad_bytes;
2456 	u8 *hdr_status;
2457 	u16 msdu_len;
2458 	int ret;
2459 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2460 
2461 	last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2462 	if (!last_buf) {
2463 		ath11k_warn(ab,
2464 			    "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2465 		ret = -EIO;
2466 		goto free_out;
2467 	}
2468 
2469 	rx_desc = (struct hal_rx_desc *)msdu->data;
2470 	lrx_desc = (struct hal_rx_desc *)last_buf->data;
2471 	rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2472 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2473 		ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2474 		ret = -EIO;
2475 		goto free_out;
2476 	}
2477 
2478 	rxcb = ATH11K_SKB_RXCB(msdu);
2479 	rxcb->rx_desc = rx_desc;
2480 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2481 	l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2482 
2483 	if (rxcb->is_frag) {
2484 		skb_pull(msdu, hal_rx_desc_sz);
2485 	} else if (!rxcb->is_continuation) {
2486 		if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2487 			hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2488 			ret = -EINVAL;
2489 			ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2490 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2491 					sizeof(struct ieee80211_hdr));
2492 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2493 					sizeof(struct hal_rx_desc));
2494 			goto free_out;
2495 		}
2496 		skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2497 		skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2498 	} else {
2499 		ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2500 						 msdu, last_buf,
2501 						 l3_pad_bytes, msdu_len);
2502 		if (ret) {
2503 			ath11k_warn(ab,
2504 				    "failed to coalesce msdu rx buffer%d\n", ret);
2505 			goto free_out;
2506 		}
2507 	}
2508 
2509 	hdr = (struct ieee80211_hdr *)msdu->data;
2510 
2511 	/* Process only data frames */
2512 	if (!ieee80211_is_data(hdr->frame_control))
2513 		return -EINVAL;
2514 
2515 	ath11k_dp_rx_h_ppdu(ar, rx_desc, &rx_status);
2516 	ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, &rx_status);
2517 
2518 	rx_status.flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2519 
2520 	status = IEEE80211_SKB_RXCB(msdu);
2521 	*status = rx_status;
2522 	return 0;
2523 
2524 free_out:
2525 	return ret;
2526 }
2527 
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int * quota,int ring_id)2528 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2529 						  struct napi_struct *napi,
2530 						  struct sk_buff_head *msdu_list,
2531 						  int *quota, int ring_id)
2532 {
2533 	struct ath11k_skb_rxcb *rxcb;
2534 	struct sk_buff *msdu;
2535 	struct ath11k *ar;
2536 	u8 mac_id;
2537 	int ret;
2538 
2539 	if (skb_queue_empty(msdu_list))
2540 		return;
2541 
2542 	rcu_read_lock();
2543 
2544 	while (*quota && (msdu = __skb_dequeue(msdu_list))) {
2545 		rxcb = ATH11K_SKB_RXCB(msdu);
2546 		mac_id = rxcb->mac_id;
2547 		ar = ab->pdevs[mac_id].ar;
2548 		if (!rcu_dereference(ab->pdevs_active[mac_id])) {
2549 			dev_kfree_skb_any(msdu);
2550 			continue;
2551 		}
2552 
2553 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
2554 			dev_kfree_skb_any(msdu);
2555 			continue;
2556 		}
2557 
2558 		ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list);
2559 		if (ret) {
2560 			ath11k_dbg(ab, ATH11K_DBG_DATA,
2561 				   "Unable to process msdu %d", ret);
2562 			dev_kfree_skb_any(msdu);
2563 			continue;
2564 		}
2565 
2566 		ath11k_dp_rx_deliver_msdu(ar, napi, msdu);
2567 		(*quota)--;
2568 	}
2569 
2570 	rcu_read_unlock();
2571 }
2572 
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2573 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2574 			 struct napi_struct *napi, int budget)
2575 {
2576 	struct ath11k_dp *dp = &ab->dp;
2577 	struct dp_rxdma_ring *rx_ring;
2578 	int num_buffs_reaped[MAX_RADIOS] = {0};
2579 	struct sk_buff_head msdu_list;
2580 	struct ath11k_skb_rxcb *rxcb;
2581 	int total_msdu_reaped = 0;
2582 	struct hal_srng *srng;
2583 	struct sk_buff *msdu;
2584 	int quota = budget;
2585 	bool done = false;
2586 	int buf_id, mac_id;
2587 	struct ath11k *ar;
2588 	u32 *rx_desc;
2589 	int i;
2590 
2591 	__skb_queue_head_init(&msdu_list);
2592 
2593 	srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2594 
2595 	spin_lock_bh(&srng->lock);
2596 
2597 	ath11k_hal_srng_access_begin(ab, srng);
2598 
2599 try_again:
2600 	while ((rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
2601 		struct hal_reo_dest_ring desc = *(struct hal_reo_dest_ring *)rx_desc;
2602 		enum hal_reo_dest_ring_push_reason push_reason;
2603 		u32 cookie;
2604 
2605 		cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2606 				   desc.buf_addr_info.info1);
2607 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2608 				   cookie);
2609 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2610 
2611 		if (unlikely(buf_id == 0))
2612 			continue;
2613 
2614 		ar = ab->pdevs[mac_id].ar;
2615 		rx_ring = &ar->dp.rx_refill_buf_ring;
2616 		spin_lock_bh(&rx_ring->idr_lock);
2617 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2618 		if (!msdu) {
2619 			ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2620 				    buf_id);
2621 			spin_unlock_bh(&rx_ring->idr_lock);
2622 			continue;
2623 		}
2624 
2625 		idr_remove(&rx_ring->bufs_idr, buf_id);
2626 		spin_unlock_bh(&rx_ring->idr_lock);
2627 
2628 		rxcb = ATH11K_SKB_RXCB(msdu);
2629 		dma_unmap_single(ab->dev, rxcb->paddr,
2630 				 msdu->len + skb_tailroom(msdu),
2631 				 DMA_FROM_DEVICE);
2632 
2633 		num_buffs_reaped[mac_id]++;
2634 		total_msdu_reaped++;
2635 
2636 		push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2637 					desc.info0);
2638 		if (push_reason !=
2639 		    HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
2640 			dev_kfree_skb_any(msdu);
2641 			ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++;
2642 			continue;
2643 		}
2644 
2645 		rxcb->is_first_msdu = !!(desc.rx_msdu_info.info0 &
2646 					 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2647 		rxcb->is_last_msdu = !!(desc.rx_msdu_info.info0 &
2648 					RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2649 		rxcb->is_continuation = !!(desc.rx_msdu_info.info0 &
2650 					   RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2651 		rxcb->mac_id = mac_id;
2652 		rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2653 				      desc.info0);
2654 
2655 		__skb_queue_tail(&msdu_list, msdu);
2656 
2657 		if (total_msdu_reaped >= quota && !rxcb->is_continuation) {
2658 			done = true;
2659 			break;
2660 		}
2661 	}
2662 
2663 	/* Hw might have updated the head pointer after we cached it.
2664 	 * In this case, even though there are entries in the ring we'll
2665 	 * get rx_desc NULL. Give the read another try with updated cached
2666 	 * head pointer so that we can reap complete MPDU in the current
2667 	 * rx processing.
2668 	 */
2669 	if (!done && ath11k_hal_srng_dst_num_free(ab, srng, true)) {
2670 		ath11k_hal_srng_access_end(ab, srng);
2671 		goto try_again;
2672 	}
2673 
2674 	ath11k_hal_srng_access_end(ab, srng);
2675 
2676 	spin_unlock_bh(&srng->lock);
2677 
2678 	if (!total_msdu_reaped)
2679 		goto exit;
2680 
2681 	for (i = 0; i < ab->num_radios; i++) {
2682 		if (!num_buffs_reaped[i])
2683 			continue;
2684 
2685 		ar = ab->pdevs[i].ar;
2686 		rx_ring = &ar->dp.rx_refill_buf_ring;
2687 
2688 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2689 					   HAL_RX_BUF_RBM_SW3_BM);
2690 	}
2691 
2692 	ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list,
2693 					      &quota, ring_id);
2694 
2695 exit:
2696 	return budget - quota;
2697 }
2698 
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2699 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2700 					   struct hal_rx_mon_ppdu_info *ppdu_info)
2701 {
2702 	struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2703 	u32 num_msdu;
2704 
2705 	if (!rx_stats)
2706 		return;
2707 
2708 	num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2709 		   ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2710 
2711 	rx_stats->num_msdu += num_msdu;
2712 	rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2713 				    ppdu_info->tcp_ack_msdu_count;
2714 	rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2715 	rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2716 
2717 	if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2718 	    ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2719 		ppdu_info->nss = 1;
2720 		ppdu_info->mcs = HAL_RX_MAX_MCS;
2721 		ppdu_info->tid = IEEE80211_NUM_TIDS;
2722 	}
2723 
2724 	if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2725 		rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2726 
2727 	if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2728 		rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2729 
2730 	if (ppdu_info->gi < HAL_RX_GI_MAX)
2731 		rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2732 
2733 	if (ppdu_info->bw < HAL_RX_BW_MAX)
2734 		rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2735 
2736 	if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2737 		rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2738 
2739 	if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2740 		rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2741 
2742 	if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2743 		rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2744 
2745 	if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2746 		rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2747 
2748 	if (ppdu_info->is_stbc)
2749 		rx_stats->stbc_count += num_msdu;
2750 
2751 	if (ppdu_info->beamformed)
2752 		rx_stats->beamformed_count += num_msdu;
2753 
2754 	if (ppdu_info->num_mpdu_fcs_ok > 1)
2755 		rx_stats->ampdu_msdu_count += num_msdu;
2756 	else
2757 		rx_stats->non_ampdu_msdu_count += num_msdu;
2758 
2759 	rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2760 	rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2761 	rx_stats->dcm_count += ppdu_info->dcm;
2762 	rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2763 
2764 	arsta->rssi_comb = ppdu_info->rssi_comb;
2765 	rx_stats->rx_duration += ppdu_info->rx_duration;
2766 	arsta->rx_duration = rx_stats->rx_duration;
2767 }
2768 
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2769 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2770 							 struct dp_rxdma_ring *rx_ring,
2771 							 int *buf_id)
2772 {
2773 	struct sk_buff *skb;
2774 	dma_addr_t paddr;
2775 
2776 	skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2777 			    DP_RX_BUFFER_ALIGN_SIZE);
2778 
2779 	if (!skb)
2780 		goto fail_alloc_skb;
2781 
2782 	if (!IS_ALIGNED((unsigned long)skb->data,
2783 			DP_RX_BUFFER_ALIGN_SIZE)) {
2784 		skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2785 			 skb->data);
2786 	}
2787 
2788 	paddr = dma_map_single(ab->dev, skb->data,
2789 			       skb->len + skb_tailroom(skb),
2790 			       DMA_FROM_DEVICE);
2791 	if (unlikely(dma_mapping_error(ab->dev, paddr)))
2792 		goto fail_free_skb;
2793 
2794 	spin_lock_bh(&rx_ring->idr_lock);
2795 	*buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2796 			    rx_ring->bufs_max, GFP_ATOMIC);
2797 	spin_unlock_bh(&rx_ring->idr_lock);
2798 	if (*buf_id < 0)
2799 		goto fail_dma_unmap;
2800 
2801 	ATH11K_SKB_RXCB(skb)->paddr = paddr;
2802 	return skb;
2803 
2804 fail_dma_unmap:
2805 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2806 			 DMA_FROM_DEVICE);
2807 fail_free_skb:
2808 	dev_kfree_skb_any(skb);
2809 fail_alloc_skb:
2810 	return NULL;
2811 }
2812 
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2813 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2814 					   struct dp_rxdma_ring *rx_ring,
2815 					   int req_entries,
2816 					   enum hal_rx_buf_return_buf_manager mgr)
2817 {
2818 	struct hal_srng *srng;
2819 	u32 *desc;
2820 	struct sk_buff *skb;
2821 	int num_free;
2822 	int num_remain;
2823 	int buf_id;
2824 	u32 cookie;
2825 	dma_addr_t paddr;
2826 
2827 	req_entries = min(req_entries, rx_ring->bufs_max);
2828 
2829 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2830 
2831 	spin_lock_bh(&srng->lock);
2832 
2833 	ath11k_hal_srng_access_begin(ab, srng);
2834 
2835 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2836 
2837 	req_entries = min(num_free, req_entries);
2838 	num_remain = req_entries;
2839 
2840 	while (num_remain > 0) {
2841 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2842 							&buf_id);
2843 		if (!skb)
2844 			break;
2845 		paddr = ATH11K_SKB_RXCB(skb)->paddr;
2846 
2847 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2848 		if (!desc)
2849 			goto fail_desc_get;
2850 
2851 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2852 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2853 
2854 		num_remain--;
2855 
2856 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2857 	}
2858 
2859 	ath11k_hal_srng_access_end(ab, srng);
2860 
2861 	spin_unlock_bh(&srng->lock);
2862 
2863 	return req_entries - num_remain;
2864 
2865 fail_desc_get:
2866 	spin_lock_bh(&rx_ring->idr_lock);
2867 	idr_remove(&rx_ring->bufs_idr, buf_id);
2868 	spin_unlock_bh(&rx_ring->idr_lock);
2869 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2870 			 DMA_FROM_DEVICE);
2871 	dev_kfree_skb_any(skb);
2872 	ath11k_hal_srng_access_end(ab, srng);
2873 	spin_unlock_bh(&srng->lock);
2874 
2875 	return req_entries - num_remain;
2876 }
2877 
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)2878 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
2879 					     int *budget, struct sk_buff_head *skb_list)
2880 {
2881 	struct ath11k *ar;
2882 	struct ath11k_pdev_dp *dp;
2883 	struct dp_rxdma_ring *rx_ring;
2884 	struct hal_srng *srng;
2885 	void *rx_mon_status_desc;
2886 	struct sk_buff *skb;
2887 	struct ath11k_skb_rxcb *rxcb;
2888 	struct hal_tlv_hdr *tlv;
2889 	u32 cookie;
2890 	int buf_id, srng_id;
2891 	dma_addr_t paddr;
2892 	u8 rbm;
2893 	int num_buffs_reaped = 0;
2894 
2895 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
2896 	dp = &ar->dp;
2897 	srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
2898 	rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
2899 
2900 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2901 
2902 	spin_lock_bh(&srng->lock);
2903 
2904 	ath11k_hal_srng_access_begin(ab, srng);
2905 	while (*budget) {
2906 		*budget -= 1;
2907 		rx_mon_status_desc =
2908 			ath11k_hal_srng_src_peek(ab, srng);
2909 		if (!rx_mon_status_desc)
2910 			break;
2911 
2912 		ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
2913 						&cookie, &rbm);
2914 		if (paddr) {
2915 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
2916 
2917 			spin_lock_bh(&rx_ring->idr_lock);
2918 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
2919 			if (!skb) {
2920 				ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
2921 					    buf_id);
2922 				spin_unlock_bh(&rx_ring->idr_lock);
2923 				goto move_next;
2924 			}
2925 
2926 			idr_remove(&rx_ring->bufs_idr, buf_id);
2927 			spin_unlock_bh(&rx_ring->idr_lock);
2928 
2929 			rxcb = ATH11K_SKB_RXCB(skb);
2930 
2931 			dma_unmap_single(ab->dev, rxcb->paddr,
2932 					 skb->len + skb_tailroom(skb),
2933 					 DMA_FROM_DEVICE);
2934 
2935 			tlv = (struct hal_tlv_hdr *)skb->data;
2936 			if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
2937 					HAL_RX_STATUS_BUFFER_DONE) {
2938 				ath11k_warn(ab, "mon status DONE not set %lx\n",
2939 					    FIELD_GET(HAL_TLV_HDR_TAG,
2940 						      tlv->tl));
2941 				dev_kfree_skb_any(skb);
2942 				goto move_next;
2943 			}
2944 
2945 			__skb_queue_tail(skb_list, skb);
2946 		}
2947 move_next:
2948 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2949 							&buf_id);
2950 
2951 		if (!skb) {
2952 			ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
2953 							HAL_RX_BUF_RBM_SW3_BM);
2954 			num_buffs_reaped++;
2955 			break;
2956 		}
2957 		rxcb = ATH11K_SKB_RXCB(skb);
2958 
2959 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2960 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2961 
2962 		ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
2963 						cookie, HAL_RX_BUF_RBM_SW3_BM);
2964 		ath11k_hal_srng_src_get_next_entry(ab, srng);
2965 		num_buffs_reaped++;
2966 	}
2967 	ath11k_hal_srng_access_end(ab, srng);
2968 	spin_unlock_bh(&srng->lock);
2969 
2970 	return num_buffs_reaped;
2971 }
2972 
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)2973 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
2974 				    struct napi_struct *napi, int budget)
2975 {
2976 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
2977 	enum hal_rx_mon_status hal_status;
2978 	struct sk_buff *skb;
2979 	struct sk_buff_head skb_list;
2980 	struct hal_rx_mon_ppdu_info ppdu_info;
2981 	struct ath11k_peer *peer;
2982 	struct ath11k_sta *arsta;
2983 	int num_buffs_reaped = 0;
2984 
2985 	__skb_queue_head_init(&skb_list);
2986 
2987 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
2988 							     &skb_list);
2989 	if (!num_buffs_reaped)
2990 		goto exit;
2991 
2992 	while ((skb = __skb_dequeue(&skb_list))) {
2993 		memset(&ppdu_info, 0, sizeof(ppdu_info));
2994 		ppdu_info.peer_id = HAL_INVALID_PEERID;
2995 
2996 		if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar))
2997 			trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
2998 
2999 		hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb);
3000 
3001 		if (ppdu_info.peer_id == HAL_INVALID_PEERID ||
3002 		    hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
3003 			dev_kfree_skb_any(skb);
3004 			continue;
3005 		}
3006 
3007 		rcu_read_lock();
3008 		spin_lock_bh(&ab->base_lock);
3009 		peer = ath11k_peer_find_by_id(ab, ppdu_info.peer_id);
3010 
3011 		if (!peer || !peer->sta) {
3012 			ath11k_dbg(ab, ATH11K_DBG_DATA,
3013 				   "failed to find the peer with peer_id %d\n",
3014 				   ppdu_info.peer_id);
3015 			spin_unlock_bh(&ab->base_lock);
3016 			rcu_read_unlock();
3017 			dev_kfree_skb_any(skb);
3018 			continue;
3019 		}
3020 
3021 		arsta = (struct ath11k_sta *)peer->sta->drv_priv;
3022 		ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info);
3023 
3024 		if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
3025 			trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
3026 
3027 		spin_unlock_bh(&ab->base_lock);
3028 		rcu_read_unlock();
3029 
3030 		dev_kfree_skb_any(skb);
3031 	}
3032 exit:
3033 	return num_buffs_reaped;
3034 }
3035 
ath11k_dp_rx_frag_timer(struct timer_list * timer)3036 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3037 {
3038 	struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
3039 
3040 	spin_lock_bh(&rx_tid->ab->base_lock);
3041 	if (rx_tid->last_frag_no &&
3042 	    rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3043 		spin_unlock_bh(&rx_tid->ab->base_lock);
3044 		return;
3045 	}
3046 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3047 	spin_unlock_bh(&rx_tid->ab->base_lock);
3048 }
3049 
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3050 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3051 {
3052 	struct ath11k_base *ab = ar->ab;
3053 	struct crypto_shash *tfm;
3054 	struct ath11k_peer *peer;
3055 	struct dp_rx_tid *rx_tid;
3056 	int i;
3057 
3058 	tfm = crypto_alloc_shash("michael_mic", 0, 0);
3059 	if (IS_ERR(tfm))
3060 		return PTR_ERR(tfm);
3061 
3062 	spin_lock_bh(&ab->base_lock);
3063 
3064 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3065 	if (!peer) {
3066 		ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3067 		spin_unlock_bh(&ab->base_lock);
3068 		crypto_free_shash(tfm);
3069 		return -ENOENT;
3070 	}
3071 
3072 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3073 		rx_tid = &peer->rx_tid[i];
3074 		rx_tid->ab = ab;
3075 		timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3076 		skb_queue_head_init(&rx_tid->rx_frags);
3077 	}
3078 
3079 	peer->tfm_mmic = tfm;
3080 	spin_unlock_bh(&ab->base_lock);
3081 
3082 	return 0;
3083 }
3084 
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3085 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3086 				      struct ieee80211_hdr *hdr, u8 *data,
3087 				      size_t data_len, u8 *mic)
3088 {
3089 	SHASH_DESC_ON_STACK(desc, tfm);
3090 	u8 mic_hdr[16] = {0};
3091 	u8 tid = 0;
3092 	int ret;
3093 
3094 	if (!tfm)
3095 		return -EINVAL;
3096 
3097 	desc->tfm = tfm;
3098 
3099 	ret = crypto_shash_setkey(tfm, key, 8);
3100 	if (ret)
3101 		goto out;
3102 
3103 	ret = crypto_shash_init(desc);
3104 	if (ret)
3105 		goto out;
3106 
3107 	/* TKIP MIC header */
3108 	memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3109 	memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3110 	if (ieee80211_is_data_qos(hdr->frame_control))
3111 		tid = ieee80211_get_tid(hdr);
3112 	mic_hdr[12] = tid;
3113 
3114 	ret = crypto_shash_update(desc, mic_hdr, 16);
3115 	if (ret)
3116 		goto out;
3117 	ret = crypto_shash_update(desc, data, data_len);
3118 	if (ret)
3119 		goto out;
3120 	ret = crypto_shash_final(desc, mic);
3121 out:
3122 	shash_desc_zero(desc);
3123 	return ret;
3124 }
3125 
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3126 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3127 					  struct sk_buff *msdu)
3128 {
3129 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3130 	struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3131 	struct ieee80211_key_conf *key_conf;
3132 	struct ieee80211_hdr *hdr;
3133 	u8 mic[IEEE80211_CCMP_MIC_LEN];
3134 	int head_len, tail_len, ret;
3135 	size_t data_len;
3136 	u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3137 	u8 *key, *data;
3138 	u8 key_idx;
3139 
3140 	if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3141 	    HAL_ENCRYPT_TYPE_TKIP_MIC)
3142 		return 0;
3143 
3144 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3145 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
3146 	head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3147 	tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3148 
3149 	if (!is_multicast_ether_addr(hdr->addr1))
3150 		key_idx = peer->ucast_keyidx;
3151 	else
3152 		key_idx = peer->mcast_keyidx;
3153 
3154 	key_conf = peer->keys[key_idx];
3155 
3156 	data = msdu->data + head_len;
3157 	data_len = msdu->len - head_len - tail_len;
3158 	key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3159 
3160 	ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3161 	if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3162 		goto mic_fail;
3163 
3164 	return 0;
3165 
3166 mic_fail:
3167 	(ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3168 	(ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3169 
3170 	rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3171 		    RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3172 	skb_pull(msdu, hal_rx_desc_sz);
3173 
3174 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3175 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3176 			       HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3177 	ieee80211_rx(ar->hw, msdu);
3178 	return -EINVAL;
3179 }
3180 
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3181 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3182 					enum hal_encrypt_type enctype, u32 flags)
3183 {
3184 	struct ieee80211_hdr *hdr;
3185 	size_t hdr_len;
3186 	size_t crypto_len;
3187 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3188 
3189 	if (!flags)
3190 		return;
3191 
3192 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3193 
3194 	if (flags & RX_FLAG_MIC_STRIPPED)
3195 		skb_trim(msdu, msdu->len -
3196 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3197 
3198 	if (flags & RX_FLAG_ICV_STRIPPED)
3199 		skb_trim(msdu, msdu->len -
3200 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3201 
3202 	if (flags & RX_FLAG_IV_STRIPPED) {
3203 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
3204 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3205 
3206 		memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3207 			(void *)msdu->data + hal_rx_desc_sz, hdr_len);
3208 		skb_pull(msdu, crypto_len);
3209 	}
3210 }
3211 
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3212 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3213 				 struct ath11k_peer *peer,
3214 				 struct dp_rx_tid *rx_tid,
3215 				 struct sk_buff **defrag_skb)
3216 {
3217 	struct hal_rx_desc *rx_desc;
3218 	struct sk_buff *skb, *first_frag, *last_frag;
3219 	struct ieee80211_hdr *hdr;
3220 	struct rx_attention *rx_attention;
3221 	enum hal_encrypt_type enctype;
3222 	bool is_decrypted = false;
3223 	int msdu_len = 0;
3224 	int extra_space;
3225 	u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3226 
3227 	first_frag = skb_peek(&rx_tid->rx_frags);
3228 	last_frag = skb_peek_tail(&rx_tid->rx_frags);
3229 
3230 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3231 		flags = 0;
3232 		rx_desc = (struct hal_rx_desc *)skb->data;
3233 		hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3234 
3235 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3236 		if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3237 			rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3238 			is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3239 		}
3240 
3241 		if (is_decrypted) {
3242 			if (skb != first_frag)
3243 				flags |=  RX_FLAG_IV_STRIPPED;
3244 			if (skb != last_frag)
3245 				flags |= RX_FLAG_ICV_STRIPPED |
3246 					 RX_FLAG_MIC_STRIPPED;
3247 		}
3248 
3249 		/* RX fragments are always raw packets */
3250 		if (skb != last_frag)
3251 			skb_trim(skb, skb->len - FCS_LEN);
3252 		ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3253 
3254 		if (skb != first_frag)
3255 			skb_pull(skb, hal_rx_desc_sz +
3256 				      ieee80211_hdrlen(hdr->frame_control));
3257 		msdu_len += skb->len;
3258 	}
3259 
3260 	extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3261 	if (extra_space > 0 &&
3262 	    (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3263 		return -ENOMEM;
3264 
3265 	__skb_unlink(first_frag, &rx_tid->rx_frags);
3266 	while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3267 		skb_put_data(first_frag, skb->data, skb->len);
3268 		dev_kfree_skb_any(skb);
3269 	}
3270 
3271 	hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3272 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3273 	ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3274 
3275 	if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3276 		first_frag = NULL;
3277 
3278 	*defrag_skb = first_frag;
3279 	return 0;
3280 }
3281 
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3282 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3283 					      struct sk_buff *defrag_skb)
3284 {
3285 	struct ath11k_base *ab = ar->ab;
3286 	struct ath11k_pdev_dp *dp = &ar->dp;
3287 	struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3288 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3289 	struct hal_reo_entrance_ring *reo_ent_ring;
3290 	struct hal_reo_dest_ring *reo_dest_ring;
3291 	struct dp_link_desc_bank *link_desc_banks;
3292 	struct hal_rx_msdu_link *msdu_link;
3293 	struct hal_rx_msdu_details *msdu0;
3294 	struct hal_srng *srng;
3295 	dma_addr_t paddr;
3296 	u32 desc_bank, msdu_info, mpdu_info;
3297 	u32 dst_idx, cookie, hal_rx_desc_sz;
3298 	int ret, buf_id;
3299 
3300 	hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3301 	link_desc_banks = ab->dp.link_desc_banks;
3302 	reo_dest_ring = rx_tid->dst_ring_desc;
3303 
3304 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3305 	msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3306 			(paddr - link_desc_banks[desc_bank].paddr));
3307 	msdu0 = &msdu_link->msdu_link[0];
3308 	dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3309 	memset(msdu0, 0, sizeof(*msdu0));
3310 
3311 	msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3312 		    FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3313 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3314 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3315 			       defrag_skb->len - hal_rx_desc_sz) |
3316 		    FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3317 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3318 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3319 	msdu0->rx_msdu_info.info0 = msdu_info;
3320 
3321 	/* change msdu len in hal rx desc */
3322 	ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3323 
3324 	paddr = dma_map_single(ab->dev, defrag_skb->data,
3325 			       defrag_skb->len + skb_tailroom(defrag_skb),
3326 			       DMA_TO_DEVICE);
3327 	if (dma_mapping_error(ab->dev, paddr))
3328 		return -ENOMEM;
3329 
3330 	spin_lock_bh(&rx_refill_ring->idr_lock);
3331 	buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3332 			   rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3333 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3334 	if (buf_id < 0) {
3335 		ret = -ENOMEM;
3336 		goto err_unmap_dma;
3337 	}
3338 
3339 	ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3340 	cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3341 		 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3342 
3343 	ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, HAL_RX_BUF_RBM_SW3_BM);
3344 
3345 	/* Fill mpdu details into reo entrace ring */
3346 	srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3347 
3348 	spin_lock_bh(&srng->lock);
3349 	ath11k_hal_srng_access_begin(ab, srng);
3350 
3351 	reo_ent_ring = (struct hal_reo_entrance_ring *)
3352 			ath11k_hal_srng_src_get_next_entry(ab, srng);
3353 	if (!reo_ent_ring) {
3354 		ath11k_hal_srng_access_end(ab, srng);
3355 		spin_unlock_bh(&srng->lock);
3356 		ret = -ENOSPC;
3357 		goto err_free_idr;
3358 	}
3359 	memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3360 
3361 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3362 	ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3363 					HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3364 
3365 	mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3366 		    FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3367 		    FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3368 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3369 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3370 		    FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3371 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3372 
3373 	reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3374 	reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3375 	reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3376 	reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3377 					 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3378 						   reo_dest_ring->info0)) |
3379 			      FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3380 	ath11k_hal_srng_access_end(ab, srng);
3381 	spin_unlock_bh(&srng->lock);
3382 
3383 	return 0;
3384 
3385 err_free_idr:
3386 	spin_lock_bh(&rx_refill_ring->idr_lock);
3387 	idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3388 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3389 err_unmap_dma:
3390 	dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3391 			 DMA_TO_DEVICE);
3392 	return ret;
3393 }
3394 
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3395 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3396 				    struct sk_buff *a, struct sk_buff *b)
3397 {
3398 	int frag1, frag2;
3399 
3400 	frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3401 	frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3402 
3403 	return frag1 - frag2;
3404 }
3405 
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3406 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3407 				      struct sk_buff_head *frag_list,
3408 				      struct sk_buff *cur_frag)
3409 {
3410 	struct sk_buff *skb;
3411 	int cmp;
3412 
3413 	skb_queue_walk(frag_list, skb) {
3414 		cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3415 		if (cmp < 0)
3416 			continue;
3417 		__skb_queue_before(frag_list, skb, cur_frag);
3418 		return;
3419 	}
3420 	__skb_queue_tail(frag_list, cur_frag);
3421 }
3422 
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3423 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3424 {
3425 	struct ieee80211_hdr *hdr;
3426 	u64 pn = 0;
3427 	u8 *ehdr;
3428 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3429 
3430 	hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3431 	ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3432 
3433 	pn = ehdr[0];
3434 	pn |= (u64)ehdr[1] << 8;
3435 	pn |= (u64)ehdr[4] << 16;
3436 	pn |= (u64)ehdr[5] << 24;
3437 	pn |= (u64)ehdr[6] << 32;
3438 	pn |= (u64)ehdr[7] << 40;
3439 
3440 	return pn;
3441 }
3442 
3443 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3444 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3445 {
3446 	enum hal_encrypt_type encrypt_type;
3447 	struct sk_buff *first_frag, *skb;
3448 	struct hal_rx_desc *desc;
3449 	u64 last_pn;
3450 	u64 cur_pn;
3451 
3452 	first_frag = skb_peek(&rx_tid->rx_frags);
3453 	desc = (struct hal_rx_desc *)first_frag->data;
3454 
3455 	encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3456 	if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3457 	    encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3458 	    encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3459 	    encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3460 		return true;
3461 
3462 	last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3463 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3464 		if (skb == first_frag)
3465 			continue;
3466 
3467 		cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3468 		if (cur_pn != last_pn + 1)
3469 			return false;
3470 		last_pn = cur_pn;
3471 	}
3472 	return true;
3473 }
3474 
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3475 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3476 				    struct sk_buff *msdu,
3477 				    u32 *ring_desc)
3478 {
3479 	struct ath11k_base *ab = ar->ab;
3480 	struct hal_rx_desc *rx_desc;
3481 	struct ath11k_peer *peer;
3482 	struct dp_rx_tid *rx_tid;
3483 	struct sk_buff *defrag_skb = NULL;
3484 	u32 peer_id;
3485 	u16 seqno, frag_no;
3486 	u8 tid;
3487 	int ret = 0;
3488 	bool more_frags;
3489 	bool is_mcbc;
3490 
3491 	rx_desc = (struct hal_rx_desc *)msdu->data;
3492 	peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3493 	tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3494 	seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3495 	frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3496 	more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3497 	is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3498 
3499 	/* Multicast/Broadcast fragments are not expected */
3500 	if (is_mcbc)
3501 		return -EINVAL;
3502 
3503 	if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3504 	    !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3505 	    tid > IEEE80211_NUM_TIDS)
3506 		return -EINVAL;
3507 
3508 	/* received unfragmented packet in reo
3509 	 * exception ring, this shouldn't happen
3510 	 * as these packets typically come from
3511 	 * reo2sw srngs.
3512 	 */
3513 	if (WARN_ON_ONCE(!frag_no && !more_frags))
3514 		return -EINVAL;
3515 
3516 	spin_lock_bh(&ab->base_lock);
3517 	peer = ath11k_peer_find_by_id(ab, peer_id);
3518 	if (!peer) {
3519 		ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3520 			    peer_id);
3521 		ret = -ENOENT;
3522 		goto out_unlock;
3523 	}
3524 	rx_tid = &peer->rx_tid[tid];
3525 
3526 	if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3527 	    skb_queue_empty(&rx_tid->rx_frags)) {
3528 		/* Flush stored fragments and start a new sequence */
3529 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
3530 		rx_tid->cur_sn = seqno;
3531 	}
3532 
3533 	if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3534 		/* Fragment already present */
3535 		ret = -EINVAL;
3536 		goto out_unlock;
3537 	}
3538 
3539 	if (frag_no > __fls(rx_tid->rx_frag_bitmap))
3540 		__skb_queue_tail(&rx_tid->rx_frags, msdu);
3541 	else
3542 		ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3543 
3544 	rx_tid->rx_frag_bitmap |= BIT(frag_no);
3545 	if (!more_frags)
3546 		rx_tid->last_frag_no = frag_no;
3547 
3548 	if (frag_no == 0) {
3549 		rx_tid->dst_ring_desc = kmemdup(ring_desc,
3550 						sizeof(*rx_tid->dst_ring_desc),
3551 						GFP_ATOMIC);
3552 		if (!rx_tid->dst_ring_desc) {
3553 			ret = -ENOMEM;
3554 			goto out_unlock;
3555 		}
3556 	} else {
3557 		ath11k_dp_rx_link_desc_return(ab, ring_desc,
3558 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3559 	}
3560 
3561 	if (!rx_tid->last_frag_no ||
3562 	    rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3563 		mod_timer(&rx_tid->frag_timer, jiffies +
3564 					       ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3565 		goto out_unlock;
3566 	}
3567 
3568 	spin_unlock_bh(&ab->base_lock);
3569 	del_timer_sync(&rx_tid->frag_timer);
3570 	spin_lock_bh(&ab->base_lock);
3571 
3572 	peer = ath11k_peer_find_by_id(ab, peer_id);
3573 	if (!peer)
3574 		goto err_frags_cleanup;
3575 
3576 	if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3577 		goto err_frags_cleanup;
3578 
3579 	if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3580 		goto err_frags_cleanup;
3581 
3582 	if (!defrag_skb)
3583 		goto err_frags_cleanup;
3584 
3585 	if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3586 		goto err_frags_cleanup;
3587 
3588 	ath11k_dp_rx_frags_cleanup(rx_tid, false);
3589 	goto out_unlock;
3590 
3591 err_frags_cleanup:
3592 	dev_kfree_skb_any(defrag_skb);
3593 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3594 out_unlock:
3595 	spin_unlock_bh(&ab->base_lock);
3596 	return ret;
3597 }
3598 
3599 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3600 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3601 {
3602 	struct ath11k_pdev_dp *dp = &ar->dp;
3603 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3604 	struct sk_buff *msdu;
3605 	struct ath11k_skb_rxcb *rxcb;
3606 	struct hal_rx_desc *rx_desc;
3607 	u8 *hdr_status;
3608 	u16 msdu_len;
3609 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3610 
3611 	spin_lock_bh(&rx_ring->idr_lock);
3612 	msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3613 	if (!msdu) {
3614 		ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3615 			    buf_id);
3616 		spin_unlock_bh(&rx_ring->idr_lock);
3617 		return -EINVAL;
3618 	}
3619 
3620 	idr_remove(&rx_ring->bufs_idr, buf_id);
3621 	spin_unlock_bh(&rx_ring->idr_lock);
3622 
3623 	rxcb = ATH11K_SKB_RXCB(msdu);
3624 	dma_unmap_single(ar->ab->dev, rxcb->paddr,
3625 			 msdu->len + skb_tailroom(msdu),
3626 			 DMA_FROM_DEVICE);
3627 
3628 	if (drop) {
3629 		dev_kfree_skb_any(msdu);
3630 		return 0;
3631 	}
3632 
3633 	rcu_read_lock();
3634 	if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3635 		dev_kfree_skb_any(msdu);
3636 		goto exit;
3637 	}
3638 
3639 	if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3640 		dev_kfree_skb_any(msdu);
3641 		goto exit;
3642 	}
3643 
3644 	rx_desc = (struct hal_rx_desc *)msdu->data;
3645 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3646 	if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3647 		hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3648 		ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3649 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3650 				sizeof(struct ieee80211_hdr));
3651 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3652 				sizeof(struct hal_rx_desc));
3653 		dev_kfree_skb_any(msdu);
3654 		goto exit;
3655 	}
3656 
3657 	skb_put(msdu, hal_rx_desc_sz + msdu_len);
3658 
3659 	if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3660 		dev_kfree_skb_any(msdu);
3661 		ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3662 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3663 	}
3664 exit:
3665 	rcu_read_unlock();
3666 	return 0;
3667 }
3668 
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3669 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3670 			     int budget)
3671 {
3672 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3673 	struct dp_link_desc_bank *link_desc_banks;
3674 	enum hal_rx_buf_return_buf_manager rbm;
3675 	int tot_n_bufs_reaped, quota, ret, i;
3676 	int n_bufs_reaped[MAX_RADIOS] = {0};
3677 	struct dp_rxdma_ring *rx_ring;
3678 	struct dp_srng *reo_except;
3679 	u32 desc_bank, num_msdus;
3680 	struct hal_srng *srng;
3681 	struct ath11k_dp *dp;
3682 	void *link_desc_va;
3683 	int buf_id, mac_id;
3684 	struct ath11k *ar;
3685 	dma_addr_t paddr;
3686 	u32 *desc;
3687 	bool is_frag;
3688 	u8 drop = 0;
3689 
3690 	tot_n_bufs_reaped = 0;
3691 	quota = budget;
3692 
3693 	dp = &ab->dp;
3694 	reo_except = &dp->reo_except_ring;
3695 	link_desc_banks = dp->link_desc_banks;
3696 
3697 	srng = &ab->hal.srng_list[reo_except->ring_id];
3698 
3699 	spin_lock_bh(&srng->lock);
3700 
3701 	ath11k_hal_srng_access_begin(ab, srng);
3702 
3703 	while (budget &&
3704 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3705 		struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3706 
3707 		ab->soc_stats.err_ring_pkts++;
3708 		ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3709 						    &desc_bank);
3710 		if (ret) {
3711 			ath11k_warn(ab, "failed to parse error reo desc %d\n",
3712 				    ret);
3713 			continue;
3714 		}
3715 		link_desc_va = link_desc_banks[desc_bank].vaddr +
3716 			       (paddr - link_desc_banks[desc_bank].paddr);
3717 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3718 						 &rbm);
3719 		if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3720 		    rbm != HAL_RX_BUF_RBM_SW3_BM) {
3721 			ab->soc_stats.invalid_rbm++;
3722 			ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3723 			ath11k_dp_rx_link_desc_return(ab, desc,
3724 						      HAL_WBM_REL_BM_ACT_REL_MSDU);
3725 			continue;
3726 		}
3727 
3728 		is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3729 
3730 		/* Process only rx fragments with one msdu per link desc below, and drop
3731 		 * msdu's indicated due to error reasons.
3732 		 */
3733 		if (!is_frag || num_msdus > 1) {
3734 			drop = 1;
3735 			/* Return the link desc back to wbm idle list */
3736 			ath11k_dp_rx_link_desc_return(ab, desc,
3737 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3738 		}
3739 
3740 		for (i = 0; i < num_msdus; i++) {
3741 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3742 					   msdu_cookies[i]);
3743 
3744 			mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3745 					   msdu_cookies[i]);
3746 
3747 			ar = ab->pdevs[mac_id].ar;
3748 
3749 			if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3750 				n_bufs_reaped[mac_id]++;
3751 				tot_n_bufs_reaped++;
3752 			}
3753 		}
3754 
3755 		if (tot_n_bufs_reaped >= quota) {
3756 			tot_n_bufs_reaped = quota;
3757 			goto exit;
3758 		}
3759 
3760 		budget = quota - tot_n_bufs_reaped;
3761 	}
3762 
3763 exit:
3764 	ath11k_hal_srng_access_end(ab, srng);
3765 
3766 	spin_unlock_bh(&srng->lock);
3767 
3768 	for (i = 0; i <  ab->num_radios; i++) {
3769 		if (!n_bufs_reaped[i])
3770 			continue;
3771 
3772 		ar = ab->pdevs[i].ar;
3773 		rx_ring = &ar->dp.rx_refill_buf_ring;
3774 
3775 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3776 					   HAL_RX_BUF_RBM_SW3_BM);
3777 	}
3778 
3779 	return tot_n_bufs_reaped;
3780 }
3781 
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3782 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3783 					     int msdu_len,
3784 					     struct sk_buff_head *msdu_list)
3785 {
3786 	struct sk_buff *skb, *tmp;
3787 	struct ath11k_skb_rxcb *rxcb;
3788 	int n_buffs;
3789 
3790 	n_buffs = DIV_ROUND_UP(msdu_len,
3791 			       (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3792 
3793 	skb_queue_walk_safe(msdu_list, skb, tmp) {
3794 		rxcb = ATH11K_SKB_RXCB(skb);
3795 		if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3796 		    rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3797 			if (!n_buffs)
3798 				break;
3799 			__skb_unlink(skb, msdu_list);
3800 			dev_kfree_skb_any(skb);
3801 			n_buffs--;
3802 		}
3803 	}
3804 }
3805 
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3806 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3807 				      struct ieee80211_rx_status *status,
3808 				      struct sk_buff_head *msdu_list)
3809 {
3810 	u16 msdu_len;
3811 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3812 	struct rx_attention *rx_attention;
3813 	u8 l3pad_bytes;
3814 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3815 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3816 
3817 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3818 
3819 	if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3820 		/* First buffer will be freed by the caller, so deduct it's length */
3821 		msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3822 		ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3823 		return -EINVAL;
3824 	}
3825 
3826 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3827 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3828 		ath11k_warn(ar->ab,
3829 			    "msdu_done bit not set in null_q_des processing\n");
3830 		__skb_queue_purge(msdu_list);
3831 		return -EIO;
3832 	}
3833 
3834 	/* Handle NULL queue descriptor violations arising out a missing
3835 	 * REO queue for a given peer or a given TID. This typically
3836 	 * may happen if a packet is received on a QOS enabled TID before the
3837 	 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3838 	 * it may also happen for MC/BC frames if they are not routed to the
3839 	 * non-QOS TID queue, in the absence of any other default TID queue.
3840 	 * This error can show up both in a REO destination or WBM release ring.
3841 	 */
3842 
3843 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3844 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3845 
3846 	if (rxcb->is_frag) {
3847 		skb_pull(msdu, hal_rx_desc_sz);
3848 	} else {
3849 		l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3850 
3851 		if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3852 			return -EINVAL;
3853 
3854 		skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3855 		skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3856 	}
3857 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3858 
3859 	ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3860 
3861 	rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
3862 
3863 	/* Please note that caller will having the access to msdu and completing
3864 	 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3865 	 */
3866 
3867 	return 0;
3868 }
3869 
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3870 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3871 				   struct ieee80211_rx_status *status,
3872 				   struct sk_buff_head *msdu_list)
3873 {
3874 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3875 	bool drop = false;
3876 
3877 	ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3878 
3879 	switch (rxcb->err_code) {
3880 	case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3881 		if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3882 			drop = true;
3883 		break;
3884 	case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3885 		/* TODO: Do not drop PN failed packets in the driver;
3886 		 * instead, it is good to drop such packets in mac80211
3887 		 * after incrementing the replay counters.
3888 		 */
3889 		fallthrough;
3890 	default:
3891 		/* TODO: Review other errors and process them to mac80211
3892 		 * as appropriate.
3893 		 */
3894 		drop = true;
3895 		break;
3896 	}
3897 
3898 	return drop;
3899 }
3900 
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3901 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
3902 					struct ieee80211_rx_status *status)
3903 {
3904 	u16 msdu_len;
3905 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3906 	u8 l3pad_bytes;
3907 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3908 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3909 
3910 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3911 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3912 
3913 	l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3914 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3915 	skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3916 	skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3917 
3918 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3919 
3920 	status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
3921 			 RX_FLAG_DECRYPTED);
3922 
3923 	ath11k_dp_rx_h_undecap(ar, msdu, desc,
3924 			       HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
3925 }
3926 
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3927 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar,  struct sk_buff *msdu,
3928 				     struct ieee80211_rx_status *status)
3929 {
3930 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3931 	bool drop = false;
3932 
3933 	ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
3934 
3935 	switch (rxcb->err_code) {
3936 	case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
3937 		ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
3938 		break;
3939 	default:
3940 		/* TODO: Review other rxdma error code to check if anything is
3941 		 * worth reporting to mac80211
3942 		 */
3943 		drop = true;
3944 		break;
3945 	}
3946 
3947 	return drop;
3948 }
3949 
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)3950 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
3951 				 struct napi_struct *napi,
3952 				 struct sk_buff *msdu,
3953 				 struct sk_buff_head *msdu_list)
3954 {
3955 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3956 	struct ieee80211_rx_status rxs = {0};
3957 	struct ieee80211_rx_status *status;
3958 	bool drop = true;
3959 
3960 	switch (rxcb->err_rel_src) {
3961 	case HAL_WBM_REL_SRC_MODULE_REO:
3962 		drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
3963 		break;
3964 	case HAL_WBM_REL_SRC_MODULE_RXDMA:
3965 		drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
3966 		break;
3967 	default:
3968 		/* msdu will get freed */
3969 		break;
3970 	}
3971 
3972 	if (drop) {
3973 		dev_kfree_skb_any(msdu);
3974 		return;
3975 	}
3976 
3977 	status = IEEE80211_SKB_RXCB(msdu);
3978 	*status = rxs;
3979 
3980 	ath11k_dp_rx_deliver_msdu(ar, napi, msdu);
3981 }
3982 
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3983 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
3984 				 struct napi_struct *napi, int budget)
3985 {
3986 	struct ath11k *ar;
3987 	struct ath11k_dp *dp = &ab->dp;
3988 	struct dp_rxdma_ring *rx_ring;
3989 	struct hal_rx_wbm_rel_info err_info;
3990 	struct hal_srng *srng;
3991 	struct sk_buff *msdu;
3992 	struct sk_buff_head msdu_list[MAX_RADIOS];
3993 	struct ath11k_skb_rxcb *rxcb;
3994 	u32 *rx_desc;
3995 	int buf_id, mac_id;
3996 	int num_buffs_reaped[MAX_RADIOS] = {0};
3997 	int total_num_buffs_reaped = 0;
3998 	int ret, i;
3999 
4000 	for (i = 0; i < ab->num_radios; i++)
4001 		__skb_queue_head_init(&msdu_list[i]);
4002 
4003 	srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4004 
4005 	spin_lock_bh(&srng->lock);
4006 
4007 	ath11k_hal_srng_access_begin(ab, srng);
4008 
4009 	while (budget) {
4010 		rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4011 		if (!rx_desc)
4012 			break;
4013 
4014 		ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4015 		if (ret) {
4016 			ath11k_warn(ab,
4017 				    "failed to parse rx error in wbm_rel ring desc %d\n",
4018 				    ret);
4019 			continue;
4020 		}
4021 
4022 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4023 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4024 
4025 		ar = ab->pdevs[mac_id].ar;
4026 		rx_ring = &ar->dp.rx_refill_buf_ring;
4027 
4028 		spin_lock_bh(&rx_ring->idr_lock);
4029 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4030 		if (!msdu) {
4031 			ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4032 				    buf_id, mac_id);
4033 			spin_unlock_bh(&rx_ring->idr_lock);
4034 			continue;
4035 		}
4036 
4037 		idr_remove(&rx_ring->bufs_idr, buf_id);
4038 		spin_unlock_bh(&rx_ring->idr_lock);
4039 
4040 		rxcb = ATH11K_SKB_RXCB(msdu);
4041 		dma_unmap_single(ab->dev, rxcb->paddr,
4042 				 msdu->len + skb_tailroom(msdu),
4043 				 DMA_FROM_DEVICE);
4044 
4045 		num_buffs_reaped[mac_id]++;
4046 		total_num_buffs_reaped++;
4047 		budget--;
4048 
4049 		if (err_info.push_reason !=
4050 		    HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4051 			dev_kfree_skb_any(msdu);
4052 			continue;
4053 		}
4054 
4055 		rxcb->err_rel_src = err_info.err_rel_src;
4056 		rxcb->err_code = err_info.err_code;
4057 		rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4058 		__skb_queue_tail(&msdu_list[mac_id], msdu);
4059 	}
4060 
4061 	ath11k_hal_srng_access_end(ab, srng);
4062 
4063 	spin_unlock_bh(&srng->lock);
4064 
4065 	if (!total_num_buffs_reaped)
4066 		goto done;
4067 
4068 	for (i = 0; i <  ab->num_radios; i++) {
4069 		if (!num_buffs_reaped[i])
4070 			continue;
4071 
4072 		ar = ab->pdevs[i].ar;
4073 		rx_ring = &ar->dp.rx_refill_buf_ring;
4074 
4075 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4076 					   HAL_RX_BUF_RBM_SW3_BM);
4077 	}
4078 
4079 	rcu_read_lock();
4080 	for (i = 0; i <  ab->num_radios; i++) {
4081 		if (!rcu_dereference(ab->pdevs_active[i])) {
4082 			__skb_queue_purge(&msdu_list[i]);
4083 			continue;
4084 		}
4085 
4086 		ar = ab->pdevs[i].ar;
4087 
4088 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4089 			__skb_queue_purge(&msdu_list[i]);
4090 			continue;
4091 		}
4092 
4093 		while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4094 			ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4095 	}
4096 	rcu_read_unlock();
4097 done:
4098 	return total_num_buffs_reaped;
4099 }
4100 
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4101 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4102 {
4103 	struct ath11k *ar;
4104 	struct dp_srng *err_ring;
4105 	struct dp_rxdma_ring *rx_ring;
4106 	struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4107 	struct hal_srng *srng;
4108 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4109 	enum hal_rx_buf_return_buf_manager rbm;
4110 	enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4111 	struct ath11k_skb_rxcb *rxcb;
4112 	struct sk_buff *skb;
4113 	struct hal_reo_entrance_ring *entr_ring;
4114 	void *desc;
4115 	int num_buf_freed = 0;
4116 	int quota = budget;
4117 	dma_addr_t paddr;
4118 	u32 desc_bank;
4119 	void *link_desc_va;
4120 	int num_msdus;
4121 	int i;
4122 	int buf_id;
4123 
4124 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4125 	err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4126 									  mac_id)];
4127 	rx_ring = &ar->dp.rx_refill_buf_ring;
4128 
4129 	srng = &ab->hal.srng_list[err_ring->ring_id];
4130 
4131 	spin_lock_bh(&srng->lock);
4132 
4133 	ath11k_hal_srng_access_begin(ab, srng);
4134 
4135 	while (quota-- &&
4136 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4137 		ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4138 
4139 		entr_ring = (struct hal_reo_entrance_ring *)desc;
4140 		rxdma_err_code =
4141 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4142 				  entr_ring->info1);
4143 		ab->soc_stats.rxdma_error[rxdma_err_code]++;
4144 
4145 		link_desc_va = link_desc_banks[desc_bank].vaddr +
4146 			       (paddr - link_desc_banks[desc_bank].paddr);
4147 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4148 						 msdu_cookies, &rbm);
4149 
4150 		for (i = 0; i < num_msdus; i++) {
4151 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4152 					   msdu_cookies[i]);
4153 
4154 			spin_lock_bh(&rx_ring->idr_lock);
4155 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
4156 			if (!skb) {
4157 				ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4158 					    buf_id);
4159 				spin_unlock_bh(&rx_ring->idr_lock);
4160 				continue;
4161 			}
4162 
4163 			idr_remove(&rx_ring->bufs_idr, buf_id);
4164 			spin_unlock_bh(&rx_ring->idr_lock);
4165 
4166 			rxcb = ATH11K_SKB_RXCB(skb);
4167 			dma_unmap_single(ab->dev, rxcb->paddr,
4168 					 skb->len + skb_tailroom(skb),
4169 					 DMA_FROM_DEVICE);
4170 			dev_kfree_skb_any(skb);
4171 
4172 			num_buf_freed++;
4173 		}
4174 
4175 		ath11k_dp_rx_link_desc_return(ab, desc,
4176 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4177 	}
4178 
4179 	ath11k_hal_srng_access_end(ab, srng);
4180 
4181 	spin_unlock_bh(&srng->lock);
4182 
4183 	if (num_buf_freed)
4184 		ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4185 					   HAL_RX_BUF_RBM_SW3_BM);
4186 
4187 	return budget - quota;
4188 }
4189 
ath11k_dp_process_reo_status(struct ath11k_base * ab)4190 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4191 {
4192 	struct ath11k_dp *dp = &ab->dp;
4193 	struct hal_srng *srng;
4194 	struct dp_reo_cmd *cmd, *tmp;
4195 	bool found = false;
4196 	u32 *reo_desc;
4197 	u16 tag;
4198 	struct hal_reo_status reo_status;
4199 
4200 	srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4201 
4202 	memset(&reo_status, 0, sizeof(reo_status));
4203 
4204 	spin_lock_bh(&srng->lock);
4205 
4206 	ath11k_hal_srng_access_begin(ab, srng);
4207 
4208 	while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4209 		tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4210 
4211 		switch (tag) {
4212 		case HAL_REO_GET_QUEUE_STATS_STATUS:
4213 			ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4214 							  &reo_status);
4215 			break;
4216 		case HAL_REO_FLUSH_QUEUE_STATUS:
4217 			ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4218 							  &reo_status);
4219 			break;
4220 		case HAL_REO_FLUSH_CACHE_STATUS:
4221 			ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4222 							  &reo_status);
4223 			break;
4224 		case HAL_REO_UNBLOCK_CACHE_STATUS:
4225 			ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4226 							  &reo_status);
4227 			break;
4228 		case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4229 			ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4230 								 &reo_status);
4231 			break;
4232 		case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4233 			ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4234 								  &reo_status);
4235 			break;
4236 		case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4237 			ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4238 								  &reo_status);
4239 			break;
4240 		default:
4241 			ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4242 			continue;
4243 		}
4244 
4245 		spin_lock_bh(&dp->reo_cmd_lock);
4246 		list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4247 			if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4248 				found = true;
4249 				list_del(&cmd->list);
4250 				break;
4251 			}
4252 		}
4253 		spin_unlock_bh(&dp->reo_cmd_lock);
4254 
4255 		if (found) {
4256 			cmd->handler(dp, (void *)&cmd->data,
4257 				     reo_status.uniform_hdr.cmd_status);
4258 			kfree(cmd);
4259 		}
4260 
4261 		found = false;
4262 	}
4263 
4264 	ath11k_hal_srng_access_end(ab, srng);
4265 
4266 	spin_unlock_bh(&srng->lock);
4267 }
4268 
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4269 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4270 {
4271 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4272 
4273 	ath11k_dp_rx_pdev_srng_free(ar);
4274 	ath11k_dp_rxdma_pdev_buf_free(ar);
4275 }
4276 
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4277 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4278 {
4279 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4280 	struct ath11k_pdev_dp *dp = &ar->dp;
4281 	u32 ring_id;
4282 	int i;
4283 	int ret;
4284 
4285 	ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4286 	if (ret) {
4287 		ath11k_warn(ab, "failed to setup rx srngs\n");
4288 		return ret;
4289 	}
4290 
4291 	ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4292 	if (ret) {
4293 		ath11k_warn(ab, "failed to setup rxdma ring\n");
4294 		return ret;
4295 	}
4296 
4297 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4298 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4299 	if (ret) {
4300 		ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4301 			    ret);
4302 		return ret;
4303 	}
4304 
4305 	if (ab->hw_params.rx_mac_buf_ring) {
4306 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4307 			ring_id = dp->rx_mac_buf_ring[i].ring_id;
4308 			ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4309 							  mac_id + i, HAL_RXDMA_BUF);
4310 			if (ret) {
4311 				ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4312 					    i, ret);
4313 				return ret;
4314 			}
4315 		}
4316 	}
4317 
4318 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4319 		ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4320 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4321 						  mac_id + i, HAL_RXDMA_DST);
4322 		if (ret) {
4323 			ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4324 				    i, ret);
4325 			return ret;
4326 		}
4327 	}
4328 
4329 	if (!ab->hw_params.rxdma1_enable)
4330 		goto config_refill_ring;
4331 
4332 	ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4333 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4334 					  mac_id, HAL_RXDMA_MONITOR_BUF);
4335 	if (ret) {
4336 		ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4337 			    ret);
4338 		return ret;
4339 	}
4340 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4341 					  dp->rxdma_mon_dst_ring.ring_id,
4342 					  mac_id, HAL_RXDMA_MONITOR_DST);
4343 	if (ret) {
4344 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4345 			    ret);
4346 		return ret;
4347 	}
4348 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4349 					  dp->rxdma_mon_desc_ring.ring_id,
4350 					  mac_id, HAL_RXDMA_MONITOR_DESC);
4351 	if (ret) {
4352 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4353 			    ret);
4354 		return ret;
4355 	}
4356 
4357 config_refill_ring:
4358 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4359 		ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4360 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4361 						  HAL_RXDMA_MONITOR_STATUS);
4362 		if (ret) {
4363 			ath11k_warn(ab,
4364 				    "failed to configure mon_status_refill_ring%d %d\n",
4365 				    i, ret);
4366 			return ret;
4367 		}
4368 	}
4369 
4370 	return 0;
4371 }
4372 
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4373 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4374 {
4375 	if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4376 		*frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4377 		*total_len -= *frag_len;
4378 	} else {
4379 		*frag_len = *total_len;
4380 		*total_len = 0;
4381 	}
4382 }
4383 
4384 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4385 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4386 					  void *p_last_buf_addr_info,
4387 					  u8 mac_id)
4388 {
4389 	struct ath11k_pdev_dp *dp = &ar->dp;
4390 	struct dp_srng *dp_srng;
4391 	void *hal_srng;
4392 	void *src_srng_desc;
4393 	int ret = 0;
4394 
4395 	if (ar->ab->hw_params.rxdma1_enable) {
4396 		dp_srng = &dp->rxdma_mon_desc_ring;
4397 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4398 	} else {
4399 		dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4400 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4401 	}
4402 
4403 	ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4404 
4405 	src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4406 
4407 	if (src_srng_desc) {
4408 		struct ath11k_buffer_addr *src_desc =
4409 				(struct ath11k_buffer_addr *)src_srng_desc;
4410 
4411 		*src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4412 	} else {
4413 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4414 			   "Monitor Link Desc Ring %d Full", mac_id);
4415 		ret = -ENOMEM;
4416 	}
4417 
4418 	ath11k_hal_srng_access_end(ar->ab, hal_srng);
4419 	return ret;
4420 }
4421 
4422 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4423 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4424 					 dma_addr_t *paddr, u32 *sw_cookie,
4425 					 u8 *rbm,
4426 					 void **pp_buf_addr_info)
4427 {
4428 	struct hal_rx_msdu_link *msdu_link =
4429 			(struct hal_rx_msdu_link *)rx_msdu_link_desc;
4430 	struct ath11k_buffer_addr *buf_addr_info;
4431 
4432 	buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4433 
4434 	ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4435 
4436 	*pp_buf_addr_info = (void *)buf_addr_info;
4437 }
4438 
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4439 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4440 {
4441 	if (skb->len > len) {
4442 		skb_trim(skb, len);
4443 	} else {
4444 		if (skb_tailroom(skb) < len - skb->len) {
4445 			if ((pskb_expand_head(skb, 0,
4446 					      len - skb->len - skb_tailroom(skb),
4447 					      GFP_ATOMIC))) {
4448 				dev_kfree_skb_any(skb);
4449 				return -ENOMEM;
4450 			}
4451 		}
4452 		skb_put(skb, (len - skb->len));
4453 	}
4454 	return 0;
4455 }
4456 
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4457 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4458 					void *msdu_link_desc,
4459 					struct hal_rx_msdu_list *msdu_list,
4460 					u16 *num_msdus)
4461 {
4462 	struct hal_rx_msdu_details *msdu_details = NULL;
4463 	struct rx_msdu_desc *msdu_desc_info = NULL;
4464 	struct hal_rx_msdu_link *msdu_link = NULL;
4465 	int i;
4466 	u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4467 	u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4468 	u8  tmp  = 0;
4469 
4470 	msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc;
4471 	msdu_details = &msdu_link->msdu_link[0];
4472 
4473 	for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4474 		if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4475 			      msdu_details[i].buf_addr_info.info0) == 0) {
4476 			msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4477 			msdu_desc_info->info0 |= last;
4478 			;
4479 			break;
4480 		}
4481 		msdu_desc_info = &msdu_details[i].rx_msdu_info;
4482 
4483 		if (!i)
4484 			msdu_desc_info->info0 |= first;
4485 		else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4486 			msdu_desc_info->info0 |= last;
4487 		msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4488 		msdu_list->msdu_info[i].msdu_len =
4489 			 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4490 		msdu_list->sw_cookie[i] =
4491 			FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4492 				  msdu_details[i].buf_addr_info.info1);
4493 		tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4494 				msdu_details[i].buf_addr_info.info1);
4495 		msdu_list->rbm[i] = tmp;
4496 	}
4497 	*num_msdus = i;
4498 }
4499 
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4500 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4501 					u32 *rx_bufs_used)
4502 {
4503 	u32 ret = 0;
4504 
4505 	if ((*ppdu_id < msdu_ppdu_id) &&
4506 	    ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4507 		*ppdu_id = msdu_ppdu_id;
4508 		ret = msdu_ppdu_id;
4509 	} else if ((*ppdu_id > msdu_ppdu_id) &&
4510 		((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4511 		/* mon_dst is behind than mon_status
4512 		 * skip dst_ring and free it
4513 		 */
4514 		*rx_bufs_used += 1;
4515 		*ppdu_id = msdu_ppdu_id;
4516 		ret = msdu_ppdu_id;
4517 	}
4518 	return ret;
4519 }
4520 
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4521 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4522 				      bool *is_frag, u32 *total_len,
4523 				      u32 *frag_len, u32 *msdu_cnt)
4524 {
4525 	if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4526 		if (!*is_frag) {
4527 			*total_len = info->msdu_len;
4528 			*is_frag = true;
4529 		}
4530 		ath11k_dp_mon_set_frag_len(total_len,
4531 					   frag_len);
4532 	} else {
4533 		if (*is_frag) {
4534 			ath11k_dp_mon_set_frag_len(total_len,
4535 						   frag_len);
4536 		} else {
4537 			*frag_len = info->msdu_len;
4538 		}
4539 		*is_frag = false;
4540 		*msdu_cnt -= 1;
4541 	}
4542 }
4543 
4544 static u32
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4545 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4546 			  void *ring_entry, struct sk_buff **head_msdu,
4547 			  struct sk_buff **tail_msdu, u32 *npackets,
4548 			  u32 *ppdu_id)
4549 {
4550 	struct ath11k_pdev_dp *dp = &ar->dp;
4551 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4552 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4553 	struct sk_buff *msdu = NULL, *last = NULL;
4554 	struct hal_rx_msdu_list msdu_list;
4555 	void *p_buf_addr_info, *p_last_buf_addr_info;
4556 	struct hal_rx_desc *rx_desc;
4557 	void *rx_msdu_link_desc;
4558 	dma_addr_t paddr;
4559 	u16 num_msdus = 0;
4560 	u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4561 	u32 rx_bufs_used = 0, i = 0;
4562 	u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4563 	u32 total_len = 0, frag_len = 0;
4564 	bool is_frag, is_first_msdu;
4565 	bool drop_mpdu = false;
4566 	struct ath11k_skb_rxcb *rxcb;
4567 	struct hal_reo_entrance_ring *ent_desc =
4568 			(struct hal_reo_entrance_ring *)ring_entry;
4569 	int buf_id;
4570 	u32 rx_link_buf_info[2];
4571 	u8 rbm;
4572 
4573 	if (!ar->ab->hw_params.rxdma1_enable)
4574 		rx_ring = &dp->rx_refill_buf_ring;
4575 
4576 	ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4577 					    &sw_cookie,
4578 					    &p_last_buf_addr_info, &rbm,
4579 					    &msdu_cnt);
4580 
4581 	if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4582 		      ent_desc->info1) ==
4583 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4584 		u8 rxdma_err =
4585 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4586 				  ent_desc->info1);
4587 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4588 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4589 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4590 			drop_mpdu = true;
4591 			pmon->rx_mon_stats.dest_mpdu_drop++;
4592 		}
4593 	}
4594 
4595 	is_frag = false;
4596 	is_first_msdu = true;
4597 
4598 	do {
4599 		if (pmon->mon_last_linkdesc_paddr == paddr) {
4600 			pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4601 			return rx_bufs_used;
4602 		}
4603 
4604 		if (ar->ab->hw_params.rxdma1_enable)
4605 			rx_msdu_link_desc =
4606 				(void *)pmon->link_desc_banks[sw_cookie].vaddr +
4607 				(paddr - pmon->link_desc_banks[sw_cookie].paddr);
4608 		else
4609 			rx_msdu_link_desc =
4610 				(void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4611 				(paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4612 
4613 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4614 					    &num_msdus);
4615 
4616 		for (i = 0; i < num_msdus; i++) {
4617 			u32 l2_hdr_offset;
4618 
4619 			if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4620 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4621 					   "i %d last_cookie %d is same\n",
4622 					   i, pmon->mon_last_buf_cookie);
4623 				drop_mpdu = true;
4624 				pmon->rx_mon_stats.dup_mon_buf_cnt++;
4625 				continue;
4626 			}
4627 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4628 					   msdu_list.sw_cookie[i]);
4629 
4630 			spin_lock_bh(&rx_ring->idr_lock);
4631 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4632 			spin_unlock_bh(&rx_ring->idr_lock);
4633 			if (!msdu) {
4634 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4635 					   "msdu_pop: invalid buf_id %d\n", buf_id);
4636 				break;
4637 			}
4638 			rxcb = ATH11K_SKB_RXCB(msdu);
4639 			if (!rxcb->unmapped) {
4640 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
4641 						 msdu->len +
4642 						 skb_tailroom(msdu),
4643 						 DMA_FROM_DEVICE);
4644 				rxcb->unmapped = 1;
4645 			}
4646 			if (drop_mpdu) {
4647 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4648 					   "i %d drop msdu %p *ppdu_id %x\n",
4649 					   i, msdu, *ppdu_id);
4650 				dev_kfree_skb_any(msdu);
4651 				msdu = NULL;
4652 				goto next_msdu;
4653 			}
4654 
4655 			rx_desc = (struct hal_rx_desc *)msdu->data;
4656 
4657 			rx_pkt_offset = sizeof(struct hal_rx_desc);
4658 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4659 
4660 			if (is_first_msdu) {
4661 				if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4662 					drop_mpdu = true;
4663 					dev_kfree_skb_any(msdu);
4664 					msdu = NULL;
4665 					pmon->mon_last_linkdesc_paddr = paddr;
4666 					goto next_msdu;
4667 				}
4668 
4669 				msdu_ppdu_id =
4670 					ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4671 
4672 				if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4673 								 ppdu_id,
4674 								 &rx_bufs_used)) {
4675 					if (rx_bufs_used) {
4676 						drop_mpdu = true;
4677 						dev_kfree_skb_any(msdu);
4678 						msdu = NULL;
4679 						goto next_msdu;
4680 					}
4681 					return rx_bufs_used;
4682 				}
4683 				pmon->mon_last_linkdesc_paddr = paddr;
4684 				is_first_msdu = false;
4685 			}
4686 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4687 						  &is_frag, &total_len,
4688 						  &frag_len, &msdu_cnt);
4689 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4690 
4691 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4692 
4693 			if (!(*head_msdu))
4694 				*head_msdu = msdu;
4695 			else if (last)
4696 				last->next = msdu;
4697 
4698 			last = msdu;
4699 next_msdu:
4700 			pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4701 			rx_bufs_used++;
4702 			spin_lock_bh(&rx_ring->idr_lock);
4703 			idr_remove(&rx_ring->bufs_idr, buf_id);
4704 			spin_unlock_bh(&rx_ring->idr_lock);
4705 		}
4706 
4707 		ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4708 
4709 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4710 						    &sw_cookie, &rbm,
4711 						    &p_buf_addr_info);
4712 
4713 		if (ar->ab->hw_params.rxdma1_enable) {
4714 			if (ath11k_dp_rx_monitor_link_desc_return(ar,
4715 								  p_last_buf_addr_info,
4716 								  dp->mac_id))
4717 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4718 					   "dp_rx_monitor_link_desc_return failed");
4719 		} else {
4720 			ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4721 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4722 		}
4723 
4724 		p_last_buf_addr_info = p_buf_addr_info;
4725 
4726 	} while (paddr && msdu_cnt);
4727 
4728 	if (last)
4729 		last->next = NULL;
4730 
4731 	*tail_msdu = msdu;
4732 
4733 	if (msdu_cnt == 0)
4734 		*npackets = 1;
4735 
4736 	return rx_bufs_used;
4737 }
4738 
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4739 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4740 {
4741 	u32 rx_pkt_offset, l2_hdr_offset;
4742 
4743 	rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4744 	l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4745 						      (struct hal_rx_desc *)msdu->data);
4746 	skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4747 }
4748 
4749 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs)4750 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4751 			    u32 mac_id, struct sk_buff *head_msdu,
4752 			    struct sk_buff *last_msdu,
4753 			    struct ieee80211_rx_status *rxs)
4754 {
4755 	struct ath11k_base *ab = ar->ab;
4756 	struct sk_buff *msdu, *mpdu_buf, *prev_buf;
4757 	u32 wifi_hdr_len;
4758 	struct hal_rx_desc *rx_desc;
4759 	char *hdr_desc;
4760 	u8 *dest, decap_format;
4761 	struct ieee80211_hdr_3addr *wh;
4762 	struct rx_attention *rx_attention;
4763 
4764 	mpdu_buf = NULL;
4765 
4766 	if (!head_msdu)
4767 		goto err_merge_fail;
4768 
4769 	rx_desc = (struct hal_rx_desc *)head_msdu->data;
4770 	rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4771 
4772 	if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4773 		return NULL;
4774 
4775 	decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4776 
4777 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4778 
4779 	if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4780 		ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4781 
4782 		prev_buf = head_msdu;
4783 		msdu = head_msdu->next;
4784 
4785 		while (msdu) {
4786 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4787 
4788 			prev_buf = msdu;
4789 			msdu = msdu->next;
4790 		}
4791 
4792 		prev_buf->next = NULL;
4793 
4794 		skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4795 	} else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4796 		__le16 qos_field;
4797 		u8 qos_pkt = 0;
4798 
4799 		rx_desc = (struct hal_rx_desc *)head_msdu->data;
4800 		hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4801 
4802 		/* Base size */
4803 		wifi_hdr_len = sizeof(struct ieee80211_hdr_3addr);
4804 		wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4805 
4806 		if (ieee80211_is_data_qos(wh->frame_control)) {
4807 			struct ieee80211_qos_hdr *qwh =
4808 					(struct ieee80211_qos_hdr *)hdr_desc;
4809 
4810 			qos_field = qwh->qos_ctrl;
4811 			qos_pkt = 1;
4812 		}
4813 		msdu = head_msdu;
4814 
4815 		while (msdu) {
4816 			rx_desc = (struct hal_rx_desc *)msdu->data;
4817 			hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4818 
4819 			if (qos_pkt) {
4820 				dest = skb_push(msdu, sizeof(__le16));
4821 				if (!dest)
4822 					goto err_merge_fail;
4823 				memcpy(dest, hdr_desc, wifi_hdr_len);
4824 				memcpy(dest + wifi_hdr_len,
4825 				       (u8 *)&qos_field, sizeof(__le16));
4826 			}
4827 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4828 			prev_buf = msdu;
4829 			msdu = msdu->next;
4830 		}
4831 		dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4832 		if (!dest)
4833 			goto err_merge_fail;
4834 
4835 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4836 			   "mpdu_buf %pK mpdu_buf->len %u",
4837 			   prev_buf, prev_buf->len);
4838 	} else {
4839 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4840 			   "decap format %d is not supported!\n",
4841 			   decap_format);
4842 		goto err_merge_fail;
4843 	}
4844 
4845 	return head_msdu;
4846 
4847 err_merge_fail:
4848 	if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) {
4849 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4850 			   "err_merge_fail mpdu_buf %pK", mpdu_buf);
4851 		/* Free the head buffer */
4852 		dev_kfree_skb_any(mpdu_buf);
4853 	}
4854 	return NULL;
4855 }
4856 
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * tail_msdu,struct napi_struct * napi)4857 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
4858 				    struct sk_buff *head_msdu,
4859 				    struct sk_buff *tail_msdu,
4860 				    struct napi_struct *napi)
4861 {
4862 	struct ath11k_pdev_dp *dp = &ar->dp;
4863 	struct sk_buff *mon_skb, *skb_next, *header;
4864 	struct ieee80211_rx_status *rxs = &dp->rx_status, *status;
4865 
4866 	mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
4867 					      tail_msdu, rxs);
4868 
4869 	if (!mon_skb)
4870 		goto mon_deliver_fail;
4871 
4872 	header = mon_skb;
4873 
4874 	rxs->flag = 0;
4875 	do {
4876 		skb_next = mon_skb->next;
4877 		if (!skb_next)
4878 			rxs->flag &= ~RX_FLAG_AMSDU_MORE;
4879 		else
4880 			rxs->flag |= RX_FLAG_AMSDU_MORE;
4881 
4882 		if (mon_skb == header) {
4883 			header = NULL;
4884 			rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
4885 		} else {
4886 			rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
4887 		}
4888 		rxs->flag |= RX_FLAG_ONLY_MONITOR;
4889 
4890 		status = IEEE80211_SKB_RXCB(mon_skb);
4891 		*status = *rxs;
4892 
4893 		ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb);
4894 		mon_skb = skb_next;
4895 	} while (mon_skb);
4896 	rxs->flag = 0;
4897 
4898 	return 0;
4899 
4900 mon_deliver_fail:
4901 	mon_skb = head_msdu;
4902 	while (mon_skb) {
4903 		skb_next = mon_skb->next;
4904 		dev_kfree_skb_any(mon_skb);
4905 		mon_skb = skb_next;
4906 	}
4907 	return -EINVAL;
4908 }
4909 
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)4910 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
4911 					  u32 quota, struct napi_struct *napi)
4912 {
4913 	struct ath11k_pdev_dp *dp = &ar->dp;
4914 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4915 	void *ring_entry;
4916 	void *mon_dst_srng;
4917 	u32 ppdu_id;
4918 	u32 rx_bufs_used;
4919 	u32 ring_id;
4920 	struct ath11k_pdev_mon_stats *rx_mon_stats;
4921 	u32	 npackets = 0;
4922 
4923 	if (ar->ab->hw_params.rxdma1_enable)
4924 		ring_id = dp->rxdma_mon_dst_ring.ring_id;
4925 	else
4926 		ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
4927 
4928 	mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
4929 
4930 	if (!mon_dst_srng) {
4931 		ath11k_warn(ar->ab,
4932 			    "HAL Monitor Destination Ring Init Failed -- %pK",
4933 			    mon_dst_srng);
4934 		return;
4935 	}
4936 
4937 	spin_lock_bh(&pmon->mon_lock);
4938 
4939 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
4940 
4941 	ppdu_id = pmon->mon_ppdu_info.ppdu_id;
4942 	rx_bufs_used = 0;
4943 	rx_mon_stats = &pmon->rx_mon_stats;
4944 
4945 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
4946 		struct sk_buff *head_msdu, *tail_msdu;
4947 
4948 		head_msdu = NULL;
4949 		tail_msdu = NULL;
4950 
4951 		rx_bufs_used += ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
4952 							  &head_msdu,
4953 							  &tail_msdu,
4954 							  &npackets, &ppdu_id);
4955 
4956 		if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
4957 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4958 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4959 				   "dest_rx: new ppdu_id %x != status ppdu_id %x",
4960 				   ppdu_id, pmon->mon_ppdu_info.ppdu_id);
4961 			break;
4962 		}
4963 		if (head_msdu && tail_msdu) {
4964 			ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
4965 						 tail_msdu, napi);
4966 			rx_mon_stats->dest_mpdu_done++;
4967 		}
4968 
4969 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
4970 								mon_dst_srng);
4971 	}
4972 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
4973 
4974 	spin_unlock_bh(&pmon->mon_lock);
4975 
4976 	if (rx_bufs_used) {
4977 		rx_mon_stats->dest_ppdu_done++;
4978 		if (ar->ab->hw_params.rxdma1_enable)
4979 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
4980 						   &dp->rxdma_mon_buf_ring,
4981 						   rx_bufs_used,
4982 						   HAL_RX_BUF_RBM_SW3_BM);
4983 		else
4984 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
4985 						   &dp->rx_refill_buf_ring,
4986 						   rx_bufs_used,
4987 						   HAL_RX_BUF_RBM_SW3_BM);
4988 	}
4989 }
4990 
ath11k_dp_rx_mon_status_process_tlv(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)4991 static void ath11k_dp_rx_mon_status_process_tlv(struct ath11k *ar,
4992 						int mac_id, u32 quota,
4993 						struct napi_struct *napi)
4994 {
4995 	struct ath11k_pdev_dp *dp = &ar->dp;
4996 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4997 	struct hal_rx_mon_ppdu_info *ppdu_info;
4998 	struct sk_buff *status_skb;
4999 	u32 tlv_status = HAL_TLV_STATUS_BUF_DONE;
5000 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5001 
5002 	ppdu_info = &pmon->mon_ppdu_info;
5003 	rx_mon_stats = &pmon->rx_mon_stats;
5004 
5005 	if (pmon->mon_ppdu_status != DP_PPDU_STATUS_START)
5006 		return;
5007 
5008 	while (!skb_queue_empty(&pmon->rx_status_q)) {
5009 		status_skb = skb_dequeue(&pmon->rx_status_q);
5010 
5011 		tlv_status = ath11k_hal_rx_parse_mon_status(ar->ab, ppdu_info,
5012 							    status_skb);
5013 		if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) {
5014 			rx_mon_stats->status_ppdu_done++;
5015 			pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5016 			ath11k_dp_rx_mon_dest_process(ar, mac_id, quota, napi);
5017 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5018 		}
5019 		dev_kfree_skb_any(status_skb);
5020 	}
5021 }
5022 
ath11k_dp_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5023 static int ath11k_dp_mon_process_rx(struct ath11k_base *ab, int mac_id,
5024 				    struct napi_struct *napi, int budget)
5025 {
5026 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5027 	struct ath11k_pdev_dp *dp = &ar->dp;
5028 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5029 	int num_buffs_reaped = 0;
5030 
5031 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ar->ab, mac_id, &budget,
5032 							     &pmon->rx_status_q);
5033 	if (num_buffs_reaped)
5034 		ath11k_dp_rx_mon_status_process_tlv(ar, mac_id, budget, napi);
5035 
5036 	return num_buffs_reaped;
5037 }
5038 
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5039 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5040 				   struct napi_struct *napi, int budget)
5041 {
5042 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5043 	int ret = 0;
5044 
5045 	if (test_bit(ATH11K_FLAG_MONITOR_ENABLED, &ar->monitor_flags))
5046 		ret = ath11k_dp_mon_process_rx(ab, mac_id, napi, budget);
5047 	else
5048 		ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5049 	return ret;
5050 }
5051 
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5052 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5053 {
5054 	struct ath11k_pdev_dp *dp = &ar->dp;
5055 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5056 
5057 	skb_queue_head_init(&pmon->rx_status_q);
5058 
5059 	pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5060 
5061 	memset(&pmon->rx_mon_stats, 0,
5062 	       sizeof(pmon->rx_mon_stats));
5063 	return 0;
5064 }
5065 
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5066 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5067 {
5068 	struct ath11k_pdev_dp *dp = &ar->dp;
5069 	struct ath11k_mon_data *pmon = &dp->mon_data;
5070 	struct hal_srng *mon_desc_srng = NULL;
5071 	struct dp_srng *dp_srng;
5072 	int ret = 0;
5073 	u32 n_link_desc = 0;
5074 
5075 	ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5076 	if (ret) {
5077 		ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5078 		return ret;
5079 	}
5080 
5081 	/* if rxdma1_enable is false, no need to setup
5082 	 * rxdma_mon_desc_ring.
5083 	 */
5084 	if (!ar->ab->hw_params.rxdma1_enable)
5085 		return 0;
5086 
5087 	dp_srng = &dp->rxdma_mon_desc_ring;
5088 	n_link_desc = dp_srng->size /
5089 		ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5090 	mon_desc_srng =
5091 		&ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5092 
5093 	ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5094 					HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5095 					n_link_desc);
5096 	if (ret) {
5097 		ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5098 		return ret;
5099 	}
5100 	pmon->mon_last_linkdesc_paddr = 0;
5101 	pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5102 	spin_lock_init(&pmon->mon_lock);
5103 
5104 	return 0;
5105 }
5106 
ath11k_dp_mon_link_free(struct ath11k * ar)5107 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5108 {
5109 	struct ath11k_pdev_dp *dp = &ar->dp;
5110 	struct ath11k_mon_data *pmon = &dp->mon_data;
5111 
5112 	ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5113 				    HAL_RXDMA_MONITOR_DESC,
5114 				    &dp->rxdma_mon_desc_ring);
5115 	return 0;
5116 }
5117 
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5118 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5119 {
5120 	ath11k_dp_mon_link_free(ar);
5121 	return 0;
5122 }
5123 
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5124 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5125 {
5126 	/* start reap timer */
5127 	mod_timer(&ab->mon_reap_timer,
5128 		  jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5129 
5130 	return 0;
5131 }
5132 
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5133 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5134 {
5135 	int ret;
5136 
5137 	if (stop_timer)
5138 		del_timer_sync(&ab->mon_reap_timer);
5139 
5140 	/* reap all the monitor related rings */
5141 	ret = ath11k_dp_purge_mon_ring(ab);
5142 	if (ret) {
5143 		ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5144 		return ret;
5145 	}
5146 
5147 	return 0;
5148 }
5149