1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc.
3 *
4 * Author: Felix Fietkau <nbd@nbd.name>
5 * Lorenzo Bianconi <lorenzo@kernel.org>
6 * Sean Wang <sean.wang@mediatek.com>
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
12
13 #include <linux/mmc/host.h>
14 #include <linux/mmc/sdio_ids.h>
15 #include <linux/mmc/sdio_func.h>
16
17 #include "../trace.h"
18 #include "mt7615.h"
19 #include "sdio.h"
20 #include "mac.h"
21
mt7663s_refill_sched_quota(struct mt76_dev * dev,u32 * data)22 static int mt7663s_refill_sched_quota(struct mt76_dev *dev, u32 *data)
23 {
24 u32 ple_ac_data_quota[] = {
25 FIELD_GET(TXQ_CNT_L, data[4]), /* VO */
26 FIELD_GET(TXQ_CNT_H, data[3]), /* VI */
27 FIELD_GET(TXQ_CNT_L, data[3]), /* BE */
28 FIELD_GET(TXQ_CNT_H, data[2]), /* BK */
29 };
30 u32 pse_ac_data_quota[] = {
31 FIELD_GET(TXQ_CNT_H, data[1]), /* VO */
32 FIELD_GET(TXQ_CNT_L, data[1]), /* VI */
33 FIELD_GET(TXQ_CNT_H, data[0]), /* BE */
34 FIELD_GET(TXQ_CNT_L, data[0]), /* BK */
35 };
36 u32 pse_mcu_quota = FIELD_GET(TXQ_CNT_L, data[2]);
37 u32 pse_data_quota = 0, ple_data_quota = 0;
38 struct mt76_sdio *sdio = &dev->sdio;
39 int i;
40
41 for (i = 0; i < ARRAY_SIZE(pse_ac_data_quota); i++) {
42 pse_data_quota += pse_ac_data_quota[i];
43 ple_data_quota += ple_ac_data_quota[i];
44 }
45
46 if (!pse_data_quota && !ple_data_quota && !pse_mcu_quota)
47 return 0;
48
49 sdio->sched.pse_mcu_quota += pse_mcu_quota;
50 sdio->sched.pse_data_quota += pse_data_quota;
51 sdio->sched.ple_data_quota += ple_data_quota;
52
53 return pse_data_quota + ple_data_quota + pse_mcu_quota;
54 }
55
mt7663s_build_rx_skb(void * data,int data_len,int buf_len)56 static struct sk_buff *mt7663s_build_rx_skb(void *data, int data_len,
57 int buf_len)
58 {
59 int len = min_t(int, data_len, MT_SKB_HEAD_LEN);
60 struct sk_buff *skb;
61
62 skb = alloc_skb(len, GFP_KERNEL);
63 if (!skb)
64 return NULL;
65
66 skb_put_data(skb, data, len);
67 if (data_len > len) {
68 struct page *page;
69
70 data += len;
71 page = virt_to_head_page(data);
72 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
73 page, data - page_address(page),
74 data_len - len, buf_len);
75 get_page(page);
76 }
77
78 return skb;
79 }
80
mt7663s_rx_run_queue(struct mt76_dev * dev,enum mt76_rxq_id qid,struct mt76s_intr * intr)81 static int mt7663s_rx_run_queue(struct mt76_dev *dev, enum mt76_rxq_id qid,
82 struct mt76s_intr *intr)
83 {
84 struct mt76_queue *q = &dev->q_rx[qid];
85 struct mt76_sdio *sdio = &dev->sdio;
86 int len = 0, err, i;
87 struct page *page;
88 u8 *buf;
89
90 for (i = 0; i < intr->rx.num[qid]; i++)
91 len += round_up(intr->rx.len[qid][i] + 4, 4);
92
93 if (!len)
94 return 0;
95
96 if (len > sdio->func->cur_blksize)
97 len = roundup(len, sdio->func->cur_blksize);
98
99 page = __dev_alloc_pages(GFP_KERNEL, get_order(len));
100 if (!page)
101 return -ENOMEM;
102
103 buf = page_address(page);
104
105 err = sdio_readsb(sdio->func, buf, MCR_WRDR(qid), len);
106 if (err < 0) {
107 dev_err(dev->dev, "sdio read data failed:%d\n", err);
108 put_page(page);
109 return err;
110 }
111
112 for (i = 0; i < intr->rx.num[qid]; i++) {
113 int index = (q->head + i) % q->ndesc;
114 struct mt76_queue_entry *e = &q->entry[index];
115
116 len = intr->rx.len[qid][i];
117 e->skb = mt7663s_build_rx_skb(buf, len, round_up(len + 4, 4));
118 if (!e->skb)
119 break;
120
121 buf += round_up(len + 4, 4);
122 if (q->queued + i + 1 == q->ndesc)
123 break;
124 }
125 put_page(page);
126
127 spin_lock_bh(&q->lock);
128 q->head = (q->head + i) % q->ndesc;
129 q->queued += i;
130 spin_unlock_bh(&q->lock);
131
132 return i;
133 }
134
mt7663s_rx_handler(struct mt76_dev * dev)135 static int mt7663s_rx_handler(struct mt76_dev *dev)
136 {
137 struct mt76_sdio *sdio = &dev->sdio;
138 struct mt76s_intr *intr = sdio->intr_data;
139 int nframes = 0, ret;
140
141 ret = sdio_readsb(sdio->func, intr, MCR_WHISR, sizeof(*intr));
142 if (ret < 0)
143 return ret;
144
145 trace_dev_irq(dev, intr->isr, 0);
146
147 if (intr->isr & WHIER_RX0_DONE_INT_EN) {
148 ret = mt7663s_rx_run_queue(dev, 0, intr);
149 if (ret > 0) {
150 mt76_worker_schedule(&sdio->net_worker);
151 nframes += ret;
152 }
153 }
154
155 if (intr->isr & WHIER_RX1_DONE_INT_EN) {
156 ret = mt7663s_rx_run_queue(dev, 1, intr);
157 if (ret > 0) {
158 mt76_worker_schedule(&sdio->net_worker);
159 nframes += ret;
160 }
161 }
162
163 nframes += !!mt7663s_refill_sched_quota(dev, intr->tx.wtqcr);
164
165 return nframes;
166 }
167
mt7663s_tx_pick_quota(struct mt76_sdio * sdio,bool mcu,int buf_sz,int * pse_size,int * ple_size)168 static int mt7663s_tx_pick_quota(struct mt76_sdio *sdio, bool mcu, int buf_sz,
169 int *pse_size, int *ple_size)
170 {
171 int pse_sz;
172
173 pse_sz = DIV_ROUND_UP(buf_sz + sdio->sched.deficit, MT_PSE_PAGE_SZ);
174
175 if (mcu) {
176 if (sdio->sched.pse_mcu_quota < *pse_size + pse_sz)
177 return -EBUSY;
178 } else {
179 if (sdio->sched.pse_data_quota < *pse_size + pse_sz ||
180 sdio->sched.ple_data_quota < *ple_size + 1)
181 return -EBUSY;
182
183 *ple_size = *ple_size + 1;
184 }
185 *pse_size = *pse_size + pse_sz;
186
187 return 0;
188 }
189
mt7663s_tx_update_quota(struct mt76_sdio * sdio,bool mcu,int pse_size,int ple_size)190 static void mt7663s_tx_update_quota(struct mt76_sdio *sdio, bool mcu,
191 int pse_size, int ple_size)
192 {
193 if (mcu) {
194 sdio->sched.pse_mcu_quota -= pse_size;
195 } else {
196 sdio->sched.pse_data_quota -= pse_size;
197 sdio->sched.ple_data_quota -= ple_size;
198 }
199 }
200
__mt7663s_xmit_queue(struct mt76_dev * dev,u8 * data,int len)201 static int __mt7663s_xmit_queue(struct mt76_dev *dev, u8 *data, int len)
202 {
203 struct mt76_sdio *sdio = &dev->sdio;
204 int err;
205
206 if (len > sdio->func->cur_blksize)
207 len = roundup(len, sdio->func->cur_blksize);
208
209 err = sdio_writesb(sdio->func, MCR_WTDR1, data, len);
210 if (err)
211 dev_err(dev->dev, "sdio write failed: %d\n", err);
212
213 return err;
214 }
215
mt7663s_tx_run_queue(struct mt76_dev * dev,struct mt76_queue * q)216 static int mt7663s_tx_run_queue(struct mt76_dev *dev, struct mt76_queue *q)
217 {
218 int qid, err, nframes = 0, len = 0, pse_sz = 0, ple_sz = 0;
219 bool mcu = q == dev->q_mcu[MT_MCUQ_WM];
220 struct mt76_sdio *sdio = &dev->sdio;
221 u8 pad;
222
223 qid = mcu ? ARRAY_SIZE(sdio->xmit_buf) - 1 : q->qid;
224 while (q->first != q->head) {
225 struct mt76_queue_entry *e = &q->entry[q->first];
226 struct sk_buff *iter;
227
228 smp_rmb();
229
230 if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->phy.state)) {
231 __skb_put_zero(e->skb, 4);
232 err = __mt7663s_xmit_queue(dev, e->skb->data,
233 e->skb->len);
234 if (err)
235 return err;
236
237 goto next;
238 }
239
240 pad = roundup(e->skb->len, 4) - e->skb->len;
241 if (len + e->skb->len + pad + 4 > MT76S_XMIT_BUF_SZ)
242 break;
243
244 if (mt7663s_tx_pick_quota(sdio, mcu, e->buf_sz, &pse_sz,
245 &ple_sz))
246 break;
247
248 memcpy(sdio->xmit_buf[qid] + len, e->skb->data,
249 skb_headlen(e->skb));
250 len += skb_headlen(e->skb);
251 nframes++;
252
253 skb_walk_frags(e->skb, iter) {
254 memcpy(sdio->xmit_buf[qid] + len, iter->data,
255 iter->len);
256 len += iter->len;
257 nframes++;
258 }
259
260 if (unlikely(pad)) {
261 memset(sdio->xmit_buf[qid] + len, 0, pad);
262 len += pad;
263 }
264 next:
265 q->first = (q->first + 1) % q->ndesc;
266 e->done = true;
267 }
268
269 if (nframes) {
270 memset(sdio->xmit_buf[qid] + len, 0, 4);
271 err = __mt7663s_xmit_queue(dev, sdio->xmit_buf[qid], len + 4);
272 if (err)
273 return err;
274 }
275 mt7663s_tx_update_quota(sdio, mcu, pse_sz, ple_sz);
276
277 mt76_worker_schedule(&sdio->status_worker);
278
279 return nframes;
280 }
281
mt7663s_txrx_worker(struct mt76_worker * w)282 void mt7663s_txrx_worker(struct mt76_worker *w)
283 {
284 struct mt76_sdio *sdio = container_of(w, struct mt76_sdio,
285 txrx_worker);
286 struct mt76_dev *mdev = container_of(sdio, struct mt76_dev, sdio);
287 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
288 int i, nframes, ret;
289
290 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
291 queue_work(mdev->wq, &dev->pm.wake_work);
292 return;
293 }
294
295 /* disable interrupt */
296 sdio_claim_host(sdio->func);
297 sdio_writel(sdio->func, WHLPCR_INT_EN_CLR, MCR_WHLPCR, NULL);
298
299 do {
300 nframes = 0;
301
302 /* tx */
303 for (i = 0; i <= MT_TXQ_PSD; i++) {
304 ret = mt7663s_tx_run_queue(mdev, mdev->phy.q_tx[i]);
305 if (ret > 0)
306 nframes += ret;
307 }
308 ret = mt7663s_tx_run_queue(mdev, mdev->q_mcu[MT_MCUQ_WM]);
309 if (ret > 0)
310 nframes += ret;
311
312 /* rx */
313 ret = mt7663s_rx_handler(mdev);
314 if (ret > 0)
315 nframes += ret;
316 } while (nframes > 0);
317
318 /* enable interrupt */
319 sdio_writel(sdio->func, WHLPCR_INT_EN_SET, MCR_WHLPCR, NULL);
320 sdio_release_host(sdio->func);
321
322 mt76_connac_pm_unref(&dev->mphy, &dev->pm);
323 }
324
mt7663s_sdio_irq(struct sdio_func * func)325 void mt7663s_sdio_irq(struct sdio_func *func)
326 {
327 struct mt7615_dev *dev = sdio_get_drvdata(func);
328 struct mt76_sdio *sdio = &dev->mt76.sdio;
329
330 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mt76.phy.state))
331 return;
332
333 mt76_worker_schedule(&sdio->txrx_worker);
334 }
335