1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/mmc/sdio_func.h>
9 #include <linux/mmc/sdio_ids.h>
10 #include <linux/mmc/host.h>
11 #include <linux/mmc/sdio.h>
12 #include <linux/of_irq.h>
13
14 #include "netdev.h"
15 #include "cfg80211.h"
16
17 #define SDIO_MODALIAS "wilc1000_sdio"
18
19 static const struct sdio_device_id wilc_sdio_ids[] = {
20 { SDIO_DEVICE(SDIO_VENDOR_ID_MICROCHIP_WILC, SDIO_DEVICE_ID_MICROCHIP_WILC1000) },
21 { },
22 };
23 MODULE_DEVICE_TABLE(sdio, wilc_sdio_ids);
24
25 #define WILC_SDIO_BLOCK_SIZE 512
26
27 struct wilc_sdio {
28 bool irq_gpio;
29 u32 block_size;
30 int has_thrpt_enh3;
31 u8 *cmd53_buf;
32 };
33
34 struct sdio_cmd52 {
35 u32 read_write: 1;
36 u32 function: 3;
37 u32 raw: 1;
38 u32 address: 17;
39 u32 data: 8;
40 };
41
42 struct sdio_cmd53 {
43 u32 read_write: 1;
44 u32 function: 3;
45 u32 block_mode: 1;
46 u32 increment: 1;
47 u32 address: 17;
48 u32 count: 9;
49 u8 *buffer;
50 u32 block_size;
51 bool use_global_buf;
52 };
53
54 static const struct wilc_hif_func wilc_hif_sdio;
55
wilc_sdio_interrupt(struct sdio_func * func)56 static void wilc_sdio_interrupt(struct sdio_func *func)
57 {
58 sdio_release_host(func);
59 wilc_handle_isr(sdio_get_drvdata(func));
60 sdio_claim_host(func);
61 }
62
wilc_sdio_cmd52(struct wilc * wilc,struct sdio_cmd52 * cmd)63 static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd)
64 {
65 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
66 int ret;
67 u8 data;
68
69 sdio_claim_host(func);
70
71 func->num = cmd->function;
72 if (cmd->read_write) { /* write */
73 if (cmd->raw) {
74 sdio_writeb(func, cmd->data, cmd->address, &ret);
75 data = sdio_readb(func, cmd->address, &ret);
76 cmd->data = data;
77 } else {
78 sdio_writeb(func, cmd->data, cmd->address, &ret);
79 }
80 } else { /* read */
81 data = sdio_readb(func, cmd->address, &ret);
82 cmd->data = data;
83 }
84
85 sdio_release_host(func);
86
87 if (ret)
88 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
89 return ret;
90 }
91
wilc_sdio_cmd53(struct wilc * wilc,struct sdio_cmd53 * cmd)92 static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd)
93 {
94 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
95 int size, ret;
96 struct wilc_sdio *sdio_priv = wilc->bus_data;
97 u8 *buf = cmd->buffer;
98
99 sdio_claim_host(func);
100
101 func->num = cmd->function;
102 func->cur_blksize = cmd->block_size;
103 if (cmd->block_mode)
104 size = cmd->count * cmd->block_size;
105 else
106 size = cmd->count;
107
108 if (cmd->use_global_buf) {
109 if (size > sizeof(u32))
110 return -EINVAL;
111
112 buf = sdio_priv->cmd53_buf;
113 }
114
115 if (cmd->read_write) { /* write */
116 if (cmd->use_global_buf)
117 memcpy(buf, cmd->buffer, size);
118
119 ret = sdio_memcpy_toio(func, cmd->address, buf, size);
120 } else { /* read */
121 ret = sdio_memcpy_fromio(func, buf, cmd->address, size);
122
123 if (cmd->use_global_buf)
124 memcpy(cmd->buffer, buf, size);
125 }
126
127 sdio_release_host(func);
128
129 if (ret)
130 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
131
132 return ret;
133 }
134
wilc_sdio_probe(struct sdio_func * func,const struct sdio_device_id * id)135 static int wilc_sdio_probe(struct sdio_func *func,
136 const struct sdio_device_id *id)
137 {
138 struct wilc *wilc;
139 int ret;
140 struct wilc_sdio *sdio_priv;
141
142 sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL);
143 if (!sdio_priv)
144 return -ENOMEM;
145
146 sdio_priv->cmd53_buf = kzalloc(sizeof(u32), GFP_KERNEL);
147 if (!sdio_priv->cmd53_buf) {
148 ret = -ENOMEM;
149 goto free;
150 }
151
152 ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO,
153 &wilc_hif_sdio);
154 if (ret)
155 goto free;
156
157 if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) {
158 struct device_node *np = func->card->dev.of_node;
159 int irq_num = of_irq_get(np, 0);
160
161 if (irq_num > 0) {
162 wilc->dev_irq_num = irq_num;
163 sdio_priv->irq_gpio = true;
164 }
165 }
166
167 sdio_set_drvdata(func, wilc);
168 wilc->bus_data = sdio_priv;
169 wilc->dev = &func->dev;
170
171 wilc->rtc_clk = devm_clk_get_optional(&func->card->dev, "rtc");
172 if (IS_ERR(wilc->rtc_clk)) {
173 ret = PTR_ERR(wilc->rtc_clk);
174 goto dispose_irq;
175 }
176 clk_prepare_enable(wilc->rtc_clk);
177
178 dev_info(&func->dev, "Driver Initializing success\n");
179 return 0;
180
181 dispose_irq:
182 irq_dispose_mapping(wilc->dev_irq_num);
183 wilc_netdev_cleanup(wilc);
184 free:
185 kfree(sdio_priv->cmd53_buf);
186 kfree(sdio_priv);
187 return ret;
188 }
189
wilc_sdio_remove(struct sdio_func * func)190 static void wilc_sdio_remove(struct sdio_func *func)
191 {
192 struct wilc *wilc = sdio_get_drvdata(func);
193 struct wilc_sdio *sdio_priv = wilc->bus_data;
194
195 clk_disable_unprepare(wilc->rtc_clk);
196 wilc_netdev_cleanup(wilc);
197 kfree(sdio_priv->cmd53_buf);
198 kfree(sdio_priv);
199 }
200
wilc_sdio_reset(struct wilc * wilc)201 static int wilc_sdio_reset(struct wilc *wilc)
202 {
203 struct sdio_cmd52 cmd;
204 int ret;
205 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
206
207 cmd.read_write = 1;
208 cmd.function = 0;
209 cmd.raw = 0;
210 cmd.address = SDIO_CCCR_ABORT;
211 cmd.data = WILC_SDIO_CCCR_ABORT_RESET;
212 ret = wilc_sdio_cmd52(wilc, &cmd);
213 if (ret) {
214 dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n");
215 return ret;
216 }
217 return 0;
218 }
219
wilc_sdio_suspend(struct device * dev)220 static int wilc_sdio_suspend(struct device *dev)
221 {
222 struct sdio_func *func = dev_to_sdio_func(dev);
223 struct wilc *wilc = sdio_get_drvdata(func);
224 int ret;
225
226 dev_info(dev, "sdio suspend\n");
227 chip_wakeup(wilc);
228
229 if (!IS_ERR(wilc->rtc_clk))
230 clk_disable_unprepare(wilc->rtc_clk);
231
232 if (wilc->suspend_event) {
233 host_sleep_notify(wilc);
234 chip_allow_sleep(wilc);
235 }
236
237 ret = wilc_sdio_reset(wilc);
238 if (ret) {
239 dev_err(&func->dev, "Fail reset sdio\n");
240 return ret;
241 }
242 sdio_claim_host(func);
243
244 return 0;
245 }
246
wilc_sdio_enable_interrupt(struct wilc * dev)247 static int wilc_sdio_enable_interrupt(struct wilc *dev)
248 {
249 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
250 int ret = 0;
251
252 sdio_claim_host(func);
253 ret = sdio_claim_irq(func, wilc_sdio_interrupt);
254 sdio_release_host(func);
255
256 if (ret < 0) {
257 dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret);
258 ret = -EIO;
259 }
260 return ret;
261 }
262
wilc_sdio_disable_interrupt(struct wilc * dev)263 static void wilc_sdio_disable_interrupt(struct wilc *dev)
264 {
265 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
266 int ret;
267
268 sdio_claim_host(func);
269 ret = sdio_release_irq(func);
270 if (ret < 0)
271 dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret);
272 sdio_release_host(func);
273 }
274
275 /********************************************
276 *
277 * Function 0
278 *
279 ********************************************/
280
wilc_sdio_set_func0_csa_address(struct wilc * wilc,u32 adr)281 static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr)
282 {
283 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
284 struct sdio_cmd52 cmd;
285 int ret;
286
287 /**
288 * Review: BIG ENDIAN
289 **/
290 cmd.read_write = 1;
291 cmd.function = 0;
292 cmd.raw = 0;
293 cmd.address = WILC_SDIO_FBR_CSA_REG;
294 cmd.data = (u8)adr;
295 ret = wilc_sdio_cmd52(wilc, &cmd);
296 if (ret) {
297 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
298 cmd.address);
299 return ret;
300 }
301
302 cmd.address = WILC_SDIO_FBR_CSA_REG + 1;
303 cmd.data = (u8)(adr >> 8);
304 ret = wilc_sdio_cmd52(wilc, &cmd);
305 if (ret) {
306 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
307 cmd.address);
308 return ret;
309 }
310
311 cmd.address = WILC_SDIO_FBR_CSA_REG + 2;
312 cmd.data = (u8)(adr >> 16);
313 ret = wilc_sdio_cmd52(wilc, &cmd);
314 if (ret) {
315 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
316 cmd.address);
317 return ret;
318 }
319
320 return 0;
321 }
322
wilc_sdio_set_block_size(struct wilc * wilc,u8 func_num,u32 block_size)323 static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num,
324 u32 block_size)
325 {
326 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
327 struct sdio_cmd52 cmd;
328 int ret;
329
330 cmd.read_write = 1;
331 cmd.function = 0;
332 cmd.raw = 0;
333 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE;
334 cmd.data = (u8)block_size;
335 ret = wilc_sdio_cmd52(wilc, &cmd);
336 if (ret) {
337 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
338 cmd.address);
339 return ret;
340 }
341
342 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE + 1;
343 cmd.data = (u8)(block_size >> 8);
344 ret = wilc_sdio_cmd52(wilc, &cmd);
345 if (ret) {
346 dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
347 cmd.address);
348 return ret;
349 }
350
351 return 0;
352 }
353
354 /********************************************
355 *
356 * Sdio interfaces
357 *
358 ********************************************/
wilc_sdio_write_reg(struct wilc * wilc,u32 addr,u32 data)359 static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data)
360 {
361 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
362 struct wilc_sdio *sdio_priv = wilc->bus_data;
363 int ret;
364
365 cpu_to_le32s(&data);
366
367 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
368 struct sdio_cmd52 cmd;
369
370 cmd.read_write = 1;
371 cmd.function = 0;
372 cmd.raw = 0;
373 cmd.address = addr;
374 cmd.data = data;
375 ret = wilc_sdio_cmd52(wilc, &cmd);
376 if (ret)
377 dev_err(&func->dev,
378 "Failed cmd 52, read reg (%08x) ...\n", addr);
379 } else {
380 struct sdio_cmd53 cmd;
381
382 /**
383 * set the AHB address
384 **/
385 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
386 if (ret)
387 return ret;
388
389 cmd.read_write = 1;
390 cmd.function = 0;
391 cmd.address = WILC_SDIO_FBR_DATA_REG;
392 cmd.block_mode = 0;
393 cmd.increment = 1;
394 cmd.count = sizeof(u32);
395 cmd.buffer = (u8 *)&data;
396 cmd.use_global_buf = true;
397 cmd.block_size = sdio_priv->block_size;
398 ret = wilc_sdio_cmd53(wilc, &cmd);
399 if (ret)
400 dev_err(&func->dev,
401 "Failed cmd53, write reg (%08x)...\n", addr);
402 }
403
404 return ret;
405 }
406
wilc_sdio_write(struct wilc * wilc,u32 addr,u8 * buf,u32 size)407 static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
408 {
409 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
410 struct wilc_sdio *sdio_priv = wilc->bus_data;
411 u32 block_size = sdio_priv->block_size;
412 struct sdio_cmd53 cmd;
413 int nblk, nleft, ret;
414
415 cmd.read_write = 1;
416 if (addr > 0) {
417 /**
418 * func 0 access
419 **/
420 cmd.function = 0;
421 cmd.address = WILC_SDIO_FBR_DATA_REG;
422 } else {
423 /**
424 * func 1 access
425 **/
426 cmd.function = 1;
427 cmd.address = WILC_SDIO_F1_DATA_REG;
428 }
429
430 size = ALIGN(size, 4);
431 nblk = size / block_size;
432 nleft = size % block_size;
433
434 cmd.use_global_buf = false;
435 if (nblk > 0) {
436 cmd.block_mode = 1;
437 cmd.increment = 1;
438 cmd.count = nblk;
439 cmd.buffer = buf;
440 cmd.block_size = block_size;
441 if (addr > 0) {
442 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
443 if (ret)
444 return ret;
445 }
446 ret = wilc_sdio_cmd53(wilc, &cmd);
447 if (ret) {
448 dev_err(&func->dev,
449 "Failed cmd53 [%x], block send...\n", addr);
450 return ret;
451 }
452 if (addr > 0)
453 addr += nblk * block_size;
454 buf += nblk * block_size;
455 }
456
457 if (nleft > 0) {
458 cmd.block_mode = 0;
459 cmd.increment = 1;
460 cmd.count = nleft;
461 cmd.buffer = buf;
462
463 cmd.block_size = block_size;
464
465 if (addr > 0) {
466 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
467 if (ret)
468 return ret;
469 }
470 ret = wilc_sdio_cmd53(wilc, &cmd);
471 if (ret) {
472 dev_err(&func->dev,
473 "Failed cmd53 [%x], bytes send...\n", addr);
474 return ret;
475 }
476 }
477
478 return 0;
479 }
480
wilc_sdio_read_reg(struct wilc * wilc,u32 addr,u32 * data)481 static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data)
482 {
483 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
484 struct wilc_sdio *sdio_priv = wilc->bus_data;
485 int ret;
486
487 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
488 struct sdio_cmd52 cmd;
489
490 cmd.read_write = 0;
491 cmd.function = 0;
492 cmd.raw = 0;
493 cmd.address = addr;
494 ret = wilc_sdio_cmd52(wilc, &cmd);
495 if (ret) {
496 dev_err(&func->dev,
497 "Failed cmd 52, read reg (%08x) ...\n", addr);
498 return ret;
499 }
500 *data = cmd.data;
501 } else {
502 struct sdio_cmd53 cmd;
503
504 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
505 if (ret)
506 return ret;
507
508 cmd.read_write = 0;
509 cmd.function = 0;
510 cmd.address = WILC_SDIO_FBR_DATA_REG;
511 cmd.block_mode = 0;
512 cmd.increment = 1;
513 cmd.count = sizeof(u32);
514 cmd.buffer = (u8 *)data;
515 cmd.use_global_buf = true;
516
517 cmd.block_size = sdio_priv->block_size;
518 ret = wilc_sdio_cmd53(wilc, &cmd);
519 if (ret) {
520 dev_err(&func->dev,
521 "Failed cmd53, read reg (%08x)...\n", addr);
522 return ret;
523 }
524 }
525
526 le32_to_cpus(data);
527 return 0;
528 }
529
wilc_sdio_read(struct wilc * wilc,u32 addr,u8 * buf,u32 size)530 static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
531 {
532 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
533 struct wilc_sdio *sdio_priv = wilc->bus_data;
534 u32 block_size = sdio_priv->block_size;
535 struct sdio_cmd53 cmd;
536 int nblk, nleft, ret;
537
538 cmd.read_write = 0;
539 if (addr > 0) {
540 /**
541 * func 0 access
542 **/
543 cmd.function = 0;
544 cmd.address = WILC_SDIO_FBR_DATA_REG;
545 } else {
546 /**
547 * func 1 access
548 **/
549 cmd.function = 1;
550 cmd.address = WILC_SDIO_F1_DATA_REG;
551 }
552
553 size = ALIGN(size, 4);
554 nblk = size / block_size;
555 nleft = size % block_size;
556
557 cmd.use_global_buf = false;
558 if (nblk > 0) {
559 cmd.block_mode = 1;
560 cmd.increment = 1;
561 cmd.count = nblk;
562 cmd.buffer = buf;
563 cmd.block_size = block_size;
564 if (addr > 0) {
565 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
566 if (ret)
567 return ret;
568 }
569 ret = wilc_sdio_cmd53(wilc, &cmd);
570 if (ret) {
571 dev_err(&func->dev,
572 "Failed cmd53 [%x], block read...\n", addr);
573 return ret;
574 }
575 if (addr > 0)
576 addr += nblk * block_size;
577 buf += nblk * block_size;
578 } /* if (nblk > 0) */
579
580 if (nleft > 0) {
581 cmd.block_mode = 0;
582 cmd.increment = 1;
583 cmd.count = nleft;
584 cmd.buffer = buf;
585
586 cmd.block_size = block_size;
587
588 if (addr > 0) {
589 ret = wilc_sdio_set_func0_csa_address(wilc, addr);
590 if (ret)
591 return ret;
592 }
593 ret = wilc_sdio_cmd53(wilc, &cmd);
594 if (ret) {
595 dev_err(&func->dev,
596 "Failed cmd53 [%x], bytes read...\n", addr);
597 return ret;
598 }
599 }
600
601 return 0;
602 }
603
604 /********************************************
605 *
606 * Bus interfaces
607 *
608 ********************************************/
609
wilc_sdio_deinit(struct wilc * wilc)610 static int wilc_sdio_deinit(struct wilc *wilc)
611 {
612 return 0;
613 }
614
wilc_sdio_init(struct wilc * wilc,bool resume)615 static int wilc_sdio_init(struct wilc *wilc, bool resume)
616 {
617 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
618 struct wilc_sdio *sdio_priv = wilc->bus_data;
619 struct sdio_cmd52 cmd;
620 int loop, ret;
621 u32 chipid;
622
623 /**
624 * function 0 csa enable
625 **/
626 cmd.read_write = 1;
627 cmd.function = 0;
628 cmd.raw = 1;
629 cmd.address = SDIO_FBR_BASE(func->num);
630 cmd.data = SDIO_FBR_ENABLE_CSA;
631 ret = wilc_sdio_cmd52(wilc, &cmd);
632 if (ret) {
633 dev_err(&func->dev, "Fail cmd 52, enable csa...\n");
634 return ret;
635 }
636
637 /**
638 * function 0 block size
639 **/
640 ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE);
641 if (ret) {
642 dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n");
643 return ret;
644 }
645 sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE;
646
647 /**
648 * enable func1 IO
649 **/
650 cmd.read_write = 1;
651 cmd.function = 0;
652 cmd.raw = 1;
653 cmd.address = SDIO_CCCR_IOEx;
654 cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1;
655 ret = wilc_sdio_cmd52(wilc, &cmd);
656 if (ret) {
657 dev_err(&func->dev,
658 "Fail cmd 52, set IOE register...\n");
659 return ret;
660 }
661
662 /**
663 * make sure func 1 is up
664 **/
665 cmd.read_write = 0;
666 cmd.function = 0;
667 cmd.raw = 0;
668 cmd.address = SDIO_CCCR_IORx;
669 loop = 3;
670 do {
671 cmd.data = 0;
672 ret = wilc_sdio_cmd52(wilc, &cmd);
673 if (ret) {
674 dev_err(&func->dev,
675 "Fail cmd 52, get IOR register...\n");
676 return ret;
677 }
678 if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1)
679 break;
680 } while (loop--);
681
682 if (loop <= 0) {
683 dev_err(&func->dev, "Fail func 1 is not ready...\n");
684 return -EINVAL;
685 }
686
687 /**
688 * func 1 is ready, set func 1 block size
689 **/
690 ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE);
691 if (ret) {
692 dev_err(&func->dev, "Fail set func 1 block size...\n");
693 return ret;
694 }
695
696 /**
697 * func 1 interrupt enable
698 **/
699 cmd.read_write = 1;
700 cmd.function = 0;
701 cmd.raw = 1;
702 cmd.address = SDIO_CCCR_IENx;
703 cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1;
704 ret = wilc_sdio_cmd52(wilc, &cmd);
705 if (ret) {
706 dev_err(&func->dev, "Fail cmd 52, set IEN register...\n");
707 return ret;
708 }
709
710 /**
711 * make sure can read back chip id correctly
712 **/
713 if (!resume) {
714 int rev;
715
716 ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid);
717 if (ret) {
718 dev_err(&func->dev, "Fail cmd read chip id...\n");
719 return ret;
720 }
721 dev_err(&func->dev, "chipid (%08x)\n", chipid);
722 rev = FIELD_GET(WILC_CHIP_REV_FIELD, chipid);
723 if (rev > FIELD_GET(WILC_CHIP_REV_FIELD, WILC_1000_BASE_ID_2A))
724 sdio_priv->has_thrpt_enh3 = 1;
725 else
726 sdio_priv->has_thrpt_enh3 = 0;
727 dev_info(&func->dev, "has_thrpt_enh3 = %d...\n",
728 sdio_priv->has_thrpt_enh3);
729 }
730
731 return 0;
732 }
733
wilc_sdio_read_size(struct wilc * wilc,u32 * size)734 static int wilc_sdio_read_size(struct wilc *wilc, u32 *size)
735 {
736 u32 tmp;
737 struct sdio_cmd52 cmd;
738
739 /**
740 * Read DMA count in words
741 **/
742 cmd.read_write = 0;
743 cmd.function = 0;
744 cmd.raw = 0;
745 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG;
746 cmd.data = 0;
747 wilc_sdio_cmd52(wilc, &cmd);
748 tmp = cmd.data;
749
750 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1;
751 cmd.data = 0;
752 wilc_sdio_cmd52(wilc, &cmd);
753 tmp |= (cmd.data << 8);
754
755 *size = tmp;
756 return 0;
757 }
758
wilc_sdio_read_int(struct wilc * wilc,u32 * int_status)759 static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status)
760 {
761 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
762 struct wilc_sdio *sdio_priv = wilc->bus_data;
763 u32 tmp;
764 u8 irq_flags;
765 struct sdio_cmd52 cmd;
766
767 wilc_sdio_read_size(wilc, &tmp);
768
769 /**
770 * Read IRQ flags
771 **/
772 if (!sdio_priv->irq_gpio) {
773 cmd.function = 1;
774 cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG;
775 } else {
776 cmd.function = 0;
777 cmd.address = WILC_SDIO_IRQ_FLAG_REG;
778 }
779 cmd.raw = 0;
780 cmd.read_write = 0;
781 cmd.data = 0;
782 wilc_sdio_cmd52(wilc, &cmd);
783 irq_flags = cmd.data;
784 tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data);
785
786 if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags))
787 dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n",
788 FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags));
789
790 *int_status = tmp;
791
792 return 0;
793 }
794
wilc_sdio_clear_int_ext(struct wilc * wilc,u32 val)795 static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val)
796 {
797 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
798 struct wilc_sdio *sdio_priv = wilc->bus_data;
799 int ret;
800 int vmm_ctl;
801
802 if (sdio_priv->has_thrpt_enh3) {
803 u32 reg = 0;
804
805 if (sdio_priv->irq_gpio)
806 reg = val & (BIT(MAX_NUM_INT) - 1);
807
808 /* select VMM table 0 */
809 if (val & SEL_VMM_TBL0)
810 reg |= BIT(5);
811 /* select VMM table 1 */
812 if (val & SEL_VMM_TBL1)
813 reg |= BIT(6);
814 /* enable VMM */
815 if (val & EN_VMM)
816 reg |= BIT(7);
817 if (reg) {
818 struct sdio_cmd52 cmd;
819
820 cmd.read_write = 1;
821 cmd.function = 0;
822 cmd.raw = 0;
823 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
824 cmd.data = reg;
825
826 ret = wilc_sdio_cmd52(wilc, &cmd);
827 if (ret) {
828 dev_err(&func->dev,
829 "Failed cmd52, set (%02x) data (%d) ...\n",
830 cmd.address, __LINE__);
831 return ret;
832 }
833 }
834 return 0;
835 }
836 if (sdio_priv->irq_gpio) {
837 /* has_thrpt_enh2 uses register 0xf8 to clear interrupts. */
838 /*
839 * Cannot clear multiple interrupts.
840 * Must clear each interrupt individually.
841 */
842 u32 flags;
843 int i;
844
845 flags = val & (BIT(MAX_NUM_INT) - 1);
846 for (i = 0; i < NUM_INT_EXT && flags; i++) {
847 if (flags & BIT(i)) {
848 struct sdio_cmd52 cmd;
849
850 cmd.read_write = 1;
851 cmd.function = 0;
852 cmd.raw = 0;
853 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
854 cmd.data = BIT(i);
855
856 ret = wilc_sdio_cmd52(wilc, &cmd);
857 if (ret) {
858 dev_err(&func->dev,
859 "Failed cmd52, set (%02x) data (%d) ...\n",
860 cmd.address, __LINE__);
861 return ret;
862 }
863 flags &= ~BIT(i);
864 }
865 }
866
867 for (i = NUM_INT_EXT; i < MAX_NUM_INT && flags; i++) {
868 if (flags & BIT(i)) {
869 dev_err(&func->dev,
870 "Unexpected interrupt cleared %d...\n",
871 i);
872 flags &= ~BIT(i);
873 }
874 }
875 }
876
877 vmm_ctl = 0;
878 /* select VMM table 0 */
879 if (val & SEL_VMM_TBL0)
880 vmm_ctl |= BIT(0);
881 /* select VMM table 1 */
882 if (val & SEL_VMM_TBL1)
883 vmm_ctl |= BIT(1);
884 /* enable VMM */
885 if (val & EN_VMM)
886 vmm_ctl |= BIT(2);
887
888 if (vmm_ctl) {
889 struct sdio_cmd52 cmd;
890
891 cmd.read_write = 1;
892 cmd.function = 0;
893 cmd.raw = 0;
894 cmd.address = WILC_SDIO_VMM_TBL_CTRL_REG;
895 cmd.data = vmm_ctl;
896 ret = wilc_sdio_cmd52(wilc, &cmd);
897 if (ret) {
898 dev_err(&func->dev,
899 "Failed cmd52, set (%02x) data (%d) ...\n",
900 cmd.address, __LINE__);
901 return ret;
902 }
903 }
904 return 0;
905 }
906
wilc_sdio_sync_ext(struct wilc * wilc,int nint)907 static int wilc_sdio_sync_ext(struct wilc *wilc, int nint)
908 {
909 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
910 struct wilc_sdio *sdio_priv = wilc->bus_data;
911 u32 reg;
912
913 if (nint > MAX_NUM_INT) {
914 dev_err(&func->dev, "Too many interrupts (%d)...\n", nint);
915 return -EINVAL;
916 }
917
918 /**
919 * Disable power sequencer
920 **/
921 if (wilc_sdio_read_reg(wilc, WILC_MISC, ®)) {
922 dev_err(&func->dev, "Failed read misc reg...\n");
923 return -EINVAL;
924 }
925
926 reg &= ~BIT(8);
927 if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) {
928 dev_err(&func->dev, "Failed write misc reg...\n");
929 return -EINVAL;
930 }
931
932 if (sdio_priv->irq_gpio) {
933 u32 reg;
934 int ret, i;
935
936 /**
937 * interrupt pin mux select
938 **/
939 ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®);
940 if (ret) {
941 dev_err(&func->dev, "Failed read reg (%08x)...\n",
942 WILC_PIN_MUX_0);
943 return ret;
944 }
945 reg |= BIT(8);
946 ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg);
947 if (ret) {
948 dev_err(&func->dev, "Failed write reg (%08x)...\n",
949 WILC_PIN_MUX_0);
950 return ret;
951 }
952
953 /**
954 * interrupt enable
955 **/
956 ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®);
957 if (ret) {
958 dev_err(&func->dev, "Failed read reg (%08x)...\n",
959 WILC_INTR_ENABLE);
960 return ret;
961 }
962
963 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
964 reg |= BIT((27 + i));
965 ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg);
966 if (ret) {
967 dev_err(&func->dev, "Failed write reg (%08x)...\n",
968 WILC_INTR_ENABLE);
969 return ret;
970 }
971 if (nint) {
972 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®);
973 if (ret) {
974 dev_err(&func->dev,
975 "Failed read reg (%08x)...\n",
976 WILC_INTR2_ENABLE);
977 return ret;
978 }
979
980 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
981 reg |= BIT(i);
982
983 ret = wilc_sdio_write_reg(wilc, WILC_INTR2_ENABLE, reg);
984 if (ret) {
985 dev_err(&func->dev,
986 "Failed write reg (%08x)...\n",
987 WILC_INTR2_ENABLE);
988 return ret;
989 }
990 }
991 }
992 return 0;
993 }
994
995 /* Global sdio HIF function table */
996 static const struct wilc_hif_func wilc_hif_sdio = {
997 .hif_init = wilc_sdio_init,
998 .hif_deinit = wilc_sdio_deinit,
999 .hif_read_reg = wilc_sdio_read_reg,
1000 .hif_write_reg = wilc_sdio_write_reg,
1001 .hif_block_rx = wilc_sdio_read,
1002 .hif_block_tx = wilc_sdio_write,
1003 .hif_read_int = wilc_sdio_read_int,
1004 .hif_clear_int_ext = wilc_sdio_clear_int_ext,
1005 .hif_read_size = wilc_sdio_read_size,
1006 .hif_block_tx_ext = wilc_sdio_write,
1007 .hif_block_rx_ext = wilc_sdio_read,
1008 .hif_sync_ext = wilc_sdio_sync_ext,
1009 .enable_interrupt = wilc_sdio_enable_interrupt,
1010 .disable_interrupt = wilc_sdio_disable_interrupt,
1011 };
1012
wilc_sdio_resume(struct device * dev)1013 static int wilc_sdio_resume(struct device *dev)
1014 {
1015 struct sdio_func *func = dev_to_sdio_func(dev);
1016 struct wilc *wilc = sdio_get_drvdata(func);
1017
1018 dev_info(dev, "sdio resume\n");
1019 sdio_release_host(func);
1020 chip_wakeup(wilc);
1021 wilc_sdio_init(wilc, true);
1022
1023 if (wilc->suspend_event)
1024 host_wakeup_notify(wilc);
1025
1026 chip_allow_sleep(wilc);
1027
1028 return 0;
1029 }
1030
1031 static const struct of_device_id wilc_of_match[] = {
1032 { .compatible = "microchip,wilc1000", },
1033 { /* sentinel */ }
1034 };
1035 MODULE_DEVICE_TABLE(of, wilc_of_match);
1036
1037 static const struct dev_pm_ops wilc_sdio_pm_ops = {
1038 .suspend = wilc_sdio_suspend,
1039 .resume = wilc_sdio_resume,
1040 };
1041
1042 static struct sdio_driver wilc_sdio_driver = {
1043 .name = SDIO_MODALIAS,
1044 .id_table = wilc_sdio_ids,
1045 .probe = wilc_sdio_probe,
1046 .remove = wilc_sdio_remove,
1047 .drv = {
1048 .pm = &wilc_sdio_pm_ops,
1049 .of_match_table = wilc_of_match,
1050 }
1051 };
1052 module_driver(wilc_sdio_driver,
1053 sdio_register_driver,
1054 sdio_unregister_driver);
1055 MODULE_LICENSE("GPL");
1056