1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Freescale i.MX6 SoCs
4 *
5 * Copyright (C) 2013 Kosagi
6 * https://www.kosagi.com
7 *
8 * Author: Sean Cross <xobs@kosagi.com>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/gpio.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
19 #include <linux/module.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_device.h>
22 #include <linux/of_address.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/resource.h>
28 #include <linux/signal.h>
29 #include <linux/types.h>
30 #include <linux/interrupt.h>
31 #include <linux/reset.h>
32 #include <linux/pm_domain.h>
33 #include <linux/pm_runtime.h>
34
35 #include "pcie-designware.h"
36
37 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
38 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
39 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
40 #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
41 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
42 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
43
44 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
45
46 enum imx6_pcie_variants {
47 IMX6Q,
48 IMX6SX,
49 IMX6QP,
50 IMX7D,
51 IMX8MQ,
52 };
53
54 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
55 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
56 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
57
58 struct imx6_pcie_drvdata {
59 enum imx6_pcie_variants variant;
60 u32 flags;
61 int dbi_length;
62 };
63
64 struct imx6_pcie {
65 struct dw_pcie *pci;
66 int reset_gpio;
67 bool gpio_active_high;
68 struct clk *pcie_bus;
69 struct clk *pcie_phy;
70 struct clk *pcie_inbound_axi;
71 struct clk *pcie;
72 struct clk *pcie_aux;
73 struct regmap *iomuxc_gpr;
74 u32 controller_id;
75 struct reset_control *pciephy_reset;
76 struct reset_control *apps_reset;
77 struct reset_control *turnoff_reset;
78 u32 tx_deemph_gen1;
79 u32 tx_deemph_gen2_3p5db;
80 u32 tx_deemph_gen2_6db;
81 u32 tx_swing_full;
82 u32 tx_swing_low;
83 struct regulator *vpcie;
84 struct regulator *vph;
85 void __iomem *phy_base;
86
87 /* power domain for pcie */
88 struct device *pd_pcie;
89 /* power domain for pcie phy */
90 struct device *pd_pcie_phy;
91 const struct imx6_pcie_drvdata *drvdata;
92 };
93
94 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
95 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
96 #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
97
98 /* PCIe Port Logic registers (memory-mapped) */
99 #define PL_OFFSET 0x700
100
101 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
102 #define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x))
103 #define PCIE_PHY_CTRL_CAP_ADR BIT(16)
104 #define PCIE_PHY_CTRL_CAP_DAT BIT(17)
105 #define PCIE_PHY_CTRL_WR BIT(18)
106 #define PCIE_PHY_CTRL_RD BIT(19)
107
108 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
109 #define PCIE_PHY_STAT_ACK BIT(16)
110
111 /* PHY registers (not memory-mapped) */
112 #define PCIE_PHY_ATEOVRD 0x10
113 #define PCIE_PHY_ATEOVRD_EN BIT(2)
114 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0
115 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1
116
117 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11
118 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2
119 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f
120 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9)
121
122 #define PCIE_PHY_RX_ASIC_OUT 0x100D
123 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
124
125 /* iMX7 PCIe PHY registers */
126 #define PCIE_PHY_CMN_REG4 0x14
127 /* These are probably the bits that *aren't* DCC_FB_EN */
128 #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29
129
130 #define PCIE_PHY_CMN_REG15 0x54
131 #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2)
132 #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5)
133 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7)
134
135 #define PCIE_PHY_CMN_REG24 0x90
136 #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6)
137 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3)
138
139 #define PCIE_PHY_CMN_REG26 0x98
140 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC
141
142 #define PHY_RX_OVRD_IN_LO 0x1005
143 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
144 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
145
pcie_phy_poll_ack(struct imx6_pcie * imx6_pcie,bool exp_val)146 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
147 {
148 struct dw_pcie *pci = imx6_pcie->pci;
149 bool val;
150 u32 max_iterations = 10;
151 u32 wait_counter = 0;
152
153 do {
154 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
155 PCIE_PHY_STAT_ACK;
156 wait_counter++;
157
158 if (val == exp_val)
159 return 0;
160
161 udelay(1);
162 } while (wait_counter < max_iterations);
163
164 return -ETIMEDOUT;
165 }
166
pcie_phy_wait_ack(struct imx6_pcie * imx6_pcie,int addr)167 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
168 {
169 struct dw_pcie *pci = imx6_pcie->pci;
170 u32 val;
171 int ret;
172
173 val = PCIE_PHY_CTRL_DATA(addr);
174 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
175
176 val |= PCIE_PHY_CTRL_CAP_ADR;
177 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
178
179 ret = pcie_phy_poll_ack(imx6_pcie, true);
180 if (ret)
181 return ret;
182
183 val = PCIE_PHY_CTRL_DATA(addr);
184 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
185
186 return pcie_phy_poll_ack(imx6_pcie, false);
187 }
188
189 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
pcie_phy_read(struct imx6_pcie * imx6_pcie,int addr,u16 * data)190 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
191 {
192 struct dw_pcie *pci = imx6_pcie->pci;
193 u32 phy_ctl;
194 int ret;
195
196 ret = pcie_phy_wait_ack(imx6_pcie, addr);
197 if (ret)
198 return ret;
199
200 /* assert Read signal */
201 phy_ctl = PCIE_PHY_CTRL_RD;
202 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
203
204 ret = pcie_phy_poll_ack(imx6_pcie, true);
205 if (ret)
206 return ret;
207
208 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
209
210 /* deassert Read signal */
211 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
212
213 return pcie_phy_poll_ack(imx6_pcie, false);
214 }
215
pcie_phy_write(struct imx6_pcie * imx6_pcie,int addr,u16 data)216 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
217 {
218 struct dw_pcie *pci = imx6_pcie->pci;
219 u32 var;
220 int ret;
221
222 /* write addr */
223 /* cap addr */
224 ret = pcie_phy_wait_ack(imx6_pcie, addr);
225 if (ret)
226 return ret;
227
228 var = PCIE_PHY_CTRL_DATA(data);
229 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
230
231 /* capture data */
232 var |= PCIE_PHY_CTRL_CAP_DAT;
233 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
234
235 ret = pcie_phy_poll_ack(imx6_pcie, true);
236 if (ret)
237 return ret;
238
239 /* deassert cap data */
240 var = PCIE_PHY_CTRL_DATA(data);
241 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
242
243 /* wait for ack de-assertion */
244 ret = pcie_phy_poll_ack(imx6_pcie, false);
245 if (ret)
246 return ret;
247
248 /* assert wr signal */
249 var = PCIE_PHY_CTRL_WR;
250 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
251
252 /* wait for ack */
253 ret = pcie_phy_poll_ack(imx6_pcie, true);
254 if (ret)
255 return ret;
256
257 /* deassert wr signal */
258 var = PCIE_PHY_CTRL_DATA(data);
259 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
260
261 /* wait for ack de-assertion */
262 ret = pcie_phy_poll_ack(imx6_pcie, false);
263 if (ret)
264 return ret;
265
266 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
267
268 return 0;
269 }
270
imx6_pcie_reset_phy(struct imx6_pcie * imx6_pcie)271 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
272 {
273 u16 tmp;
274
275 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
276 return;
277
278 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
279 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
280 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
281 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
282
283 usleep_range(2000, 3000);
284
285 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
286 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
287 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
288 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
289 }
290
291 #ifdef CONFIG_ARM
292 /* Added for PCI abort handling */
imx6q_pcie_abort_handler(unsigned long addr,unsigned int fsr,struct pt_regs * regs)293 static int imx6q_pcie_abort_handler(unsigned long addr,
294 unsigned int fsr, struct pt_regs *regs)
295 {
296 unsigned long pc = instruction_pointer(regs);
297 unsigned long instr = *(unsigned long *)pc;
298 int reg = (instr >> 12) & 15;
299
300 /*
301 * If the instruction being executed was a read,
302 * make it look like it read all-ones.
303 */
304 if ((instr & 0x0c100000) == 0x04100000) {
305 unsigned long val;
306
307 if (instr & 0x00400000)
308 val = 255;
309 else
310 val = -1;
311
312 regs->uregs[reg] = val;
313 regs->ARM_pc += 4;
314 return 0;
315 }
316
317 if ((instr & 0x0e100090) == 0x00100090) {
318 regs->uregs[reg] = -1;
319 regs->ARM_pc += 4;
320 return 0;
321 }
322
323 return 1;
324 }
325 #endif
326
imx6_pcie_attach_pd(struct device * dev)327 static int imx6_pcie_attach_pd(struct device *dev)
328 {
329 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
330 struct device_link *link;
331
332 /* Do nothing when in a single power domain */
333 if (dev->pm_domain)
334 return 0;
335
336 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
337 if (IS_ERR(imx6_pcie->pd_pcie))
338 return PTR_ERR(imx6_pcie->pd_pcie);
339 /* Do nothing when power domain missing */
340 if (!imx6_pcie->pd_pcie)
341 return 0;
342 link = device_link_add(dev, imx6_pcie->pd_pcie,
343 DL_FLAG_STATELESS |
344 DL_FLAG_PM_RUNTIME |
345 DL_FLAG_RPM_ACTIVE);
346 if (!link) {
347 dev_err(dev, "Failed to add device_link to pcie pd.\n");
348 return -EINVAL;
349 }
350
351 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
352 if (IS_ERR(imx6_pcie->pd_pcie_phy))
353 return PTR_ERR(imx6_pcie->pd_pcie_phy);
354
355 link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
356 DL_FLAG_STATELESS |
357 DL_FLAG_PM_RUNTIME |
358 DL_FLAG_RPM_ACTIVE);
359 if (!link) {
360 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n");
361 return -EINVAL;
362 }
363
364 return 0;
365 }
366
imx6_pcie_assert_core_reset(struct imx6_pcie * imx6_pcie)367 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
368 {
369 struct device *dev = imx6_pcie->pci->dev;
370
371 switch (imx6_pcie->drvdata->variant) {
372 case IMX7D:
373 case IMX8MQ:
374 reset_control_assert(imx6_pcie->pciephy_reset);
375 reset_control_assert(imx6_pcie->apps_reset);
376 break;
377 case IMX6SX:
378 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
379 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
380 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
381 /* Force PCIe PHY reset */
382 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
383 IMX6SX_GPR5_PCIE_BTNRST_RESET,
384 IMX6SX_GPR5_PCIE_BTNRST_RESET);
385 break;
386 case IMX6QP:
387 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
388 IMX6Q_GPR1_PCIE_SW_RST,
389 IMX6Q_GPR1_PCIE_SW_RST);
390 break;
391 case IMX6Q:
392 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
393 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
394 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
395 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
396 break;
397 }
398
399 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
400 int ret = regulator_disable(imx6_pcie->vpcie);
401
402 if (ret)
403 dev_err(dev, "failed to disable vpcie regulator: %d\n",
404 ret);
405 }
406
407 /* Some boards don't have PCIe reset GPIO. */
408 if (gpio_is_valid(imx6_pcie->reset_gpio))
409 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
410 imx6_pcie->gpio_active_high);
411 }
412
imx6_pcie_grp_offset(const struct imx6_pcie * imx6_pcie)413 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
414 {
415 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
416 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
417 }
418
imx6_pcie_enable_ref_clk(struct imx6_pcie * imx6_pcie)419 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
420 {
421 struct dw_pcie *pci = imx6_pcie->pci;
422 struct device *dev = pci->dev;
423 unsigned int offset;
424 int ret = 0;
425
426 switch (imx6_pcie->drvdata->variant) {
427 case IMX6SX:
428 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
429 if (ret) {
430 dev_err(dev, "unable to enable pcie_axi clock\n");
431 break;
432 }
433
434 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
435 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
436 break;
437 case IMX6QP:
438 case IMX6Q:
439 /* power up core phy and enable ref clock */
440 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
441 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
442 /*
443 * the async reset input need ref clock to sync internally,
444 * when the ref clock comes after reset, internal synced
445 * reset time is too short, cannot meet the requirement.
446 * add one ~10us delay here.
447 */
448 usleep_range(10, 100);
449 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
450 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
451 break;
452 case IMX7D:
453 break;
454 case IMX8MQ:
455 ret = clk_prepare_enable(imx6_pcie->pcie_aux);
456 if (ret) {
457 dev_err(dev, "unable to enable pcie_aux clock\n");
458 break;
459 }
460
461 offset = imx6_pcie_grp_offset(imx6_pcie);
462 /*
463 * Set the over ride low and enabled
464 * make sure that REF_CLK is turned on.
465 */
466 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
467 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
468 0);
469 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
470 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
471 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
472 break;
473 }
474
475 return ret;
476 }
477
imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie * imx6_pcie)478 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
479 {
480 u32 val;
481 struct device *dev = imx6_pcie->pci->dev;
482
483 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
484 IOMUXC_GPR22, val,
485 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
486 PHY_PLL_LOCK_WAIT_USLEEP_MAX,
487 PHY_PLL_LOCK_WAIT_TIMEOUT))
488 dev_err(dev, "PCIe PLL lock timeout\n");
489 }
490
imx6_pcie_deassert_core_reset(struct imx6_pcie * imx6_pcie)491 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
492 {
493 struct dw_pcie *pci = imx6_pcie->pci;
494 struct device *dev = pci->dev;
495 int ret;
496
497 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
498 ret = regulator_enable(imx6_pcie->vpcie);
499 if (ret) {
500 dev_err(dev, "failed to enable vpcie regulator: %d\n",
501 ret);
502 return;
503 }
504 }
505
506 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
507 if (ret) {
508 dev_err(dev, "unable to enable pcie_phy clock\n");
509 goto err_pcie_phy;
510 }
511
512 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
513 if (ret) {
514 dev_err(dev, "unable to enable pcie_bus clock\n");
515 goto err_pcie_bus;
516 }
517
518 ret = clk_prepare_enable(imx6_pcie->pcie);
519 if (ret) {
520 dev_err(dev, "unable to enable pcie clock\n");
521 goto err_pcie;
522 }
523
524 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
525 if (ret) {
526 dev_err(dev, "unable to enable pcie ref clock\n");
527 goto err_ref_clk;
528 }
529
530 /* allow the clocks to stabilize */
531 usleep_range(200, 500);
532
533 switch (imx6_pcie->drvdata->variant) {
534 case IMX8MQ:
535 reset_control_deassert(imx6_pcie->pciephy_reset);
536 break;
537 case IMX7D:
538 reset_control_deassert(imx6_pcie->pciephy_reset);
539
540 /* Workaround for ERR010728, failure of PCI-e PLL VCO to
541 * oscillate, especially when cold. This turns off "Duty-cycle
542 * Corrector" and other mysterious undocumented things.
543 */
544 if (likely(imx6_pcie->phy_base)) {
545 /* De-assert DCC_FB_EN */
546 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
547 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
548 /* Assert RX_EQS and RX_EQS_SEL */
549 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
550 | PCIE_PHY_CMN_REG24_RX_EQ,
551 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
552 /* Assert ATT_MODE */
553 writel(PCIE_PHY_CMN_REG26_ATT_MODE,
554 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
555 } else {
556 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
557 }
558
559 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
560 break;
561 case IMX6SX:
562 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
563 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
564 break;
565 case IMX6QP:
566 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
567 IMX6Q_GPR1_PCIE_SW_RST, 0);
568
569 usleep_range(200, 500);
570 break;
571 case IMX6Q: /* Nothing to do */
572 break;
573 }
574
575 /* Some boards don't have PCIe reset GPIO. */
576 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
577 msleep(100);
578 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
579 !imx6_pcie->gpio_active_high);
580 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
581 msleep(100);
582 }
583
584 return;
585
586 err_ref_clk:
587 clk_disable_unprepare(imx6_pcie->pcie);
588 err_pcie:
589 clk_disable_unprepare(imx6_pcie->pcie_bus);
590 err_pcie_bus:
591 clk_disable_unprepare(imx6_pcie->pcie_phy);
592 err_pcie_phy:
593 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
594 ret = regulator_disable(imx6_pcie->vpcie);
595 if (ret)
596 dev_err(dev, "failed to disable vpcie regulator: %d\n",
597 ret);
598 }
599 }
600
imx6_pcie_configure_type(struct imx6_pcie * imx6_pcie)601 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
602 {
603 unsigned int mask, val;
604
605 if (imx6_pcie->drvdata->variant == IMX8MQ &&
606 imx6_pcie->controller_id == 1) {
607 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
608 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
609 PCI_EXP_TYPE_ROOT_PORT);
610 } else {
611 mask = IMX6Q_GPR12_DEVICE_TYPE;
612 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
613 PCI_EXP_TYPE_ROOT_PORT);
614 }
615
616 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
617 }
618
imx6_pcie_init_phy(struct imx6_pcie * imx6_pcie)619 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
620 {
621 switch (imx6_pcie->drvdata->variant) {
622 case IMX8MQ:
623 /*
624 * TODO: Currently this code assumes external
625 * oscillator is being used
626 */
627 regmap_update_bits(imx6_pcie->iomuxc_gpr,
628 imx6_pcie_grp_offset(imx6_pcie),
629 IMX8MQ_GPR_PCIE_REF_USE_PAD,
630 IMX8MQ_GPR_PCIE_REF_USE_PAD);
631 /*
632 * Regarding the datasheet, the PCIE_VPH is suggested
633 * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
634 * VREG_BYPASS should be cleared to zero.
635 */
636 if (imx6_pcie->vph &&
637 regulator_get_voltage(imx6_pcie->vph) > 3000000)
638 regmap_update_bits(imx6_pcie->iomuxc_gpr,
639 imx6_pcie_grp_offset(imx6_pcie),
640 IMX8MQ_GPR_PCIE_VREG_BYPASS,
641 0);
642 break;
643 case IMX7D:
644 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
645 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
646 break;
647 case IMX6SX:
648 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
649 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
650 IMX6SX_GPR12_PCIE_RX_EQ_2);
651 fallthrough;
652 default:
653 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
654 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
655
656 /* configure constant input signal to the pcie ctrl and phy */
657 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
658 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
659
660 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
661 IMX6Q_GPR8_TX_DEEMPH_GEN1,
662 imx6_pcie->tx_deemph_gen1 << 0);
663 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
664 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
665 imx6_pcie->tx_deemph_gen2_3p5db << 6);
666 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
667 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
668 imx6_pcie->tx_deemph_gen2_6db << 12);
669 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
670 IMX6Q_GPR8_TX_SWING_FULL,
671 imx6_pcie->tx_swing_full << 18);
672 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
673 IMX6Q_GPR8_TX_SWING_LOW,
674 imx6_pcie->tx_swing_low << 25);
675 break;
676 }
677
678 imx6_pcie_configure_type(imx6_pcie);
679 }
680
imx6_setup_phy_mpll(struct imx6_pcie * imx6_pcie)681 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
682 {
683 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
684 int mult, div;
685 u16 val;
686
687 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
688 return 0;
689
690 switch (phy_rate) {
691 case 125000000:
692 /*
693 * The default settings of the MPLL are for a 125MHz input
694 * clock, so no need to reconfigure anything in that case.
695 */
696 return 0;
697 case 100000000:
698 mult = 25;
699 div = 0;
700 break;
701 case 200000000:
702 mult = 25;
703 div = 1;
704 break;
705 default:
706 dev_err(imx6_pcie->pci->dev,
707 "Unsupported PHY reference clock rate %lu\n", phy_rate);
708 return -EINVAL;
709 }
710
711 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
712 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
713 PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
714 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
715 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
716 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
717
718 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
719 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
720 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
721 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
722 val |= PCIE_PHY_ATEOVRD_EN;
723 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
724
725 return 0;
726 }
727
imx6_pcie_wait_for_speed_change(struct imx6_pcie * imx6_pcie)728 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
729 {
730 struct dw_pcie *pci = imx6_pcie->pci;
731 struct device *dev = pci->dev;
732 u32 tmp;
733 unsigned int retries;
734
735 for (retries = 0; retries < 200; retries++) {
736 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
737 /* Test if the speed change finished. */
738 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
739 return 0;
740 usleep_range(100, 1000);
741 }
742
743 dev_err(dev, "Speed change timeout\n");
744 return -ETIMEDOUT;
745 }
746
imx6_pcie_ltssm_enable(struct device * dev)747 static void imx6_pcie_ltssm_enable(struct device *dev)
748 {
749 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
750
751 switch (imx6_pcie->drvdata->variant) {
752 case IMX6Q:
753 case IMX6SX:
754 case IMX6QP:
755 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
756 IMX6Q_GPR12_PCIE_CTL_2,
757 IMX6Q_GPR12_PCIE_CTL_2);
758 break;
759 case IMX7D:
760 case IMX8MQ:
761 reset_control_deassert(imx6_pcie->apps_reset);
762 break;
763 }
764 }
765
imx6_pcie_start_link(struct dw_pcie * pci)766 static int imx6_pcie_start_link(struct dw_pcie *pci)
767 {
768 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
769 struct device *dev = pci->dev;
770 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
771 u32 tmp;
772 int ret;
773
774 /*
775 * Force Gen1 operation when starting the link. In case the link is
776 * started in Gen2 mode, there is a possibility the devices on the
777 * bus will not be detected at all. This happens with PCIe switches.
778 */
779 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
780 tmp &= ~PCI_EXP_LNKCAP_SLS;
781 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
782 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
783
784 /* Start LTSSM. */
785 imx6_pcie_ltssm_enable(dev);
786
787 dw_pcie_wait_for_link(pci);
788
789 if (pci->link_gen == 2) {
790 /* Allow Gen2 mode after the link is up. */
791 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
792 tmp &= ~PCI_EXP_LNKCAP_SLS;
793 tmp |= PCI_EXP_LNKCAP_SLS_5_0GB;
794 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
795
796 /*
797 * Start Directed Speed Change so the best possible
798 * speed both link partners support can be negotiated.
799 */
800 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
801 tmp |= PORT_LOGIC_SPEED_CHANGE;
802 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
803
804 if (imx6_pcie->drvdata->flags &
805 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
806 /*
807 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
808 * from i.MX6 family when no link speed transition
809 * occurs and we go Gen1 -> yep, Gen1. The difference
810 * is that, in such case, it will not be cleared by HW
811 * which will cause the following code to report false
812 * failure.
813 */
814
815 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
816 if (ret) {
817 dev_err(dev, "Failed to bring link up!\n");
818 goto err_reset_phy;
819 }
820 }
821
822 /* Make sure link training is finished as well! */
823 dw_pcie_wait_for_link(pci);
824 } else {
825 dev_info(dev, "Link: Gen2 disabled\n");
826 }
827
828 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
829 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
830 return 0;
831
832 err_reset_phy:
833 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
834 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
835 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
836 imx6_pcie_reset_phy(imx6_pcie);
837 return ret;
838 }
839
imx6_pcie_host_init(struct pcie_port * pp)840 static int imx6_pcie_host_init(struct pcie_port *pp)
841 {
842 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
843 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
844
845 imx6_pcie_assert_core_reset(imx6_pcie);
846 imx6_pcie_init_phy(imx6_pcie);
847 imx6_pcie_deassert_core_reset(imx6_pcie);
848 imx6_setup_phy_mpll(imx6_pcie);
849
850 return 0;
851 }
852
853 static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
854 .host_init = imx6_pcie_host_init,
855 };
856
857 static const struct dw_pcie_ops dw_pcie_ops = {
858 .start_link = imx6_pcie_start_link,
859 };
860
861 #ifdef CONFIG_PM_SLEEP
imx6_pcie_ltssm_disable(struct device * dev)862 static void imx6_pcie_ltssm_disable(struct device *dev)
863 {
864 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
865
866 switch (imx6_pcie->drvdata->variant) {
867 case IMX6SX:
868 case IMX6QP:
869 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
870 IMX6Q_GPR12_PCIE_CTL_2, 0);
871 break;
872 case IMX7D:
873 reset_control_assert(imx6_pcie->apps_reset);
874 break;
875 default:
876 dev_err(dev, "ltssm_disable not supported\n");
877 }
878 }
879
imx6_pcie_pm_turnoff(struct imx6_pcie * imx6_pcie)880 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
881 {
882 struct device *dev = imx6_pcie->pci->dev;
883
884 /* Some variants have a turnoff reset in DT */
885 if (imx6_pcie->turnoff_reset) {
886 reset_control_assert(imx6_pcie->turnoff_reset);
887 reset_control_deassert(imx6_pcie->turnoff_reset);
888 goto pm_turnoff_sleep;
889 }
890
891 /* Others poke directly at IOMUXC registers */
892 switch (imx6_pcie->drvdata->variant) {
893 case IMX6SX:
894 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
895 IMX6SX_GPR12_PCIE_PM_TURN_OFF,
896 IMX6SX_GPR12_PCIE_PM_TURN_OFF);
897 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
898 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
899 break;
900 default:
901 dev_err(dev, "PME_Turn_Off not implemented\n");
902 return;
903 }
904
905 /*
906 * Components with an upstream port must respond to
907 * PME_Turn_Off with PME_TO_Ack but we can't check.
908 *
909 * The standard recommends a 1-10ms timeout after which to
910 * proceed anyway as if acks were received.
911 */
912 pm_turnoff_sleep:
913 usleep_range(1000, 10000);
914 }
915
imx6_pcie_clk_disable(struct imx6_pcie * imx6_pcie)916 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
917 {
918 clk_disable_unprepare(imx6_pcie->pcie);
919 clk_disable_unprepare(imx6_pcie->pcie_phy);
920 clk_disable_unprepare(imx6_pcie->pcie_bus);
921
922 switch (imx6_pcie->drvdata->variant) {
923 case IMX6SX:
924 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
925 break;
926 case IMX7D:
927 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
928 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
929 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
930 break;
931 case IMX8MQ:
932 clk_disable_unprepare(imx6_pcie->pcie_aux);
933 break;
934 default:
935 break;
936 }
937 }
938
imx6_pcie_suspend_noirq(struct device * dev)939 static int imx6_pcie_suspend_noirq(struct device *dev)
940 {
941 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
942
943 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
944 return 0;
945
946 imx6_pcie_pm_turnoff(imx6_pcie);
947 imx6_pcie_clk_disable(imx6_pcie);
948 imx6_pcie_ltssm_disable(dev);
949
950 return 0;
951 }
952
imx6_pcie_resume_noirq(struct device * dev)953 static int imx6_pcie_resume_noirq(struct device *dev)
954 {
955 int ret;
956 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
957 struct pcie_port *pp = &imx6_pcie->pci->pp;
958
959 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
960 return 0;
961
962 imx6_pcie_assert_core_reset(imx6_pcie);
963 imx6_pcie_init_phy(imx6_pcie);
964 imx6_pcie_deassert_core_reset(imx6_pcie);
965 dw_pcie_setup_rc(pp);
966
967 ret = imx6_pcie_start_link(imx6_pcie->pci);
968 if (ret < 0)
969 dev_info(dev, "pcie link is down after resume.\n");
970
971 return 0;
972 }
973 #endif
974
975 static const struct dev_pm_ops imx6_pcie_pm_ops = {
976 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
977 imx6_pcie_resume_noirq)
978 };
979
imx6_pcie_probe(struct platform_device * pdev)980 static int imx6_pcie_probe(struct platform_device *pdev)
981 {
982 struct device *dev = &pdev->dev;
983 struct dw_pcie *pci;
984 struct imx6_pcie *imx6_pcie;
985 struct device_node *np;
986 struct resource *dbi_base;
987 struct device_node *node = dev->of_node;
988 int ret;
989 u16 val;
990
991 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
992 if (!imx6_pcie)
993 return -ENOMEM;
994
995 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
996 if (!pci)
997 return -ENOMEM;
998
999 pci->dev = dev;
1000 pci->ops = &dw_pcie_ops;
1001 pci->pp.ops = &imx6_pcie_host_ops;
1002
1003 imx6_pcie->pci = pci;
1004 imx6_pcie->drvdata = of_device_get_match_data(dev);
1005
1006 /* Find the PHY if one is defined, only imx7d uses it */
1007 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1008 if (np) {
1009 struct resource res;
1010
1011 ret = of_address_to_resource(np, 0, &res);
1012 if (ret) {
1013 dev_err(dev, "Unable to map PCIe PHY\n");
1014 return ret;
1015 }
1016 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
1017 if (IS_ERR(imx6_pcie->phy_base))
1018 return PTR_ERR(imx6_pcie->phy_base);
1019 }
1020
1021 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1022 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
1023 if (IS_ERR(pci->dbi_base))
1024 return PTR_ERR(pci->dbi_base);
1025
1026 /* Fetch GPIOs */
1027 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
1028 imx6_pcie->gpio_active_high = of_property_read_bool(node,
1029 "reset-gpio-active-high");
1030 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
1031 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
1032 imx6_pcie->gpio_active_high ?
1033 GPIOF_OUT_INIT_HIGH :
1034 GPIOF_OUT_INIT_LOW,
1035 "PCIe reset");
1036 if (ret) {
1037 dev_err(dev, "unable to get reset gpio\n");
1038 return ret;
1039 }
1040 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
1041 return imx6_pcie->reset_gpio;
1042 }
1043
1044 /* Fetch clocks */
1045 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
1046 if (IS_ERR(imx6_pcie->pcie_phy))
1047 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
1048 "pcie_phy clock source missing or invalid\n");
1049
1050 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
1051 if (IS_ERR(imx6_pcie->pcie_bus))
1052 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
1053 "pcie_bus clock source missing or invalid\n");
1054
1055 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1056 if (IS_ERR(imx6_pcie->pcie))
1057 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
1058 "pcie clock source missing or invalid\n");
1059
1060 switch (imx6_pcie->drvdata->variant) {
1061 case IMX6SX:
1062 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
1063 "pcie_inbound_axi");
1064 if (IS_ERR(imx6_pcie->pcie_inbound_axi))
1065 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi),
1066 "pcie_inbound_axi clock missing or invalid\n");
1067 break;
1068 case IMX8MQ:
1069 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1070 if (IS_ERR(imx6_pcie->pcie_aux))
1071 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1072 "pcie_aux clock source missing or invalid\n");
1073 fallthrough;
1074 case IMX7D:
1075 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1076 imx6_pcie->controller_id = 1;
1077
1078 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
1079 "pciephy");
1080 if (IS_ERR(imx6_pcie->pciephy_reset)) {
1081 dev_err(dev, "Failed to get PCIEPHY reset control\n");
1082 return PTR_ERR(imx6_pcie->pciephy_reset);
1083 }
1084
1085 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1086 "apps");
1087 if (IS_ERR(imx6_pcie->apps_reset)) {
1088 dev_err(dev, "Failed to get PCIE APPS reset control\n");
1089 return PTR_ERR(imx6_pcie->apps_reset);
1090 }
1091 break;
1092 default:
1093 break;
1094 }
1095
1096 /* Grab turnoff reset */
1097 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1098 if (IS_ERR(imx6_pcie->turnoff_reset)) {
1099 dev_err(dev, "Failed to get TURNOFF reset control\n");
1100 return PTR_ERR(imx6_pcie->turnoff_reset);
1101 }
1102
1103 /* Grab GPR config register range */
1104 imx6_pcie->iomuxc_gpr =
1105 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
1106 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1107 dev_err(dev, "unable to find iomuxc registers\n");
1108 return PTR_ERR(imx6_pcie->iomuxc_gpr);
1109 }
1110
1111 /* Grab PCIe PHY Tx Settings */
1112 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
1113 &imx6_pcie->tx_deemph_gen1))
1114 imx6_pcie->tx_deemph_gen1 = 0;
1115
1116 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
1117 &imx6_pcie->tx_deemph_gen2_3p5db))
1118 imx6_pcie->tx_deemph_gen2_3p5db = 0;
1119
1120 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
1121 &imx6_pcie->tx_deemph_gen2_6db))
1122 imx6_pcie->tx_deemph_gen2_6db = 20;
1123
1124 if (of_property_read_u32(node, "fsl,tx-swing-full",
1125 &imx6_pcie->tx_swing_full))
1126 imx6_pcie->tx_swing_full = 127;
1127
1128 if (of_property_read_u32(node, "fsl,tx-swing-low",
1129 &imx6_pcie->tx_swing_low))
1130 imx6_pcie->tx_swing_low = 127;
1131
1132 /* Limit link speed */
1133 pci->link_gen = 1;
1134 ret = of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
1135
1136 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1137 if (IS_ERR(imx6_pcie->vpcie)) {
1138 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
1139 return PTR_ERR(imx6_pcie->vpcie);
1140 imx6_pcie->vpcie = NULL;
1141 }
1142
1143 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
1144 if (IS_ERR(imx6_pcie->vph)) {
1145 if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
1146 return PTR_ERR(imx6_pcie->vph);
1147 imx6_pcie->vph = NULL;
1148 }
1149
1150 platform_set_drvdata(pdev, imx6_pcie);
1151
1152 ret = imx6_pcie_attach_pd(dev);
1153 if (ret)
1154 return ret;
1155
1156 ret = dw_pcie_host_init(&pci->pp);
1157 if (ret < 0)
1158 return ret;
1159
1160 if (pci_msi_enabled()) {
1161 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
1162 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
1163 val |= PCI_MSI_FLAGS_ENABLE;
1164 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
1165 }
1166
1167 return 0;
1168 }
1169
imx6_pcie_shutdown(struct platform_device * pdev)1170 static void imx6_pcie_shutdown(struct platform_device *pdev)
1171 {
1172 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
1173
1174 /* bring down link, so bootloader gets clean state in case of reboot */
1175 imx6_pcie_assert_core_reset(imx6_pcie);
1176 }
1177
1178 static const struct imx6_pcie_drvdata drvdata[] = {
1179 [IMX6Q] = {
1180 .variant = IMX6Q,
1181 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1182 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1183 .dbi_length = 0x200,
1184 },
1185 [IMX6SX] = {
1186 .variant = IMX6SX,
1187 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1188 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
1189 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1190 },
1191 [IMX6QP] = {
1192 .variant = IMX6QP,
1193 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1194 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1195 .dbi_length = 0x200,
1196 },
1197 [IMX7D] = {
1198 .variant = IMX7D,
1199 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1200 },
1201 [IMX8MQ] = {
1202 .variant = IMX8MQ,
1203 },
1204 };
1205
1206 static const struct of_device_id imx6_pcie_of_match[] = {
1207 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1208 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1209 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1210 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1211 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
1212 {},
1213 };
1214
1215 static struct platform_driver imx6_pcie_driver = {
1216 .driver = {
1217 .name = "imx6q-pcie",
1218 .of_match_table = imx6_pcie_of_match,
1219 .suppress_bind_attrs = true,
1220 .pm = &imx6_pcie_pm_ops,
1221 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1222 },
1223 .probe = imx6_pcie_probe,
1224 .shutdown = imx6_pcie_shutdown,
1225 };
1226
imx6_pcie_quirk(struct pci_dev * dev)1227 static void imx6_pcie_quirk(struct pci_dev *dev)
1228 {
1229 struct pci_bus *bus = dev->bus;
1230 struct pcie_port *pp = bus->sysdata;
1231
1232 /* Bus parent is the PCI bridge, its parent is this platform driver */
1233 if (!bus->dev.parent || !bus->dev.parent->parent)
1234 return;
1235
1236 /* Make sure we only quirk devices associated with this driver */
1237 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
1238 return;
1239
1240 if (pci_is_root_bus(bus)) {
1241 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1242 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
1243
1244 /*
1245 * Limit config length to avoid the kernel reading beyond
1246 * the register set and causing an abort on i.MX 6Quad
1247 */
1248 if (imx6_pcie->drvdata->dbi_length) {
1249 dev->cfg_size = imx6_pcie->drvdata->dbi_length;
1250 dev_info(&dev->dev, "Limiting cfg_size to %d\n",
1251 dev->cfg_size);
1252 }
1253 }
1254 }
1255 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
1256 PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
1257
imx6_pcie_init(void)1258 static int __init imx6_pcie_init(void)
1259 {
1260 #ifdef CONFIG_ARM
1261 struct device_node *np;
1262
1263 np = of_find_matching_node(NULL, imx6_pcie_of_match);
1264 if (!np)
1265 return -ENODEV;
1266 of_node_put(np);
1267
1268 /*
1269 * Since probe() can be deferred we need to make sure that
1270 * hook_fault_code is not called after __init memory is freed
1271 * by kernel and since imx6q_pcie_abort_handler() is a no-op,
1272 * we can install the handler here without risking it
1273 * accessing some uninitialized driver state.
1274 */
1275 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1276 "external abort on non-linefetch");
1277 #endif
1278
1279 return platform_driver_register(&imx6_pcie_driver);
1280 }
1281 device_initcall(imx6_pcie_init);
1282