1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe controller EP driver for Freescale Layerscape SoCs
4 *
5 * Copyright (C) 2018 NXP Semiconductor.
6 *
7 * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/of_pci.h>
13 #include <linux/of_platform.h>
14 #include <linux/of_address.h>
15 #include <linux/pci.h>
16 #include <linux/platform_device.h>
17 #include <linux/resource.h>
18
19 #include "pcie-designware.h"
20
21 #define PEX_PF0_CONFIG 0xC0014
22 #define PEX_PF0_CFG_READY BIT(0)
23
24 /* PEX PFa PCIE PME and message interrupt registers*/
25 #define PEX_PF0_PME_MES_DR 0xC0020
26 #define PEX_PF0_PME_MES_DR_LUD BIT(7)
27 #define PEX_PF0_PME_MES_DR_LDD BIT(9)
28 #define PEX_PF0_PME_MES_DR_HRD BIT(10)
29
30 #define PEX_PF0_PME_MES_IER 0xC0028
31 #define PEX_PF0_PME_MES_IER_LUDIE BIT(7)
32 #define PEX_PF0_PME_MES_IER_LDDIE BIT(9)
33 #define PEX_PF0_PME_MES_IER_HRDIE BIT(10)
34
35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
36
37 struct ls_pcie_ep_drvdata {
38 u32 func_offset;
39 const struct dw_pcie_ep_ops *ops;
40 const struct dw_pcie_ops *dw_pcie_ops;
41 };
42
43 struct ls_pcie_ep {
44 struct dw_pcie *pci;
45 struct pci_epc_features *ls_epc;
46 const struct ls_pcie_ep_drvdata *drvdata;
47 int irq;
48 u32 lnkcap;
49 bool big_endian;
50 };
51
ls_lut_readl(struct ls_pcie_ep * pcie,u32 offset)52 static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset)
53 {
54 struct dw_pcie *pci = pcie->pci;
55
56 if (pcie->big_endian)
57 return ioread32be(pci->dbi_base + offset);
58 else
59 return ioread32(pci->dbi_base + offset);
60 }
61
ls_lut_writel(struct ls_pcie_ep * pcie,u32 offset,u32 value)62 static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)
63 {
64 struct dw_pcie *pci = pcie->pci;
65
66 if (pcie->big_endian)
67 iowrite32be(value, pci->dbi_base + offset);
68 else
69 iowrite32(value, pci->dbi_base + offset);
70 }
71
ls_pcie_ep_event_handler(int irq,void * dev_id)72 static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
73 {
74 struct ls_pcie_ep *pcie = dev_id;
75 struct dw_pcie *pci = pcie->pci;
76 u32 val, cfg;
77 u8 offset;
78
79 val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
80 ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
81
82 if (!val)
83 return IRQ_NONE;
84
85 if (val & PEX_PF0_PME_MES_DR_LUD) {
86
87 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
88
89 /*
90 * The values of the Maximum Link Width and Supported Link
91 * Speed from the Link Capabilities Register will be lost
92 * during link down or hot reset. Restore initial value
93 * that configured by the Reset Configuration Word (RCW).
94 */
95 dw_pcie_dbi_ro_wr_en(pci);
96 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
97 dw_pcie_dbi_ro_wr_dis(pci);
98
99 cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
100 cfg |= PEX_PF0_CFG_READY;
101 ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
102 dw_pcie_ep_linkup(&pci->ep);
103
104 dev_dbg(pci->dev, "Link up\n");
105 } else if (val & PEX_PF0_PME_MES_DR_LDD) {
106 dev_dbg(pci->dev, "Link down\n");
107 } else if (val & PEX_PF0_PME_MES_DR_HRD) {
108 dev_dbg(pci->dev, "Hot reset\n");
109 }
110
111 return IRQ_HANDLED;
112 }
113
ls_pcie_ep_interrupt_init(struct ls_pcie_ep * pcie,struct platform_device * pdev)114 static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie,
115 struct platform_device *pdev)
116 {
117 u32 val;
118 int ret;
119
120 pcie->irq = platform_get_irq_byname(pdev, "pme");
121 if (pcie->irq < 0)
122 return pcie->irq;
123
124 ret = devm_request_irq(&pdev->dev, pcie->irq, ls_pcie_ep_event_handler,
125 IRQF_SHARED, pdev->name, pcie);
126 if (ret) {
127 dev_err(&pdev->dev, "Can't register PCIe IRQ\n");
128 return ret;
129 }
130
131 /* Enable interrupts */
132 val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER);
133 val |= PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE |
134 PEX_PF0_PME_MES_IER_LUDIE;
135 ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);
136
137 return 0;
138 }
139
140 static const struct pci_epc_features*
ls_pcie_ep_get_features(struct dw_pcie_ep * ep)141 ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
142 {
143 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
144 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
145
146 return pcie->ls_epc;
147 }
148
ls_pcie_ep_init(struct dw_pcie_ep * ep)149 static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
150 {
151 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
152 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
153 struct dw_pcie_ep_func *ep_func;
154 enum pci_barno bar;
155
156 ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
157 if (!ep_func)
158 return;
159
160 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
161 dw_pcie_ep_reset_bar(pci, bar);
162
163 pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
164 pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
165 }
166
ls_pcie_ep_raise_irq(struct dw_pcie_ep * ep,u8 func_no,enum pci_epc_irq_type type,u16 interrupt_num)167 static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
168 enum pci_epc_irq_type type, u16 interrupt_num)
169 {
170 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
171
172 switch (type) {
173 case PCI_EPC_IRQ_LEGACY:
174 return dw_pcie_ep_raise_legacy_irq(ep, func_no);
175 case PCI_EPC_IRQ_MSI:
176 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
177 case PCI_EPC_IRQ_MSIX:
178 return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
179 interrupt_num);
180 default:
181 dev_err(pci->dev, "UNKNOWN IRQ type\n");
182 return -EINVAL;
183 }
184 }
185
ls_pcie_ep_func_conf_select(struct dw_pcie_ep * ep,u8 func_no)186 static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
187 u8 func_no)
188 {
189 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
190 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
191
192 WARN_ON(func_no && !pcie->drvdata->func_offset);
193 return pcie->drvdata->func_offset * func_no;
194 }
195
196 static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
197 .ep_init = ls_pcie_ep_init,
198 .raise_irq = ls_pcie_ep_raise_irq,
199 .get_features = ls_pcie_ep_get_features,
200 .func_conf_select = ls_pcie_ep_func_conf_select,
201 };
202
203 static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
204 .ops = &ls_pcie_ep_ops,
205 };
206
207 static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {
208 .func_offset = 0x20000,
209 .ops = &ls_pcie_ep_ops,
210 };
211
212 static const struct ls_pcie_ep_drvdata lx2_ep_drvdata = {
213 .func_offset = 0x8000,
214 .ops = &ls_pcie_ep_ops,
215 };
216
217 static const struct of_device_id ls_pcie_ep_of_match[] = {
218 { .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata },
219 { .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },
220 { .compatible = "fsl,ls2088a-pcie-ep", .data = &ls2_ep_drvdata },
221 { .compatible = "fsl,lx2160ar2-pcie-ep", .data = &lx2_ep_drvdata },
222 { },
223 };
224
ls_pcie_ep_probe(struct platform_device * pdev)225 static int __init ls_pcie_ep_probe(struct platform_device *pdev)
226 {
227 struct device *dev = &pdev->dev;
228 struct dw_pcie *pci;
229 struct ls_pcie_ep *pcie;
230 struct pci_epc_features *ls_epc;
231 struct resource *dbi_base;
232 u8 offset;
233 int ret;
234
235 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
236 if (!pcie)
237 return -ENOMEM;
238
239 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
240 if (!pci)
241 return -ENOMEM;
242
243 ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL);
244 if (!ls_epc)
245 return -ENOMEM;
246
247 pcie->drvdata = of_device_get_match_data(dev);
248
249 pci->dev = dev;
250 pci->ops = pcie->drvdata->dw_pcie_ops;
251
252 ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4);
253 ls_epc->linkup_notifier = true;
254
255 pcie->pci = pci;
256 pcie->ls_epc = ls_epc;
257
258 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
259 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
260 if (IS_ERR(pci->dbi_base))
261 return PTR_ERR(pci->dbi_base);
262
263 pci->ep.ops = &ls_pcie_ep_ops;
264
265 pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");
266
267 platform_set_drvdata(pdev, pcie);
268
269 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
270 pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
271
272 ret = dw_pcie_ep_init(&pci->ep);
273 if (ret)
274 return ret;
275
276 return ls_pcie_ep_interrupt_init(pcie, pdev);
277 }
278
279 static struct platform_driver ls_pcie_ep_driver = {
280 .driver = {
281 .name = "layerscape-pcie-ep",
282 .of_match_table = ls_pcie_ep_of_match,
283 .suppress_bind_attrs = true,
284 },
285 };
286 builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
287