1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/msi.h>
14 #include <linux/of_address.h>
15 #include <linux/of_pci.h>
16 #include <linux/pci_regs.h>
17 #include <linux/platform_device.h>
18
19 #include "../../pci.h"
20 #include "pcie-designware.h"
21
22 static struct pci_ops dw_pcie_ops;
23 static struct pci_ops dw_child_pcie_ops;
24
dw_msi_ack_irq(struct irq_data * d)25 static void dw_msi_ack_irq(struct irq_data *d)
26 {
27 irq_chip_ack_parent(d);
28 }
29
dw_msi_mask_irq(struct irq_data * d)30 static void dw_msi_mask_irq(struct irq_data *d)
31 {
32 pci_msi_mask_irq(d);
33 irq_chip_mask_parent(d);
34 }
35
dw_msi_unmask_irq(struct irq_data * d)36 static void dw_msi_unmask_irq(struct irq_data *d)
37 {
38 pci_msi_unmask_irq(d);
39 irq_chip_unmask_parent(d);
40 }
41
42 static struct irq_chip dw_pcie_msi_irq_chip = {
43 .name = "PCI-MSI",
44 .irq_ack = dw_msi_ack_irq,
45 .irq_mask = dw_msi_mask_irq,
46 .irq_unmask = dw_msi_unmask_irq,
47 };
48
49 static struct msi_domain_info dw_pcie_msi_domain_info = {
50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
52 .chip = &dw_pcie_msi_irq_chip,
53 };
54
55 /* MSI int handler */
dw_handle_msi_irq(struct pcie_port * pp)56 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
57 {
58 int i, pos;
59 unsigned long val;
60 u32 status, num_ctrls;
61 irqreturn_t ret = IRQ_NONE;
62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
63
64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
65
66 for (i = 0; i < num_ctrls; i++) {
67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
68 (i * MSI_REG_CTRL_BLOCK_SIZE));
69 if (!status)
70 continue;
71
72 ret = IRQ_HANDLED;
73 val = status;
74 pos = 0;
75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
76 pos)) != MAX_MSI_IRQS_PER_CTRL) {
77 generic_handle_domain_irq(pp->irq_domain,
78 (i * MAX_MSI_IRQS_PER_CTRL) +
79 pos);
80 pos++;
81 }
82 }
83
84 return ret;
85 }
86 EXPORT_SYMBOL_GPL(dw_handle_msi_irq);
87
88 /* Chained MSI interrupt service routine */
dw_chained_msi_isr(struct irq_desc * desc)89 static void dw_chained_msi_isr(struct irq_desc *desc)
90 {
91 struct irq_chip *chip = irq_desc_get_chip(desc);
92 struct pcie_port *pp;
93
94 chained_irq_enter(chip, desc);
95
96 pp = irq_desc_get_handler_data(desc);
97 dw_handle_msi_irq(pp);
98
99 chained_irq_exit(chip, desc);
100 }
101
dw_pci_setup_msi_msg(struct irq_data * d,struct msi_msg * msg)102 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
103 {
104 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
105 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
106 u64 msi_target;
107
108 msi_target = (u64)pp->msi_data;
109
110 msg->address_lo = lower_32_bits(msi_target);
111 msg->address_hi = upper_32_bits(msi_target);
112
113 msg->data = d->hwirq;
114
115 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
116 (int)d->hwirq, msg->address_hi, msg->address_lo);
117 }
118
dw_pci_msi_set_affinity(struct irq_data * d,const struct cpumask * mask,bool force)119 static int dw_pci_msi_set_affinity(struct irq_data *d,
120 const struct cpumask *mask, bool force)
121 {
122 return -EINVAL;
123 }
124
dw_pci_bottom_mask(struct irq_data * d)125 static void dw_pci_bottom_mask(struct irq_data *d)
126 {
127 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
128 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
129 unsigned int res, bit, ctrl;
130 unsigned long flags;
131
132 raw_spin_lock_irqsave(&pp->lock, flags);
133
134 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
135 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
136 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
137
138 pp->irq_mask[ctrl] |= BIT(bit);
139 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
140
141 raw_spin_unlock_irqrestore(&pp->lock, flags);
142 }
143
dw_pci_bottom_unmask(struct irq_data * d)144 static void dw_pci_bottom_unmask(struct irq_data *d)
145 {
146 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
147 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
148 unsigned int res, bit, ctrl;
149 unsigned long flags;
150
151 raw_spin_lock_irqsave(&pp->lock, flags);
152
153 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
154 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
155 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
156
157 pp->irq_mask[ctrl] &= ~BIT(bit);
158 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
159
160 raw_spin_unlock_irqrestore(&pp->lock, flags);
161 }
162
dw_pci_bottom_ack(struct irq_data * d)163 static void dw_pci_bottom_ack(struct irq_data *d)
164 {
165 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
166 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
167 unsigned int res, bit, ctrl;
168
169 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
170 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
171 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
172
173 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
174 }
175
176 static struct irq_chip dw_pci_msi_bottom_irq_chip = {
177 .name = "DWPCI-MSI",
178 .irq_ack = dw_pci_bottom_ack,
179 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
180 .irq_set_affinity = dw_pci_msi_set_affinity,
181 .irq_mask = dw_pci_bottom_mask,
182 .irq_unmask = dw_pci_bottom_unmask,
183 };
184
dw_pcie_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)185 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
186 unsigned int virq, unsigned int nr_irqs,
187 void *args)
188 {
189 struct pcie_port *pp = domain->host_data;
190 unsigned long flags;
191 u32 i;
192 int bit;
193
194 raw_spin_lock_irqsave(&pp->lock, flags);
195
196 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
197 order_base_2(nr_irqs));
198
199 raw_spin_unlock_irqrestore(&pp->lock, flags);
200
201 if (bit < 0)
202 return -ENOSPC;
203
204 for (i = 0; i < nr_irqs; i++)
205 irq_domain_set_info(domain, virq + i, bit + i,
206 pp->msi_irq_chip,
207 pp, handle_edge_irq,
208 NULL, NULL);
209
210 return 0;
211 }
212
dw_pcie_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)213 static void dw_pcie_irq_domain_free(struct irq_domain *domain,
214 unsigned int virq, unsigned int nr_irqs)
215 {
216 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
217 struct pcie_port *pp = domain->host_data;
218 unsigned long flags;
219
220 raw_spin_lock_irqsave(&pp->lock, flags);
221
222 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
223 order_base_2(nr_irqs));
224
225 raw_spin_unlock_irqrestore(&pp->lock, flags);
226 }
227
228 static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
229 .alloc = dw_pcie_irq_domain_alloc,
230 .free = dw_pcie_irq_domain_free,
231 };
232
dw_pcie_allocate_domains(struct pcie_port * pp)233 int dw_pcie_allocate_domains(struct pcie_port *pp)
234 {
235 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
236 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
237
238 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
239 &dw_pcie_msi_domain_ops, pp);
240 if (!pp->irq_domain) {
241 dev_err(pci->dev, "Failed to create IRQ domain\n");
242 return -ENOMEM;
243 }
244
245 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
246
247 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
248 &dw_pcie_msi_domain_info,
249 pp->irq_domain);
250 if (!pp->msi_domain) {
251 dev_err(pci->dev, "Failed to create MSI domain\n");
252 irq_domain_remove(pp->irq_domain);
253 return -ENOMEM;
254 }
255
256 return 0;
257 }
258
dw_pcie_free_msi(struct pcie_port * pp)259 static void dw_pcie_free_msi(struct pcie_port *pp)
260 {
261 if (pp->msi_irq)
262 irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
263
264 irq_domain_remove(pp->msi_domain);
265 irq_domain_remove(pp->irq_domain);
266 }
267
dw_pcie_msi_init(struct pcie_port * pp)268 static void dw_pcie_msi_init(struct pcie_port *pp)
269 {
270 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
271 u64 msi_target = (u64)pp->msi_data;
272
273 if (!pci_msi_enabled() || !pp->has_msi_ctrl)
274 return;
275
276 /* Program the msi_data */
277 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
278 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
279 }
280
dw_pcie_host_init(struct pcie_port * pp)281 int dw_pcie_host_init(struct pcie_port *pp)
282 {
283 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
284 struct device *dev = pci->dev;
285 struct device_node *np = dev->of_node;
286 struct platform_device *pdev = to_platform_device(dev);
287 struct resource_entry *win;
288 struct pci_host_bridge *bridge;
289 struct resource *cfg_res;
290 u64 *msi_vaddr;
291 int ret;
292
293 raw_spin_lock_init(&pci->pp.lock);
294
295 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
296 if (cfg_res) {
297 pp->cfg0_size = resource_size(cfg_res);
298 pp->cfg0_base = cfg_res->start;
299
300 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, cfg_res);
301 if (IS_ERR(pp->va_cfg0_base))
302 return PTR_ERR(pp->va_cfg0_base);
303 } else {
304 dev_err(dev, "Missing *config* reg space\n");
305 return -ENODEV;
306 }
307
308 if (!pci->dbi_base) {
309 struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
310 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
311 if (IS_ERR(pci->dbi_base))
312 return PTR_ERR(pci->dbi_base);
313 }
314
315 bridge = devm_pci_alloc_host_bridge(dev, 0);
316 if (!bridge)
317 return -ENOMEM;
318
319 pp->bridge = bridge;
320
321 /* Get the I/O range from DT */
322 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
323 if (win) {
324 pp->io_size = resource_size(win->res);
325 pp->io_bus_addr = win->res->start - win->offset;
326 pp->io_base = pci_pio_to_address(win->res->start);
327 }
328
329 if (pci->link_gen < 1)
330 pci->link_gen = of_pci_get_max_link_speed(np);
331
332 if (pci_msi_enabled()) {
333 pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
334 of_property_read_bool(np, "msi-parent") ||
335 of_property_read_bool(np, "msi-map"));
336
337 if (!pp->num_vectors) {
338 pp->num_vectors = MSI_DEF_NUM_VECTORS;
339 } else if (pp->num_vectors > MAX_MSI_IRQS) {
340 dev_err(dev, "Invalid number of vectors\n");
341 return -EINVAL;
342 }
343
344 if (pp->ops->msi_host_init) {
345 ret = pp->ops->msi_host_init(pp);
346 if (ret < 0)
347 return ret;
348 } else if (pp->has_msi_ctrl) {
349 if (!pp->msi_irq) {
350 pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
351 if (pp->msi_irq < 0) {
352 pp->msi_irq = platform_get_irq(pdev, 0);
353 if (pp->msi_irq < 0)
354 return pp->msi_irq;
355 }
356 }
357
358 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
359
360 ret = dw_pcie_allocate_domains(pp);
361 if (ret)
362 return ret;
363
364 if (pp->msi_irq > 0)
365 irq_set_chained_handler_and_data(pp->msi_irq,
366 dw_chained_msi_isr,
367 pp);
368
369 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
370 if (ret)
371 dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
372
373 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
374 GFP_KERNEL);
375 if (!msi_vaddr) {
376 u16 msi_capabilities;
377
378 /* Retry the allocation with a 64-bit mask if supported. */
379 msi_capabilities = dw_pcie_msi_capabilities(pci);
380 if ((msi_capabilities & PCI_MSI_FLAGS_ENABLE) &&
381 (msi_capabilities & PCI_MSI_FLAGS_64BIT)) {
382 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
383 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64),
384 &pp->msi_data,
385 GFP_KERNEL);
386 }
387 if (!msi_vaddr) {
388 dev_err(dev, "Failed to alloc and map MSI data\n");
389 ret = -ENOMEM;
390 goto err_free_msi;
391 }
392 }
393 }
394 }
395
396 /* Set default bus ops */
397 bridge->ops = &dw_pcie_ops;
398 bridge->child_ops = &dw_child_pcie_ops;
399
400 if (pp->ops->host_init) {
401 ret = pp->ops->host_init(pp);
402 if (ret)
403 goto err_free_msi;
404 }
405 dw_pcie_iatu_detect(pci);
406
407 dw_pcie_setup_rc(pp);
408
409 if (!dw_pcie_link_up(pci)) {
410 ret = dw_pcie_start_link(pci);
411 if (ret)
412 goto err_free_msi;
413 }
414
415 /* Ignore errors, the link may come up later */
416 dw_pcie_wait_for_link(pci);
417
418 bridge->sysdata = pp;
419
420 ret = pci_host_probe(bridge);
421 if (ret)
422 goto err_stop_link;
423
424 return 0;
425
426 err_stop_link:
427 dw_pcie_stop_link(pci);
428
429 err_free_msi:
430 if (pp->has_msi_ctrl)
431 dw_pcie_free_msi(pp);
432 return ret;
433 }
434 EXPORT_SYMBOL_GPL(dw_pcie_host_init);
435
dw_pcie_host_deinit(struct pcie_port * pp)436 void dw_pcie_host_deinit(struct pcie_port *pp)
437 {
438 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
439
440 pci_stop_root_bus(pp->bridge->bus);
441 pci_remove_root_bus(pp->bridge->bus);
442
443 dw_pcie_stop_link(pci);
444
445 if (pp->has_msi_ctrl)
446 dw_pcie_free_msi(pp);
447 }
448 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
449
dw_pcie_other_conf_map_bus(struct pci_bus * bus,unsigned int devfn,int where)450 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
451 unsigned int devfn, int where)
452 {
453 int type;
454 u32 busdev;
455 struct pcie_port *pp = bus->sysdata;
456 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
457
458 /*
459 * Checking whether the link is up here is a last line of defense
460 * against platforms that forward errors on the system bus as
461 * SError upon PCI configuration transactions issued when the link
462 * is down. This check is racy by definition and does not stop
463 * the system from triggering an SError if the link goes down
464 * after this check is performed.
465 */
466 if (!dw_pcie_link_up(pci))
467 return NULL;
468
469 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
470 PCIE_ATU_FUNC(PCI_FUNC(devfn));
471
472 if (pci_is_root_bus(bus->parent))
473 type = PCIE_ATU_TYPE_CFG0;
474 else
475 type = PCIE_ATU_TYPE_CFG1;
476
477
478 dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, pp->cfg0_size);
479
480 return pp->va_cfg0_base + where;
481 }
482
dw_pcie_rd_other_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)483 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
484 int where, int size, u32 *val)
485 {
486 int ret;
487 struct pcie_port *pp = bus->sysdata;
488 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
489
490 ret = pci_generic_config_read(bus, devfn, where, size, val);
491
492 if (!ret && pci->io_cfg_atu_shared)
493 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
494 pp->io_bus_addr, pp->io_size);
495
496 return ret;
497 }
498
dw_pcie_wr_other_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)499 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
500 int where, int size, u32 val)
501 {
502 int ret;
503 struct pcie_port *pp = bus->sysdata;
504 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
505
506 ret = pci_generic_config_write(bus, devfn, where, size, val);
507
508 if (!ret && pci->io_cfg_atu_shared)
509 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
510 pp->io_bus_addr, pp->io_size);
511
512 return ret;
513 }
514
515 static struct pci_ops dw_child_pcie_ops = {
516 .map_bus = dw_pcie_other_conf_map_bus,
517 .read = dw_pcie_rd_other_conf,
518 .write = dw_pcie_wr_other_conf,
519 };
520
dw_pcie_own_conf_map_bus(struct pci_bus * bus,unsigned int devfn,int where)521 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
522 {
523 struct pcie_port *pp = bus->sysdata;
524 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
525
526 if (PCI_SLOT(devfn) > 0)
527 return NULL;
528
529 return pci->dbi_base + where;
530 }
531 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
532
533 static struct pci_ops dw_pcie_ops = {
534 .map_bus = dw_pcie_own_conf_map_bus,
535 .read = pci_generic_config_read,
536 .write = pci_generic_config_write,
537 };
538
dw_pcie_setup_rc(struct pcie_port * pp)539 void dw_pcie_setup_rc(struct pcie_port *pp)
540 {
541 u32 val, ctrl, num_ctrls;
542 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
543
544 /*
545 * Enable DBI read-only registers for writing/updating configuration.
546 * Write permission gets disabled towards the end of this function.
547 */
548 dw_pcie_dbi_ro_wr_en(pci);
549
550 dw_pcie_setup(pci);
551
552 if (pp->has_msi_ctrl) {
553 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
554
555 /* Initialize IRQ Status array */
556 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
557 pp->irq_mask[ctrl] = ~0;
558 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
559 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
560 pp->irq_mask[ctrl]);
561 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
562 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
563 ~0);
564 }
565 }
566
567 dw_pcie_msi_init(pp);
568
569 /* Setup RC BARs */
570 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
571 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
572
573 /* Setup interrupt pins */
574 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
575 val &= 0xffff00ff;
576 val |= 0x00000100;
577 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
578
579 /* Setup bus numbers */
580 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
581 val &= 0xff000000;
582 val |= 0x00ff0100;
583 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
584
585 /* Setup command register */
586 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
587 val &= 0xffff0000;
588 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
589 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
590 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
591
592 /*
593 * If the platform provides its own child bus config accesses, it means
594 * the platform uses its own address translation component rather than
595 * ATU, so we should not program the ATU here.
596 */
597 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
598 int i, atu_idx = 0;
599 struct resource_entry *entry;
600
601 /*
602 * Disable all outbound windows to make sure a transaction
603 * can't match multiple windows.
604 */
605 for (i = 0; i < pci->num_ob_windows; i++)
606 dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
607
608 /* Get last memory resource entry */
609 resource_list_for_each_entry(entry, &pp->bridge->windows) {
610 if (resource_type(entry->res) != IORESOURCE_MEM)
611 continue;
612
613 if (pci->num_ob_windows <= ++atu_idx)
614 break;
615
616 dw_pcie_prog_outbound_atu(pci, atu_idx,
617 PCIE_ATU_TYPE_MEM, entry->res->start,
618 entry->res->start - entry->offset,
619 resource_size(entry->res));
620 }
621
622 if (pp->io_size) {
623 if (pci->num_ob_windows > ++atu_idx)
624 dw_pcie_prog_outbound_atu(pci, atu_idx,
625 PCIE_ATU_TYPE_IO, pp->io_base,
626 pp->io_bus_addr, pp->io_size);
627 else
628 pci->io_cfg_atu_shared = true;
629 }
630
631 if (pci->num_ob_windows <= atu_idx)
632 dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)",
633 pci->num_ob_windows);
634 }
635
636 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
637
638 /* Program correct class for RC */
639 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
640
641 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
642 val |= PORT_LOGIC_SPEED_CHANGE;
643 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
644
645 dw_pcie_dbi_ro_wr_dis(pci);
646 }
647 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
648