1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/msi.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_pci.h>
22 #include <linux/of_platform.h>
23 #include <linux/pci.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29
30 #include "../pci.h"
31
32 /* PCIe shared registers */
33 #define PCIE_SYS_CFG 0x00
34 #define PCIE_INT_ENABLE 0x0c
35 #define PCIE_CFG_ADDR 0x20
36 #define PCIE_CFG_DATA 0x24
37
38 /* PCIe per port registers */
39 #define PCIE_BAR0_SETUP 0x10
40 #define PCIE_CLASS 0x34
41 #define PCIE_LINK_STATUS 0x50
42
43 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
44 #define PCIE_PORT_PERST(x) BIT(1 + (x))
45 #define PCIE_PORT_LINKUP BIT(0)
46 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
47
48 #define PCIE_BAR_ENABLE BIT(0)
49 #define PCIE_REVISION_ID BIT(0)
50 #define PCIE_CLASS_CODE (0x60400 << 8)
51 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
52 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
53 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
54 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
55 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
56 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
57 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
58 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
59
60 /* MediaTek specific configuration registers */
61 #define PCIE_FTS_NUM 0x70c
62 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
63 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
64
65 #define PCIE_FC_CREDIT 0x73c
66 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
67 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
68
69 /* PCIe V2 share registers */
70 #define PCIE_SYS_CFG_V2 0x0
71 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
72 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
73
74 /* PCIe V2 per-port registers */
75 #define PCIE_MSI_VECTOR 0x0c0
76
77 #define PCIE_CONF_VEND_ID 0x100
78 #define PCIE_CONF_DEVICE_ID 0x102
79 #define PCIE_CONF_CLASS_ID 0x106
80
81 #define PCIE_INT_MASK 0x420
82 #define INTX_MASK GENMASK(19, 16)
83 #define INTX_SHIFT 16
84 #define PCIE_INT_STATUS 0x424
85 #define MSI_STATUS BIT(23)
86 #define PCIE_IMSI_STATUS 0x42c
87 #define PCIE_IMSI_ADDR 0x430
88 #define MSI_MASK BIT(23)
89 #define MTK_MSI_IRQS_NUM 32
90
91 #define PCIE_AHB_TRANS_BASE0_L 0x438
92 #define PCIE_AHB_TRANS_BASE0_H 0x43c
93 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
94 #define PCIE_AXI_WINDOW0 0x448
95 #define WIN_ENABLE BIT(7)
96 /*
97 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
98 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
99 * start from 0x40000000).
100 */
101 #define PCIE2AHB_SIZE 0x21
102
103 /* PCIe V2 configuration transaction header */
104 #define PCIE_CFG_HEADER0 0x460
105 #define PCIE_CFG_HEADER1 0x464
106 #define PCIE_CFG_HEADER2 0x468
107 #define PCIE_CFG_WDATA 0x470
108 #define PCIE_APP_TLP_REQ 0x488
109 #define PCIE_CFG_RDATA 0x48c
110 #define APP_CFG_REQ BIT(0)
111 #define APP_CPL_STATUS GENMASK(7, 5)
112
113 #define CFG_WRRD_TYPE_0 4
114 #define CFG_WR_FMT 2
115 #define CFG_RD_FMT 0
116
117 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
118 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
119 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
120 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
121 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
122 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
123 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
124 #define CFG_HEADER_DW0(type, fmt) \
125 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
126 #define CFG_HEADER_DW1(where, size) \
127 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
128 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
129 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
130 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
131
132 #define PCIE_RST_CTRL 0x510
133 #define PCIE_PHY_RSTB BIT(0)
134 #define PCIE_PIPE_SRSTB BIT(1)
135 #define PCIE_MAC_SRSTB BIT(2)
136 #define PCIE_CRSTB BIT(3)
137 #define PCIE_PERSTB BIT(8)
138 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
139 #define PCIE_LINK_STATUS_V2 0x804
140 #define PCIE_PORT_LINKUP_V2 BIT(10)
141
142 struct mtk_pcie_port;
143
144 /**
145 * struct mtk_pcie_soc - differentiate between host generations
146 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
147 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
148 * @no_msi: Bridge has no MSI support, and relies on an external block
149 * @device_id: device ID which this host need to be fixed
150 * @ops: pointer to configuration access functions
151 * @startup: pointer to controller setting functions
152 * @setup_irq: pointer to initialize IRQ functions
153 */
154 struct mtk_pcie_soc {
155 bool need_fix_class_id;
156 bool need_fix_device_id;
157 bool no_msi;
158 unsigned int device_id;
159 struct pci_ops *ops;
160 int (*startup)(struct mtk_pcie_port *port);
161 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
162 };
163
164 /**
165 * struct mtk_pcie_port - PCIe port information
166 * @base: IO mapped register base
167 * @list: port list
168 * @pcie: pointer to PCIe host info
169 * @reset: pointer to port reset control
170 * @sys_ck: pointer to transaction/data link layer clock
171 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
172 * and RC initiated MMIO access
173 * @axi_ck: pointer to application layer MMIO channel operating clock
174 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
175 * when pcie_mac_ck/pcie_pipe_ck is turned off
176 * @obff_ck: pointer to OBFF functional block operating clock
177 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
178 * @phy: pointer to PHY control block
179 * @slot: port slot
180 * @irq: GIC irq
181 * @irq_domain: legacy INTx IRQ domain
182 * @inner_domain: inner IRQ domain
183 * @msi_domain: MSI IRQ domain
184 * @lock: protect the msi_irq_in_use bitmap
185 * @msi_irq_in_use: bit map for assigned MSI IRQ
186 */
187 struct mtk_pcie_port {
188 void __iomem *base;
189 struct list_head list;
190 struct mtk_pcie *pcie;
191 struct reset_control *reset;
192 struct clk *sys_ck;
193 struct clk *ahb_ck;
194 struct clk *axi_ck;
195 struct clk *aux_ck;
196 struct clk *obff_ck;
197 struct clk *pipe_ck;
198 struct phy *phy;
199 u32 slot;
200 int irq;
201 struct irq_domain *irq_domain;
202 struct irq_domain *inner_domain;
203 struct irq_domain *msi_domain;
204 struct mutex lock;
205 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
206 };
207
208 /**
209 * struct mtk_pcie - PCIe host information
210 * @dev: pointer to PCIe device
211 * @base: IO mapped register base
212 * @cfg: IO mapped register map for PCIe config
213 * @free_ck: free-run reference clock
214 * @mem: non-prefetchable memory resource
215 * @ports: pointer to PCIe port information
216 * @soc: pointer to SoC-dependent operations
217 */
218 struct mtk_pcie {
219 struct device *dev;
220 void __iomem *base;
221 struct regmap *cfg;
222 struct clk *free_ck;
223
224 struct list_head ports;
225 const struct mtk_pcie_soc *soc;
226 };
227
mtk_pcie_subsys_powerdown(struct mtk_pcie * pcie)228 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
229 {
230 struct device *dev = pcie->dev;
231
232 clk_disable_unprepare(pcie->free_ck);
233
234 pm_runtime_put_sync(dev);
235 pm_runtime_disable(dev);
236 }
237
mtk_pcie_port_free(struct mtk_pcie_port * port)238 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
239 {
240 struct mtk_pcie *pcie = port->pcie;
241 struct device *dev = pcie->dev;
242
243 devm_iounmap(dev, port->base);
244 list_del(&port->list);
245 devm_kfree(dev, port);
246 }
247
mtk_pcie_put_resources(struct mtk_pcie * pcie)248 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
249 {
250 struct mtk_pcie_port *port, *tmp;
251
252 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
253 phy_power_off(port->phy);
254 phy_exit(port->phy);
255 clk_disable_unprepare(port->pipe_ck);
256 clk_disable_unprepare(port->obff_ck);
257 clk_disable_unprepare(port->axi_ck);
258 clk_disable_unprepare(port->aux_ck);
259 clk_disable_unprepare(port->ahb_ck);
260 clk_disable_unprepare(port->sys_ck);
261 mtk_pcie_port_free(port);
262 }
263
264 mtk_pcie_subsys_powerdown(pcie);
265 }
266
mtk_pcie_check_cfg_cpld(struct mtk_pcie_port * port)267 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
268 {
269 u32 val;
270 int err;
271
272 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
273 !(val & APP_CFG_REQ), 10,
274 100 * USEC_PER_MSEC);
275 if (err)
276 return PCIBIOS_SET_FAILED;
277
278 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
279 return PCIBIOS_SET_FAILED;
280
281 return PCIBIOS_SUCCESSFUL;
282 }
283
mtk_pcie_hw_rd_cfg(struct mtk_pcie_port * port,u32 bus,u32 devfn,int where,int size,u32 * val)284 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
285 int where, int size, u32 *val)
286 {
287 u32 tmp;
288
289 /* Write PCIe configuration transaction header for Cfgrd */
290 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
291 port->base + PCIE_CFG_HEADER0);
292 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
293 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
294 port->base + PCIE_CFG_HEADER2);
295
296 /* Trigger h/w to transmit Cfgrd TLP */
297 tmp = readl(port->base + PCIE_APP_TLP_REQ);
298 tmp |= APP_CFG_REQ;
299 writel(tmp, port->base + PCIE_APP_TLP_REQ);
300
301 /* Check completion status */
302 if (mtk_pcie_check_cfg_cpld(port))
303 return PCIBIOS_SET_FAILED;
304
305 /* Read cpld payload of Cfgrd */
306 *val = readl(port->base + PCIE_CFG_RDATA);
307
308 if (size == 1)
309 *val = (*val >> (8 * (where & 3))) & 0xff;
310 else if (size == 2)
311 *val = (*val >> (8 * (where & 3))) & 0xffff;
312
313 return PCIBIOS_SUCCESSFUL;
314 }
315
mtk_pcie_hw_wr_cfg(struct mtk_pcie_port * port,u32 bus,u32 devfn,int where,int size,u32 val)316 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
317 int where, int size, u32 val)
318 {
319 /* Write PCIe configuration transaction header for Cfgwr */
320 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
321 port->base + PCIE_CFG_HEADER0);
322 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
323 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
324 port->base + PCIE_CFG_HEADER2);
325
326 /* Write Cfgwr data */
327 val = val << 8 * (where & 3);
328 writel(val, port->base + PCIE_CFG_WDATA);
329
330 /* Trigger h/w to transmit Cfgwr TLP */
331 val = readl(port->base + PCIE_APP_TLP_REQ);
332 val |= APP_CFG_REQ;
333 writel(val, port->base + PCIE_APP_TLP_REQ);
334
335 /* Check completion status */
336 return mtk_pcie_check_cfg_cpld(port);
337 }
338
mtk_pcie_find_port(struct pci_bus * bus,unsigned int devfn)339 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
340 unsigned int devfn)
341 {
342 struct mtk_pcie *pcie = bus->sysdata;
343 struct mtk_pcie_port *port;
344 struct pci_dev *dev = NULL;
345
346 /*
347 * Walk the bus hierarchy to get the devfn value
348 * of the port in the root bus.
349 */
350 while (bus && bus->number) {
351 dev = bus->self;
352 bus = dev->bus;
353 devfn = dev->devfn;
354 }
355
356 list_for_each_entry(port, &pcie->ports, list)
357 if (port->slot == PCI_SLOT(devfn))
358 return port;
359
360 return NULL;
361 }
362
mtk_pcie_config_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)363 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
364 int where, int size, u32 *val)
365 {
366 struct mtk_pcie_port *port;
367 u32 bn = bus->number;
368 int ret;
369
370 port = mtk_pcie_find_port(bus, devfn);
371 if (!port) {
372 *val = ~0;
373 return PCIBIOS_DEVICE_NOT_FOUND;
374 }
375
376 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
377 if (ret)
378 *val = ~0;
379
380 return ret;
381 }
382
mtk_pcie_config_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)383 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
384 int where, int size, u32 val)
385 {
386 struct mtk_pcie_port *port;
387 u32 bn = bus->number;
388
389 port = mtk_pcie_find_port(bus, devfn);
390 if (!port)
391 return PCIBIOS_DEVICE_NOT_FOUND;
392
393 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
394 }
395
396 static struct pci_ops mtk_pcie_ops_v2 = {
397 .read = mtk_pcie_config_read,
398 .write = mtk_pcie_config_write,
399 };
400
mtk_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)401 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
402 {
403 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
404 phys_addr_t addr;
405
406 /* MT2712/MT7622 only support 32-bit MSI addresses */
407 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
408 msg->address_hi = 0;
409 msg->address_lo = lower_32_bits(addr);
410
411 msg->data = data->hwirq;
412
413 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
414 (int)data->hwirq, msg->address_hi, msg->address_lo);
415 }
416
mtk_msi_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)417 static int mtk_msi_set_affinity(struct irq_data *irq_data,
418 const struct cpumask *mask, bool force)
419 {
420 return -EINVAL;
421 }
422
mtk_msi_ack_irq(struct irq_data * data)423 static void mtk_msi_ack_irq(struct irq_data *data)
424 {
425 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
426 u32 hwirq = data->hwirq;
427
428 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
429 }
430
431 static struct irq_chip mtk_msi_bottom_irq_chip = {
432 .name = "MTK MSI",
433 .irq_compose_msi_msg = mtk_compose_msi_msg,
434 .irq_set_affinity = mtk_msi_set_affinity,
435 .irq_ack = mtk_msi_ack_irq,
436 };
437
mtk_pcie_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)438 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
439 unsigned int nr_irqs, void *args)
440 {
441 struct mtk_pcie_port *port = domain->host_data;
442 unsigned long bit;
443
444 WARN_ON(nr_irqs != 1);
445 mutex_lock(&port->lock);
446
447 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
448 if (bit >= MTK_MSI_IRQS_NUM) {
449 mutex_unlock(&port->lock);
450 return -ENOSPC;
451 }
452
453 __set_bit(bit, port->msi_irq_in_use);
454
455 mutex_unlock(&port->lock);
456
457 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
458 domain->host_data, handle_edge_irq,
459 NULL, NULL);
460
461 return 0;
462 }
463
mtk_pcie_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)464 static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
465 unsigned int virq, unsigned int nr_irqs)
466 {
467 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
468 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
469
470 mutex_lock(&port->lock);
471
472 if (!test_bit(d->hwirq, port->msi_irq_in_use))
473 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
474 d->hwirq);
475 else
476 __clear_bit(d->hwirq, port->msi_irq_in_use);
477
478 mutex_unlock(&port->lock);
479
480 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
481 }
482
483 static const struct irq_domain_ops msi_domain_ops = {
484 .alloc = mtk_pcie_irq_domain_alloc,
485 .free = mtk_pcie_irq_domain_free,
486 };
487
488 static struct irq_chip mtk_msi_irq_chip = {
489 .name = "MTK PCIe MSI",
490 .irq_ack = irq_chip_ack_parent,
491 .irq_mask = pci_msi_mask_irq,
492 .irq_unmask = pci_msi_unmask_irq,
493 };
494
495 static struct msi_domain_info mtk_msi_domain_info = {
496 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
497 MSI_FLAG_PCI_MSIX),
498 .chip = &mtk_msi_irq_chip,
499 };
500
mtk_pcie_allocate_msi_domains(struct mtk_pcie_port * port)501 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
502 {
503 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
504
505 mutex_init(&port->lock);
506
507 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
508 &msi_domain_ops, port);
509 if (!port->inner_domain) {
510 dev_err(port->pcie->dev, "failed to create IRQ domain\n");
511 return -ENOMEM;
512 }
513
514 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
515 port->inner_domain);
516 if (!port->msi_domain) {
517 dev_err(port->pcie->dev, "failed to create MSI domain\n");
518 irq_domain_remove(port->inner_domain);
519 return -ENOMEM;
520 }
521
522 return 0;
523 }
524
mtk_pcie_enable_msi(struct mtk_pcie_port * port)525 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
526 {
527 u32 val;
528 phys_addr_t msg_addr;
529
530 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
531 val = lower_32_bits(msg_addr);
532 writel(val, port->base + PCIE_IMSI_ADDR);
533
534 val = readl(port->base + PCIE_INT_MASK);
535 val &= ~MSI_MASK;
536 writel(val, port->base + PCIE_INT_MASK);
537 }
538
mtk_pcie_irq_teardown(struct mtk_pcie * pcie)539 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
540 {
541 struct mtk_pcie_port *port, *tmp;
542
543 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
544 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
545
546 if (port->irq_domain)
547 irq_domain_remove(port->irq_domain);
548
549 if (IS_ENABLED(CONFIG_PCI_MSI)) {
550 if (port->msi_domain)
551 irq_domain_remove(port->msi_domain);
552 if (port->inner_domain)
553 irq_domain_remove(port->inner_domain);
554 }
555
556 irq_dispose_mapping(port->irq);
557 }
558 }
559
mtk_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)560 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
561 irq_hw_number_t hwirq)
562 {
563 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
564 irq_set_chip_data(irq, domain->host_data);
565
566 return 0;
567 }
568
569 static const struct irq_domain_ops intx_domain_ops = {
570 .map = mtk_pcie_intx_map,
571 };
572
mtk_pcie_init_irq_domain(struct mtk_pcie_port * port,struct device_node * node)573 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
574 struct device_node *node)
575 {
576 struct device *dev = port->pcie->dev;
577 struct device_node *pcie_intc_node;
578 int ret;
579
580 /* Setup INTx */
581 pcie_intc_node = of_get_next_child(node, NULL);
582 if (!pcie_intc_node) {
583 dev_err(dev, "no PCIe Intc node found\n");
584 return -ENODEV;
585 }
586
587 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
588 &intx_domain_ops, port);
589 of_node_put(pcie_intc_node);
590 if (!port->irq_domain) {
591 dev_err(dev, "failed to get INTx IRQ domain\n");
592 return -ENODEV;
593 }
594
595 if (IS_ENABLED(CONFIG_PCI_MSI)) {
596 ret = mtk_pcie_allocate_msi_domains(port);
597 if (ret)
598 return ret;
599 }
600
601 return 0;
602 }
603
mtk_pcie_intr_handler(struct irq_desc * desc)604 static void mtk_pcie_intr_handler(struct irq_desc *desc)
605 {
606 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
607 struct irq_chip *irqchip = irq_desc_get_chip(desc);
608 unsigned long status;
609 u32 bit = INTX_SHIFT;
610
611 chained_irq_enter(irqchip, desc);
612
613 status = readl(port->base + PCIE_INT_STATUS);
614 if (status & INTX_MASK) {
615 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
616 /* Clear the INTx */
617 writel(1 << bit, port->base + PCIE_INT_STATUS);
618 generic_handle_domain_irq(port->irq_domain,
619 bit - INTX_SHIFT);
620 }
621 }
622
623 if (IS_ENABLED(CONFIG_PCI_MSI)) {
624 if (status & MSI_STATUS){
625 unsigned long imsi_status;
626
627 /*
628 * The interrupt status can be cleared even if the
629 * MSI status remains pending. As such, given the
630 * edge-triggered interrupt type, its status should
631 * be cleared before being dispatched to the
632 * handler of the underlying device.
633 */
634 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
635 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
636 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
637 generic_handle_domain_irq(port->inner_domain, bit);
638 }
639 }
640 }
641
642 chained_irq_exit(irqchip, desc);
643 }
644
mtk_pcie_setup_irq(struct mtk_pcie_port * port,struct device_node * node)645 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
646 struct device_node *node)
647 {
648 struct mtk_pcie *pcie = port->pcie;
649 struct device *dev = pcie->dev;
650 struct platform_device *pdev = to_platform_device(dev);
651 int err;
652
653 err = mtk_pcie_init_irq_domain(port, node);
654 if (err) {
655 dev_err(dev, "failed to init PCIe IRQ domain\n");
656 return err;
657 }
658
659 if (of_find_property(dev->of_node, "interrupt-names", NULL))
660 port->irq = platform_get_irq_byname(pdev, "pcie_irq");
661 else
662 port->irq = platform_get_irq(pdev, port->slot);
663
664 if (port->irq < 0)
665 return port->irq;
666
667 irq_set_chained_handler_and_data(port->irq,
668 mtk_pcie_intr_handler, port);
669
670 return 0;
671 }
672
mtk_pcie_startup_port_v2(struct mtk_pcie_port * port)673 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
674 {
675 struct mtk_pcie *pcie = port->pcie;
676 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
677 struct resource *mem = NULL;
678 struct resource_entry *entry;
679 const struct mtk_pcie_soc *soc = port->pcie->soc;
680 u32 val;
681 int err;
682
683 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
684 if (entry)
685 mem = entry->res;
686 if (!mem)
687 return -EINVAL;
688
689 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
690 if (pcie->base) {
691 val = readl(pcie->base + PCIE_SYS_CFG_V2);
692 val |= PCIE_CSR_LTSSM_EN(port->slot) |
693 PCIE_CSR_ASPM_L1_EN(port->slot);
694 writel(val, pcie->base + PCIE_SYS_CFG_V2);
695 } else if (pcie->cfg) {
696 val = PCIE_CSR_LTSSM_EN(port->slot) |
697 PCIE_CSR_ASPM_L1_EN(port->slot);
698 regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
699 }
700
701 /* Assert all reset signals */
702 writel(0, port->base + PCIE_RST_CTRL);
703
704 /*
705 * Enable PCIe link down reset, if link status changed from link up to
706 * link down, this will reset MAC control registers and configuration
707 * space.
708 */
709 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
710
711 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
712 val = readl(port->base + PCIE_RST_CTRL);
713 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
714 PCIE_MAC_SRSTB | PCIE_CRSTB;
715 writel(val, port->base + PCIE_RST_CTRL);
716
717 /* Set up vendor ID and class code */
718 if (soc->need_fix_class_id) {
719 val = PCI_VENDOR_ID_MEDIATEK;
720 writew(val, port->base + PCIE_CONF_VEND_ID);
721
722 val = PCI_CLASS_BRIDGE_PCI;
723 writew(val, port->base + PCIE_CONF_CLASS_ID);
724 }
725
726 if (soc->need_fix_device_id)
727 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
728
729 /* 100ms timeout value should be enough for Gen1/2 training */
730 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
731 !!(val & PCIE_PORT_LINKUP_V2), 20,
732 100 * USEC_PER_MSEC);
733 if (err)
734 return -ETIMEDOUT;
735
736 /* Set INTx mask */
737 val = readl(port->base + PCIE_INT_MASK);
738 val &= ~INTX_MASK;
739 writel(val, port->base + PCIE_INT_MASK);
740
741 if (IS_ENABLED(CONFIG_PCI_MSI))
742 mtk_pcie_enable_msi(port);
743
744 /* Set AHB to PCIe translation windows */
745 val = lower_32_bits(mem->start) |
746 AHB2PCIE_SIZE(fls(resource_size(mem)));
747 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
748
749 val = upper_32_bits(mem->start);
750 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
751
752 /* Set PCIe to AXI translation memory space.*/
753 val = PCIE2AHB_SIZE | WIN_ENABLE;
754 writel(val, port->base + PCIE_AXI_WINDOW0);
755
756 return 0;
757 }
758
mtk_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)759 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
760 unsigned int devfn, int where)
761 {
762 struct mtk_pcie *pcie = bus->sysdata;
763
764 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
765 bus->number), pcie->base + PCIE_CFG_ADDR);
766
767 return pcie->base + PCIE_CFG_DATA + (where & 3);
768 }
769
770 static struct pci_ops mtk_pcie_ops = {
771 .map_bus = mtk_pcie_map_bus,
772 .read = pci_generic_config_read,
773 .write = pci_generic_config_write,
774 };
775
mtk_pcie_startup_port(struct mtk_pcie_port * port)776 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
777 {
778 struct mtk_pcie *pcie = port->pcie;
779 u32 func = PCI_FUNC(port->slot);
780 u32 slot = PCI_SLOT(port->slot << 3);
781 u32 val;
782 int err;
783
784 /* assert port PERST_N */
785 val = readl(pcie->base + PCIE_SYS_CFG);
786 val |= PCIE_PORT_PERST(port->slot);
787 writel(val, pcie->base + PCIE_SYS_CFG);
788
789 /* de-assert port PERST_N */
790 val = readl(pcie->base + PCIE_SYS_CFG);
791 val &= ~PCIE_PORT_PERST(port->slot);
792 writel(val, pcie->base + PCIE_SYS_CFG);
793
794 /* 100ms timeout value should be enough for Gen1/2 training */
795 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
796 !!(val & PCIE_PORT_LINKUP), 20,
797 100 * USEC_PER_MSEC);
798 if (err)
799 return -ETIMEDOUT;
800
801 /* enable interrupt */
802 val = readl(pcie->base + PCIE_INT_ENABLE);
803 val |= PCIE_PORT_INT_EN(port->slot);
804 writel(val, pcie->base + PCIE_INT_ENABLE);
805
806 /* map to all DDR region. We need to set it before cfg operation. */
807 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
808 port->base + PCIE_BAR0_SETUP);
809
810 /* configure class code and revision ID */
811 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
812
813 /* configure FC credit */
814 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
815 pcie->base + PCIE_CFG_ADDR);
816 val = readl(pcie->base + PCIE_CFG_DATA);
817 val &= ~PCIE_FC_CREDIT_MASK;
818 val |= PCIE_FC_CREDIT_VAL(0x806c);
819 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
820 pcie->base + PCIE_CFG_ADDR);
821 writel(val, pcie->base + PCIE_CFG_DATA);
822
823 /* configure RC FTS number to 250 when it leaves L0s */
824 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
825 pcie->base + PCIE_CFG_ADDR);
826 val = readl(pcie->base + PCIE_CFG_DATA);
827 val &= ~PCIE_FTS_NUM_MASK;
828 val |= PCIE_FTS_NUM_L0(0x50);
829 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
830 pcie->base + PCIE_CFG_ADDR);
831 writel(val, pcie->base + PCIE_CFG_DATA);
832
833 return 0;
834 }
835
mtk_pcie_enable_port(struct mtk_pcie_port * port)836 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
837 {
838 struct mtk_pcie *pcie = port->pcie;
839 struct device *dev = pcie->dev;
840 int err;
841
842 err = clk_prepare_enable(port->sys_ck);
843 if (err) {
844 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
845 goto err_sys_clk;
846 }
847
848 err = clk_prepare_enable(port->ahb_ck);
849 if (err) {
850 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
851 goto err_ahb_clk;
852 }
853
854 err = clk_prepare_enable(port->aux_ck);
855 if (err) {
856 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
857 goto err_aux_clk;
858 }
859
860 err = clk_prepare_enable(port->axi_ck);
861 if (err) {
862 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
863 goto err_axi_clk;
864 }
865
866 err = clk_prepare_enable(port->obff_ck);
867 if (err) {
868 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
869 goto err_obff_clk;
870 }
871
872 err = clk_prepare_enable(port->pipe_ck);
873 if (err) {
874 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
875 goto err_pipe_clk;
876 }
877
878 reset_control_assert(port->reset);
879 reset_control_deassert(port->reset);
880
881 err = phy_init(port->phy);
882 if (err) {
883 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
884 goto err_phy_init;
885 }
886
887 err = phy_power_on(port->phy);
888 if (err) {
889 dev_err(dev, "failed to power on port%d phy\n", port->slot);
890 goto err_phy_on;
891 }
892
893 if (!pcie->soc->startup(port))
894 return;
895
896 dev_info(dev, "Port%d link down\n", port->slot);
897
898 phy_power_off(port->phy);
899 err_phy_on:
900 phy_exit(port->phy);
901 err_phy_init:
902 clk_disable_unprepare(port->pipe_ck);
903 err_pipe_clk:
904 clk_disable_unprepare(port->obff_ck);
905 err_obff_clk:
906 clk_disable_unprepare(port->axi_ck);
907 err_axi_clk:
908 clk_disable_unprepare(port->aux_ck);
909 err_aux_clk:
910 clk_disable_unprepare(port->ahb_ck);
911 err_ahb_clk:
912 clk_disable_unprepare(port->sys_ck);
913 err_sys_clk:
914 mtk_pcie_port_free(port);
915 }
916
mtk_pcie_parse_port(struct mtk_pcie * pcie,struct device_node * node,int slot)917 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
918 struct device_node *node,
919 int slot)
920 {
921 struct mtk_pcie_port *port;
922 struct device *dev = pcie->dev;
923 struct platform_device *pdev = to_platform_device(dev);
924 char name[10];
925 int err;
926
927 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
928 if (!port)
929 return -ENOMEM;
930
931 snprintf(name, sizeof(name), "port%d", slot);
932 port->base = devm_platform_ioremap_resource_byname(pdev, name);
933 if (IS_ERR(port->base)) {
934 dev_err(dev, "failed to map port%d base\n", slot);
935 return PTR_ERR(port->base);
936 }
937
938 snprintf(name, sizeof(name), "sys_ck%d", slot);
939 port->sys_ck = devm_clk_get(dev, name);
940 if (IS_ERR(port->sys_ck)) {
941 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
942 return PTR_ERR(port->sys_ck);
943 }
944
945 /* sys_ck might be divided into the following parts in some chips */
946 snprintf(name, sizeof(name), "ahb_ck%d", slot);
947 port->ahb_ck = devm_clk_get_optional(dev, name);
948 if (IS_ERR(port->ahb_ck))
949 return PTR_ERR(port->ahb_ck);
950
951 snprintf(name, sizeof(name), "axi_ck%d", slot);
952 port->axi_ck = devm_clk_get_optional(dev, name);
953 if (IS_ERR(port->axi_ck))
954 return PTR_ERR(port->axi_ck);
955
956 snprintf(name, sizeof(name), "aux_ck%d", slot);
957 port->aux_ck = devm_clk_get_optional(dev, name);
958 if (IS_ERR(port->aux_ck))
959 return PTR_ERR(port->aux_ck);
960
961 snprintf(name, sizeof(name), "obff_ck%d", slot);
962 port->obff_ck = devm_clk_get_optional(dev, name);
963 if (IS_ERR(port->obff_ck))
964 return PTR_ERR(port->obff_ck);
965
966 snprintf(name, sizeof(name), "pipe_ck%d", slot);
967 port->pipe_ck = devm_clk_get_optional(dev, name);
968 if (IS_ERR(port->pipe_ck))
969 return PTR_ERR(port->pipe_ck);
970
971 snprintf(name, sizeof(name), "pcie-rst%d", slot);
972 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
973 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
974 return PTR_ERR(port->reset);
975
976 /* some platforms may use default PHY setting */
977 snprintf(name, sizeof(name), "pcie-phy%d", slot);
978 port->phy = devm_phy_optional_get(dev, name);
979 if (IS_ERR(port->phy))
980 return PTR_ERR(port->phy);
981
982 port->slot = slot;
983 port->pcie = pcie;
984
985 if (pcie->soc->setup_irq) {
986 err = pcie->soc->setup_irq(port, node);
987 if (err)
988 return err;
989 }
990
991 INIT_LIST_HEAD(&port->list);
992 list_add_tail(&port->list, &pcie->ports);
993
994 return 0;
995 }
996
mtk_pcie_subsys_powerup(struct mtk_pcie * pcie)997 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
998 {
999 struct device *dev = pcie->dev;
1000 struct platform_device *pdev = to_platform_device(dev);
1001 struct resource *regs;
1002 struct device_node *cfg_node;
1003 int err;
1004
1005 /* get shared registers, which are optional */
1006 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
1007 if (regs) {
1008 pcie->base = devm_ioremap_resource(dev, regs);
1009 if (IS_ERR(pcie->base))
1010 return PTR_ERR(pcie->base);
1011 }
1012
1013 cfg_node = of_find_compatible_node(NULL, NULL,
1014 "mediatek,generic-pciecfg");
1015 if (cfg_node) {
1016 pcie->cfg = syscon_node_to_regmap(cfg_node);
1017 of_node_put(cfg_node);
1018 if (IS_ERR(pcie->cfg))
1019 return PTR_ERR(pcie->cfg);
1020 }
1021
1022 pcie->free_ck = devm_clk_get(dev, "free_ck");
1023 if (IS_ERR(pcie->free_ck)) {
1024 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
1025 return -EPROBE_DEFER;
1026
1027 pcie->free_ck = NULL;
1028 }
1029
1030 pm_runtime_enable(dev);
1031 pm_runtime_get_sync(dev);
1032
1033 /* enable top level clock */
1034 err = clk_prepare_enable(pcie->free_ck);
1035 if (err) {
1036 dev_err(dev, "failed to enable free_ck\n");
1037 goto err_free_ck;
1038 }
1039
1040 return 0;
1041
1042 err_free_ck:
1043 pm_runtime_put_sync(dev);
1044 pm_runtime_disable(dev);
1045
1046 return err;
1047 }
1048
mtk_pcie_setup(struct mtk_pcie * pcie)1049 static int mtk_pcie_setup(struct mtk_pcie *pcie)
1050 {
1051 struct device *dev = pcie->dev;
1052 struct device_node *node = dev->of_node, *child;
1053 struct mtk_pcie_port *port, *tmp;
1054 int err, slot;
1055
1056 slot = of_get_pci_domain_nr(dev->of_node);
1057 if (slot < 0) {
1058 for_each_available_child_of_node(node, child) {
1059 err = of_pci_get_devfn(child);
1060 if (err < 0) {
1061 dev_err(dev, "failed to get devfn: %d\n", err);
1062 goto error_put_node;
1063 }
1064
1065 slot = PCI_SLOT(err);
1066
1067 err = mtk_pcie_parse_port(pcie, child, slot);
1068 if (err)
1069 goto error_put_node;
1070 }
1071 } else {
1072 err = mtk_pcie_parse_port(pcie, node, slot);
1073 if (err)
1074 return err;
1075 }
1076
1077 err = mtk_pcie_subsys_powerup(pcie);
1078 if (err)
1079 return err;
1080
1081 /* enable each port, and then check link status */
1082 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1083 mtk_pcie_enable_port(port);
1084
1085 /* power down PCIe subsys if slots are all empty (link down) */
1086 if (list_empty(&pcie->ports))
1087 mtk_pcie_subsys_powerdown(pcie);
1088
1089 return 0;
1090 error_put_node:
1091 of_node_put(child);
1092 return err;
1093 }
1094
mtk_pcie_probe(struct platform_device * pdev)1095 static int mtk_pcie_probe(struct platform_device *pdev)
1096 {
1097 struct device *dev = &pdev->dev;
1098 struct mtk_pcie *pcie;
1099 struct pci_host_bridge *host;
1100 int err;
1101
1102 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1103 if (!host)
1104 return -ENOMEM;
1105
1106 pcie = pci_host_bridge_priv(host);
1107
1108 pcie->dev = dev;
1109 pcie->soc = of_device_get_match_data(dev);
1110 platform_set_drvdata(pdev, pcie);
1111 INIT_LIST_HEAD(&pcie->ports);
1112
1113 err = mtk_pcie_setup(pcie);
1114 if (err)
1115 return err;
1116
1117 host->ops = pcie->soc->ops;
1118 host->sysdata = pcie;
1119 host->msi_domain = pcie->soc->no_msi;
1120
1121 err = pci_host_probe(host);
1122 if (err)
1123 goto put_resources;
1124
1125 return 0;
1126
1127 put_resources:
1128 if (!list_empty(&pcie->ports))
1129 mtk_pcie_put_resources(pcie);
1130
1131 return err;
1132 }
1133
1134
mtk_pcie_free_resources(struct mtk_pcie * pcie)1135 static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1136 {
1137 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1138 struct list_head *windows = &host->windows;
1139
1140 pci_free_resource_list(windows);
1141 }
1142
mtk_pcie_remove(struct platform_device * pdev)1143 static int mtk_pcie_remove(struct platform_device *pdev)
1144 {
1145 struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1146 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1147
1148 pci_stop_root_bus(host->bus);
1149 pci_remove_root_bus(host->bus);
1150 mtk_pcie_free_resources(pcie);
1151
1152 mtk_pcie_irq_teardown(pcie);
1153
1154 mtk_pcie_put_resources(pcie);
1155
1156 return 0;
1157 }
1158
mtk_pcie_suspend_noirq(struct device * dev)1159 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
1160 {
1161 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1162 struct mtk_pcie_port *port;
1163
1164 if (list_empty(&pcie->ports))
1165 return 0;
1166
1167 list_for_each_entry(port, &pcie->ports, list) {
1168 clk_disable_unprepare(port->pipe_ck);
1169 clk_disable_unprepare(port->obff_ck);
1170 clk_disable_unprepare(port->axi_ck);
1171 clk_disable_unprepare(port->aux_ck);
1172 clk_disable_unprepare(port->ahb_ck);
1173 clk_disable_unprepare(port->sys_ck);
1174 phy_power_off(port->phy);
1175 phy_exit(port->phy);
1176 }
1177
1178 clk_disable_unprepare(pcie->free_ck);
1179
1180 return 0;
1181 }
1182
mtk_pcie_resume_noirq(struct device * dev)1183 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
1184 {
1185 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1186 struct mtk_pcie_port *port, *tmp;
1187
1188 if (list_empty(&pcie->ports))
1189 return 0;
1190
1191 clk_prepare_enable(pcie->free_ck);
1192
1193 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1194 mtk_pcie_enable_port(port);
1195
1196 /* In case of EP was removed while system suspend. */
1197 if (list_empty(&pcie->ports))
1198 clk_disable_unprepare(pcie->free_ck);
1199
1200 return 0;
1201 }
1202
1203 static const struct dev_pm_ops mtk_pcie_pm_ops = {
1204 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1205 mtk_pcie_resume_noirq)
1206 };
1207
1208 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1209 .no_msi = true,
1210 .ops = &mtk_pcie_ops,
1211 .startup = mtk_pcie_startup_port,
1212 };
1213
1214 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1215 .ops = &mtk_pcie_ops_v2,
1216 .startup = mtk_pcie_startup_port_v2,
1217 .setup_irq = mtk_pcie_setup_irq,
1218 };
1219
1220 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1221 .need_fix_class_id = true,
1222 .ops = &mtk_pcie_ops_v2,
1223 .startup = mtk_pcie_startup_port_v2,
1224 .setup_irq = mtk_pcie_setup_irq,
1225 };
1226
1227 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1228 .need_fix_class_id = true,
1229 .need_fix_device_id = true,
1230 .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1231 .ops = &mtk_pcie_ops_v2,
1232 .startup = mtk_pcie_startup_port_v2,
1233 .setup_irq = mtk_pcie_setup_irq,
1234 };
1235
1236 static const struct of_device_id mtk_pcie_ids[] = {
1237 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1238 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1239 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1240 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1241 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1242 {},
1243 };
1244 MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
1245
1246 static struct platform_driver mtk_pcie_driver = {
1247 .probe = mtk_pcie_probe,
1248 .remove = mtk_pcie_remove,
1249 .driver = {
1250 .name = "mtk-pcie",
1251 .of_match_table = mtk_pcie_ids,
1252 .suppress_bind_attrs = true,
1253 .pm = &mtk_pcie_pm_ops,
1254 },
1255 };
1256 module_platform_driver(mtk_pcie_driver);
1257 MODULE_LICENSE("GPL v2");
1258