1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2017 NXP
4 * Copyright 2016 Freescale Semiconductor, Inc.
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_irq.h>
16 #include <linux/perf_event.h>
17 #include <linux/slab.h>
18
19 #define COUNTER_CNTL 0x0
20 #define COUNTER_READ 0x20
21
22 #define COUNTER_DPCR1 0x30
23
24 #define CNTL_OVER 0x1
25 #define CNTL_CLEAR 0x2
26 #define CNTL_EN 0x4
27 #define CNTL_EN_MASK 0xFFFFFFFB
28 #define CNTL_CLEAR_MASK 0xFFFFFFFD
29 #define CNTL_OVER_MASK 0xFFFFFFFE
30
31 #define CNTL_CP_SHIFT 16
32 #define CNTL_CP_MASK (0xFF << CNTL_CP_SHIFT)
33 #define CNTL_CSV_SHIFT 24
34 #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT)
35
36 #define EVENT_CYCLES_ID 0
37 #define EVENT_CYCLES_COUNTER 0
38 #define NUM_COUNTERS 4
39
40 /* For removing bias if cycle counter CNTL.CP is set to 0xf0 */
41 #define CYCLES_COUNTER_MASK 0x0FFFFFFF
42 #define AXI_MASKING_REVERT 0xffff0000 /* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */
43
44 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
45
46 #define DDR_PERF_DEV_NAME "imx8_ddr"
47 #define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu"
48
49 static DEFINE_IDA(ddr_ida);
50
51 /* DDR Perf hardware feature */
52 #define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */
53 #define DDR_CAP_AXI_ID_FILTER_ENHANCED 0x3 /* support enhanced AXI ID filter */
54
55 struct fsl_ddr_devtype_data {
56 unsigned int quirks; /* quirks needed for different DDR Perf core */
57 const char *identifier; /* system PMU identifier for userspace */
58 };
59
60 static const struct fsl_ddr_devtype_data imx8_devtype_data;
61
62 static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
63 .quirks = DDR_CAP_AXI_ID_FILTER,
64 };
65
66 static const struct fsl_ddr_devtype_data imx8mq_devtype_data = {
67 .quirks = DDR_CAP_AXI_ID_FILTER,
68 .identifier = "i.MX8MQ",
69 };
70
71 static const struct fsl_ddr_devtype_data imx8mm_devtype_data = {
72 .quirks = DDR_CAP_AXI_ID_FILTER,
73 .identifier = "i.MX8MM",
74 };
75
76 static const struct fsl_ddr_devtype_data imx8mn_devtype_data = {
77 .quirks = DDR_CAP_AXI_ID_FILTER,
78 .identifier = "i.MX8MN",
79 };
80
81 static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {
82 .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,
83 .identifier = "i.MX8MP",
84 };
85
86 static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
87 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
88 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
89 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
90 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
91 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
92 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
93 { /* sentinel */ }
94 };
95 MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
96
97 struct ddr_pmu {
98 struct pmu pmu;
99 void __iomem *base;
100 unsigned int cpu;
101 struct hlist_node node;
102 struct device *dev;
103 struct perf_event *events[NUM_COUNTERS];
104 int active_events;
105 enum cpuhp_state cpuhp_state;
106 const struct fsl_ddr_devtype_data *devtype_data;
107 int irq;
108 int id;
109 int active_counter;
110 };
111
ddr_perf_identifier_show(struct device * dev,struct device_attribute * attr,char * page)112 static ssize_t ddr_perf_identifier_show(struct device *dev,
113 struct device_attribute *attr,
114 char *page)
115 {
116 struct ddr_pmu *pmu = dev_get_drvdata(dev);
117
118 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier);
119 }
120
ddr_perf_identifier_attr_visible(struct kobject * kobj,struct attribute * attr,int n)121 static umode_t ddr_perf_identifier_attr_visible(struct kobject *kobj,
122 struct attribute *attr,
123 int n)
124 {
125 struct device *dev = kobj_to_dev(kobj);
126 struct ddr_pmu *pmu = dev_get_drvdata(dev);
127
128 if (!pmu->devtype_data->identifier)
129 return 0;
130 return attr->mode;
131 };
132
133 static struct device_attribute ddr_perf_identifier_attr =
134 __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
135
136 static struct attribute *ddr_perf_identifier_attrs[] = {
137 &ddr_perf_identifier_attr.attr,
138 NULL,
139 };
140
141 static const struct attribute_group ddr_perf_identifier_attr_group = {
142 .attrs = ddr_perf_identifier_attrs,
143 .is_visible = ddr_perf_identifier_attr_visible,
144 };
145
146 enum ddr_perf_filter_capabilities {
147 PERF_CAP_AXI_ID_FILTER = 0,
148 PERF_CAP_AXI_ID_FILTER_ENHANCED,
149 PERF_CAP_AXI_ID_FEAT_MAX,
150 };
151
ddr_perf_filter_cap_get(struct ddr_pmu * pmu,int cap)152 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap)
153 {
154 u32 quirks = pmu->devtype_data->quirks;
155
156 switch (cap) {
157 case PERF_CAP_AXI_ID_FILTER:
158 return !!(quirks & DDR_CAP_AXI_ID_FILTER);
159 case PERF_CAP_AXI_ID_FILTER_ENHANCED:
160 quirks &= DDR_CAP_AXI_ID_FILTER_ENHANCED;
161 return quirks == DDR_CAP_AXI_ID_FILTER_ENHANCED;
162 default:
163 WARN(1, "unknown filter cap %d\n", cap);
164 }
165
166 return 0;
167 }
168
ddr_perf_filter_cap_show(struct device * dev,struct device_attribute * attr,char * buf)169 static ssize_t ddr_perf_filter_cap_show(struct device *dev,
170 struct device_attribute *attr,
171 char *buf)
172 {
173 struct ddr_pmu *pmu = dev_get_drvdata(dev);
174 struct dev_ext_attribute *ea =
175 container_of(attr, struct dev_ext_attribute, attr);
176 int cap = (long)ea->var;
177
178 return sysfs_emit(buf, "%u\n", ddr_perf_filter_cap_get(pmu, cap));
179 }
180
181 #define PERF_EXT_ATTR_ENTRY(_name, _func, _var) \
182 (&((struct dev_ext_attribute) { \
183 __ATTR(_name, 0444, _func, NULL), (void *)_var \
184 }).attr.attr)
185
186 #define PERF_FILTER_EXT_ATTR_ENTRY(_name, _var) \
187 PERF_EXT_ATTR_ENTRY(_name, ddr_perf_filter_cap_show, _var)
188
189 static struct attribute *ddr_perf_filter_cap_attr[] = {
190 PERF_FILTER_EXT_ATTR_ENTRY(filter, PERF_CAP_AXI_ID_FILTER),
191 PERF_FILTER_EXT_ATTR_ENTRY(enhanced_filter, PERF_CAP_AXI_ID_FILTER_ENHANCED),
192 NULL,
193 };
194
195 static const struct attribute_group ddr_perf_filter_cap_attr_group = {
196 .name = "caps",
197 .attrs = ddr_perf_filter_cap_attr,
198 };
199
ddr_perf_cpumask_show(struct device * dev,struct device_attribute * attr,char * buf)200 static ssize_t ddr_perf_cpumask_show(struct device *dev,
201 struct device_attribute *attr, char *buf)
202 {
203 struct ddr_pmu *pmu = dev_get_drvdata(dev);
204
205 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
206 }
207
208 static struct device_attribute ddr_perf_cpumask_attr =
209 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
210
211 static struct attribute *ddr_perf_cpumask_attrs[] = {
212 &ddr_perf_cpumask_attr.attr,
213 NULL,
214 };
215
216 static const struct attribute_group ddr_perf_cpumask_attr_group = {
217 .attrs = ddr_perf_cpumask_attrs,
218 };
219
220 static ssize_t
ddr_pmu_event_show(struct device * dev,struct device_attribute * attr,char * page)221 ddr_pmu_event_show(struct device *dev, struct device_attribute *attr,
222 char *page)
223 {
224 struct perf_pmu_events_attr *pmu_attr;
225
226 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
227 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
228 }
229
230 #define IMX8_DDR_PMU_EVENT_ATTR(_name, _id) \
231 PMU_EVENT_ATTR_ID(_name, ddr_pmu_event_show, _id)
232
233 static struct attribute *ddr_perf_events_attrs[] = {
234 IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID),
235 IMX8_DDR_PMU_EVENT_ATTR(selfresh, 0x01),
236 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),
237 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),
238 IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08),
239 IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09),
240 IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10),
241 IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11),
242 IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12),
243 IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20),
244 IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21),
245 IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22),
246 IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23),
247 IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24),
248 IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25),
249 IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26),
250 IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27),
251 IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29),
252 IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a),
253 IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b),
254 IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30),
255 IMX8_DDR_PMU_EVENT_ATTR(precharge, 0x31),
256 IMX8_DDR_PMU_EVENT_ATTR(activate, 0x32),
257 IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33),
258 IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34),
259 IMX8_DDR_PMU_EVENT_ATTR(read, 0x35),
260 IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36),
261 IMX8_DDR_PMU_EVENT_ATTR(refresh, 0x37),
262 IMX8_DDR_PMU_EVENT_ATTR(write, 0x38),
263 IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39),
264 IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41),
265 IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42),
266 NULL,
267 };
268
269 static const struct attribute_group ddr_perf_events_attr_group = {
270 .name = "events",
271 .attrs = ddr_perf_events_attrs,
272 };
273
274 PMU_FORMAT_ATTR(event, "config:0-7");
275 PMU_FORMAT_ATTR(axi_id, "config1:0-15");
276 PMU_FORMAT_ATTR(axi_mask, "config1:16-31");
277
278 static struct attribute *ddr_perf_format_attrs[] = {
279 &format_attr_event.attr,
280 &format_attr_axi_id.attr,
281 &format_attr_axi_mask.attr,
282 NULL,
283 };
284
285 static const struct attribute_group ddr_perf_format_attr_group = {
286 .name = "format",
287 .attrs = ddr_perf_format_attrs,
288 };
289
290 static const struct attribute_group *attr_groups[] = {
291 &ddr_perf_events_attr_group,
292 &ddr_perf_format_attr_group,
293 &ddr_perf_cpumask_attr_group,
294 &ddr_perf_filter_cap_attr_group,
295 &ddr_perf_identifier_attr_group,
296 NULL,
297 };
298
ddr_perf_is_filtered(struct perf_event * event)299 static bool ddr_perf_is_filtered(struct perf_event *event)
300 {
301 return event->attr.config == 0x41 || event->attr.config == 0x42;
302 }
303
ddr_perf_filter_val(struct perf_event * event)304 static u32 ddr_perf_filter_val(struct perf_event *event)
305 {
306 return event->attr.config1;
307 }
308
ddr_perf_filters_compatible(struct perf_event * a,struct perf_event * b)309 static bool ddr_perf_filters_compatible(struct perf_event *a,
310 struct perf_event *b)
311 {
312 if (!ddr_perf_is_filtered(a))
313 return true;
314 if (!ddr_perf_is_filtered(b))
315 return true;
316 return ddr_perf_filter_val(a) == ddr_perf_filter_val(b);
317 }
318
ddr_perf_is_enhanced_filtered(struct perf_event * event)319 static bool ddr_perf_is_enhanced_filtered(struct perf_event *event)
320 {
321 unsigned int filt;
322 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
323
324 filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED;
325 return (filt == DDR_CAP_AXI_ID_FILTER_ENHANCED) &&
326 ddr_perf_is_filtered(event);
327 }
328
ddr_perf_alloc_counter(struct ddr_pmu * pmu,int event)329 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event)
330 {
331 int i;
332
333 /*
334 * Always map cycle event to counter 0
335 * Cycles counter is dedicated for cycle event
336 * can't used for the other events
337 */
338 if (event == EVENT_CYCLES_ID) {
339 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL)
340 return EVENT_CYCLES_COUNTER;
341 else
342 return -ENOENT;
343 }
344
345 for (i = 1; i < NUM_COUNTERS; i++) {
346 if (pmu->events[i] == NULL)
347 return i;
348 }
349
350 return -ENOENT;
351 }
352
ddr_perf_free_counter(struct ddr_pmu * pmu,int counter)353 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)
354 {
355 pmu->events[counter] = NULL;
356 }
357
ddr_perf_read_counter(struct ddr_pmu * pmu,int counter)358 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
359 {
360 struct perf_event *event = pmu->events[counter];
361 void __iomem *base = pmu->base;
362
363 /*
364 * return bytes instead of bursts from ddr transaction for
365 * axid-read and axid-write event if PMU core supports enhanced
366 * filter.
367 */
368 base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 :
369 COUNTER_READ;
370 return readl_relaxed(base + counter * 4);
371 }
372
ddr_perf_event_init(struct perf_event * event)373 static int ddr_perf_event_init(struct perf_event *event)
374 {
375 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
376 struct hw_perf_event *hwc = &event->hw;
377 struct perf_event *sibling;
378
379 if (event->attr.type != event->pmu->type)
380 return -ENOENT;
381
382 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
383 return -EOPNOTSUPP;
384
385 if (event->cpu < 0) {
386 dev_warn(pmu->dev, "Can't provide per-task data!\n");
387 return -EOPNOTSUPP;
388 }
389
390 /*
391 * We must NOT create groups containing mixed PMUs, although software
392 * events are acceptable (for example to create a CCN group
393 * periodically read when a hrtimer aka cpu-clock leader triggers).
394 */
395 if (event->group_leader->pmu != event->pmu &&
396 !is_software_event(event->group_leader))
397 return -EINVAL;
398
399 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
400 if (!ddr_perf_filters_compatible(event, event->group_leader))
401 return -EINVAL;
402 for_each_sibling_event(sibling, event->group_leader) {
403 if (!ddr_perf_filters_compatible(event, sibling))
404 return -EINVAL;
405 }
406 }
407
408 for_each_sibling_event(sibling, event->group_leader) {
409 if (sibling->pmu != event->pmu &&
410 !is_software_event(sibling))
411 return -EINVAL;
412 }
413
414 event->cpu = pmu->cpu;
415 hwc->idx = -1;
416
417 return 0;
418 }
419
ddr_perf_counter_enable(struct ddr_pmu * pmu,int config,int counter,bool enable)420 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
421 int counter, bool enable)
422 {
423 u8 reg = counter * 4 + COUNTER_CNTL;
424 int val;
425
426 if (enable) {
427 /*
428 * cycle counter is special which should firstly write 0 then
429 * write 1 into CLEAR bit to clear it. Other counters only
430 * need write 0 into CLEAR bit and it turns out to be 1 by
431 * hardware. Below enable flow is harmless for all counters.
432 */
433 writel(0, pmu->base + reg);
434 val = CNTL_EN | CNTL_CLEAR;
435 val |= FIELD_PREP(CNTL_CSV_MASK, config);
436
437 /*
438 * On i.MX8MP we need to bias the cycle counter to overflow more often.
439 * We do this by initializing bits [23:16] of the counter value via the
440 * COUNTER_CTRL Counter Parameter (CP) field.
441 */
442 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
443 if (counter == EVENT_CYCLES_COUNTER)
444 val |= FIELD_PREP(CNTL_CP_MASK, 0xf0);
445 }
446
447 writel(val, pmu->base + reg);
448 } else {
449 /* Disable counter */
450 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK;
451 writel(val, pmu->base + reg);
452 }
453 }
454
ddr_perf_counter_overflow(struct ddr_pmu * pmu,int counter)455 static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter)
456 {
457 int val;
458
459 val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL);
460
461 return val & CNTL_OVER;
462 }
463
ddr_perf_counter_clear(struct ddr_pmu * pmu,int counter)464 static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter)
465 {
466 u8 reg = counter * 4 + COUNTER_CNTL;
467 int val;
468
469 val = readl_relaxed(pmu->base + reg);
470 val &= ~CNTL_CLEAR;
471 writel(val, pmu->base + reg);
472
473 val |= CNTL_CLEAR;
474 writel(val, pmu->base + reg);
475 }
476
ddr_perf_event_update(struct perf_event * event)477 static void ddr_perf_event_update(struct perf_event *event)
478 {
479 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
480 struct hw_perf_event *hwc = &event->hw;
481 u64 new_raw_count;
482 int counter = hwc->idx;
483 int ret;
484
485 new_raw_count = ddr_perf_read_counter(pmu, counter);
486 /* Remove the bias applied in ddr_perf_counter_enable(). */
487 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
488 if (counter == EVENT_CYCLES_COUNTER)
489 new_raw_count &= CYCLES_COUNTER_MASK;
490 }
491
492 local64_add(new_raw_count, &event->count);
493
494 /*
495 * For legacy SoCs: event counter continue counting when overflow,
496 * no need to clear the counter.
497 * For new SoCs: event counter stop counting when overflow, need
498 * clear counter to let it count again.
499 */
500 if (counter != EVENT_CYCLES_COUNTER) {
501 ret = ddr_perf_counter_overflow(pmu, counter);
502 if (ret)
503 dev_warn_ratelimited(pmu->dev, "events lost due to counter overflow (config 0x%llx)\n",
504 event->attr.config);
505 }
506
507 /* clear counter every time for both cycle counter and event counter */
508 ddr_perf_counter_clear(pmu, counter);
509 }
510
ddr_perf_event_start(struct perf_event * event,int flags)511 static void ddr_perf_event_start(struct perf_event *event, int flags)
512 {
513 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
514 struct hw_perf_event *hwc = &event->hw;
515 int counter = hwc->idx;
516
517 local64_set(&hwc->prev_count, 0);
518
519 ddr_perf_counter_enable(pmu, event->attr.config, counter, true);
520
521 if (!pmu->active_counter++)
522 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID,
523 EVENT_CYCLES_COUNTER, true);
524
525 hwc->state = 0;
526 }
527
ddr_perf_event_add(struct perf_event * event,int flags)528 static int ddr_perf_event_add(struct perf_event *event, int flags)
529 {
530 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
531 struct hw_perf_event *hwc = &event->hw;
532 int counter;
533 int cfg = event->attr.config;
534 int cfg1 = event->attr.config1;
535
536 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
537 int i;
538
539 for (i = 1; i < NUM_COUNTERS; i++) {
540 if (pmu->events[i] &&
541 !ddr_perf_filters_compatible(event, pmu->events[i]))
542 return -EINVAL;
543 }
544
545 if (ddr_perf_is_filtered(event)) {
546 /* revert axi id masking(axi_mask) value */
547 cfg1 ^= AXI_MASKING_REVERT;
548 writel(cfg1, pmu->base + COUNTER_DPCR1);
549 }
550 }
551
552 counter = ddr_perf_alloc_counter(pmu, cfg);
553 if (counter < 0) {
554 dev_dbg(pmu->dev, "There are not enough counters\n");
555 return -EOPNOTSUPP;
556 }
557
558 pmu->events[counter] = event;
559 pmu->active_events++;
560 hwc->idx = counter;
561
562 hwc->state |= PERF_HES_STOPPED;
563
564 if (flags & PERF_EF_START)
565 ddr_perf_event_start(event, flags);
566
567 return 0;
568 }
569
ddr_perf_event_stop(struct perf_event * event,int flags)570 static void ddr_perf_event_stop(struct perf_event *event, int flags)
571 {
572 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
573 struct hw_perf_event *hwc = &event->hw;
574 int counter = hwc->idx;
575
576 ddr_perf_counter_enable(pmu, event->attr.config, counter, false);
577 ddr_perf_event_update(event);
578
579 if (!--pmu->active_counter)
580 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID,
581 EVENT_CYCLES_COUNTER, false);
582
583 hwc->state |= PERF_HES_STOPPED;
584 }
585
ddr_perf_event_del(struct perf_event * event,int flags)586 static void ddr_perf_event_del(struct perf_event *event, int flags)
587 {
588 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
589 struct hw_perf_event *hwc = &event->hw;
590 int counter = hwc->idx;
591
592 ddr_perf_event_stop(event, PERF_EF_UPDATE);
593
594 ddr_perf_free_counter(pmu, counter);
595 pmu->active_events--;
596 hwc->idx = -1;
597 }
598
ddr_perf_pmu_enable(struct pmu * pmu)599 static void ddr_perf_pmu_enable(struct pmu *pmu)
600 {
601 }
602
ddr_perf_pmu_disable(struct pmu * pmu)603 static void ddr_perf_pmu_disable(struct pmu *pmu)
604 {
605 }
606
ddr_perf_init(struct ddr_pmu * pmu,void __iomem * base,struct device * dev)607 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
608 struct device *dev)
609 {
610 *pmu = (struct ddr_pmu) {
611 .pmu = (struct pmu) {
612 .module = THIS_MODULE,
613 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
614 .task_ctx_nr = perf_invalid_context,
615 .attr_groups = attr_groups,
616 .event_init = ddr_perf_event_init,
617 .add = ddr_perf_event_add,
618 .del = ddr_perf_event_del,
619 .start = ddr_perf_event_start,
620 .stop = ddr_perf_event_stop,
621 .read = ddr_perf_event_update,
622 .pmu_enable = ddr_perf_pmu_enable,
623 .pmu_disable = ddr_perf_pmu_disable,
624 },
625 .base = base,
626 .dev = dev,
627 };
628
629 pmu->id = ida_simple_get(&ddr_ida, 0, 0, GFP_KERNEL);
630 return pmu->id;
631 }
632
ddr_perf_irq_handler(int irq,void * p)633 static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
634 {
635 int i;
636 struct ddr_pmu *pmu = (struct ddr_pmu *) p;
637 struct perf_event *event;
638
639 /* all counter will stop if cycle counter disabled */
640 ddr_perf_counter_enable(pmu,
641 EVENT_CYCLES_ID,
642 EVENT_CYCLES_COUNTER,
643 false);
644 /*
645 * When the cycle counter overflows, all counters are stopped,
646 * and an IRQ is raised. If any other counter overflows, it
647 * continues counting, and no IRQ is raised. But for new SoCs,
648 * such as i.MX8MP, event counter would stop when overflow, so
649 * we need use cycle counter to stop overflow of event counter.
650 *
651 * Cycles occur at least 4 times as often as other events, so we
652 * can update all events on a cycle counter overflow and not
653 * lose events.
654 *
655 */
656 for (i = 0; i < NUM_COUNTERS; i++) {
657
658 if (!pmu->events[i])
659 continue;
660
661 event = pmu->events[i];
662
663 ddr_perf_event_update(event);
664 }
665
666 ddr_perf_counter_enable(pmu,
667 EVENT_CYCLES_ID,
668 EVENT_CYCLES_COUNTER,
669 true);
670
671 return IRQ_HANDLED;
672 }
673
ddr_perf_offline_cpu(unsigned int cpu,struct hlist_node * node)674 static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
675 {
676 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
677 int target;
678
679 if (cpu != pmu->cpu)
680 return 0;
681
682 target = cpumask_any_but(cpu_online_mask, cpu);
683 if (target >= nr_cpu_ids)
684 return 0;
685
686 perf_pmu_migrate_context(&pmu->pmu, cpu, target);
687 pmu->cpu = target;
688
689 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)));
690
691 return 0;
692 }
693
ddr_perf_probe(struct platform_device * pdev)694 static int ddr_perf_probe(struct platform_device *pdev)
695 {
696 struct ddr_pmu *pmu;
697 struct device_node *np;
698 void __iomem *base;
699 char *name;
700 int num;
701 int ret;
702 int irq;
703
704 base = devm_platform_ioremap_resource(pdev, 0);
705 if (IS_ERR(base))
706 return PTR_ERR(base);
707
708 np = pdev->dev.of_node;
709
710 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
711 if (!pmu)
712 return -ENOMEM;
713
714 num = ddr_perf_init(pmu, base, &pdev->dev);
715
716 platform_set_drvdata(pdev, pmu);
717
718 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d",
719 num);
720 if (!name) {
721 ret = -ENOMEM;
722 goto cpuhp_state_err;
723 }
724
725 pmu->devtype_data = of_device_get_match_data(&pdev->dev);
726
727 pmu->cpu = raw_smp_processor_id();
728 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
729 DDR_CPUHP_CB_NAME,
730 NULL,
731 ddr_perf_offline_cpu);
732
733 if (ret < 0) {
734 dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n");
735 goto cpuhp_state_err;
736 }
737
738 pmu->cpuhp_state = ret;
739
740 /* Register the pmu instance for cpu hotplug */
741 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
742 if (ret) {
743 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
744 goto cpuhp_instance_err;
745 }
746
747 /* Request irq */
748 irq = of_irq_get(np, 0);
749 if (irq < 0) {
750 dev_err(&pdev->dev, "Failed to get irq: %d", irq);
751 ret = irq;
752 goto ddr_perf_err;
753 }
754
755 ret = devm_request_irq(&pdev->dev, irq,
756 ddr_perf_irq_handler,
757 IRQF_NOBALANCING | IRQF_NO_THREAD,
758 DDR_CPUHP_CB_NAME,
759 pmu);
760 if (ret < 0) {
761 dev_err(&pdev->dev, "Request irq failed: %d", ret);
762 goto ddr_perf_err;
763 }
764
765 pmu->irq = irq;
766 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu));
767 if (ret) {
768 dev_err(pmu->dev, "Failed to set interrupt affinity!\n");
769 goto ddr_perf_err;
770 }
771
772 ret = perf_pmu_register(&pmu->pmu, name, -1);
773 if (ret)
774 goto ddr_perf_err;
775
776 return 0;
777
778 ddr_perf_err:
779 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
780 cpuhp_instance_err:
781 cpuhp_remove_multi_state(pmu->cpuhp_state);
782 cpuhp_state_err:
783 ida_simple_remove(&ddr_ida, pmu->id);
784 dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret);
785 return ret;
786 }
787
ddr_perf_remove(struct platform_device * pdev)788 static int ddr_perf_remove(struct platform_device *pdev)
789 {
790 struct ddr_pmu *pmu = platform_get_drvdata(pdev);
791
792 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
793 cpuhp_remove_multi_state(pmu->cpuhp_state);
794
795 perf_pmu_unregister(&pmu->pmu);
796
797 ida_simple_remove(&ddr_ida, pmu->id);
798 return 0;
799 }
800
801 static struct platform_driver imx_ddr_pmu_driver = {
802 .driver = {
803 .name = "imx-ddr-pmu",
804 .of_match_table = imx_ddr_pmu_dt_ids,
805 .suppress_bind_attrs = true,
806 },
807 .probe = ddr_perf_probe,
808 .remove = ddr_perf_remove,
809 };
810
811 module_platform_driver(imx_ddr_pmu_driver);
812 MODULE_LICENSE("GPL v2");
813