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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * UFS PHY driver data for Samsung EXYNOSAUTO v9 SoC
4  *
5  * Copyright (C) 2021 Samsung Electronics Co., Ltd.
6  */
7 
8 #include "phy-samsung-ufs.h"
9 
10 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL		0x728
11 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
12 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
13 
14 #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
15 	PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
16 
17 /* Calibration for phy initialization */
18 static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = {
19 	PHY_COMN_REG_CFG(0x023, 0x80, PWR_MODE_ANY),
20 	PHY_COMN_REG_CFG(0x01d, 0x10, PWR_MODE_ANY),
21 
22 	PHY_TRSV_REG_CFG_AUTOV9(0x044, 0xb5, PWR_MODE_ANY),
23 	PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x43, PWR_MODE_ANY),
24 	PHY_TRSV_REG_CFG_AUTOV9(0x05b, 0x20, PWR_MODE_ANY),
25 	PHY_TRSV_REG_CFG_AUTOV9(0x05e, 0xc0, PWR_MODE_ANY),
26 	PHY_TRSV_REG_CFG_AUTOV9(0x038, 0x12, PWR_MODE_ANY),
27 	PHY_TRSV_REG_CFG_AUTOV9(0x059, 0x58, PWR_MODE_ANY),
28 	PHY_TRSV_REG_CFG_AUTOV9(0x06c, 0x18, PWR_MODE_ANY),
29 	PHY_TRSV_REG_CFG_AUTOV9(0x06d, 0x02, PWR_MODE_ANY),
30 
31 	PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
32 	PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),
33 
34 	PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
35 	PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),
36 
37 	END_UFS_PHY_CFG,
38 };
39 
40 /* Calibration for HS mode series A/B */
41 static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
42 	PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
43 	PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
44 	PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),
45 
46 	PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
47 	PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
48 				PWR_MODE_HS_G3_SER_B),
49 	PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
50 
51 	END_UFS_PHY_CFG,
52 };
53 
54 static const struct samsung_ufs_phy_cfg *exynosautov9_ufs_phy_cfgs[CFG_TAG_MAX] = {
55 	[CFG_PRE_INIT]		= exynosautov9_pre_init_cfg,
56 	[CFG_PRE_PWR_HS]	= exynosautov9_pre_pwr_hs_cfg,
57 };
58 
59 const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
60 	.cfg = exynosautov9_ufs_phy_cfgs,
61 	.isol = {
62 		.offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL,
63 		.mask = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK,
64 		.en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
65 	},
66 	.has_symbol_clk = 0,
67 };
68