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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * STMicroelectronics STM32 USB PHY Controller driver
4  *
5  * Copyright (C) 2018 STMicroelectronics
6  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
7  */
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_platform.h>
16 #include <linux/phy/phy.h>
17 #include <linux/reset.h>
18 #include <linux/units.h>
19 
20 #define STM32_USBPHYC_PLL	0x0
21 #define STM32_USBPHYC_MISC	0x8
22 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
23 #define STM32_USBPHYC_VERSION	0x3F4
24 
25 /* STM32_USBPHYC_PLL bit fields */
26 #define PLLNDIV			GENMASK(6, 0)
27 #define PLLFRACIN		GENMASK(25, 10)
28 #define PLLEN			BIT(26)
29 #define PLLSTRB			BIT(27)
30 #define PLLSTRBYP		BIT(28)
31 #define PLLFRACCTL		BIT(29)
32 #define PLLDITHEN0		BIT(30)
33 #define PLLDITHEN1		BIT(31)
34 
35 /* STM32_USBPHYC_MISC bit fields */
36 #define SWITHOST		BIT(0)
37 
38 /* STM32_USBPHYC_MONITOR bit fields */
39 #define STM32_USBPHYC_MON_OUT	GENMASK(3, 0)
40 #define STM32_USBPHYC_MON_SEL	GENMASK(8, 4)
41 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
42 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
43 
44 /* STM32_USBPHYC_VERSION bit fields */
45 #define MINREV			GENMASK(3, 0)
46 #define MAJREV			GENMASK(7, 4)
47 
48 #define PLL_FVCO_MHZ		2880
49 #define PLL_INFF_MIN_RATE_HZ	19200000
50 #define PLL_INFF_MAX_RATE_HZ	38400000
51 
52 struct pll_params {
53 	u8 ndiv;
54 	u16 frac;
55 };
56 
57 struct stm32_usbphyc_phy {
58 	struct phy *phy;
59 	struct stm32_usbphyc *usbphyc;
60 	struct regulator *vbus;
61 	u32 index;
62 	bool active;
63 };
64 
65 struct stm32_usbphyc {
66 	struct device *dev;
67 	void __iomem *base;
68 	struct clk *clk;
69 	struct reset_control *rst;
70 	struct stm32_usbphyc_phy **phys;
71 	int nphys;
72 	struct regulator *vdda1v1;
73 	struct regulator *vdda1v8;
74 	atomic_t n_pll_cons;
75 	struct clk_hw clk48_hw;
76 	int switch_setup;
77 };
78 
stm32_usbphyc_set_bits(void __iomem * reg,u32 bits)79 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
80 {
81 	writel_relaxed(readl_relaxed(reg) | bits, reg);
82 }
83 
stm32_usbphyc_clr_bits(void __iomem * reg,u32 bits)84 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
85 {
86 	writel_relaxed(readl_relaxed(reg) & ~bits, reg);
87 }
88 
stm32_usbphyc_regulators_enable(struct stm32_usbphyc * usbphyc)89 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
90 {
91 	int ret;
92 
93 	ret = regulator_enable(usbphyc->vdda1v1);
94 	if (ret)
95 		return ret;
96 
97 	ret = regulator_enable(usbphyc->vdda1v8);
98 	if (ret)
99 		goto vdda1v1_disable;
100 
101 	return 0;
102 
103 vdda1v1_disable:
104 	regulator_disable(usbphyc->vdda1v1);
105 
106 	return ret;
107 }
108 
stm32_usbphyc_regulators_disable(struct stm32_usbphyc * usbphyc)109 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
110 {
111 	int ret;
112 
113 	ret = regulator_disable(usbphyc->vdda1v8);
114 	if (ret)
115 		return ret;
116 
117 	ret = regulator_disable(usbphyc->vdda1v1);
118 	if (ret)
119 		return ret;
120 
121 	return 0;
122 }
123 
stm32_usbphyc_get_pll_params(u32 clk_rate,struct pll_params * pll_params)124 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
125 					 struct pll_params *pll_params)
126 {
127 	unsigned long long fvco, ndiv, frac;
128 
129 	/*    _
130 	 *   | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
131 	 *   | FVCO = 2880MHz
132 	 *  <
133 	 *   | NDIV = integer part of input bits to set the LDF
134 	 *   |_FRACT = fractional part of input bits to set the LDF
135 	 *  =>	PLLNDIV = integer part of (FVCO / (INFF*2))
136 	 *  =>	PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
137 	 * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
138 	 */
139 	fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
140 
141 	ndiv = fvco;
142 	do_div(ndiv, (clk_rate * 2));
143 	pll_params->ndiv = (u8)ndiv;
144 
145 	frac = fvco * (1 << 16);
146 	do_div(frac, (clk_rate * 2));
147 	frac = frac - (ndiv * (1 << 16));
148 	pll_params->frac = (u16)frac;
149 }
150 
stm32_usbphyc_pll_init(struct stm32_usbphyc * usbphyc)151 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
152 {
153 	struct pll_params pll_params;
154 	u32 clk_rate = clk_get_rate(usbphyc->clk);
155 	u32 ndiv, frac;
156 	u32 usbphyc_pll;
157 
158 	if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
159 	    (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
160 		dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
161 			clk_rate);
162 		return -EINVAL;
163 	}
164 
165 	stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
166 	ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
167 	frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
168 
169 	usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
170 
171 	if (pll_params.frac)
172 		usbphyc_pll |= PLLFRACCTL | frac;
173 
174 	writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
175 
176 	dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
177 		clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
178 		FIELD_GET(PLLFRACIN, usbphyc_pll));
179 
180 	return 0;
181 }
182 
__stm32_usbphyc_pll_disable(struct stm32_usbphyc * usbphyc)183 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
184 {
185 	void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
186 	u32 pllen;
187 
188 	stm32_usbphyc_clr_bits(pll_reg, PLLEN);
189 
190 	/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
191 	if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
192 		dev_err(usbphyc->dev, "PLL not reset\n");
193 
194 	return stm32_usbphyc_regulators_disable(usbphyc);
195 }
196 
stm32_usbphyc_pll_disable(struct stm32_usbphyc * usbphyc)197 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
198 {
199 	/* Check if a phy port is still active or clk48 in use */
200 	if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
201 		return 0;
202 
203 	return __stm32_usbphyc_pll_disable(usbphyc);
204 }
205 
stm32_usbphyc_pll_enable(struct stm32_usbphyc * usbphyc)206 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
207 {
208 	void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
209 	bool pllen = readl_relaxed(pll_reg) & PLLEN;
210 	int ret;
211 
212 	/*
213 	 * Check if a phy port or clk48 prepare has configured the pll
214 	 * and ensure the PLL is enabled
215 	 */
216 	if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
217 		return 0;
218 
219 	if (pllen) {
220 		/*
221 		 * PLL shouldn't be enabled without known consumer,
222 		 * disable it and reinit n_pll_cons
223 		 */
224 		dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
225 
226 		ret = __stm32_usbphyc_pll_disable(usbphyc);
227 		if (ret)
228 			goto dec_n_pll_cons;
229 	}
230 
231 	ret = stm32_usbphyc_regulators_enable(usbphyc);
232 	if (ret)
233 		goto dec_n_pll_cons;
234 
235 	ret = stm32_usbphyc_pll_init(usbphyc);
236 	if (ret)
237 		goto reg_disable;
238 
239 	stm32_usbphyc_set_bits(pll_reg, PLLEN);
240 
241 	return 0;
242 
243 reg_disable:
244 	stm32_usbphyc_regulators_disable(usbphyc);
245 
246 dec_n_pll_cons:
247 	atomic_dec(&usbphyc->n_pll_cons);
248 
249 	return ret;
250 }
251 
stm32_usbphyc_phy_init(struct phy * phy)252 static int stm32_usbphyc_phy_init(struct phy *phy)
253 {
254 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
255 	struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
256 	u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
257 	u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
258 				STM32_USBPHYC_MON_SEL_LOCKP);
259 	u32 monout;
260 	int ret;
261 
262 	ret = stm32_usbphyc_pll_enable(usbphyc);
263 	if (ret)
264 		return ret;
265 
266 	/* Check that PLL Lock input to PHY is High */
267 	writel_relaxed(monsel, usbphyc->base + reg_mon);
268 	ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
269 					 (monout & STM32_USBPHYC_MON_OUT_LOCKP),
270 					 100, 1000);
271 	if (ret) {
272 		dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
273 			(u32)(monout & STM32_USBPHYC_MON_OUT));
274 		goto pll_disable;
275 	}
276 
277 	usbphyc_phy->active = true;
278 
279 	return 0;
280 
281 pll_disable:
282 	stm32_usbphyc_pll_disable(usbphyc);
283 
284 	return ret;
285 }
286 
stm32_usbphyc_phy_exit(struct phy * phy)287 static int stm32_usbphyc_phy_exit(struct phy *phy)
288 {
289 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
290 	struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
291 
292 	usbphyc_phy->active = false;
293 
294 	return stm32_usbphyc_pll_disable(usbphyc);
295 }
296 
stm32_usbphyc_phy_power_on(struct phy * phy)297 static int stm32_usbphyc_phy_power_on(struct phy *phy)
298 {
299 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
300 
301 	if (usbphyc_phy->vbus)
302 		return regulator_enable(usbphyc_phy->vbus);
303 
304 	return 0;
305 }
306 
stm32_usbphyc_phy_power_off(struct phy * phy)307 static int stm32_usbphyc_phy_power_off(struct phy *phy)
308 {
309 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
310 
311 	if (usbphyc_phy->vbus)
312 		return regulator_disable(usbphyc_phy->vbus);
313 
314 	return 0;
315 }
316 
317 static const struct phy_ops stm32_usbphyc_phy_ops = {
318 	.init = stm32_usbphyc_phy_init,
319 	.exit = stm32_usbphyc_phy_exit,
320 	.power_on = stm32_usbphyc_phy_power_on,
321 	.power_off = stm32_usbphyc_phy_power_off,
322 	.owner = THIS_MODULE,
323 };
324 
stm32_usbphyc_clk48_prepare(struct clk_hw * hw)325 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
326 {
327 	struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
328 
329 	return stm32_usbphyc_pll_enable(usbphyc);
330 }
331 
stm32_usbphyc_clk48_unprepare(struct clk_hw * hw)332 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
333 {
334 	struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
335 
336 	stm32_usbphyc_pll_disable(usbphyc);
337 }
338 
stm32_usbphyc_clk48_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)339 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
340 {
341 	return 48000000;
342 }
343 
344 static const struct clk_ops usbphyc_clk48_ops = {
345 	.prepare = stm32_usbphyc_clk48_prepare,
346 	.unprepare = stm32_usbphyc_clk48_unprepare,
347 	.recalc_rate = stm32_usbphyc_clk48_recalc_rate,
348 };
349 
stm32_usbphyc_clk48_unregister(void * data)350 static void stm32_usbphyc_clk48_unregister(void *data)
351 {
352 	struct stm32_usbphyc *usbphyc = data;
353 
354 	of_clk_del_provider(usbphyc->dev->of_node);
355 	clk_hw_unregister(&usbphyc->clk48_hw);
356 }
357 
stm32_usbphyc_clk48_register(struct stm32_usbphyc * usbphyc)358 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
359 {
360 	struct device_node *node = usbphyc->dev->of_node;
361 	struct clk_init_data init = { };
362 	int ret = 0;
363 
364 	init.name = "ck_usbo_48m";
365 	init.ops = &usbphyc_clk48_ops;
366 
367 	usbphyc->clk48_hw.init = &init;
368 
369 	ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
370 	if (ret)
371 		return ret;
372 
373 	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
374 	if (ret)
375 		clk_hw_unregister(&usbphyc->clk48_hw);
376 
377 	return ret;
378 }
379 
stm32_usbphyc_switch_setup(struct stm32_usbphyc * usbphyc,u32 utmi_switch)380 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
381 				       u32 utmi_switch)
382 {
383 	if (!utmi_switch)
384 		stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
385 				       SWITHOST);
386 	else
387 		stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
388 				       SWITHOST);
389 	usbphyc->switch_setup = utmi_switch;
390 }
391 
stm32_usbphyc_of_xlate(struct device * dev,struct of_phandle_args * args)392 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
393 					  struct of_phandle_args *args)
394 {
395 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
396 	struct stm32_usbphyc_phy *usbphyc_phy = NULL;
397 	struct device_node *phynode = args->np;
398 	int port = 0;
399 
400 	for (port = 0; port < usbphyc->nphys; port++) {
401 		if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
402 			usbphyc_phy = usbphyc->phys[port];
403 			break;
404 		}
405 	}
406 	if (!usbphyc_phy) {
407 		dev_err(dev, "failed to find phy\n");
408 		return ERR_PTR(-EINVAL);
409 	}
410 
411 	if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
412 	    ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
413 		dev_err(dev, "invalid number of cells for phy port%d\n",
414 			usbphyc_phy->index);
415 		return ERR_PTR(-EINVAL);
416 	}
417 
418 	/* Configure the UTMI switch for PHY port#2 */
419 	if (usbphyc_phy->index == 1) {
420 		if (usbphyc->switch_setup < 0) {
421 			stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
422 		} else {
423 			if (args->args[0] != usbphyc->switch_setup) {
424 				dev_err(dev, "phy port1 already used\n");
425 				return ERR_PTR(-EBUSY);
426 			}
427 		}
428 	}
429 
430 	return usbphyc_phy->phy;
431 }
432 
stm32_usbphyc_probe(struct platform_device * pdev)433 static int stm32_usbphyc_probe(struct platform_device *pdev)
434 {
435 	struct stm32_usbphyc *usbphyc;
436 	struct device *dev = &pdev->dev;
437 	struct device_node *child, *np = dev->of_node;
438 	struct phy_provider *phy_provider;
439 	u32 pllen, version;
440 	int ret, port = 0;
441 
442 	usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
443 	if (!usbphyc)
444 		return -ENOMEM;
445 	usbphyc->dev = dev;
446 	dev_set_drvdata(dev, usbphyc);
447 
448 	usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
449 	if (IS_ERR(usbphyc->base))
450 		return PTR_ERR(usbphyc->base);
451 
452 	usbphyc->clk = devm_clk_get(dev, NULL);
453 	if (IS_ERR(usbphyc->clk))
454 		return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
455 
456 	ret = clk_prepare_enable(usbphyc->clk);
457 	if (ret) {
458 		dev_err(dev, "clk enable failed: %d\n", ret);
459 		return ret;
460 	}
461 
462 	usbphyc->rst = devm_reset_control_get(dev, NULL);
463 	if (!IS_ERR(usbphyc->rst)) {
464 		reset_control_assert(usbphyc->rst);
465 		udelay(2);
466 		reset_control_deassert(usbphyc->rst);
467 	} else {
468 		ret = PTR_ERR(usbphyc->rst);
469 		if (ret == -EPROBE_DEFER)
470 			goto clk_disable;
471 
472 		stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
473 	}
474 
475 	/*
476 	 * Wait for minimum width of powerdown pulse (ENABLE = Low):
477 	 * we have to ensure the PLL is disabled before phys initialization.
478 	 */
479 	if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
480 				       pllen, !(pllen & PLLEN), 5, 50)) {
481 		dev_warn(usbphyc->dev, "PLL not reset\n");
482 		ret = -EPROBE_DEFER;
483 		goto clk_disable;
484 	}
485 
486 	usbphyc->switch_setup = -EINVAL;
487 	usbphyc->nphys = of_get_child_count(np);
488 	usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
489 				     sizeof(*usbphyc->phys), GFP_KERNEL);
490 	if (!usbphyc->phys) {
491 		ret = -ENOMEM;
492 		goto clk_disable;
493 	}
494 
495 	usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
496 	if (IS_ERR(usbphyc->vdda1v1)) {
497 		ret = PTR_ERR(usbphyc->vdda1v1);
498 		if (ret != -EPROBE_DEFER)
499 			dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
500 		goto clk_disable;
501 	}
502 
503 	usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
504 	if (IS_ERR(usbphyc->vdda1v8)) {
505 		ret = PTR_ERR(usbphyc->vdda1v8);
506 		if (ret != -EPROBE_DEFER)
507 			dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
508 		goto clk_disable;
509 	}
510 
511 	for_each_child_of_node(np, child) {
512 		struct stm32_usbphyc_phy *usbphyc_phy;
513 		struct phy *phy;
514 		u32 index;
515 
516 		phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
517 		if (IS_ERR(phy)) {
518 			ret = PTR_ERR(phy);
519 			if (ret != -EPROBE_DEFER)
520 				dev_err(dev, "failed to create phy%d: %d\n",
521 					port, ret);
522 			goto put_child;
523 		}
524 
525 		usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
526 					   GFP_KERNEL);
527 		if (!usbphyc_phy) {
528 			ret = -ENOMEM;
529 			goto put_child;
530 		}
531 
532 		ret = of_property_read_u32(child, "reg", &index);
533 		if (ret || index > usbphyc->nphys) {
534 			dev_err(&phy->dev, "invalid reg property: %d\n", ret);
535 			if (!ret)
536 				ret = -EINVAL;
537 			goto put_child;
538 		}
539 
540 		usbphyc->phys[port] = usbphyc_phy;
541 		phy_set_bus_width(phy, 8);
542 		phy_set_drvdata(phy, usbphyc_phy);
543 
544 		usbphyc->phys[port]->phy = phy;
545 		usbphyc->phys[port]->usbphyc = usbphyc;
546 		usbphyc->phys[port]->index = index;
547 		usbphyc->phys[port]->active = false;
548 
549 		usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
550 		if (IS_ERR(usbphyc->phys[port]->vbus)) {
551 			ret = PTR_ERR(usbphyc->phys[port]->vbus);
552 			if (ret == -EPROBE_DEFER)
553 				goto put_child;
554 			usbphyc->phys[port]->vbus = NULL;
555 		}
556 
557 		port++;
558 	}
559 
560 	phy_provider = devm_of_phy_provider_register(dev,
561 						     stm32_usbphyc_of_xlate);
562 	if (IS_ERR(phy_provider)) {
563 		ret = PTR_ERR(phy_provider);
564 		dev_err(dev, "failed to register phy provider: %d\n", ret);
565 		goto clk_disable;
566 	}
567 
568 	ret = stm32_usbphyc_clk48_register(usbphyc);
569 	if (ret) {
570 		dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
571 		goto clk_disable;
572 	}
573 
574 	version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
575 	dev_info(dev, "registered rev:%lu.%lu\n",
576 		 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
577 
578 	return 0;
579 
580 put_child:
581 	of_node_put(child);
582 clk_disable:
583 	clk_disable_unprepare(usbphyc->clk);
584 
585 	return ret;
586 }
587 
stm32_usbphyc_remove(struct platform_device * pdev)588 static int stm32_usbphyc_remove(struct platform_device *pdev)
589 {
590 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
591 	int port;
592 
593 	/* Ensure PHYs are not active, to allow PLL disabling */
594 	for (port = 0; port < usbphyc->nphys; port++)
595 		if (usbphyc->phys[port]->active)
596 			stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
597 
598 	stm32_usbphyc_clk48_unregister(usbphyc);
599 
600 	clk_disable_unprepare(usbphyc->clk);
601 
602 	return 0;
603 }
604 
605 static const struct of_device_id stm32_usbphyc_of_match[] = {
606 	{ .compatible = "st,stm32mp1-usbphyc", },
607 	{ },
608 };
609 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
610 
611 static struct platform_driver stm32_usbphyc_driver = {
612 	.probe = stm32_usbphyc_probe,
613 	.remove = stm32_usbphyc_remove,
614 	.driver = {
615 		.of_match_table = stm32_usbphyc_of_match,
616 		.name = "stm32-usbphyc",
617 	}
618 };
619 module_platform_driver(stm32_usbphyc_driver);
620 
621 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
622 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
623 MODULE_LICENSE("GPL v2");
624