1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl driver for Rockchip SoCs
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22 #include <linux/bitops.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/of_address.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/irqchip/chained_irq.h>
33 #include <linux/clk.h>
34 #include <linux/regmap.h>
35 #include <linux/mfd/syscon.h>
36 #include <dt-bindings/pinctrl/rockchip.h>
37
38 #include "core.h"
39 #include "pinconf.h"
40 #include "pinctrl-rockchip.h"
41
42 /**
43 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
44 * register 31:16 area.
45 */
46 #define WRITE_MASK_VAL(h, l, v) \
47 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
48
49 /*
50 * Encode variants of iomux registers into a type variable
51 */
52 #define IOMUX_GPIO_ONLY BIT(0)
53 #define IOMUX_WIDTH_4BIT BIT(1)
54 #define IOMUX_SOURCE_PMU BIT(2)
55 #define IOMUX_UNROUTED BIT(3)
56 #define IOMUX_WIDTH_3BIT BIT(4)
57 #define IOMUX_WIDTH_2BIT BIT(5)
58
59 #define PIN_BANK(id, pins, label) \
60 { \
61 .bank_num = id, \
62 .nr_pins = pins, \
63 .name = label, \
64 .iomux = { \
65 { .offset = -1 }, \
66 { .offset = -1 }, \
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 }, \
70 }
71
72 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
73 { \
74 .bank_num = id, \
75 .nr_pins = pins, \
76 .name = label, \
77 .iomux = { \
78 { .type = iom0, .offset = -1 }, \
79 { .type = iom1, .offset = -1 }, \
80 { .type = iom2, .offset = -1 }, \
81 { .type = iom3, .offset = -1 }, \
82 }, \
83 }
84
85 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
86 { \
87 .bank_num = id, \
88 .nr_pins = pins, \
89 .name = label, \
90 .iomux = { \
91 { .offset = -1 }, \
92 { .offset = -1 }, \
93 { .offset = -1 }, \
94 { .offset = -1 }, \
95 }, \
96 .drv = { \
97 { .drv_type = type0, .offset = -1 }, \
98 { .drv_type = type1, .offset = -1 }, \
99 { .drv_type = type2, .offset = -1 }, \
100 { .drv_type = type3, .offset = -1 }, \
101 }, \
102 }
103
104 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
105 drv2, drv3, pull0, pull1, \
106 pull2, pull3) \
107 { \
108 .bank_num = id, \
109 .nr_pins = pins, \
110 .name = label, \
111 .iomux = { \
112 { .offset = -1 }, \
113 { .offset = -1 }, \
114 { .offset = -1 }, \
115 { .offset = -1 }, \
116 }, \
117 .drv = { \
118 { .drv_type = drv0, .offset = -1 }, \
119 { .drv_type = drv1, .offset = -1 }, \
120 { .drv_type = drv2, .offset = -1 }, \
121 { .drv_type = drv3, .offset = -1 }, \
122 }, \
123 .pull_type[0] = pull0, \
124 .pull_type[1] = pull1, \
125 .pull_type[2] = pull2, \
126 .pull_type[3] = pull3, \
127 }
128
129 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
130 iom2, iom3, drv0, drv1, drv2, \
131 drv3, offset0, offset1, \
132 offset2, offset3) \
133 { \
134 .bank_num = id, \
135 .nr_pins = pins, \
136 .name = label, \
137 .iomux = { \
138 { .type = iom0, .offset = -1 }, \
139 { .type = iom1, .offset = -1 }, \
140 { .type = iom2, .offset = -1 }, \
141 { .type = iom3, .offset = -1 }, \
142 }, \
143 .drv = { \
144 { .drv_type = drv0, .offset = offset0 }, \
145 { .drv_type = drv1, .offset = offset1 }, \
146 { .drv_type = drv2, .offset = offset2 }, \
147 { .drv_type = drv3, .offset = offset3 }, \
148 }, \
149 }
150
151 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
152 label, iom0, iom1, iom2, \
153 iom3, drv0, drv1, drv2, \
154 drv3, offset0, offset1, \
155 offset2, offset3, pull0, \
156 pull1, pull2, pull3) \
157 { \
158 .bank_num = id, \
159 .nr_pins = pins, \
160 .name = label, \
161 .iomux = { \
162 { .type = iom0, .offset = -1 }, \
163 { .type = iom1, .offset = -1 }, \
164 { .type = iom2, .offset = -1 }, \
165 { .type = iom3, .offset = -1 }, \
166 }, \
167 .drv = { \
168 { .drv_type = drv0, .offset = offset0 }, \
169 { .drv_type = drv1, .offset = offset1 }, \
170 { .drv_type = drv2, .offset = offset2 }, \
171 { .drv_type = drv3, .offset = offset3 }, \
172 }, \
173 .pull_type[0] = pull0, \
174 .pull_type[1] = pull1, \
175 .pull_type[2] = pull2, \
176 .pull_type[3] = pull3, \
177 }
178
179 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
180 { \
181 .bank_num = ID, \
182 .pin = PIN, \
183 .func = FUNC, \
184 .route_offset = REG, \
185 .route_val = VAL, \
186 .route_location = FLAG, \
187 }
188
189 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
190 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
191
192 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
193 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
194
195 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
196 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
197
198 static struct regmap_config rockchip_regmap_config = {
199 .reg_bits = 32,
200 .val_bits = 32,
201 .reg_stride = 4,
202 };
203
pinctrl_name_to_group(const struct rockchip_pinctrl * info,const char * name)204 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
205 const struct rockchip_pinctrl *info,
206 const char *name)
207 {
208 int i;
209
210 for (i = 0; i < info->ngroups; i++) {
211 if (!strcmp(info->groups[i].name, name))
212 return &info->groups[i];
213 }
214
215 return NULL;
216 }
217
218 /*
219 * given a pin number that is local to a pin controller, find out the pin bank
220 * and the register base of the pin bank.
221 */
pin_to_bank(struct rockchip_pinctrl * info,unsigned pin)222 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
223 unsigned pin)
224 {
225 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
226
227 while (pin >= (b->pin_base + b->nr_pins))
228 b++;
229
230 return b;
231 }
232
bank_num_to_bank(struct rockchip_pinctrl * info,unsigned num)233 static struct rockchip_pin_bank *bank_num_to_bank(
234 struct rockchip_pinctrl *info,
235 unsigned num)
236 {
237 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
238 int i;
239
240 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
241 if (b->bank_num == num)
242 return b;
243 }
244
245 return ERR_PTR(-EINVAL);
246 }
247
248 /*
249 * Pinctrl_ops handling
250 */
251
rockchip_get_groups_count(struct pinctrl_dev * pctldev)252 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
253 {
254 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
255
256 return info->ngroups;
257 }
258
rockchip_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)259 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
260 unsigned selector)
261 {
262 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
263
264 return info->groups[selector].name;
265 }
266
rockchip_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)267 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
268 unsigned selector, const unsigned **pins,
269 unsigned *npins)
270 {
271 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
272
273 if (selector >= info->ngroups)
274 return -EINVAL;
275
276 *pins = info->groups[selector].pins;
277 *npins = info->groups[selector].npins;
278
279 return 0;
280 }
281
rockchip_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)282 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
283 struct device_node *np,
284 struct pinctrl_map **map, unsigned *num_maps)
285 {
286 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
287 const struct rockchip_pin_group *grp;
288 struct device *dev = info->dev;
289 struct pinctrl_map *new_map;
290 struct device_node *parent;
291 int map_num = 1;
292 int i;
293
294 /*
295 * first find the group of this node and check if we need to create
296 * config maps for pins
297 */
298 grp = pinctrl_name_to_group(info, np->name);
299 if (!grp) {
300 dev_err(dev, "unable to find group for node %pOFn\n", np);
301 return -EINVAL;
302 }
303
304 map_num += grp->npins;
305
306 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
307 if (!new_map)
308 return -ENOMEM;
309
310 *map = new_map;
311 *num_maps = map_num;
312
313 /* create mux map */
314 parent = of_get_parent(np);
315 if (!parent) {
316 kfree(new_map);
317 return -EINVAL;
318 }
319 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
320 new_map[0].data.mux.function = parent->name;
321 new_map[0].data.mux.group = np->name;
322 of_node_put(parent);
323
324 /* create config map */
325 new_map++;
326 for (i = 0; i < grp->npins; i++) {
327 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
328 new_map[i].data.configs.group_or_pin =
329 pin_get_name(pctldev, grp->pins[i]);
330 new_map[i].data.configs.configs = grp->data[i].configs;
331 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
332 }
333
334 dev_dbg(dev, "maps: function %s group %s num %d\n",
335 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
336
337 return 0;
338 }
339
rockchip_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)340 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
341 struct pinctrl_map *map, unsigned num_maps)
342 {
343 kfree(map);
344 }
345
346 static const struct pinctrl_ops rockchip_pctrl_ops = {
347 .get_groups_count = rockchip_get_groups_count,
348 .get_group_name = rockchip_get_group_name,
349 .get_group_pins = rockchip_get_group_pins,
350 .dt_node_to_map = rockchip_dt_node_to_map,
351 .dt_free_map = rockchip_dt_free_map,
352 };
353
354 /*
355 * Hardware access
356 */
357
358 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
359 {
360 .num = 1,
361 .pin = 0,
362 .reg = 0x418,
363 .bit = 0,
364 .mask = 0x3
365 }, {
366 .num = 1,
367 .pin = 1,
368 .reg = 0x418,
369 .bit = 2,
370 .mask = 0x3
371 }, {
372 .num = 1,
373 .pin = 2,
374 .reg = 0x418,
375 .bit = 4,
376 .mask = 0x3
377 }, {
378 .num = 1,
379 .pin = 3,
380 .reg = 0x418,
381 .bit = 6,
382 .mask = 0x3
383 }, {
384 .num = 1,
385 .pin = 4,
386 .reg = 0x418,
387 .bit = 8,
388 .mask = 0x3
389 }, {
390 .num = 1,
391 .pin = 5,
392 .reg = 0x418,
393 .bit = 10,
394 .mask = 0x3
395 }, {
396 .num = 1,
397 .pin = 6,
398 .reg = 0x418,
399 .bit = 12,
400 .mask = 0x3
401 }, {
402 .num = 1,
403 .pin = 7,
404 .reg = 0x418,
405 .bit = 14,
406 .mask = 0x3
407 }, {
408 .num = 1,
409 .pin = 8,
410 .reg = 0x41c,
411 .bit = 0,
412 .mask = 0x3
413 }, {
414 .num = 1,
415 .pin = 9,
416 .reg = 0x41c,
417 .bit = 2,
418 .mask = 0x3
419 },
420 };
421
422 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
423 {
424 .num = 2,
425 .pin = 20,
426 .reg = 0xe8,
427 .bit = 0,
428 .mask = 0x7
429 }, {
430 .num = 2,
431 .pin = 21,
432 .reg = 0xe8,
433 .bit = 4,
434 .mask = 0x7
435 }, {
436 .num = 2,
437 .pin = 22,
438 .reg = 0xe8,
439 .bit = 8,
440 .mask = 0x7
441 }, {
442 .num = 2,
443 .pin = 23,
444 .reg = 0xe8,
445 .bit = 12,
446 .mask = 0x7
447 }, {
448 .num = 2,
449 .pin = 24,
450 .reg = 0xd4,
451 .bit = 12,
452 .mask = 0x7
453 },
454 };
455
456 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
457 {
458 /* gpio1b6_sel */
459 .num = 1,
460 .pin = 14,
461 .reg = 0x28,
462 .bit = 12,
463 .mask = 0xf
464 }, {
465 /* gpio1b7_sel */
466 .num = 1,
467 .pin = 15,
468 .reg = 0x2c,
469 .bit = 0,
470 .mask = 0x3
471 }, {
472 /* gpio1c2_sel */
473 .num = 1,
474 .pin = 18,
475 .reg = 0x30,
476 .bit = 4,
477 .mask = 0xf
478 }, {
479 /* gpio1c3_sel */
480 .num = 1,
481 .pin = 19,
482 .reg = 0x30,
483 .bit = 8,
484 .mask = 0xf
485 }, {
486 /* gpio1c4_sel */
487 .num = 1,
488 .pin = 20,
489 .reg = 0x30,
490 .bit = 12,
491 .mask = 0xf
492 }, {
493 /* gpio1c5_sel */
494 .num = 1,
495 .pin = 21,
496 .reg = 0x34,
497 .bit = 0,
498 .mask = 0xf
499 }, {
500 /* gpio1c6_sel */
501 .num = 1,
502 .pin = 22,
503 .reg = 0x34,
504 .bit = 4,
505 .mask = 0xf
506 }, {
507 /* gpio1c7_sel */
508 .num = 1,
509 .pin = 23,
510 .reg = 0x34,
511 .bit = 8,
512 .mask = 0xf
513 }, {
514 /* gpio3b4_sel */
515 .num = 3,
516 .pin = 12,
517 .reg = 0x68,
518 .bit = 8,
519 .mask = 0xf
520 }, {
521 /* gpio3b5_sel */
522 .num = 3,
523 .pin = 13,
524 .reg = 0x68,
525 .bit = 12,
526 .mask = 0xf
527 }, {
528 /* gpio2a2_sel */
529 .num = 2,
530 .pin = 2,
531 .reg = 0x40,
532 .bit = 4,
533 .mask = 0x3
534 }, {
535 /* gpio2a3_sel */
536 .num = 2,
537 .pin = 3,
538 .reg = 0x40,
539 .bit = 6,
540 .mask = 0x3
541 }, {
542 /* gpio2c0_sel */
543 .num = 2,
544 .pin = 16,
545 .reg = 0x50,
546 .bit = 0,
547 .mask = 0x3
548 }, {
549 /* gpio3b2_sel */
550 .num = 3,
551 .pin = 10,
552 .reg = 0x68,
553 .bit = 4,
554 .mask = 0x3
555 }, {
556 /* gpio3b3_sel */
557 .num = 3,
558 .pin = 11,
559 .reg = 0x68,
560 .bit = 6,
561 .mask = 0x3
562 },
563 };
564
565 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
566 {
567 .num = 2,
568 .pin = 12,
569 .reg = 0x24,
570 .bit = 8,
571 .mask = 0x3
572 }, {
573 .num = 2,
574 .pin = 15,
575 .reg = 0x28,
576 .bit = 0,
577 .mask = 0x7
578 }, {
579 .num = 2,
580 .pin = 23,
581 .reg = 0x30,
582 .bit = 14,
583 .mask = 0x3
584 },
585 };
586
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)587 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
588 int *reg, u8 *bit, int *mask)
589 {
590 struct rockchip_pinctrl *info = bank->drvdata;
591 struct rockchip_pin_ctrl *ctrl = info->ctrl;
592 struct rockchip_mux_recalced_data *data;
593 int i;
594
595 for (i = 0; i < ctrl->niomux_recalced; i++) {
596 data = &ctrl->iomux_recalced[i];
597 if (data->num == bank->bank_num &&
598 data->pin == pin)
599 break;
600 }
601
602 if (i >= ctrl->niomux_recalced)
603 return;
604
605 *reg = data->reg;
606 *mask = data->mask;
607 *bit = data->bit;
608 }
609
610 static struct rockchip_mux_route_data px30_mux_route_data[] = {
611 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
612 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
613 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
614 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
615 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
616 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
617 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
618 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
619 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
620 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
621 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
622 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
623 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
624 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
625 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
626 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
627 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
628 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
629 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
630 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
631 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
632 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
633 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
634 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
635 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
636 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
637 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
638 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
639 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
640 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
641 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
642 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
643 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
644 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
645 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
646 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
647 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
648 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
649 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
650 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
651 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
652 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
653 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
654 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
655 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
656 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
657 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
658 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
659 };
660
661 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
662 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
663 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
664 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
665 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
666 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
667 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
668 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
669 };
670
671 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
672 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
673 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
674 };
675
676 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
677 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
678 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
679 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
680 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
681 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
682 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
683 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
684 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
685 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
686 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
687 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
688 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
689 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
690 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
691 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
692 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
693 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
694 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
695 };
696
697 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
698 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
699 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
700 };
701
702 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
703 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
704 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
705 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
706 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
707 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
708 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
709 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
710 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
711 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
712 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
713 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
714 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
715 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
716 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
717 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
718 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
719 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
720 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
721 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
722 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
723 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
724 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
725 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
726 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
727 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
728 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
729 };
730
731 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
732 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
733 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
734 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
735 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
736 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
737 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
738 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
739 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
740 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
741 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
742 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
743 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
744 };
745
746 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
747 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
748 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
749 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
750 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
751 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
752 };
753
754 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
755 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
756 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
757 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
758 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
759 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
760 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
761 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
762 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
763 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
764 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
765 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
766 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
767 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
768 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
769 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
770 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
771 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
772 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
773 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
774 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
775 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
776 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
777 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
778 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
779 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
780 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
781 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
782 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
783 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
784 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
785 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
786 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
787 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
788 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
789 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
790 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
791 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
792 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
793 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
794 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
795 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
796 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
797 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
798 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
799 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
800 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
801 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
802 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
803 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
804 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
805 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
806 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
807 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
808 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
809 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
810 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
811 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
812 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
813 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
814 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
815 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
816 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
817 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
818 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
819 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
820 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
821 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
822 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
823 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
824 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
825 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
826 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
827 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
828 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
829 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
830 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
831 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
832 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
833 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
834 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
835 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
836 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
837 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
838 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
839 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
840 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
841 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
842 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
843 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
844 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
845 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
846 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
847 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
848 };
849
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * loc,u32 * reg,u32 * value)850 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
851 int mux, u32 *loc, u32 *reg, u32 *value)
852 {
853 struct rockchip_pinctrl *info = bank->drvdata;
854 struct rockchip_pin_ctrl *ctrl = info->ctrl;
855 struct rockchip_mux_route_data *data;
856 int i;
857
858 for (i = 0; i < ctrl->niomux_routes; i++) {
859 data = &ctrl->iomux_routes[i];
860 if ((data->bank_num == bank->bank_num) &&
861 (data->pin == pin) && (data->func == mux))
862 break;
863 }
864
865 if (i >= ctrl->niomux_routes)
866 return false;
867
868 *loc = data->route_location;
869 *reg = data->route_offset;
870 *value = data->route_val;
871
872 return true;
873 }
874
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)875 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
876 {
877 struct rockchip_pinctrl *info = bank->drvdata;
878 int iomux_num = (pin / 8);
879 struct regmap *regmap;
880 unsigned int val;
881 int reg, ret, mask, mux_type;
882 u8 bit;
883
884 if (iomux_num > 3)
885 return -EINVAL;
886
887 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
888 dev_err(info->dev, "pin %d is unrouted\n", pin);
889 return -EINVAL;
890 }
891
892 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
893 return RK_FUNC_GPIO;
894
895 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
896 ? info->regmap_pmu : info->regmap_base;
897
898 /* get basic quadrupel of mux registers and the correct reg inside */
899 mux_type = bank->iomux[iomux_num].type;
900 reg = bank->iomux[iomux_num].offset;
901 if (mux_type & IOMUX_WIDTH_4BIT) {
902 if ((pin % 8) >= 4)
903 reg += 0x4;
904 bit = (pin % 4) * 4;
905 mask = 0xf;
906 } else if (mux_type & IOMUX_WIDTH_3BIT) {
907 if ((pin % 8) >= 5)
908 reg += 0x4;
909 bit = (pin % 8 % 5) * 3;
910 mask = 0x7;
911 } else {
912 bit = (pin % 8) * 2;
913 mask = 0x3;
914 }
915
916 if (bank->recalced_mask & BIT(pin))
917 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
918
919 ret = regmap_read(regmap, reg, &val);
920 if (ret)
921 return ret;
922
923 return ((val >> bit) & mask);
924 }
925
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)926 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
927 int pin, int mux)
928 {
929 struct rockchip_pinctrl *info = bank->drvdata;
930 struct device *dev = info->dev;
931 int iomux_num = (pin / 8);
932
933 if (iomux_num > 3)
934 return -EINVAL;
935
936 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
937 dev_err(dev, "pin %d is unrouted\n", pin);
938 return -EINVAL;
939 }
940
941 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
942 if (mux != RK_FUNC_GPIO) {
943 dev_err(dev, "pin %d only supports a gpio mux\n", pin);
944 return -ENOTSUPP;
945 }
946 }
947
948 return 0;
949 }
950
951 /*
952 * Set a new mux function for a pin.
953 *
954 * The register is divided into the upper and lower 16 bit. When changing
955 * a value, the previous register value is not read and changed. Instead
956 * it seems the changed bits are marked in the upper 16 bit, while the
957 * changed value gets set in the same offset in the lower 16 bit.
958 * All pin settings seem to be 2 bit wide in both the upper and lower
959 * parts.
960 * @bank: pin bank to change
961 * @pin: pin to change
962 * @mux: new mux function to set
963 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)964 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
965 {
966 struct rockchip_pinctrl *info = bank->drvdata;
967 struct device *dev = info->dev;
968 int iomux_num = (pin / 8);
969 struct regmap *regmap;
970 int reg, ret, mask, mux_type;
971 u8 bit;
972 u32 data, rmask, route_location, route_reg, route_val;
973
974 ret = rockchip_verify_mux(bank, pin, mux);
975 if (ret < 0)
976 return ret;
977
978 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
979 return 0;
980
981 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
982
983 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
984 ? info->regmap_pmu : info->regmap_base;
985
986 /* get basic quadrupel of mux registers and the correct reg inside */
987 mux_type = bank->iomux[iomux_num].type;
988 reg = bank->iomux[iomux_num].offset;
989 if (mux_type & IOMUX_WIDTH_4BIT) {
990 if ((pin % 8) >= 4)
991 reg += 0x4;
992 bit = (pin % 4) * 4;
993 mask = 0xf;
994 } else if (mux_type & IOMUX_WIDTH_3BIT) {
995 if ((pin % 8) >= 5)
996 reg += 0x4;
997 bit = (pin % 8 % 5) * 3;
998 mask = 0x7;
999 } else {
1000 bit = (pin % 8) * 2;
1001 mask = 0x3;
1002 }
1003
1004 if (bank->recalced_mask & BIT(pin))
1005 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1006
1007 if (bank->route_mask & BIT(pin)) {
1008 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1009 &route_reg, &route_val)) {
1010 struct regmap *route_regmap = regmap;
1011
1012 /* handle special locations */
1013 switch (route_location) {
1014 case ROCKCHIP_ROUTE_PMU:
1015 route_regmap = info->regmap_pmu;
1016 break;
1017 case ROCKCHIP_ROUTE_GRF:
1018 route_regmap = info->regmap_base;
1019 break;
1020 }
1021
1022 ret = regmap_write(route_regmap, route_reg, route_val);
1023 if (ret)
1024 return ret;
1025 }
1026 }
1027
1028 data = (mask << (bit + 16));
1029 rmask = data | (data >> 16);
1030 data |= (mux & mask) << bit;
1031 ret = regmap_update_bits(regmap, reg, rmask, data);
1032
1033 return ret;
1034 }
1035
1036 #define PX30_PULL_PMU_OFFSET 0x10
1037 #define PX30_PULL_GRF_OFFSET 0x60
1038 #define PX30_PULL_BITS_PER_PIN 2
1039 #define PX30_PULL_PINS_PER_REG 8
1040 #define PX30_PULL_BANK_STRIDE 16
1041
px30_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1042 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1043 int pin_num, struct regmap **regmap,
1044 int *reg, u8 *bit)
1045 {
1046 struct rockchip_pinctrl *info = bank->drvdata;
1047
1048 /* The first 32 pins of the first bank are located in PMU */
1049 if (bank->bank_num == 0) {
1050 *regmap = info->regmap_pmu;
1051 *reg = PX30_PULL_PMU_OFFSET;
1052 } else {
1053 *regmap = info->regmap_base;
1054 *reg = PX30_PULL_GRF_OFFSET;
1055
1056 /* correct the offset, as we're starting with the 2nd bank */
1057 *reg -= 0x10;
1058 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1059 }
1060
1061 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1062 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1063 *bit *= PX30_PULL_BITS_PER_PIN;
1064
1065 return 0;
1066 }
1067
1068 #define PX30_DRV_PMU_OFFSET 0x20
1069 #define PX30_DRV_GRF_OFFSET 0xf0
1070 #define PX30_DRV_BITS_PER_PIN 2
1071 #define PX30_DRV_PINS_PER_REG 8
1072 #define PX30_DRV_BANK_STRIDE 16
1073
px30_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1074 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1075 int pin_num, struct regmap **regmap,
1076 int *reg, u8 *bit)
1077 {
1078 struct rockchip_pinctrl *info = bank->drvdata;
1079
1080 /* The first 32 pins of the first bank are located in PMU */
1081 if (bank->bank_num == 0) {
1082 *regmap = info->regmap_pmu;
1083 *reg = PX30_DRV_PMU_OFFSET;
1084 } else {
1085 *regmap = info->regmap_base;
1086 *reg = PX30_DRV_GRF_OFFSET;
1087
1088 /* correct the offset, as we're starting with the 2nd bank */
1089 *reg -= 0x10;
1090 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1091 }
1092
1093 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1094 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1095 *bit *= PX30_DRV_BITS_PER_PIN;
1096
1097 return 0;
1098 }
1099
1100 #define PX30_SCHMITT_PMU_OFFSET 0x38
1101 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1102 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1103 #define PX30_SCHMITT_BANK_STRIDE 16
1104 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1105
px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1106 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1107 int pin_num,
1108 struct regmap **regmap,
1109 int *reg, u8 *bit)
1110 {
1111 struct rockchip_pinctrl *info = bank->drvdata;
1112 int pins_per_reg;
1113
1114 if (bank->bank_num == 0) {
1115 *regmap = info->regmap_pmu;
1116 *reg = PX30_SCHMITT_PMU_OFFSET;
1117 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1118 } else {
1119 *regmap = info->regmap_base;
1120 *reg = PX30_SCHMITT_GRF_OFFSET;
1121 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1122 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1123 }
1124
1125 *reg += ((pin_num / pins_per_reg) * 4);
1126 *bit = pin_num % pins_per_reg;
1127
1128 return 0;
1129 }
1130
1131 #define RV1108_PULL_PMU_OFFSET 0x10
1132 #define RV1108_PULL_OFFSET 0x110
1133 #define RV1108_PULL_PINS_PER_REG 8
1134 #define RV1108_PULL_BITS_PER_PIN 2
1135 #define RV1108_PULL_BANK_STRIDE 16
1136
rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1137 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1138 int pin_num, struct regmap **regmap,
1139 int *reg, u8 *bit)
1140 {
1141 struct rockchip_pinctrl *info = bank->drvdata;
1142
1143 /* The first 24 pins of the first bank are located in PMU */
1144 if (bank->bank_num == 0) {
1145 *regmap = info->regmap_pmu;
1146 *reg = RV1108_PULL_PMU_OFFSET;
1147 } else {
1148 *reg = RV1108_PULL_OFFSET;
1149 *regmap = info->regmap_base;
1150 /* correct the offset, as we're starting with the 2nd bank */
1151 *reg -= 0x10;
1152 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1153 }
1154
1155 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1156 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1157 *bit *= RV1108_PULL_BITS_PER_PIN;
1158
1159 return 0;
1160 }
1161
1162 #define RV1108_DRV_PMU_OFFSET 0x20
1163 #define RV1108_DRV_GRF_OFFSET 0x210
1164 #define RV1108_DRV_BITS_PER_PIN 2
1165 #define RV1108_DRV_PINS_PER_REG 8
1166 #define RV1108_DRV_BANK_STRIDE 16
1167
rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1168 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1169 int pin_num, struct regmap **regmap,
1170 int *reg, u8 *bit)
1171 {
1172 struct rockchip_pinctrl *info = bank->drvdata;
1173
1174 /* The first 24 pins of the first bank are located in PMU */
1175 if (bank->bank_num == 0) {
1176 *regmap = info->regmap_pmu;
1177 *reg = RV1108_DRV_PMU_OFFSET;
1178 } else {
1179 *regmap = info->regmap_base;
1180 *reg = RV1108_DRV_GRF_OFFSET;
1181
1182 /* correct the offset, as we're starting with the 2nd bank */
1183 *reg -= 0x10;
1184 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1185 }
1186
1187 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1188 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1189 *bit *= RV1108_DRV_BITS_PER_PIN;
1190
1191 return 0;
1192 }
1193
1194 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1195 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1196 #define RV1108_SCHMITT_BANK_STRIDE 8
1197 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1198 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1199
rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1200 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1201 int pin_num,
1202 struct regmap **regmap,
1203 int *reg, u8 *bit)
1204 {
1205 struct rockchip_pinctrl *info = bank->drvdata;
1206 int pins_per_reg;
1207
1208 if (bank->bank_num == 0) {
1209 *regmap = info->regmap_pmu;
1210 *reg = RV1108_SCHMITT_PMU_OFFSET;
1211 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1212 } else {
1213 *regmap = info->regmap_base;
1214 *reg = RV1108_SCHMITT_GRF_OFFSET;
1215 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1216 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1217 }
1218 *reg += ((pin_num / pins_per_reg) * 4);
1219 *bit = pin_num % pins_per_reg;
1220
1221 return 0;
1222 }
1223
1224 #define RK3308_SCHMITT_PINS_PER_REG 8
1225 #define RK3308_SCHMITT_BANK_STRIDE 16
1226 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1227
rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1228 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1229 int pin_num, struct regmap **regmap,
1230 int *reg, u8 *bit)
1231 {
1232 struct rockchip_pinctrl *info = bank->drvdata;
1233
1234 *regmap = info->regmap_base;
1235 *reg = RK3308_SCHMITT_GRF_OFFSET;
1236
1237 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1238 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1239 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1240
1241 return 0;
1242 }
1243
1244 #define RK2928_PULL_OFFSET 0x118
1245 #define RK2928_PULL_PINS_PER_REG 16
1246 #define RK2928_PULL_BANK_STRIDE 8
1247
rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1248 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1249 int pin_num, struct regmap **regmap,
1250 int *reg, u8 *bit)
1251 {
1252 struct rockchip_pinctrl *info = bank->drvdata;
1253
1254 *regmap = info->regmap_base;
1255 *reg = RK2928_PULL_OFFSET;
1256 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1257 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1258
1259 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1260
1261 return 0;
1262 };
1263
1264 #define RK3128_PULL_OFFSET 0x118
1265
rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1266 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1267 int pin_num, struct regmap **regmap,
1268 int *reg, u8 *bit)
1269 {
1270 struct rockchip_pinctrl *info = bank->drvdata;
1271
1272 *regmap = info->regmap_base;
1273 *reg = RK3128_PULL_OFFSET;
1274 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1275 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1276
1277 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1278
1279 return 0;
1280 }
1281
1282 #define RK3188_PULL_OFFSET 0x164
1283 #define RK3188_PULL_BITS_PER_PIN 2
1284 #define RK3188_PULL_PINS_PER_REG 8
1285 #define RK3188_PULL_BANK_STRIDE 16
1286 #define RK3188_PULL_PMU_OFFSET 0x64
1287
rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1288 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1289 int pin_num, struct regmap **regmap,
1290 int *reg, u8 *bit)
1291 {
1292 struct rockchip_pinctrl *info = bank->drvdata;
1293
1294 /* The first 12 pins of the first bank are located elsewhere */
1295 if (bank->bank_num == 0 && pin_num < 12) {
1296 *regmap = info->regmap_pmu ? info->regmap_pmu
1297 : bank->regmap_pull;
1298 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1299 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1300 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1301 *bit *= RK3188_PULL_BITS_PER_PIN;
1302 } else {
1303 *regmap = info->regmap_pull ? info->regmap_pull
1304 : info->regmap_base;
1305 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1306
1307 /* correct the offset, as it is the 2nd pull register */
1308 *reg -= 4;
1309 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1310 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1311
1312 /*
1313 * The bits in these registers have an inverse ordering
1314 * with the lowest pin being in bits 15:14 and the highest
1315 * pin in bits 1:0
1316 */
1317 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1318 *bit *= RK3188_PULL_BITS_PER_PIN;
1319 }
1320
1321 return 0;
1322 }
1323
1324 #define RK3288_PULL_OFFSET 0x140
rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1325 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1326 int pin_num, struct regmap **regmap,
1327 int *reg, u8 *bit)
1328 {
1329 struct rockchip_pinctrl *info = bank->drvdata;
1330
1331 /* The first 24 pins of the first bank are located in PMU */
1332 if (bank->bank_num == 0) {
1333 *regmap = info->regmap_pmu;
1334 *reg = RK3188_PULL_PMU_OFFSET;
1335
1336 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1337 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1338 *bit *= RK3188_PULL_BITS_PER_PIN;
1339 } else {
1340 *regmap = info->regmap_base;
1341 *reg = RK3288_PULL_OFFSET;
1342
1343 /* correct the offset, as we're starting with the 2nd bank */
1344 *reg -= 0x10;
1345 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1346 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1347
1348 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1349 *bit *= RK3188_PULL_BITS_PER_PIN;
1350 }
1351
1352 return 0;
1353 }
1354
1355 #define RK3288_DRV_PMU_OFFSET 0x70
1356 #define RK3288_DRV_GRF_OFFSET 0x1c0
1357 #define RK3288_DRV_BITS_PER_PIN 2
1358 #define RK3288_DRV_PINS_PER_REG 8
1359 #define RK3288_DRV_BANK_STRIDE 16
1360
rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1361 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1362 int pin_num, struct regmap **regmap,
1363 int *reg, u8 *bit)
1364 {
1365 struct rockchip_pinctrl *info = bank->drvdata;
1366
1367 /* The first 24 pins of the first bank are located in PMU */
1368 if (bank->bank_num == 0) {
1369 *regmap = info->regmap_pmu;
1370 *reg = RK3288_DRV_PMU_OFFSET;
1371
1372 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1373 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1374 *bit *= RK3288_DRV_BITS_PER_PIN;
1375 } else {
1376 *regmap = info->regmap_base;
1377 *reg = RK3288_DRV_GRF_OFFSET;
1378
1379 /* correct the offset, as we're starting with the 2nd bank */
1380 *reg -= 0x10;
1381 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1382 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1383
1384 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1385 *bit *= RK3288_DRV_BITS_PER_PIN;
1386 }
1387
1388 return 0;
1389 }
1390
1391 #define RK3228_PULL_OFFSET 0x100
1392
rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1393 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1394 int pin_num, struct regmap **regmap,
1395 int *reg, u8 *bit)
1396 {
1397 struct rockchip_pinctrl *info = bank->drvdata;
1398
1399 *regmap = info->regmap_base;
1400 *reg = RK3228_PULL_OFFSET;
1401 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1402 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1403
1404 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1405 *bit *= RK3188_PULL_BITS_PER_PIN;
1406
1407 return 0;
1408 }
1409
1410 #define RK3228_DRV_GRF_OFFSET 0x200
1411
rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1412 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1413 int pin_num, struct regmap **regmap,
1414 int *reg, u8 *bit)
1415 {
1416 struct rockchip_pinctrl *info = bank->drvdata;
1417
1418 *regmap = info->regmap_base;
1419 *reg = RK3228_DRV_GRF_OFFSET;
1420 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1421 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1422
1423 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1424 *bit *= RK3288_DRV_BITS_PER_PIN;
1425
1426 return 0;
1427 }
1428
1429 #define RK3308_PULL_OFFSET 0xa0
1430
rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1431 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1432 int pin_num, struct regmap **regmap,
1433 int *reg, u8 *bit)
1434 {
1435 struct rockchip_pinctrl *info = bank->drvdata;
1436
1437 *regmap = info->regmap_base;
1438 *reg = RK3308_PULL_OFFSET;
1439 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1440 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1441
1442 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1443 *bit *= RK3188_PULL_BITS_PER_PIN;
1444
1445 return 0;
1446 }
1447
1448 #define RK3308_DRV_GRF_OFFSET 0x100
1449
rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1450 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1451 int pin_num, struct regmap **regmap,
1452 int *reg, u8 *bit)
1453 {
1454 struct rockchip_pinctrl *info = bank->drvdata;
1455
1456 *regmap = info->regmap_base;
1457 *reg = RK3308_DRV_GRF_OFFSET;
1458 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1459 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1460
1461 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1462 *bit *= RK3288_DRV_BITS_PER_PIN;
1463
1464 return 0;
1465 }
1466
1467 #define RK3368_PULL_GRF_OFFSET 0x100
1468 #define RK3368_PULL_PMU_OFFSET 0x10
1469
rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1470 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1471 int pin_num, struct regmap **regmap,
1472 int *reg, u8 *bit)
1473 {
1474 struct rockchip_pinctrl *info = bank->drvdata;
1475
1476 /* The first 32 pins of the first bank are located in PMU */
1477 if (bank->bank_num == 0) {
1478 *regmap = info->regmap_pmu;
1479 *reg = RK3368_PULL_PMU_OFFSET;
1480
1481 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1482 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1483 *bit *= RK3188_PULL_BITS_PER_PIN;
1484 } else {
1485 *regmap = info->regmap_base;
1486 *reg = RK3368_PULL_GRF_OFFSET;
1487
1488 /* correct the offset, as we're starting with the 2nd bank */
1489 *reg -= 0x10;
1490 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1491 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1492
1493 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1494 *bit *= RK3188_PULL_BITS_PER_PIN;
1495 }
1496
1497 return 0;
1498 }
1499
1500 #define RK3368_DRV_PMU_OFFSET 0x20
1501 #define RK3368_DRV_GRF_OFFSET 0x200
1502
rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1503 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1504 int pin_num, struct regmap **regmap,
1505 int *reg, u8 *bit)
1506 {
1507 struct rockchip_pinctrl *info = bank->drvdata;
1508
1509 /* The first 32 pins of the first bank are located in PMU */
1510 if (bank->bank_num == 0) {
1511 *regmap = info->regmap_pmu;
1512 *reg = RK3368_DRV_PMU_OFFSET;
1513
1514 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1515 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1516 *bit *= RK3288_DRV_BITS_PER_PIN;
1517 } else {
1518 *regmap = info->regmap_base;
1519 *reg = RK3368_DRV_GRF_OFFSET;
1520
1521 /* correct the offset, as we're starting with the 2nd bank */
1522 *reg -= 0x10;
1523 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1524 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1525
1526 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1527 *bit *= RK3288_DRV_BITS_PER_PIN;
1528 }
1529
1530 return 0;
1531 }
1532
1533 #define RK3399_PULL_GRF_OFFSET 0xe040
1534 #define RK3399_PULL_PMU_OFFSET 0x40
1535 #define RK3399_DRV_3BITS_PER_PIN 3
1536
rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1537 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1538 int pin_num, struct regmap **regmap,
1539 int *reg, u8 *bit)
1540 {
1541 struct rockchip_pinctrl *info = bank->drvdata;
1542
1543 /* The bank0:16 and bank1:32 pins are located in PMU */
1544 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1545 *regmap = info->regmap_pmu;
1546 *reg = RK3399_PULL_PMU_OFFSET;
1547
1548 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1549
1550 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1551 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1552 *bit *= RK3188_PULL_BITS_PER_PIN;
1553 } else {
1554 *regmap = info->regmap_base;
1555 *reg = RK3399_PULL_GRF_OFFSET;
1556
1557 /* correct the offset, as we're starting with the 3rd bank */
1558 *reg -= 0x20;
1559 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1560 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1561
1562 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1563 *bit *= RK3188_PULL_BITS_PER_PIN;
1564 }
1565
1566 return 0;
1567 }
1568
rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1569 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1570 int pin_num, struct regmap **regmap,
1571 int *reg, u8 *bit)
1572 {
1573 struct rockchip_pinctrl *info = bank->drvdata;
1574 int drv_num = (pin_num / 8);
1575
1576 /* The bank0:16 and bank1:32 pins are located in PMU */
1577 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1578 *regmap = info->regmap_pmu;
1579 else
1580 *regmap = info->regmap_base;
1581
1582 *reg = bank->drv[drv_num].offset;
1583 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1584 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1585 *bit = (pin_num % 8) * 3;
1586 else
1587 *bit = (pin_num % 8) * 2;
1588
1589 return 0;
1590 }
1591
1592 #define RK3568_PULL_PMU_OFFSET 0x20
1593 #define RK3568_PULL_GRF_OFFSET 0x80
1594 #define RK3568_PULL_BITS_PER_PIN 2
1595 #define RK3568_PULL_PINS_PER_REG 8
1596 #define RK3568_PULL_BANK_STRIDE 0x10
1597
rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1598 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1599 int pin_num, struct regmap **regmap,
1600 int *reg, u8 *bit)
1601 {
1602 struct rockchip_pinctrl *info = bank->drvdata;
1603
1604 if (bank->bank_num == 0) {
1605 *regmap = info->regmap_pmu;
1606 *reg = RK3568_PULL_PMU_OFFSET;
1607 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1608 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1609
1610 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
1611 *bit *= RK3568_PULL_BITS_PER_PIN;
1612 } else {
1613 *regmap = info->regmap_base;
1614 *reg = RK3568_PULL_GRF_OFFSET;
1615 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1616 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1617
1618 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1619 *bit *= RK3568_PULL_BITS_PER_PIN;
1620 }
1621
1622 return 0;
1623 }
1624
1625 #define RK3568_DRV_PMU_OFFSET 0x70
1626 #define RK3568_DRV_GRF_OFFSET 0x200
1627 #define RK3568_DRV_BITS_PER_PIN 8
1628 #define RK3568_DRV_PINS_PER_REG 2
1629 #define RK3568_DRV_BANK_STRIDE 0x40
1630
rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1631 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1632 int pin_num, struct regmap **regmap,
1633 int *reg, u8 *bit)
1634 {
1635 struct rockchip_pinctrl *info = bank->drvdata;
1636
1637 /* The first 32 pins of the first bank are located in PMU */
1638 if (bank->bank_num == 0) {
1639 *regmap = info->regmap_pmu;
1640 *reg = RK3568_DRV_PMU_OFFSET;
1641 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1642
1643 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
1644 *bit *= RK3568_DRV_BITS_PER_PIN;
1645 } else {
1646 *regmap = info->regmap_base;
1647 *reg = RK3568_DRV_GRF_OFFSET;
1648 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
1649 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1650
1651 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
1652 *bit *= RK3568_DRV_BITS_PER_PIN;
1653 }
1654
1655 return 0;
1656 }
1657
1658 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1659 { 2, 4, 8, 12, -1, -1, -1, -1 },
1660 { 3, 6, 9, 12, -1, -1, -1, -1 },
1661 { 5, 10, 15, 20, -1, -1, -1, -1 },
1662 { 4, 6, 8, 10, 12, 14, 16, 18 },
1663 { 4, 7, 10, 13, 16, 19, 22, 26 }
1664 };
1665
rockchip_get_drive_perpin(struct rockchip_pin_bank * bank,int pin_num)1666 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1667 int pin_num)
1668 {
1669 struct rockchip_pinctrl *info = bank->drvdata;
1670 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1671 struct device *dev = info->dev;
1672 struct regmap *regmap;
1673 int reg, ret;
1674 u32 data, temp, rmask_bits;
1675 u8 bit;
1676 int drv_type = bank->drv[pin_num / 8].drv_type;
1677
1678 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1679 if (ret)
1680 return ret;
1681
1682 switch (drv_type) {
1683 case DRV_TYPE_IO_1V8_3V0_AUTO:
1684 case DRV_TYPE_IO_3V3_ONLY:
1685 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1686 switch (bit) {
1687 case 0 ... 12:
1688 /* regular case, nothing to do */
1689 break;
1690 case 15:
1691 /*
1692 * drive-strength offset is special, as it is
1693 * spread over 2 registers
1694 */
1695 ret = regmap_read(regmap, reg, &data);
1696 if (ret)
1697 return ret;
1698
1699 ret = regmap_read(regmap, reg + 0x4, &temp);
1700 if (ret)
1701 return ret;
1702
1703 /*
1704 * the bit data[15] contains bit 0 of the value
1705 * while temp[1:0] contains bits 2 and 1
1706 */
1707 data >>= 15;
1708 temp &= 0x3;
1709 temp <<= 1;
1710 data |= temp;
1711
1712 return rockchip_perpin_drv_list[drv_type][data];
1713 case 18 ... 21:
1714 /* setting fully enclosed in the second register */
1715 reg += 4;
1716 bit -= 16;
1717 break;
1718 default:
1719 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1720 bit, drv_type);
1721 return -EINVAL;
1722 }
1723
1724 break;
1725 case DRV_TYPE_IO_DEFAULT:
1726 case DRV_TYPE_IO_1V8_OR_3V0:
1727 case DRV_TYPE_IO_1V8_ONLY:
1728 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1729 break;
1730 default:
1731 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
1732 return -EINVAL;
1733 }
1734
1735 ret = regmap_read(regmap, reg, &data);
1736 if (ret)
1737 return ret;
1738
1739 data >>= bit;
1740 data &= (1 << rmask_bits) - 1;
1741
1742 return rockchip_perpin_drv_list[drv_type][data];
1743 }
1744
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)1745 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1746 int pin_num, int strength)
1747 {
1748 struct rockchip_pinctrl *info = bank->drvdata;
1749 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1750 struct device *dev = info->dev;
1751 struct regmap *regmap;
1752 int reg, ret, i;
1753 u32 data, rmask, rmask_bits, temp;
1754 u8 bit;
1755 int drv_type = bank->drv[pin_num / 8].drv_type;
1756
1757 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
1758 bank->bank_num, pin_num, strength);
1759
1760 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1761 if (ret)
1762 return ret;
1763 if (ctrl->type == RK3568) {
1764 rmask_bits = RK3568_DRV_BITS_PER_PIN;
1765 ret = (1 << (strength + 1)) - 1;
1766 goto config;
1767 }
1768
1769 ret = -EINVAL;
1770 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1771 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1772 ret = i;
1773 break;
1774 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1775 ret = rockchip_perpin_drv_list[drv_type][i];
1776 break;
1777 }
1778 }
1779
1780 if (ret < 0) {
1781 dev_err(dev, "unsupported driver strength %d\n", strength);
1782 return ret;
1783 }
1784
1785 switch (drv_type) {
1786 case DRV_TYPE_IO_1V8_3V0_AUTO:
1787 case DRV_TYPE_IO_3V3_ONLY:
1788 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1789 switch (bit) {
1790 case 0 ... 12:
1791 /* regular case, nothing to do */
1792 break;
1793 case 15:
1794 /*
1795 * drive-strength offset is special, as it is spread
1796 * over 2 registers, the bit data[15] contains bit 0
1797 * of the value while temp[1:0] contains bits 2 and 1
1798 */
1799 data = (ret & 0x1) << 15;
1800 temp = (ret >> 0x1) & 0x3;
1801
1802 rmask = BIT(15) | BIT(31);
1803 data |= BIT(31);
1804 ret = regmap_update_bits(regmap, reg, rmask, data);
1805 if (ret)
1806 return ret;
1807
1808 rmask = 0x3 | (0x3 << 16);
1809 temp |= (0x3 << 16);
1810 reg += 0x4;
1811 ret = regmap_update_bits(regmap, reg, rmask, temp);
1812
1813 return ret;
1814 case 18 ... 21:
1815 /* setting fully enclosed in the second register */
1816 reg += 4;
1817 bit -= 16;
1818 break;
1819 default:
1820 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1821 bit, drv_type);
1822 return -EINVAL;
1823 }
1824 break;
1825 case DRV_TYPE_IO_DEFAULT:
1826 case DRV_TYPE_IO_1V8_OR_3V0:
1827 case DRV_TYPE_IO_1V8_ONLY:
1828 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1829 break;
1830 default:
1831 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
1832 return -EINVAL;
1833 }
1834
1835 config:
1836 /* enable the write to the equivalent lower bits */
1837 data = ((1 << rmask_bits) - 1) << (bit + 16);
1838 rmask = data | (data >> 16);
1839 data |= (ret << bit);
1840
1841 ret = regmap_update_bits(regmap, reg, rmask, data);
1842
1843 return ret;
1844 }
1845
1846 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1847 {
1848 PIN_CONFIG_BIAS_DISABLE,
1849 PIN_CONFIG_BIAS_PULL_UP,
1850 PIN_CONFIG_BIAS_PULL_DOWN,
1851 PIN_CONFIG_BIAS_BUS_HOLD
1852 },
1853 {
1854 PIN_CONFIG_BIAS_DISABLE,
1855 PIN_CONFIG_BIAS_PULL_DOWN,
1856 PIN_CONFIG_BIAS_DISABLE,
1857 PIN_CONFIG_BIAS_PULL_UP
1858 },
1859 };
1860
rockchip_get_pull(struct rockchip_pin_bank * bank,int pin_num)1861 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1862 {
1863 struct rockchip_pinctrl *info = bank->drvdata;
1864 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1865 struct device *dev = info->dev;
1866 struct regmap *regmap;
1867 int reg, ret, pull_type;
1868 u8 bit;
1869 u32 data;
1870
1871 /* rk3066b does support any pulls */
1872 if (ctrl->type == RK3066B)
1873 return PIN_CONFIG_BIAS_DISABLE;
1874
1875 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1876 if (ret)
1877 return ret;
1878
1879 ret = regmap_read(regmap, reg, &data);
1880 if (ret)
1881 return ret;
1882
1883 switch (ctrl->type) {
1884 case RK2928:
1885 case RK3128:
1886 return !(data & BIT(bit))
1887 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1888 : PIN_CONFIG_BIAS_DISABLE;
1889 case PX30:
1890 case RV1108:
1891 case RK3188:
1892 case RK3288:
1893 case RK3308:
1894 case RK3368:
1895 case RK3399:
1896 case RK3568:
1897 pull_type = bank->pull_type[pin_num / 8];
1898 data >>= bit;
1899 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1900 /*
1901 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
1902 * where that pull up value becomes 3.
1903 */
1904 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
1905 if (data == 3)
1906 data = 1;
1907 }
1908
1909 return rockchip_pull_list[pull_type][data];
1910 default:
1911 dev_err(dev, "unsupported pinctrl type\n");
1912 return -EINVAL;
1913 };
1914 }
1915
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)1916 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1917 int pin_num, int pull)
1918 {
1919 struct rockchip_pinctrl *info = bank->drvdata;
1920 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1921 struct device *dev = info->dev;
1922 struct regmap *regmap;
1923 int reg, ret, i, pull_type;
1924 u8 bit;
1925 u32 data, rmask;
1926
1927 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
1928
1929 /* rk3066b does support any pulls */
1930 if (ctrl->type == RK3066B)
1931 return pull ? -EINVAL : 0;
1932
1933 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1934 if (ret)
1935 return ret;
1936
1937 switch (ctrl->type) {
1938 case RK2928:
1939 case RK3128:
1940 data = BIT(bit + 16);
1941 if (pull == PIN_CONFIG_BIAS_DISABLE)
1942 data |= BIT(bit);
1943 ret = regmap_write(regmap, reg, data);
1944 break;
1945 case PX30:
1946 case RV1108:
1947 case RK3188:
1948 case RK3288:
1949 case RK3308:
1950 case RK3368:
1951 case RK3399:
1952 case RK3568:
1953 pull_type = bank->pull_type[pin_num / 8];
1954 ret = -EINVAL;
1955 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1956 i++) {
1957 if (rockchip_pull_list[pull_type][i] == pull) {
1958 ret = i;
1959 break;
1960 }
1961 }
1962 /*
1963 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
1964 * where that pull up value becomes 3.
1965 */
1966 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
1967 if (ret == 1)
1968 ret = 3;
1969 }
1970
1971 if (ret < 0) {
1972 dev_err(dev, "unsupported pull setting %d\n", pull);
1973 return ret;
1974 }
1975
1976 /* enable the write to the equivalent lower bits */
1977 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1978 rmask = data | (data >> 16);
1979 data |= (ret << bit);
1980
1981 ret = regmap_update_bits(regmap, reg, rmask, data);
1982 break;
1983 default:
1984 dev_err(dev, "unsupported pinctrl type\n");
1985 return -EINVAL;
1986 }
1987
1988 return ret;
1989 }
1990
1991 #define RK3328_SCHMITT_BITS_PER_PIN 1
1992 #define RK3328_SCHMITT_PINS_PER_REG 16
1993 #define RK3328_SCHMITT_BANK_STRIDE 8
1994 #define RK3328_SCHMITT_GRF_OFFSET 0x380
1995
rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1996 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1997 int pin_num,
1998 struct regmap **regmap,
1999 int *reg, u8 *bit)
2000 {
2001 struct rockchip_pinctrl *info = bank->drvdata;
2002
2003 *regmap = info->regmap_base;
2004 *reg = RK3328_SCHMITT_GRF_OFFSET;
2005
2006 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2007 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2008 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2009
2010 return 0;
2011 }
2012
2013 #define RK3568_SCHMITT_BITS_PER_PIN 2
2014 #define RK3568_SCHMITT_PINS_PER_REG 8
2015 #define RK3568_SCHMITT_BANK_STRIDE 0x10
2016 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
2017 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
2018
rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2019 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2020 int pin_num,
2021 struct regmap **regmap,
2022 int *reg, u8 *bit)
2023 {
2024 struct rockchip_pinctrl *info = bank->drvdata;
2025
2026 if (bank->bank_num == 0) {
2027 *regmap = info->regmap_pmu;
2028 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
2029 } else {
2030 *regmap = info->regmap_base;
2031 *reg = RK3568_SCHMITT_GRF_OFFSET;
2032 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
2033 }
2034
2035 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
2036 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
2037 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
2038
2039 return 0;
2040 }
2041
rockchip_get_schmitt(struct rockchip_pin_bank * bank,int pin_num)2042 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2043 {
2044 struct rockchip_pinctrl *info = bank->drvdata;
2045 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2046 struct regmap *regmap;
2047 int reg, ret;
2048 u8 bit;
2049 u32 data;
2050
2051 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2052 if (ret)
2053 return ret;
2054
2055 ret = regmap_read(regmap, reg, &data);
2056 if (ret)
2057 return ret;
2058
2059 data >>= bit;
2060 switch (ctrl->type) {
2061 case RK3568:
2062 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2063 default:
2064 break;
2065 }
2066
2067 return data & 0x1;
2068 }
2069
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)2070 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2071 int pin_num, int enable)
2072 {
2073 struct rockchip_pinctrl *info = bank->drvdata;
2074 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2075 struct device *dev = info->dev;
2076 struct regmap *regmap;
2077 int reg, ret;
2078 u8 bit;
2079 u32 data, rmask;
2080
2081 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
2082 bank->bank_num, pin_num, enable);
2083
2084 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2085 if (ret)
2086 return ret;
2087
2088 /* enable the write to the equivalent lower bits */
2089 switch (ctrl->type) {
2090 case RK3568:
2091 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2092 rmask = data | (data >> 16);
2093 data |= ((enable ? 0x2 : 0x1) << bit);
2094 break;
2095 default:
2096 data = BIT(bit + 16) | (enable << bit);
2097 rmask = BIT(bit + 16) | BIT(bit);
2098 break;
2099 }
2100
2101 return regmap_update_bits(regmap, reg, rmask, data);
2102 }
2103
2104 /*
2105 * Pinmux_ops handling
2106 */
2107
rockchip_pmx_get_funcs_count(struct pinctrl_dev * pctldev)2108 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2109 {
2110 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2111
2112 return info->nfunctions;
2113 }
2114
rockchip_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)2115 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2116 unsigned selector)
2117 {
2118 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2119
2120 return info->functions[selector].name;
2121 }
2122
rockchip_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)2123 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2124 unsigned selector, const char * const **groups,
2125 unsigned * const num_groups)
2126 {
2127 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2128
2129 *groups = info->functions[selector].groups;
2130 *num_groups = info->functions[selector].ngroups;
2131
2132 return 0;
2133 }
2134
rockchip_pmx_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned group)2135 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2136 unsigned group)
2137 {
2138 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2139 const unsigned int *pins = info->groups[group].pins;
2140 const struct rockchip_pin_config *data = info->groups[group].data;
2141 struct device *dev = info->dev;
2142 struct rockchip_pin_bank *bank;
2143 int cnt, ret = 0;
2144
2145 dev_dbg(dev, "enable function %s group %s\n",
2146 info->functions[selector].name, info->groups[group].name);
2147
2148 /*
2149 * for each pin in the pin group selected, program the corresponding
2150 * pin function number in the config register.
2151 */
2152 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2153 bank = pin_to_bank(info, pins[cnt]);
2154 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2155 data[cnt].func);
2156 if (ret)
2157 break;
2158 }
2159
2160 if (ret) {
2161 /* revert the already done pin settings */
2162 for (cnt--; cnt >= 0; cnt--)
2163 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2164
2165 return ret;
2166 }
2167
2168 return 0;
2169 }
2170
rockchip_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset,bool input)2171 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2172 struct pinctrl_gpio_range *range,
2173 unsigned offset,
2174 bool input)
2175 {
2176 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2177 struct rockchip_pin_bank *bank;
2178
2179 bank = pin_to_bank(info, offset);
2180 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
2181 }
2182
2183 static const struct pinmux_ops rockchip_pmx_ops = {
2184 .get_functions_count = rockchip_pmx_get_funcs_count,
2185 .get_function_name = rockchip_pmx_get_func_name,
2186 .get_function_groups = rockchip_pmx_get_groups,
2187 .set_mux = rockchip_pmx_set,
2188 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2189 };
2190
2191 /*
2192 * Pinconf_ops handling
2193 */
2194
rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl * ctrl,enum pin_config_param pull)2195 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2196 enum pin_config_param pull)
2197 {
2198 switch (ctrl->type) {
2199 case RK2928:
2200 case RK3128:
2201 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2202 pull == PIN_CONFIG_BIAS_DISABLE);
2203 case RK3066B:
2204 return pull ? false : true;
2205 case PX30:
2206 case RV1108:
2207 case RK3188:
2208 case RK3288:
2209 case RK3308:
2210 case RK3368:
2211 case RK3399:
2212 case RK3568:
2213 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2214 }
2215
2216 return false;
2217 }
2218
rockchip_pinconf_defer_pin(struct rockchip_pin_bank * bank,unsigned int pin,u32 param,u32 arg)2219 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
2220 unsigned int pin, u32 param, u32 arg)
2221 {
2222 struct rockchip_pin_deferred *cfg;
2223
2224 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2225 if (!cfg)
2226 return -ENOMEM;
2227
2228 cfg->pin = pin;
2229 cfg->param = param;
2230 cfg->arg = arg;
2231
2232 list_add_tail(&cfg->head, &bank->deferred_pins);
2233
2234 return 0;
2235 }
2236
2237 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned num_configs)2238 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2239 unsigned long *configs, unsigned num_configs)
2240 {
2241 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2242 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2243 struct gpio_chip *gpio = &bank->gpio_chip;
2244 enum pin_config_param param;
2245 u32 arg;
2246 int i;
2247 int rc;
2248
2249 for (i = 0; i < num_configs; i++) {
2250 param = pinconf_to_config_param(configs[i]);
2251 arg = pinconf_to_config_argument(configs[i]);
2252
2253 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
2254 /*
2255 * Check for gpio driver not being probed yet.
2256 * The lock makes sure that either gpio-probe has completed
2257 * or the gpio driver hasn't probed yet.
2258 */
2259 mutex_lock(&bank->deferred_lock);
2260 if (!gpio || !gpio->direction_output) {
2261 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
2262 arg);
2263 mutex_unlock(&bank->deferred_lock);
2264 if (rc)
2265 return rc;
2266
2267 break;
2268 }
2269 mutex_unlock(&bank->deferred_lock);
2270 }
2271
2272 switch (param) {
2273 case PIN_CONFIG_BIAS_DISABLE:
2274 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2275 param);
2276 if (rc)
2277 return rc;
2278 break;
2279 case PIN_CONFIG_BIAS_PULL_UP:
2280 case PIN_CONFIG_BIAS_PULL_DOWN:
2281 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2282 case PIN_CONFIG_BIAS_BUS_HOLD:
2283 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2284 return -ENOTSUPP;
2285
2286 if (!arg)
2287 return -EINVAL;
2288
2289 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2290 param);
2291 if (rc)
2292 return rc;
2293 break;
2294 case PIN_CONFIG_OUTPUT:
2295 rc = rockchip_set_mux(bank, pin - bank->pin_base,
2296 RK_FUNC_GPIO);
2297 if (rc != RK_FUNC_GPIO)
2298 return -EINVAL;
2299
2300 rc = gpio->direction_output(gpio, pin - bank->pin_base,
2301 arg);
2302 if (rc)
2303 return rc;
2304 break;
2305 case PIN_CONFIG_INPUT_ENABLE:
2306 rc = rockchip_set_mux(bank, pin - bank->pin_base,
2307 RK_FUNC_GPIO);
2308 if (rc != RK_FUNC_GPIO)
2309 return -EINVAL;
2310
2311 rc = gpio->direction_input(gpio, pin - bank->pin_base);
2312 if (rc)
2313 return rc;
2314 break;
2315 case PIN_CONFIG_DRIVE_STRENGTH:
2316 /* rk3288 is the first with per-pin drive-strength */
2317 if (!info->ctrl->drv_calc_reg)
2318 return -ENOTSUPP;
2319
2320 rc = rockchip_set_drive_perpin(bank,
2321 pin - bank->pin_base, arg);
2322 if (rc < 0)
2323 return rc;
2324 break;
2325 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2326 if (!info->ctrl->schmitt_calc_reg)
2327 return -ENOTSUPP;
2328
2329 rc = rockchip_set_schmitt(bank,
2330 pin - bank->pin_base, arg);
2331 if (rc < 0)
2332 return rc;
2333 break;
2334 default:
2335 return -ENOTSUPP;
2336 break;
2337 }
2338 } /* for each config */
2339
2340 return 0;
2341 }
2342
2343 /* get the pin config settings for a specified pin */
rockchip_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)2344 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2345 unsigned long *config)
2346 {
2347 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2348 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2349 struct gpio_chip *gpio = &bank->gpio_chip;
2350 enum pin_config_param param = pinconf_to_config_param(*config);
2351 u16 arg;
2352 int rc;
2353
2354 switch (param) {
2355 case PIN_CONFIG_BIAS_DISABLE:
2356 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2357 return -EINVAL;
2358
2359 arg = 0;
2360 break;
2361 case PIN_CONFIG_BIAS_PULL_UP:
2362 case PIN_CONFIG_BIAS_PULL_DOWN:
2363 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2364 case PIN_CONFIG_BIAS_BUS_HOLD:
2365 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2366 return -ENOTSUPP;
2367
2368 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2369 return -EINVAL;
2370
2371 arg = 1;
2372 break;
2373 case PIN_CONFIG_OUTPUT:
2374 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2375 if (rc != RK_FUNC_GPIO)
2376 return -EINVAL;
2377
2378 if (!gpio || !gpio->get) {
2379 arg = 0;
2380 break;
2381 }
2382
2383 rc = gpio->get(gpio, pin - bank->pin_base);
2384 if (rc < 0)
2385 return rc;
2386
2387 arg = rc ? 1 : 0;
2388 break;
2389 case PIN_CONFIG_DRIVE_STRENGTH:
2390 /* rk3288 is the first with per-pin drive-strength */
2391 if (!info->ctrl->drv_calc_reg)
2392 return -ENOTSUPP;
2393
2394 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2395 if (rc < 0)
2396 return rc;
2397
2398 arg = rc;
2399 break;
2400 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2401 if (!info->ctrl->schmitt_calc_reg)
2402 return -ENOTSUPP;
2403
2404 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2405 if (rc < 0)
2406 return rc;
2407
2408 arg = rc;
2409 break;
2410 default:
2411 return -ENOTSUPP;
2412 break;
2413 }
2414
2415 *config = pinconf_to_config_packed(param, arg);
2416
2417 return 0;
2418 }
2419
2420 static const struct pinconf_ops rockchip_pinconf_ops = {
2421 .pin_config_get = rockchip_pinconf_get,
2422 .pin_config_set = rockchip_pinconf_set,
2423 .is_generic = true,
2424 };
2425
2426 static const struct of_device_id rockchip_bank_match[] = {
2427 { .compatible = "rockchip,gpio-bank" },
2428 { .compatible = "rockchip,rk3188-gpio-bank0" },
2429 {},
2430 };
2431
rockchip_pinctrl_child_count(struct rockchip_pinctrl * info,struct device_node * np)2432 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2433 struct device_node *np)
2434 {
2435 struct device_node *child;
2436
2437 for_each_child_of_node(np, child) {
2438 if (of_match_node(rockchip_bank_match, child))
2439 continue;
2440
2441 info->nfunctions++;
2442 info->ngroups += of_get_child_count(child);
2443 }
2444 }
2445
rockchip_pinctrl_parse_groups(struct device_node * np,struct rockchip_pin_group * grp,struct rockchip_pinctrl * info,u32 index)2446 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2447 struct rockchip_pin_group *grp,
2448 struct rockchip_pinctrl *info,
2449 u32 index)
2450 {
2451 struct device *dev = info->dev;
2452 struct rockchip_pin_bank *bank;
2453 int size;
2454 const __be32 *list;
2455 int num;
2456 int i, j;
2457 int ret;
2458
2459 dev_dbg(dev, "group(%d): %pOFn\n", index, np);
2460
2461 /* Initialise group */
2462 grp->name = np->name;
2463
2464 /*
2465 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2466 * do sanity check and calculate pins number
2467 */
2468 list = of_get_property(np, "rockchip,pins", &size);
2469 /* we do not check return since it's safe node passed down */
2470 size /= sizeof(*list);
2471 if (!size || size % 4) {
2472 dev_err(dev, "wrong pins number or pins and configs should be by 4\n");
2473 return -EINVAL;
2474 }
2475
2476 grp->npins = size / 4;
2477
2478 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
2479 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
2480 if (!grp->pins || !grp->data)
2481 return -ENOMEM;
2482
2483 for (i = 0, j = 0; i < size; i += 4, j++) {
2484 const __be32 *phandle;
2485 struct device_node *np_config;
2486
2487 num = be32_to_cpu(*list++);
2488 bank = bank_num_to_bank(info, num);
2489 if (IS_ERR(bank))
2490 return PTR_ERR(bank);
2491
2492 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2493 grp->data[j].func = be32_to_cpu(*list++);
2494
2495 phandle = list++;
2496 if (!phandle)
2497 return -EINVAL;
2498
2499 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2500 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2501 &grp->data[j].configs, &grp->data[j].nconfigs);
2502 of_node_put(np_config);
2503 if (ret)
2504 return ret;
2505 }
2506
2507 return 0;
2508 }
2509
rockchip_pinctrl_parse_functions(struct device_node * np,struct rockchip_pinctrl * info,u32 index)2510 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2511 struct rockchip_pinctrl *info,
2512 u32 index)
2513 {
2514 struct device *dev = info->dev;
2515 struct device_node *child;
2516 struct rockchip_pmx_func *func;
2517 struct rockchip_pin_group *grp;
2518 int ret;
2519 static u32 grp_index;
2520 u32 i = 0;
2521
2522 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
2523
2524 func = &info->functions[index];
2525
2526 /* Initialise function */
2527 func->name = np->name;
2528 func->ngroups = of_get_child_count(np);
2529 if (func->ngroups <= 0)
2530 return 0;
2531
2532 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
2533 if (!func->groups)
2534 return -ENOMEM;
2535
2536 for_each_child_of_node(np, child) {
2537 func->groups[i] = child->name;
2538 grp = &info->groups[grp_index++];
2539 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2540 if (ret) {
2541 of_node_put(child);
2542 return ret;
2543 }
2544 }
2545
2546 return 0;
2547 }
2548
rockchip_pinctrl_parse_dt(struct platform_device * pdev,struct rockchip_pinctrl * info)2549 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2550 struct rockchip_pinctrl *info)
2551 {
2552 struct device *dev = &pdev->dev;
2553 struct device_node *np = dev->of_node;
2554 struct device_node *child;
2555 int ret;
2556 int i;
2557
2558 rockchip_pinctrl_child_count(info, np);
2559
2560 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
2561 dev_dbg(dev, "ngroups = %d\n", info->ngroups);
2562
2563 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
2564 if (!info->functions)
2565 return -ENOMEM;
2566
2567 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
2568 if (!info->groups)
2569 return -ENOMEM;
2570
2571 i = 0;
2572
2573 for_each_child_of_node(np, child) {
2574 if (of_match_node(rockchip_bank_match, child))
2575 continue;
2576
2577 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2578 if (ret) {
2579 dev_err(dev, "failed to parse function\n");
2580 of_node_put(child);
2581 return ret;
2582 }
2583 }
2584
2585 return 0;
2586 }
2587
rockchip_pinctrl_register(struct platform_device * pdev,struct rockchip_pinctrl * info)2588 static int rockchip_pinctrl_register(struct platform_device *pdev,
2589 struct rockchip_pinctrl *info)
2590 {
2591 struct pinctrl_desc *ctrldesc = &info->pctl;
2592 struct pinctrl_pin_desc *pindesc, *pdesc;
2593 struct rockchip_pin_bank *pin_bank;
2594 struct device *dev = &pdev->dev;
2595 int pin, bank, ret;
2596 int k;
2597
2598 ctrldesc->name = "rockchip-pinctrl";
2599 ctrldesc->owner = THIS_MODULE;
2600 ctrldesc->pctlops = &rockchip_pctrl_ops;
2601 ctrldesc->pmxops = &rockchip_pmx_ops;
2602 ctrldesc->confops = &rockchip_pinconf_ops;
2603
2604 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
2605 if (!pindesc)
2606 return -ENOMEM;
2607
2608 ctrldesc->pins = pindesc;
2609 ctrldesc->npins = info->ctrl->nr_pins;
2610
2611 pdesc = pindesc;
2612 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
2613 pin_bank = &info->ctrl->pin_banks[bank];
2614 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2615 pdesc->number = k;
2616 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2617 pin_bank->name, pin);
2618 pdesc++;
2619 }
2620
2621 INIT_LIST_HEAD(&pin_bank->deferred_pins);
2622 mutex_init(&pin_bank->deferred_lock);
2623 }
2624
2625 ret = rockchip_pinctrl_parse_dt(pdev, info);
2626 if (ret)
2627 return ret;
2628
2629 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
2630 if (IS_ERR(info->pctl_dev)) {
2631 dev_err(dev, "could not register pinctrl driver\n");
2632 return PTR_ERR(info->pctl_dev);
2633 }
2634
2635 return 0;
2636 }
2637
2638 static const struct of_device_id rockchip_pinctrl_dt_match[];
2639
2640 /* retrieve the soc specific data */
rockchip_pinctrl_get_soc_data(struct rockchip_pinctrl * d,struct platform_device * pdev)2641 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2642 struct rockchip_pinctrl *d,
2643 struct platform_device *pdev)
2644 {
2645 struct device *dev = &pdev->dev;
2646 struct device_node *node = dev->of_node;
2647 const struct of_device_id *match;
2648 struct rockchip_pin_ctrl *ctrl;
2649 struct rockchip_pin_bank *bank;
2650 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2651
2652 match = of_match_node(rockchip_pinctrl_dt_match, node);
2653 ctrl = (struct rockchip_pin_ctrl *)match->data;
2654
2655 grf_offs = ctrl->grf_mux_offset;
2656 pmu_offs = ctrl->pmu_mux_offset;
2657 drv_pmu_offs = ctrl->pmu_drv_offset;
2658 drv_grf_offs = ctrl->grf_drv_offset;
2659 bank = ctrl->pin_banks;
2660 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2661 int bank_pins = 0;
2662
2663 raw_spin_lock_init(&bank->slock);
2664 bank->drvdata = d;
2665 bank->pin_base = ctrl->nr_pins;
2666 ctrl->nr_pins += bank->nr_pins;
2667
2668 /* calculate iomux and drv offsets */
2669 for (j = 0; j < 4; j++) {
2670 struct rockchip_iomux *iom = &bank->iomux[j];
2671 struct rockchip_drv *drv = &bank->drv[j];
2672 int inc;
2673
2674 if (bank_pins >= bank->nr_pins)
2675 break;
2676
2677 /* preset iomux offset value, set new start value */
2678 if (iom->offset >= 0) {
2679 if (iom->type & IOMUX_SOURCE_PMU)
2680 pmu_offs = iom->offset;
2681 else
2682 grf_offs = iom->offset;
2683 } else { /* set current iomux offset */
2684 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2685 pmu_offs : grf_offs;
2686 }
2687
2688 /* preset drv offset value, set new start value */
2689 if (drv->offset >= 0) {
2690 if (iom->type & IOMUX_SOURCE_PMU)
2691 drv_pmu_offs = drv->offset;
2692 else
2693 drv_grf_offs = drv->offset;
2694 } else { /* set current drv offset */
2695 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2696 drv_pmu_offs : drv_grf_offs;
2697 }
2698
2699 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2700 i, j, iom->offset, drv->offset);
2701
2702 /*
2703 * Increase offset according to iomux width.
2704 * 4bit iomux'es are spread over two registers.
2705 */
2706 inc = (iom->type & (IOMUX_WIDTH_4BIT |
2707 IOMUX_WIDTH_3BIT |
2708 IOMUX_WIDTH_2BIT)) ? 8 : 4;
2709 if (iom->type & IOMUX_SOURCE_PMU)
2710 pmu_offs += inc;
2711 else
2712 grf_offs += inc;
2713
2714 /*
2715 * Increase offset according to drv width.
2716 * 3bit drive-strenth'es are spread over two registers.
2717 */
2718 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2719 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2720 inc = 8;
2721 else
2722 inc = 4;
2723
2724 if (iom->type & IOMUX_SOURCE_PMU)
2725 drv_pmu_offs += inc;
2726 else
2727 drv_grf_offs += inc;
2728
2729 bank_pins += 8;
2730 }
2731
2732 /* calculate the per-bank recalced_mask */
2733 for (j = 0; j < ctrl->niomux_recalced; j++) {
2734 int pin = 0;
2735
2736 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
2737 pin = ctrl->iomux_recalced[j].pin;
2738 bank->recalced_mask |= BIT(pin);
2739 }
2740 }
2741
2742 /* calculate the per-bank route_mask */
2743 for (j = 0; j < ctrl->niomux_routes; j++) {
2744 int pin = 0;
2745
2746 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
2747 pin = ctrl->iomux_routes[j].pin;
2748 bank->route_mask |= BIT(pin);
2749 }
2750 }
2751 }
2752
2753 return ctrl;
2754 }
2755
2756 #define RK3288_GRF_GPIO6C_IOMUX 0x64
2757 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2758
2759 static u32 rk3288_grf_gpio6c_iomux;
2760
rockchip_pinctrl_suspend(struct device * dev)2761 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2762 {
2763 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2764 int ret = pinctrl_force_sleep(info->pctl_dev);
2765
2766 if (ret)
2767 return ret;
2768
2769 /*
2770 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2771 * the setting here, and restore it at resume.
2772 */
2773 if (info->ctrl->type == RK3288) {
2774 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2775 &rk3288_grf_gpio6c_iomux);
2776 if (ret) {
2777 pinctrl_force_default(info->pctl_dev);
2778 return ret;
2779 }
2780 }
2781
2782 return 0;
2783 }
2784
rockchip_pinctrl_resume(struct device * dev)2785 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2786 {
2787 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2788 int ret;
2789
2790 if (info->ctrl->type == RK3288) {
2791 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2792 rk3288_grf_gpio6c_iomux |
2793 GPIO6C6_SEL_WRITE_ENABLE);
2794 if (ret)
2795 return ret;
2796 }
2797
2798 return pinctrl_force_default(info->pctl_dev);
2799 }
2800
2801 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2802 rockchip_pinctrl_resume);
2803
rockchip_pinctrl_probe(struct platform_device * pdev)2804 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2805 {
2806 struct rockchip_pinctrl *info;
2807 struct device *dev = &pdev->dev;
2808 struct device_node *np = dev->of_node, *node;
2809 struct rockchip_pin_ctrl *ctrl;
2810 struct resource *res;
2811 void __iomem *base;
2812 int ret;
2813
2814 if (!dev->of_node) {
2815 dev_err(dev, "device tree node not found\n");
2816 return -ENODEV;
2817 }
2818
2819 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2820 if (!info)
2821 return -ENOMEM;
2822
2823 info->dev = dev;
2824
2825 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2826 if (!ctrl) {
2827 dev_err(dev, "driver data not available\n");
2828 return -EINVAL;
2829 }
2830 info->ctrl = ctrl;
2831
2832 node = of_parse_phandle(np, "rockchip,grf", 0);
2833 if (node) {
2834 info->regmap_base = syscon_node_to_regmap(node);
2835 of_node_put(node);
2836 if (IS_ERR(info->regmap_base))
2837 return PTR_ERR(info->regmap_base);
2838 } else {
2839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2840 base = devm_ioremap_resource(&pdev->dev, res);
2841 if (IS_ERR(base))
2842 return PTR_ERR(base);
2843
2844 rockchip_regmap_config.max_register = resource_size(res) - 4;
2845 rockchip_regmap_config.name = "rockchip,pinctrl";
2846 info->regmap_base =
2847 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
2848
2849 /* to check for the old dt-bindings */
2850 info->reg_size = resource_size(res);
2851
2852 /* Honor the old binding, with pull registers as 2nd resource */
2853 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2854 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2855 base = devm_ioremap_resource(&pdev->dev, res);
2856 if (IS_ERR(base))
2857 return PTR_ERR(base);
2858
2859 rockchip_regmap_config.max_register = resource_size(res) - 4;
2860 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2861 info->regmap_pull =
2862 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
2863 }
2864 }
2865
2866 /* try to find the optional reference to the pmu syscon */
2867 node = of_parse_phandle(np, "rockchip,pmu", 0);
2868 if (node) {
2869 info->regmap_pmu = syscon_node_to_regmap(node);
2870 of_node_put(node);
2871 if (IS_ERR(info->regmap_pmu))
2872 return PTR_ERR(info->regmap_pmu);
2873 }
2874
2875 ret = rockchip_pinctrl_register(pdev, info);
2876 if (ret)
2877 return ret;
2878
2879 platform_set_drvdata(pdev, info);
2880
2881 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
2882 if (ret) {
2883 dev_err(dev, "failed to register gpio device\n");
2884 return ret;
2885 }
2886
2887 return 0;
2888 }
2889
rockchip_pinctrl_remove(struct platform_device * pdev)2890 static int rockchip_pinctrl_remove(struct platform_device *pdev)
2891 {
2892 struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
2893 struct rockchip_pin_bank *bank;
2894 struct rockchip_pin_deferred *cfg;
2895 int i;
2896
2897 of_platform_depopulate(&pdev->dev);
2898
2899 for (i = 0; i < info->ctrl->nr_banks; i++) {
2900 bank = &info->ctrl->pin_banks[i];
2901
2902 mutex_lock(&bank->deferred_lock);
2903 while (!list_empty(&bank->deferred_pins)) {
2904 cfg = list_first_entry(&bank->deferred_pins,
2905 struct rockchip_pin_deferred, head);
2906 list_del(&cfg->head);
2907 kfree(cfg);
2908 }
2909 mutex_unlock(&bank->deferred_lock);
2910 }
2911
2912 return 0;
2913 }
2914
2915 static struct rockchip_pin_bank px30_pin_banks[] = {
2916 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2917 IOMUX_SOURCE_PMU,
2918 IOMUX_SOURCE_PMU,
2919 IOMUX_SOURCE_PMU
2920 ),
2921 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
2922 IOMUX_WIDTH_4BIT,
2923 IOMUX_WIDTH_4BIT,
2924 IOMUX_WIDTH_4BIT
2925 ),
2926 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
2927 IOMUX_WIDTH_4BIT,
2928 IOMUX_WIDTH_4BIT,
2929 IOMUX_WIDTH_4BIT
2930 ),
2931 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
2932 IOMUX_WIDTH_4BIT,
2933 IOMUX_WIDTH_4BIT,
2934 IOMUX_WIDTH_4BIT
2935 ),
2936 };
2937
2938 static struct rockchip_pin_ctrl px30_pin_ctrl = {
2939 .pin_banks = px30_pin_banks,
2940 .nr_banks = ARRAY_SIZE(px30_pin_banks),
2941 .label = "PX30-GPIO",
2942 .type = PX30,
2943 .grf_mux_offset = 0x0,
2944 .pmu_mux_offset = 0x0,
2945 .iomux_routes = px30_mux_route_data,
2946 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
2947 .pull_calc_reg = px30_calc_pull_reg_and_bit,
2948 .drv_calc_reg = px30_calc_drv_reg_and_bit,
2949 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
2950 };
2951
2952 static struct rockchip_pin_bank rv1108_pin_banks[] = {
2953 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2954 IOMUX_SOURCE_PMU,
2955 IOMUX_SOURCE_PMU,
2956 IOMUX_SOURCE_PMU),
2957 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2958 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2959 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2960 };
2961
2962 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
2963 .pin_banks = rv1108_pin_banks,
2964 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
2965 .label = "RV1108-GPIO",
2966 .type = RV1108,
2967 .grf_mux_offset = 0x10,
2968 .pmu_mux_offset = 0x0,
2969 .iomux_recalced = rv1108_mux_recalced_data,
2970 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
2971 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
2972 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
2973 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
2974 };
2975
2976 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2977 PIN_BANK(0, 32, "gpio0"),
2978 PIN_BANK(1, 32, "gpio1"),
2979 PIN_BANK(2, 32, "gpio2"),
2980 PIN_BANK(3, 32, "gpio3"),
2981 };
2982
2983 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2984 .pin_banks = rk2928_pin_banks,
2985 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2986 .label = "RK2928-GPIO",
2987 .type = RK2928,
2988 .grf_mux_offset = 0xa8,
2989 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2990 };
2991
2992 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2993 PIN_BANK(0, 32, "gpio0"),
2994 PIN_BANK(1, 32, "gpio1"),
2995 PIN_BANK(2, 32, "gpio2"),
2996 };
2997
2998 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2999 .pin_banks = rk3036_pin_banks,
3000 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3001 .label = "RK3036-GPIO",
3002 .type = RK2928,
3003 .grf_mux_offset = 0xa8,
3004 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3005 };
3006
3007 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3008 PIN_BANK(0, 32, "gpio0"),
3009 PIN_BANK(1, 32, "gpio1"),
3010 PIN_BANK(2, 32, "gpio2"),
3011 PIN_BANK(3, 32, "gpio3"),
3012 PIN_BANK(4, 32, "gpio4"),
3013 PIN_BANK(6, 16, "gpio6"),
3014 };
3015
3016 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3017 .pin_banks = rk3066a_pin_banks,
3018 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3019 .label = "RK3066a-GPIO",
3020 .type = RK2928,
3021 .grf_mux_offset = 0xa8,
3022 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3023 };
3024
3025 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3026 PIN_BANK(0, 32, "gpio0"),
3027 PIN_BANK(1, 32, "gpio1"),
3028 PIN_BANK(2, 32, "gpio2"),
3029 PIN_BANK(3, 32, "gpio3"),
3030 };
3031
3032 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3033 .pin_banks = rk3066b_pin_banks,
3034 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3035 .label = "RK3066b-GPIO",
3036 .type = RK3066B,
3037 .grf_mux_offset = 0x60,
3038 };
3039
3040 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3041 PIN_BANK(0, 32, "gpio0"),
3042 PIN_BANK(1, 32, "gpio1"),
3043 PIN_BANK(2, 32, "gpio2"),
3044 PIN_BANK(3, 32, "gpio3"),
3045 };
3046
3047 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3048 .pin_banks = rk3128_pin_banks,
3049 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3050 .label = "RK3128-GPIO",
3051 .type = RK3128,
3052 .grf_mux_offset = 0xa8,
3053 .iomux_recalced = rk3128_mux_recalced_data,
3054 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3055 .iomux_routes = rk3128_mux_route_data,
3056 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3057 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3058 };
3059
3060 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3061 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3062 PIN_BANK(1, 32, "gpio1"),
3063 PIN_BANK(2, 32, "gpio2"),
3064 PIN_BANK(3, 32, "gpio3"),
3065 };
3066
3067 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3068 .pin_banks = rk3188_pin_banks,
3069 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3070 .label = "RK3188-GPIO",
3071 .type = RK3188,
3072 .grf_mux_offset = 0x60,
3073 .iomux_routes = rk3188_mux_route_data,
3074 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
3075 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3076 };
3077
3078 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3079 PIN_BANK(0, 32, "gpio0"),
3080 PIN_BANK(1, 32, "gpio1"),
3081 PIN_BANK(2, 32, "gpio2"),
3082 PIN_BANK(3, 32, "gpio3"),
3083 };
3084
3085 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3086 .pin_banks = rk3228_pin_banks,
3087 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3088 .label = "RK3228-GPIO",
3089 .type = RK3288,
3090 .grf_mux_offset = 0x0,
3091 .iomux_routes = rk3228_mux_route_data,
3092 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3093 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3094 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3095 };
3096
3097 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3098 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3099 IOMUX_SOURCE_PMU,
3100 IOMUX_SOURCE_PMU,
3101 IOMUX_UNROUTED
3102 ),
3103 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3104 IOMUX_UNROUTED,
3105 IOMUX_UNROUTED,
3106 0
3107 ),
3108 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3109 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3110 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3111 IOMUX_WIDTH_4BIT,
3112 0,
3113 0
3114 ),
3115 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3116 0,
3117 0,
3118 IOMUX_UNROUTED
3119 ),
3120 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3121 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3122 0,
3123 IOMUX_WIDTH_4BIT,
3124 IOMUX_UNROUTED
3125 ),
3126 PIN_BANK(8, 16, "gpio8"),
3127 };
3128
3129 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3130 .pin_banks = rk3288_pin_banks,
3131 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3132 .label = "RK3288-GPIO",
3133 .type = RK3288,
3134 .grf_mux_offset = 0x0,
3135 .pmu_mux_offset = 0x84,
3136 .iomux_routes = rk3288_mux_route_data,
3137 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3138 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3139 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3140 };
3141
3142 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3143 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3144 IOMUX_WIDTH_2BIT,
3145 IOMUX_WIDTH_2BIT,
3146 IOMUX_WIDTH_2BIT),
3147 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3148 IOMUX_WIDTH_2BIT,
3149 IOMUX_WIDTH_2BIT,
3150 IOMUX_WIDTH_2BIT),
3151 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3152 IOMUX_WIDTH_2BIT,
3153 IOMUX_WIDTH_2BIT,
3154 IOMUX_WIDTH_2BIT),
3155 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3156 IOMUX_WIDTH_2BIT,
3157 IOMUX_WIDTH_2BIT,
3158 IOMUX_WIDTH_2BIT),
3159 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3160 IOMUX_WIDTH_2BIT,
3161 IOMUX_WIDTH_2BIT,
3162 IOMUX_WIDTH_2BIT),
3163 };
3164
3165 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3166 .pin_banks = rk3308_pin_banks,
3167 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
3168 .label = "RK3308-GPIO",
3169 .type = RK3308,
3170 .grf_mux_offset = 0x0,
3171 .iomux_recalced = rk3308_mux_recalced_data,
3172 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
3173 .iomux_routes = rk3308_mux_route_data,
3174 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
3175 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3176 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3177 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
3178 };
3179
3180 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3181 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3182 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3183 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3184 IOMUX_WIDTH_3BIT,
3185 IOMUX_WIDTH_3BIT,
3186 0),
3187 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3188 IOMUX_WIDTH_3BIT,
3189 IOMUX_WIDTH_3BIT,
3190 0,
3191 0),
3192 };
3193
3194 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3195 .pin_banks = rk3328_pin_banks,
3196 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3197 .label = "RK3328-GPIO",
3198 .type = RK3288,
3199 .grf_mux_offset = 0x0,
3200 .iomux_recalced = rk3328_mux_recalced_data,
3201 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3202 .iomux_routes = rk3328_mux_route_data,
3203 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3204 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3205 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3206 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3207 };
3208
3209 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3210 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3211 IOMUX_SOURCE_PMU,
3212 IOMUX_SOURCE_PMU,
3213 IOMUX_SOURCE_PMU
3214 ),
3215 PIN_BANK(1, 32, "gpio1"),
3216 PIN_BANK(2, 32, "gpio2"),
3217 PIN_BANK(3, 32, "gpio3"),
3218 };
3219
3220 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3221 .pin_banks = rk3368_pin_banks,
3222 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3223 .label = "RK3368-GPIO",
3224 .type = RK3368,
3225 .grf_mux_offset = 0x0,
3226 .pmu_mux_offset = 0x0,
3227 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3228 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3229 };
3230
3231 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3232 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3233 IOMUX_SOURCE_PMU,
3234 IOMUX_SOURCE_PMU,
3235 IOMUX_SOURCE_PMU,
3236 IOMUX_SOURCE_PMU,
3237 DRV_TYPE_IO_1V8_ONLY,
3238 DRV_TYPE_IO_1V8_ONLY,
3239 DRV_TYPE_IO_DEFAULT,
3240 DRV_TYPE_IO_DEFAULT,
3241 0x80,
3242 0x88,
3243 -1,
3244 -1,
3245 PULL_TYPE_IO_1V8_ONLY,
3246 PULL_TYPE_IO_1V8_ONLY,
3247 PULL_TYPE_IO_DEFAULT,
3248 PULL_TYPE_IO_DEFAULT
3249 ),
3250 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3251 IOMUX_SOURCE_PMU,
3252 IOMUX_SOURCE_PMU,
3253 IOMUX_SOURCE_PMU,
3254 DRV_TYPE_IO_1V8_OR_3V0,
3255 DRV_TYPE_IO_1V8_OR_3V0,
3256 DRV_TYPE_IO_1V8_OR_3V0,
3257 DRV_TYPE_IO_1V8_OR_3V0,
3258 0xa0,
3259 0xa8,
3260 0xb0,
3261 0xb8
3262 ),
3263 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3264 DRV_TYPE_IO_1V8_OR_3V0,
3265 DRV_TYPE_IO_1V8_ONLY,
3266 DRV_TYPE_IO_1V8_ONLY,
3267 PULL_TYPE_IO_DEFAULT,
3268 PULL_TYPE_IO_DEFAULT,
3269 PULL_TYPE_IO_1V8_ONLY,
3270 PULL_TYPE_IO_1V8_ONLY
3271 ),
3272 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3273 DRV_TYPE_IO_3V3_ONLY,
3274 DRV_TYPE_IO_3V3_ONLY,
3275 DRV_TYPE_IO_1V8_OR_3V0
3276 ),
3277 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3278 DRV_TYPE_IO_1V8_3V0_AUTO,
3279 DRV_TYPE_IO_1V8_OR_3V0,
3280 DRV_TYPE_IO_1V8_OR_3V0
3281 ),
3282 };
3283
3284 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3285 .pin_banks = rk3399_pin_banks,
3286 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3287 .label = "RK3399-GPIO",
3288 .type = RK3399,
3289 .grf_mux_offset = 0xe000,
3290 .pmu_mux_offset = 0x0,
3291 .grf_drv_offset = 0xe100,
3292 .pmu_drv_offset = 0x80,
3293 .iomux_routes = rk3399_mux_route_data,
3294 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3295 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3296 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3297 };
3298
3299 static struct rockchip_pin_bank rk3568_pin_banks[] = {
3300 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3301 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3302 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3303 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
3304 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3305 IOMUX_WIDTH_4BIT,
3306 IOMUX_WIDTH_4BIT,
3307 IOMUX_WIDTH_4BIT),
3308 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3309 IOMUX_WIDTH_4BIT,
3310 IOMUX_WIDTH_4BIT,
3311 IOMUX_WIDTH_4BIT),
3312 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3313 IOMUX_WIDTH_4BIT,
3314 IOMUX_WIDTH_4BIT,
3315 IOMUX_WIDTH_4BIT),
3316 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3317 IOMUX_WIDTH_4BIT,
3318 IOMUX_WIDTH_4BIT,
3319 IOMUX_WIDTH_4BIT),
3320 };
3321
3322 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
3323 .pin_banks = rk3568_pin_banks,
3324 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
3325 .label = "RK3568-GPIO",
3326 .type = RK3568,
3327 .grf_mux_offset = 0x0,
3328 .pmu_mux_offset = 0x0,
3329 .grf_drv_offset = 0x0200,
3330 .pmu_drv_offset = 0x0070,
3331 .iomux_routes = rk3568_mux_route_data,
3332 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
3333 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
3334 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
3335 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
3336 };
3337
3338 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3339 { .compatible = "rockchip,px30-pinctrl",
3340 .data = &px30_pin_ctrl },
3341 { .compatible = "rockchip,rv1108-pinctrl",
3342 .data = &rv1108_pin_ctrl },
3343 { .compatible = "rockchip,rk2928-pinctrl",
3344 .data = &rk2928_pin_ctrl },
3345 { .compatible = "rockchip,rk3036-pinctrl",
3346 .data = &rk3036_pin_ctrl },
3347 { .compatible = "rockchip,rk3066a-pinctrl",
3348 .data = &rk3066a_pin_ctrl },
3349 { .compatible = "rockchip,rk3066b-pinctrl",
3350 .data = &rk3066b_pin_ctrl },
3351 { .compatible = "rockchip,rk3128-pinctrl",
3352 .data = (void *)&rk3128_pin_ctrl },
3353 { .compatible = "rockchip,rk3188-pinctrl",
3354 .data = &rk3188_pin_ctrl },
3355 { .compatible = "rockchip,rk3228-pinctrl",
3356 .data = &rk3228_pin_ctrl },
3357 { .compatible = "rockchip,rk3288-pinctrl",
3358 .data = &rk3288_pin_ctrl },
3359 { .compatible = "rockchip,rk3308-pinctrl",
3360 .data = &rk3308_pin_ctrl },
3361 { .compatible = "rockchip,rk3328-pinctrl",
3362 .data = &rk3328_pin_ctrl },
3363 { .compatible = "rockchip,rk3368-pinctrl",
3364 .data = &rk3368_pin_ctrl },
3365 { .compatible = "rockchip,rk3399-pinctrl",
3366 .data = &rk3399_pin_ctrl },
3367 { .compatible = "rockchip,rk3568-pinctrl",
3368 .data = &rk3568_pin_ctrl },
3369 {},
3370 };
3371
3372 static struct platform_driver rockchip_pinctrl_driver = {
3373 .probe = rockchip_pinctrl_probe,
3374 .remove = rockchip_pinctrl_remove,
3375 .driver = {
3376 .name = "rockchip-pinctrl",
3377 .pm = &rockchip_pinctrl_dev_pm_ops,
3378 .of_match_table = rockchip_pinctrl_dt_match,
3379 },
3380 };
3381
rockchip_pinctrl_drv_register(void)3382 static int __init rockchip_pinctrl_drv_register(void)
3383 {
3384 return platform_driver_register(&rockchip_pinctrl_driver);
3385 }
3386 postcore_initcall(rockchip_pinctrl_drv_register);
3387
rockchip_pinctrl_drv_unregister(void)3388 static void __exit rockchip_pinctrl_drv_unregister(void)
3389 {
3390 platform_driver_unregister(&rockchip_pinctrl_driver);
3391 }
3392 module_exit(rockchip_pinctrl_drv_unregister);
3393
3394 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
3395 MODULE_LICENSE("GPL");
3396 MODULE_ALIAS("platform:pinctrl-rockchip");
3397 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
3398