1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * PWM controller driver for Amlogic Meson SoCs.
4 *
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
7 * two periods (low and high). The counter then has to be set to switch after
8 * N cycles for the first half period.
9 * The hardware has no "polarity" setting. This driver reverses the period
10 * cycles (the low length is inverted with the high length) for
11 * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
12 * from the hardware.
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
15 * current period to complete first).
16 *
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
18 * controller starting on page 543:
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
20 * An updated version of this IP block is found in S922X (G12B) SoCs. The
21 * datasheet contains the description for this IP block revision starting at
22 * page 1084:
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
24 *
25 * Copyright (c) 2016 BayLibre, SAS.
26 * Author: Neil Armstrong <narmstrong@baylibre.com>
27 * Copyright (C) 2014 Amlogic, Inc.
28 */
29
30 #include <linux/bitfield.h>
31 #include <linux/bits.h>
32 #include <linux/clk.h>
33 #include <linux/clk-provider.h>
34 #include <linux/err.h>
35 #include <linux/io.h>
36 #include <linux/kernel.h>
37 #include <linux/math64.h>
38 #include <linux/module.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/platform_device.h>
42 #include <linux/pwm.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
45
46 #define REG_PWM_A 0x0
47 #define REG_PWM_B 0x4
48 #define PWM_LOW_MASK GENMASK(15, 0)
49 #define PWM_HIGH_MASK GENMASK(31, 16)
50
51 #define REG_MISC_AB 0x8
52 #define MISC_B_CLK_EN BIT(23)
53 #define MISC_A_CLK_EN BIT(15)
54 #define MISC_CLK_DIV_MASK 0x7f
55 #define MISC_B_CLK_DIV_SHIFT 16
56 #define MISC_A_CLK_DIV_SHIFT 8
57 #define MISC_B_CLK_SEL_SHIFT 6
58 #define MISC_A_CLK_SEL_SHIFT 4
59 #define MISC_CLK_SEL_MASK 0x3
60 #define MISC_B_EN BIT(1)
61 #define MISC_A_EN BIT(0)
62
63 #define MESON_NUM_PWMS 2
64
65 static struct meson_pwm_channel_data {
66 u8 reg_offset;
67 u8 clk_sel_shift;
68 u8 clk_div_shift;
69 u32 clk_en_mask;
70 u32 pwm_en_mask;
71 } meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
72 {
73 .reg_offset = REG_PWM_A,
74 .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
75 .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
76 .clk_en_mask = MISC_A_CLK_EN,
77 .pwm_en_mask = MISC_A_EN,
78 },
79 {
80 .reg_offset = REG_PWM_B,
81 .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
82 .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
83 .clk_en_mask = MISC_B_CLK_EN,
84 .pwm_en_mask = MISC_B_EN,
85 }
86 };
87
88 struct meson_pwm_channel {
89 unsigned int hi;
90 unsigned int lo;
91 u8 pre_div;
92
93 struct clk *clk_parent;
94 struct clk_mux mux;
95 struct clk *clk;
96 };
97
98 struct meson_pwm_data {
99 const char * const *parent_names;
100 unsigned int num_parents;
101 };
102
103 struct meson_pwm {
104 struct pwm_chip chip;
105 const struct meson_pwm_data *data;
106 struct meson_pwm_channel channels[MESON_NUM_PWMS];
107 void __iomem *base;
108 /*
109 * Protects register (write) access to the REG_MISC_AB register
110 * that is shared between the two PWMs.
111 */
112 spinlock_t lock;
113 };
114
to_meson_pwm(struct pwm_chip * chip)115 static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
116 {
117 return container_of(chip, struct meson_pwm, chip);
118 }
119
meson_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)120 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
121 {
122 struct meson_pwm *meson = to_meson_pwm(chip);
123 struct meson_pwm_channel *channel;
124 struct device *dev = chip->dev;
125 int err;
126
127 channel = pwm_get_chip_data(pwm);
128 if (channel)
129 return 0;
130
131 channel = &meson->channels[pwm->hwpwm];
132
133 if (channel->clk_parent) {
134 err = clk_set_parent(channel->clk, channel->clk_parent);
135 if (err < 0) {
136 dev_err(dev, "failed to set parent %s for %s: %d\n",
137 __clk_get_name(channel->clk_parent),
138 __clk_get_name(channel->clk), err);
139 return err;
140 }
141 }
142
143 err = clk_prepare_enable(channel->clk);
144 if (err < 0) {
145 dev_err(dev, "failed to enable clock %s: %d\n",
146 __clk_get_name(channel->clk), err);
147 return err;
148 }
149
150 return 0;
151 }
152
meson_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)153 static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
154 {
155 struct meson_pwm *meson = to_meson_pwm(chip);
156 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
157
158 if (channel)
159 clk_disable_unprepare(channel->clk);
160 }
161
meson_pwm_calc(struct meson_pwm * meson,struct pwm_device * pwm,const struct pwm_state * state)162 static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
163 const struct pwm_state *state)
164 {
165 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
166 unsigned int pre_div, cnt, duty_cnt;
167 unsigned long fin_freq;
168 u64 duty, period;
169
170 duty = state->duty_cycle;
171 period = state->period;
172
173 /*
174 * Note this is wrong. The result is an output wave that isn't really
175 * inverted and so is wrongly identified by .get_state as normal.
176 * Fixing this needs some care however as some machines might rely on
177 * this.
178 */
179 if (state->polarity == PWM_POLARITY_INVERSED)
180 duty = period - duty;
181
182 fin_freq = clk_get_rate(channel->clk);
183 if (fin_freq == 0) {
184 dev_err(meson->chip.dev, "invalid source clock frequency\n");
185 return -EINVAL;
186 }
187
188 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
189
190 pre_div = div64_u64(fin_freq * period, NSEC_PER_SEC * 0xffffLL);
191 if (pre_div > MISC_CLK_DIV_MASK) {
192 dev_err(meson->chip.dev, "unable to get period pre_div\n");
193 return -EINVAL;
194 }
195
196 cnt = div64_u64(fin_freq * period, NSEC_PER_SEC * (pre_div + 1));
197 if (cnt > 0xffff) {
198 dev_err(meson->chip.dev, "unable to get period cnt\n");
199 return -EINVAL;
200 }
201
202 dev_dbg(meson->chip.dev, "period=%llu pre_div=%u cnt=%u\n", period,
203 pre_div, cnt);
204
205 if (duty == period) {
206 channel->pre_div = pre_div;
207 channel->hi = cnt;
208 channel->lo = 0;
209 } else if (duty == 0) {
210 channel->pre_div = pre_div;
211 channel->hi = 0;
212 channel->lo = cnt;
213 } else {
214 /* Then check is we can have the duty with the same pre_div */
215 duty_cnt = div64_u64(fin_freq * duty, NSEC_PER_SEC * (pre_div + 1));
216 if (duty_cnt > 0xffff) {
217 dev_err(meson->chip.dev, "unable to get duty cycle\n");
218 return -EINVAL;
219 }
220
221 dev_dbg(meson->chip.dev, "duty=%llu pre_div=%u duty_cnt=%u\n",
222 duty, pre_div, duty_cnt);
223
224 channel->pre_div = pre_div;
225 channel->hi = duty_cnt;
226 channel->lo = cnt - duty_cnt;
227 }
228
229 return 0;
230 }
231
meson_pwm_enable(struct meson_pwm * meson,struct pwm_device * pwm)232 static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
233 {
234 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
235 struct meson_pwm_channel_data *channel_data;
236 unsigned long flags;
237 u32 value;
238
239 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
240
241 spin_lock_irqsave(&meson->lock, flags);
242
243 value = readl(meson->base + REG_MISC_AB);
244 value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
245 value |= channel->pre_div << channel_data->clk_div_shift;
246 value |= channel_data->clk_en_mask;
247 writel(value, meson->base + REG_MISC_AB);
248
249 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
250 FIELD_PREP(PWM_LOW_MASK, channel->lo);
251 writel(value, meson->base + channel_data->reg_offset);
252
253 value = readl(meson->base + REG_MISC_AB);
254 value |= channel_data->pwm_en_mask;
255 writel(value, meson->base + REG_MISC_AB);
256
257 spin_unlock_irqrestore(&meson->lock, flags);
258 }
259
meson_pwm_disable(struct meson_pwm * meson,struct pwm_device * pwm)260 static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
261 {
262 unsigned long flags;
263 u32 value;
264
265 spin_lock_irqsave(&meson->lock, flags);
266
267 value = readl(meson->base + REG_MISC_AB);
268 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
269 writel(value, meson->base + REG_MISC_AB);
270
271 spin_unlock_irqrestore(&meson->lock, flags);
272 }
273
meson_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)274 static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
275 const struct pwm_state *state)
276 {
277 struct meson_pwm *meson = to_meson_pwm(chip);
278 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
279 int err = 0;
280
281 if (!state)
282 return -EINVAL;
283
284 if (!state->enabled) {
285 if (state->polarity == PWM_POLARITY_INVERSED) {
286 /*
287 * This IP block revision doesn't have an "always high"
288 * setting which we can use for "inverted disabled".
289 * Instead we achieve this using the same settings
290 * that we use a pre_div of 0 (to get the shortest
291 * possible duration for one "count") and
292 * "period == duty_cycle". This results in a signal
293 * which is LOW for one "count", while being HIGH for
294 * the rest of the (so the signal is HIGH for slightly
295 * less than 100% of the period, but this is the best
296 * we can achieve).
297 */
298 channel->pre_div = 0;
299 channel->hi = ~0;
300 channel->lo = 0;
301
302 meson_pwm_enable(meson, pwm);
303 } else {
304 meson_pwm_disable(meson, pwm);
305 }
306 } else {
307 err = meson_pwm_calc(meson, pwm, state);
308 if (err < 0)
309 return err;
310
311 meson_pwm_enable(meson, pwm);
312 }
313
314 return 0;
315 }
316
meson_pwm_cnt_to_ns(struct pwm_chip * chip,struct pwm_device * pwm,u32 cnt)317 static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
318 struct pwm_device *pwm, u32 cnt)
319 {
320 struct meson_pwm *meson = to_meson_pwm(chip);
321 struct meson_pwm_channel *channel;
322 unsigned long fin_freq;
323 u32 fin_ns;
324
325 /* to_meson_pwm() can only be used after .get_state() is called */
326 channel = &meson->channels[pwm->hwpwm];
327
328 fin_freq = clk_get_rate(channel->clk);
329 if (fin_freq == 0)
330 return 0;
331
332 fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
333
334 return cnt * fin_ns * (channel->pre_div + 1);
335 }
336
meson_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)337 static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
338 struct pwm_state *state)
339 {
340 struct meson_pwm *meson = to_meson_pwm(chip);
341 struct meson_pwm_channel_data *channel_data;
342 struct meson_pwm_channel *channel;
343 u32 value, tmp;
344
345 if (!state)
346 return;
347
348 channel = &meson->channels[pwm->hwpwm];
349 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
350
351 value = readl(meson->base + REG_MISC_AB);
352
353 tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
354 state->enabled = (value & tmp) == tmp;
355
356 tmp = value >> channel_data->clk_div_shift;
357 channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
358
359 value = readl(meson->base + channel_data->reg_offset);
360
361 channel->lo = FIELD_GET(PWM_LOW_MASK, value);
362 channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
363
364 if (channel->lo == 0) {
365 state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
366 state->duty_cycle = state->period;
367 } else if (channel->lo >= channel->hi) {
368 state->period = meson_pwm_cnt_to_ns(chip, pwm,
369 channel->lo + channel->hi);
370 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
371 channel->hi);
372 } else {
373 state->period = 0;
374 state->duty_cycle = 0;
375 }
376 state->polarity = PWM_POLARITY_NORMAL;
377 }
378
379 static const struct pwm_ops meson_pwm_ops = {
380 .request = meson_pwm_request,
381 .free = meson_pwm_free,
382 .apply = meson_pwm_apply,
383 .get_state = meson_pwm_get_state,
384 .owner = THIS_MODULE,
385 };
386
387 static const char * const pwm_meson8b_parent_names[] = {
388 "xtal", "vid_pll", "fclk_div4", "fclk_div3"
389 };
390
391 static const struct meson_pwm_data pwm_meson8b_data = {
392 .parent_names = pwm_meson8b_parent_names,
393 .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
394 };
395
396 static const char * const pwm_gxbb_parent_names[] = {
397 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
398 };
399
400 static const struct meson_pwm_data pwm_gxbb_data = {
401 .parent_names = pwm_gxbb_parent_names,
402 .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
403 };
404
405 /*
406 * Only the 2 first inputs of the GXBB AO PWMs are valid
407 * The last 2 are grounded
408 */
409 static const char * const pwm_gxbb_ao_parent_names[] = {
410 "xtal", "clk81"
411 };
412
413 static const struct meson_pwm_data pwm_gxbb_ao_data = {
414 .parent_names = pwm_gxbb_ao_parent_names,
415 .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
416 };
417
418 static const char * const pwm_axg_ee_parent_names[] = {
419 "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
420 };
421
422 static const struct meson_pwm_data pwm_axg_ee_data = {
423 .parent_names = pwm_axg_ee_parent_names,
424 .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
425 };
426
427 static const char * const pwm_axg_ao_parent_names[] = {
428 "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5"
429 };
430
431 static const struct meson_pwm_data pwm_axg_ao_data = {
432 .parent_names = pwm_axg_ao_parent_names,
433 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
434 };
435
436 static const char * const pwm_g12a_ao_ab_parent_names[] = {
437 "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5"
438 };
439
440 static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
441 .parent_names = pwm_g12a_ao_ab_parent_names,
442 .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
443 };
444
445 static const char * const pwm_g12a_ao_cd_parent_names[] = {
446 "xtal", "g12a_ao_clk81",
447 };
448
449 static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
450 .parent_names = pwm_g12a_ao_cd_parent_names,
451 .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
452 };
453
454 static const char * const pwm_g12a_ee_parent_names[] = {
455 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
456 };
457
458 static const struct meson_pwm_data pwm_g12a_ee_data = {
459 .parent_names = pwm_g12a_ee_parent_names,
460 .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
461 };
462
463 static const struct of_device_id meson_pwm_matches[] = {
464 {
465 .compatible = "amlogic,meson8b-pwm",
466 .data = &pwm_meson8b_data
467 },
468 {
469 .compatible = "amlogic,meson-gxbb-pwm",
470 .data = &pwm_gxbb_data
471 },
472 {
473 .compatible = "amlogic,meson-gxbb-ao-pwm",
474 .data = &pwm_gxbb_ao_data
475 },
476 {
477 .compatible = "amlogic,meson-axg-ee-pwm",
478 .data = &pwm_axg_ee_data
479 },
480 {
481 .compatible = "amlogic,meson-axg-ao-pwm",
482 .data = &pwm_axg_ao_data
483 },
484 {
485 .compatible = "amlogic,meson-g12a-ee-pwm",
486 .data = &pwm_g12a_ee_data
487 },
488 {
489 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
490 .data = &pwm_g12a_ao_ab_data
491 },
492 {
493 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
494 .data = &pwm_g12a_ao_cd_data
495 },
496 {},
497 };
498 MODULE_DEVICE_TABLE(of, meson_pwm_matches);
499
meson_pwm_init_channels(struct meson_pwm * meson)500 static int meson_pwm_init_channels(struct meson_pwm *meson)
501 {
502 struct device *dev = meson->chip.dev;
503 struct clk_init_data init;
504 unsigned int i;
505 char name[255];
506 int err;
507
508 for (i = 0; i < meson->chip.npwm; i++) {
509 struct meson_pwm_channel *channel = &meson->channels[i];
510
511 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
512
513 init.name = name;
514 init.ops = &clk_mux_ops;
515 init.flags = 0;
516 init.parent_names = meson->data->parent_names;
517 init.num_parents = meson->data->num_parents;
518
519 channel->mux.reg = meson->base + REG_MISC_AB;
520 channel->mux.shift =
521 meson_pwm_per_channel_data[i].clk_sel_shift;
522 channel->mux.mask = MISC_CLK_SEL_MASK;
523 channel->mux.flags = 0;
524 channel->mux.lock = &meson->lock;
525 channel->mux.table = NULL;
526 channel->mux.hw.init = &init;
527
528 channel->clk = devm_clk_register(dev, &channel->mux.hw);
529 if (IS_ERR(channel->clk)) {
530 err = PTR_ERR(channel->clk);
531 dev_err(dev, "failed to register %s: %d\n", name, err);
532 return err;
533 }
534
535 snprintf(name, sizeof(name), "clkin%u", i);
536
537 channel->clk_parent = devm_clk_get_optional(dev, name);
538 if (IS_ERR(channel->clk_parent))
539 return PTR_ERR(channel->clk_parent);
540 }
541
542 return 0;
543 }
544
meson_pwm_probe(struct platform_device * pdev)545 static int meson_pwm_probe(struct platform_device *pdev)
546 {
547 struct meson_pwm *meson;
548 int err;
549
550 meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
551 if (!meson)
552 return -ENOMEM;
553
554 meson->base = devm_platform_ioremap_resource(pdev, 0);
555 if (IS_ERR(meson->base))
556 return PTR_ERR(meson->base);
557
558 spin_lock_init(&meson->lock);
559 meson->chip.dev = &pdev->dev;
560 meson->chip.ops = &meson_pwm_ops;
561 meson->chip.npwm = MESON_NUM_PWMS;
562
563 meson->data = of_device_get_match_data(&pdev->dev);
564
565 err = meson_pwm_init_channels(meson);
566 if (err < 0)
567 return err;
568
569 err = devm_pwmchip_add(&pdev->dev, &meson->chip);
570 if (err < 0) {
571 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
572 return err;
573 }
574
575 return 0;
576 }
577
578 static struct platform_driver meson_pwm_driver = {
579 .driver = {
580 .name = "meson-pwm",
581 .of_match_table = meson_pwm_matches,
582 },
583 .probe = meson_pwm_probe,
584 };
585 module_platform_driver(meson_pwm_driver);
586
587 MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
588 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
589 MODULE_LICENSE("Dual BSD/GPL");
590