1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015, Sony Mobile Communications AB.
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 #include <linux/regulator/driver.h>
12 #include <linux/regulator/of_regulator.h>
13 #include <linux/soc/qcom/smd-rpm.h>
14
15 struct qcom_rpm_reg {
16 struct device *dev;
17
18 struct qcom_smd_rpm *rpm;
19
20 u32 type;
21 u32 id;
22
23 struct regulator_desc desc;
24
25 int is_enabled;
26 int uV;
27 u32 load;
28
29 unsigned int enabled_updated:1;
30 unsigned int uv_updated:1;
31 unsigned int load_updated:1;
32 };
33
34 struct rpm_regulator_req {
35 __le32 key;
36 __le32 nbytes;
37 __le32 value;
38 };
39
40 #define RPM_KEY_SWEN 0x6e657773 /* "swen" */
41 #define RPM_KEY_UV 0x00007675 /* "uv" */
42 #define RPM_KEY_MA 0x0000616d /* "ma" */
43
rpm_reg_write_active(struct qcom_rpm_reg * vreg)44 static int rpm_reg_write_active(struct qcom_rpm_reg *vreg)
45 {
46 struct rpm_regulator_req req[3];
47 int reqlen = 0;
48 int ret;
49
50 if (vreg->enabled_updated) {
51 req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN);
52 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
53 req[reqlen].value = cpu_to_le32(vreg->is_enabled);
54 reqlen++;
55 }
56
57 if (vreg->uv_updated && vreg->is_enabled) {
58 req[reqlen].key = cpu_to_le32(RPM_KEY_UV);
59 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
60 req[reqlen].value = cpu_to_le32(vreg->uV);
61 reqlen++;
62 }
63
64 if (vreg->load_updated && vreg->is_enabled) {
65 req[reqlen].key = cpu_to_le32(RPM_KEY_MA);
66 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
67 req[reqlen].value = cpu_to_le32(vreg->load / 1000);
68 reqlen++;
69 }
70
71 if (!reqlen)
72 return 0;
73
74 ret = qcom_rpm_smd_write(vreg->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
75 vreg->type, vreg->id,
76 req, sizeof(req[0]) * reqlen);
77 if (!ret) {
78 vreg->enabled_updated = 0;
79 vreg->uv_updated = 0;
80 vreg->load_updated = 0;
81 }
82
83 return ret;
84 }
85
rpm_reg_enable(struct regulator_dev * rdev)86 static int rpm_reg_enable(struct regulator_dev *rdev)
87 {
88 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
89 int ret;
90
91 vreg->is_enabled = 1;
92 vreg->enabled_updated = 1;
93
94 ret = rpm_reg_write_active(vreg);
95 if (ret)
96 vreg->is_enabled = 0;
97
98 return ret;
99 }
100
rpm_reg_is_enabled(struct regulator_dev * rdev)101 static int rpm_reg_is_enabled(struct regulator_dev *rdev)
102 {
103 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
104
105 return vreg->is_enabled;
106 }
107
rpm_reg_disable(struct regulator_dev * rdev)108 static int rpm_reg_disable(struct regulator_dev *rdev)
109 {
110 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
111 int ret;
112
113 vreg->is_enabled = 0;
114 vreg->enabled_updated = 1;
115
116 ret = rpm_reg_write_active(vreg);
117 if (ret)
118 vreg->is_enabled = 1;
119
120 return ret;
121 }
122
rpm_reg_get_voltage(struct regulator_dev * rdev)123 static int rpm_reg_get_voltage(struct regulator_dev *rdev)
124 {
125 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
126
127 return vreg->uV;
128 }
129
rpm_reg_set_voltage(struct regulator_dev * rdev,int min_uV,int max_uV,unsigned * selector)130 static int rpm_reg_set_voltage(struct regulator_dev *rdev,
131 int min_uV,
132 int max_uV,
133 unsigned *selector)
134 {
135 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
136 int ret;
137 int old_uV = vreg->uV;
138
139 vreg->uV = min_uV;
140 vreg->uv_updated = 1;
141
142 ret = rpm_reg_write_active(vreg);
143 if (ret)
144 vreg->uV = old_uV;
145
146 return ret;
147 }
148
rpm_reg_set_load(struct regulator_dev * rdev,int load_uA)149 static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
150 {
151 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
152 u32 old_load = vreg->load;
153 int ret;
154
155 vreg->load = load_uA;
156 vreg->load_updated = 1;
157 ret = rpm_reg_write_active(vreg);
158 if (ret)
159 vreg->load = old_load;
160
161 return ret;
162 }
163
164 static const struct regulator_ops rpm_smps_ldo_ops = {
165 .enable = rpm_reg_enable,
166 .disable = rpm_reg_disable,
167 .is_enabled = rpm_reg_is_enabled,
168 .list_voltage = regulator_list_voltage_linear_range,
169
170 .get_voltage = rpm_reg_get_voltage,
171 .set_voltage = rpm_reg_set_voltage,
172
173 .set_load = rpm_reg_set_load,
174 };
175
176 static const struct regulator_ops rpm_smps_ldo_ops_fixed = {
177 .enable = rpm_reg_enable,
178 .disable = rpm_reg_disable,
179 .is_enabled = rpm_reg_is_enabled,
180
181 .get_voltage = rpm_reg_get_voltage,
182 .set_voltage = rpm_reg_set_voltage,
183
184 .set_load = rpm_reg_set_load,
185 };
186
187 static const struct regulator_ops rpm_switch_ops = {
188 .enable = rpm_reg_enable,
189 .disable = rpm_reg_disable,
190 .is_enabled = rpm_reg_is_enabled,
191 };
192
193 static const struct regulator_ops rpm_bob_ops = {
194 .enable = rpm_reg_enable,
195 .disable = rpm_reg_disable,
196 .is_enabled = rpm_reg_is_enabled,
197
198 .get_voltage = rpm_reg_get_voltage,
199 .set_voltage = rpm_reg_set_voltage,
200 };
201
202 static const struct regulator_ops rpm_mp5496_ops = {
203 .enable = rpm_reg_enable,
204 .disable = rpm_reg_disable,
205 .is_enabled = rpm_reg_is_enabled,
206 .list_voltage = regulator_list_voltage_linear_range,
207
208 .set_voltage = rpm_reg_set_voltage,
209 };
210
211 static const struct regulator_desc pma8084_hfsmps = {
212 .linear_ranges = (struct linear_range[]) {
213 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
214 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
215 },
216 .n_linear_ranges = 2,
217 .n_voltages = 159,
218 .ops = &rpm_smps_ldo_ops,
219 };
220
221 static const struct regulator_desc pma8084_ftsmps = {
222 .linear_ranges = (struct linear_range[]) {
223 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
224 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
225 },
226 .n_linear_ranges = 2,
227 .n_voltages = 262,
228 .ops = &rpm_smps_ldo_ops,
229 };
230
231 static const struct regulator_desc pma8084_pldo = {
232 .linear_ranges = (struct linear_range[]) {
233 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
234 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
235 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
236 },
237 .n_linear_ranges = 3,
238 .n_voltages = 164,
239 .ops = &rpm_smps_ldo_ops,
240 };
241
242 static const struct regulator_desc pma8084_nldo = {
243 .linear_ranges = (struct linear_range[]) {
244 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
245 },
246 .n_linear_ranges = 1,
247 .n_voltages = 64,
248 .ops = &rpm_smps_ldo_ops,
249 };
250
251 static const struct regulator_desc pma8084_switch = {
252 .ops = &rpm_switch_ops,
253 };
254
255 static const struct regulator_desc pm8226_hfsmps = {
256 .linear_ranges = (struct linear_range[]) {
257 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
258 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
259 },
260 .n_linear_ranges = 2,
261 .n_voltages = 159,
262 .ops = &rpm_smps_ldo_ops,
263 };
264
265 static const struct regulator_desc pm8226_ftsmps = {
266 .linear_ranges = (struct linear_range[]) {
267 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
268 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
269 },
270 .n_linear_ranges = 2,
271 .n_voltages = 262,
272 .ops = &rpm_smps_ldo_ops,
273 };
274
275 static const struct regulator_desc pm8226_pldo = {
276 .linear_ranges = (struct linear_range[]) {
277 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
278 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
279 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
280 },
281 .n_linear_ranges = 3,
282 .n_voltages = 164,
283 .ops = &rpm_smps_ldo_ops,
284 };
285
286 static const struct regulator_desc pm8226_nldo = {
287 .linear_ranges = (struct linear_range[]) {
288 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
289 },
290 .n_linear_ranges = 1,
291 .n_voltages = 64,
292 .ops = &rpm_smps_ldo_ops,
293 };
294
295 static const struct regulator_desc pm8226_switch = {
296 .ops = &rpm_switch_ops,
297 };
298
299 static const struct regulator_desc pm8x41_hfsmps = {
300 .linear_ranges = (struct linear_range[]) {
301 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
302 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
303 },
304 .n_linear_ranges = 2,
305 .n_voltages = 159,
306 .ops = &rpm_smps_ldo_ops,
307 };
308
309 static const struct regulator_desc pm8841_ftsmps = {
310 .linear_ranges = (struct linear_range[]) {
311 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
312 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
313 },
314 .n_linear_ranges = 2,
315 .n_voltages = 262,
316 .ops = &rpm_smps_ldo_ops,
317 };
318
319 static const struct regulator_desc pm8941_boost = {
320 .linear_ranges = (struct linear_range[]) {
321 REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000),
322 },
323 .n_linear_ranges = 1,
324 .n_voltages = 31,
325 .ops = &rpm_smps_ldo_ops,
326 };
327
328 static const struct regulator_desc pm8941_pldo = {
329 .linear_ranges = (struct linear_range[]) {
330 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
331 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
332 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
333 },
334 .n_linear_ranges = 3,
335 .n_voltages = 164,
336 .ops = &rpm_smps_ldo_ops,
337 };
338
339 static const struct regulator_desc pm8941_nldo = {
340 .linear_ranges = (struct linear_range[]) {
341 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
342 },
343 .n_linear_ranges = 1,
344 .n_voltages = 64,
345 .ops = &rpm_smps_ldo_ops,
346 };
347
348 static const struct regulator_desc pm8941_lnldo = {
349 .fixed_uV = 1740000,
350 .n_voltages = 1,
351 .ops = &rpm_smps_ldo_ops_fixed,
352 };
353
354 static const struct regulator_desc pm8941_switch = {
355 .ops = &rpm_switch_ops,
356 };
357
358 static const struct regulator_desc pm8916_pldo = {
359 .linear_ranges = (struct linear_range[]) {
360 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
361 },
362 .n_linear_ranges = 1,
363 .n_voltages = 128,
364 .ops = &rpm_smps_ldo_ops,
365 };
366
367 static const struct regulator_desc pm8916_nldo = {
368 .linear_ranges = (struct linear_range[]) {
369 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
370 },
371 .n_linear_ranges = 1,
372 .n_voltages = 94,
373 .ops = &rpm_smps_ldo_ops,
374 };
375
376 static const struct regulator_desc pm8916_buck_lvo_smps = {
377 .linear_ranges = (struct linear_range[]) {
378 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
379 REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
380 },
381 .n_linear_ranges = 2,
382 .n_voltages = 128,
383 .ops = &rpm_smps_ldo_ops,
384 };
385
386 static const struct regulator_desc pm8916_buck_hvo_smps = {
387 .linear_ranges = (struct linear_range[]) {
388 REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
389 },
390 .n_linear_ranges = 1,
391 .n_voltages = 32,
392 .ops = &rpm_smps_ldo_ops,
393 };
394
395 static const struct regulator_desc pm8950_hfsmps = {
396 .linear_ranges = (struct linear_range[]) {
397 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
398 REGULATOR_LINEAR_RANGE(1550000, 96, 127, 25000),
399 },
400 .n_linear_ranges = 2,
401 .n_voltages = 128,
402 .ops = &rpm_smps_ldo_ops,
403 };
404
405 static const struct regulator_desc pm8950_ftsmps2p5 = {
406 .linear_ranges = (struct linear_range[]) {
407 REGULATOR_LINEAR_RANGE(80000, 0, 255, 5000),
408 REGULATOR_LINEAR_RANGE(160000, 256, 460, 10000),
409 },
410 .n_linear_ranges = 2,
411 .n_voltages = 461,
412 .ops = &rpm_smps_ldo_ops,
413 };
414
415 static const struct regulator_desc pm8950_ult_nldo = {
416 .linear_ranges = (struct linear_range[]) {
417 REGULATOR_LINEAR_RANGE(375000, 0, 202, 12500),
418 },
419 .n_linear_ranges = 1,
420 .n_voltages = 203,
421 .ops = &rpm_smps_ldo_ops,
422 };
423
424 static const struct regulator_desc pm8950_ult_pldo = {
425 .linear_ranges = (struct linear_range[]) {
426 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
427 },
428 .n_linear_ranges = 1,
429 .n_voltages = 128,
430 .ops = &rpm_smps_ldo_ops,
431 };
432
433 static const struct regulator_desc pm8950_pldo_lv = {
434 .linear_ranges = (struct linear_range[]) {
435 REGULATOR_LINEAR_RANGE(1500000, 0, 16, 25000),
436 },
437 .n_linear_ranges = 1,
438 .n_voltages = 17,
439 .ops = &rpm_smps_ldo_ops,
440 };
441
442 static const struct regulator_desc pm8950_pldo = {
443 .linear_ranges = (struct linear_range[]) {
444 REGULATOR_LINEAR_RANGE(975000, 0, 164, 12500),
445 },
446 .n_linear_ranges = 1,
447 .n_voltages = 165,
448 .ops = &rpm_smps_ldo_ops,
449 };
450
451 static const struct regulator_desc pm8953_lnldo = {
452 .linear_ranges = (struct linear_range[]) {
453 REGULATOR_LINEAR_RANGE(690000, 0, 7, 60000),
454 REGULATOR_LINEAR_RANGE(1380000, 8, 15, 120000),
455 },
456 .n_linear_ranges = 2,
457 .n_voltages = 16,
458 .ops = &rpm_smps_ldo_ops,
459 };
460
461 static const struct regulator_desc pm8953_ult_nldo = {
462 .linear_ranges = (struct linear_range[]) {
463 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
464 },
465 .n_linear_ranges = 1,
466 .n_voltages = 94,
467 .ops = &rpm_smps_ldo_ops,
468 };
469
470 static const struct regulator_desc pm8994_hfsmps = {
471 .linear_ranges = (struct linear_range[]) {
472 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
473 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
474 },
475 .n_linear_ranges = 2,
476 .n_voltages = 159,
477 .ops = &rpm_smps_ldo_ops,
478 };
479
480 static const struct regulator_desc pm8994_ftsmps = {
481 .linear_ranges = (struct linear_range[]) {
482 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
483 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
484 },
485 .n_linear_ranges = 2,
486 .n_voltages = 350,
487 .ops = &rpm_smps_ldo_ops,
488 };
489
490 static const struct regulator_desc pm8994_nldo = {
491 .linear_ranges = (struct linear_range[]) {
492 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
493 },
494 .n_linear_ranges = 1,
495 .n_voltages = 64,
496 .ops = &rpm_smps_ldo_ops,
497 };
498
499 static const struct regulator_desc pm8994_pldo = {
500 .linear_ranges = (struct linear_range[]) {
501 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
502 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
503 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
504 },
505 .n_linear_ranges = 3,
506 .n_voltages = 164,
507 .ops = &rpm_smps_ldo_ops,
508 };
509
510 static const struct regulator_desc pm8994_switch = {
511 .ops = &rpm_switch_ops,
512 };
513
514 static const struct regulator_desc pm8994_lnldo = {
515 .fixed_uV = 1740000,
516 .n_voltages = 1,
517 .ops = &rpm_smps_ldo_ops_fixed,
518 };
519
520 static const struct regulator_desc pmi8994_ftsmps = {
521 .linear_ranges = (struct linear_range[]) {
522 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
523 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
524 },
525 .n_linear_ranges = 2,
526 .n_voltages = 350,
527 .ops = &rpm_smps_ldo_ops,
528 };
529
530 static const struct regulator_desc pmi8994_hfsmps = {
531 .linear_ranges = (struct linear_range[]) {
532 REGULATOR_LINEAR_RANGE(350000, 0, 80, 12500),
533 REGULATOR_LINEAR_RANGE(700000, 81, 141, 25000),
534 },
535 .n_linear_ranges = 2,
536 .n_voltages = 142,
537 .ops = &rpm_smps_ldo_ops,
538 };
539
540 static const struct regulator_desc pmi8994_bby = {
541 .linear_ranges = (struct linear_range[]) {
542 REGULATOR_LINEAR_RANGE(3000000, 0, 44, 50000),
543 },
544 .n_linear_ranges = 1,
545 .n_voltages = 45,
546 .ops = &rpm_bob_ops,
547 };
548
549 static const struct regulator_desc pm8998_ftsmps = {
550 .linear_ranges = (struct linear_range[]) {
551 REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000),
552 },
553 .n_linear_ranges = 1,
554 .n_voltages = 259,
555 .ops = &rpm_smps_ldo_ops,
556 };
557
558 static const struct regulator_desc pm8998_hfsmps = {
559 .linear_ranges = (struct linear_range[]) {
560 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
561 },
562 .n_linear_ranges = 1,
563 .n_voltages = 216,
564 .ops = &rpm_smps_ldo_ops,
565 };
566
567 static const struct regulator_desc pm8998_nldo = {
568 .linear_ranges = (struct linear_range[]) {
569 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
570 },
571 .n_linear_ranges = 1,
572 .n_voltages = 128,
573 .ops = &rpm_smps_ldo_ops,
574 };
575
576 static const struct regulator_desc pm8998_pldo = {
577 .linear_ranges = (struct linear_range[]) {
578 REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000),
579 },
580 .n_linear_ranges = 1,
581 .n_voltages = 256,
582 .ops = &rpm_smps_ldo_ops,
583 };
584
585 static const struct regulator_desc pm8998_pldo_lv = {
586 .linear_ranges = (struct linear_range[]) {
587 REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000),
588 },
589 .n_linear_ranges = 1,
590 .n_voltages = 128,
591 .ops = &rpm_smps_ldo_ops,
592 };
593
594 static const struct regulator_desc pm8998_switch = {
595 .ops = &rpm_switch_ops,
596 };
597
598 static const struct regulator_desc pmi8998_bob = {
599 .linear_ranges = (struct linear_range[]) {
600 REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000),
601 },
602 .n_linear_ranges = 1,
603 .n_voltages = 84,
604 .ops = &rpm_bob_ops,
605 };
606
607 static const struct regulator_desc pm660_ftsmps = {
608 .linear_ranges = (struct linear_range[]) {
609 REGULATOR_LINEAR_RANGE(355000, 0, 199, 5000),
610 },
611 .n_linear_ranges = 1,
612 .n_voltages = 200,
613 .ops = &rpm_smps_ldo_ops,
614 };
615
616 static const struct regulator_desc pm660_hfsmps = {
617 .linear_ranges = (struct linear_range[]) {
618 REGULATOR_LINEAR_RANGE(320000, 0, 216, 8000),
619 },
620 .n_linear_ranges = 1,
621 .n_voltages = 217,
622 .ops = &rpm_smps_ldo_ops,
623 };
624
625 static const struct regulator_desc pm660_ht_nldo = {
626 .linear_ranges = (struct linear_range[]) {
627 REGULATOR_LINEAR_RANGE(312000, 0, 124, 8000),
628 },
629 .n_linear_ranges = 1,
630 .n_voltages = 125,
631 .ops = &rpm_smps_ldo_ops,
632 };
633
634 static const struct regulator_desc pm660_ht_lvpldo = {
635 .linear_ranges = (struct linear_range[]) {
636 REGULATOR_LINEAR_RANGE(1504000, 0, 62, 8000),
637 },
638 .n_linear_ranges = 1,
639 .n_voltages = 63,
640 .ops = &rpm_smps_ldo_ops,
641 };
642
643 static const struct regulator_desc pm660_nldo660 = {
644 .linear_ranges = (struct linear_range[]) {
645 REGULATOR_LINEAR_RANGE(320000, 0, 123, 8000),
646 },
647 .n_linear_ranges = 1,
648 .n_voltages = 124,
649 .ops = &rpm_smps_ldo_ops,
650 };
651
652 static const struct regulator_desc pm660_pldo660 = {
653 .linear_ranges = (struct linear_range[]) {
654 REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
655 },
656 .n_linear_ranges = 1,
657 .n_voltages = 256,
658 .ops = &rpm_smps_ldo_ops,
659 };
660
661 static const struct regulator_desc pm660l_bob = {
662 .linear_ranges = (struct linear_range[]) {
663 REGULATOR_LINEAR_RANGE(1800000, 0, 84, 32000),
664 },
665 .n_linear_ranges = 1,
666 .n_voltages = 85,
667 .ops = &rpm_bob_ops,
668 };
669
670 static const struct regulator_desc pms405_hfsmps3 = {
671 .linear_ranges = (struct linear_range[]) {
672 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
673 },
674 .n_linear_ranges = 1,
675 .n_voltages = 216,
676 .ops = &rpm_smps_ldo_ops,
677 };
678
679 static const struct regulator_desc pms405_nldo300 = {
680 .linear_ranges = (struct linear_range[]) {
681 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
682 },
683 .n_linear_ranges = 1,
684 .n_voltages = 128,
685 .ops = &rpm_smps_ldo_ops,
686 };
687
688 static const struct regulator_desc pms405_nldo1200 = {
689 .linear_ranges = (struct linear_range[]) {
690 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
691 },
692 .n_linear_ranges = 1,
693 .n_voltages = 128,
694 .ops = &rpm_smps_ldo_ops,
695 };
696
697 static const struct regulator_desc pms405_pldo50 = {
698 .linear_ranges = (struct linear_range[]) {
699 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
700 },
701 .n_linear_ranges = 1,
702 .n_voltages = 129,
703 .ops = &rpm_smps_ldo_ops,
704 };
705
706 static const struct regulator_desc pms405_pldo150 = {
707 .linear_ranges = (struct linear_range[]) {
708 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
709 },
710 .n_linear_ranges = 1,
711 .n_voltages = 129,
712 .ops = &rpm_smps_ldo_ops,
713 };
714
715 static const struct regulator_desc pms405_pldo600 = {
716 .linear_ranges = (struct linear_range[]) {
717 REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000),
718 },
719 .n_linear_ranges = 1,
720 .n_voltages = 99,
721 .ops = &rpm_smps_ldo_ops,
722 };
723
724 static const struct regulator_desc mp5496_smpa2 = {
725 .linear_ranges = (struct linear_range[]) {
726 REGULATOR_LINEAR_RANGE(725000, 0, 27, 12500),
727 },
728 .n_linear_ranges = 1,
729 .n_voltages = 28,
730 .ops = &rpm_mp5496_ops,
731 };
732
733 static const struct regulator_desc mp5496_ldoa2 = {
734 .linear_ranges = (struct linear_range[]) {
735 REGULATOR_LINEAR_RANGE(1800000, 0, 60, 25000),
736 },
737 .n_linear_ranges = 1,
738 .n_voltages = 61,
739 .ops = &rpm_mp5496_ops,
740 };
741
742 struct rpm_regulator_data {
743 const char *name;
744 u32 type;
745 u32 id;
746 const struct regulator_desc *desc;
747 const char *supply;
748 };
749
750 static const struct rpm_regulator_data rpm_mp5496_regulators[] = {
751 { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" },
752 { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" },
753 {}
754 };
755
756 static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
757 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
758 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
759 { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
760 { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
761 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
762 { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
763 { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
764 { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
765 {}
766 };
767
768 static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
769 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
770 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
771 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
772 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
773 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
774 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
775 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
776 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
777 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
778 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
779 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
780 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
781 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
782 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
783 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
784 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
785 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
786 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
787 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
788 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
789 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
790 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
791 {}
792 };
793
794 static const struct rpm_regulator_data rpm_pm8226_regulators[] = {
795 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8226_hfsmps, "vdd_s1" },
796 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8226_ftsmps, "vdd_s2" },
797 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8226_hfsmps, "vdd_s3" },
798 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8226_hfsmps, "vdd_s4" },
799 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8226_hfsmps, "vdd_s5" },
800 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
801 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
802 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8226_nldo, "vdd_l3_l24_l26" },
803 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
804 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
805 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
806 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
807 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
808 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
809 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8226_pldo, "vdd_l10_l11_l13" },
810 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l10_l11_l13" },
811 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8226_pldo, "vdd_l12_l14" },
812 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8226_pldo, "vdd_l10_l11_l13" },
813 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8226_pldo, "vdd_l12_l14" },
814 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
815 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
816 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
817 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
818 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
819 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
820 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
821 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
822 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
823 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8226_nldo, "vdd_l3_l24_l26" },
824 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8226_pldo, "vdd_l25" },
825 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8226_nldo, "vdd_l3_l24_l26" },
826 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
827 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
828 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8226_switch, "vdd_lvs1" },
829 {}
830 };
831
832 static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
833 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
834 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
835 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
836 { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
837
838 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
839 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
840 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
841 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
842 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
843 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
844 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
845 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
846 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
847 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
848 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
849 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
850 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
851 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
852 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
853 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
854 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
855 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
856 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
857 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
858 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
859 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
860 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
861 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
862
863 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
864 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
865 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
866
867 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
868 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
869
870 {}
871 };
872
873 static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
874 { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
875 { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
876 { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
877 { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
878 { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
879 { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
880 { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
881 { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
882 { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
883 { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
884 { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
885 { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
886
887 { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
888 { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
889 { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
890 { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
891 { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
892 { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
893 { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
894 { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
895 { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
896 { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
897 { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
898 { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
899 { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
900 { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
901 { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
902 { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
903 { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
904 { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
905 { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
906 { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
907 { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
908 { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
909 { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
910 { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
911 { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
912 { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
913 { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
914
915 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
916 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
917 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
918 { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
919 { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
920
921 {}
922 };
923
924 static const struct rpm_regulator_data rpm_pm8950_regulators[] = {
925 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8950_hfsmps, "vdd_s1" },
926 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8950_hfsmps, "vdd_s2" },
927 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8950_hfsmps, "vdd_s3" },
928 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8950_hfsmps, "vdd_s4" },
929 /* S5 is managed via SPMI. */
930 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_hfsmps, "vdd_s6" },
931
932 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8950_ult_nldo, "vdd_l1_l19" },
933 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8950_ult_nldo, "vdd_l2_l23" },
934 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8950_ult_nldo, "vdd_l3" },
935 /* L4 seems not to exist. */
936 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
937 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
938 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
939 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
940 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
941 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_nldo, "vdd_l9_l10_l13_l14_l15_l18"},
942 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
943 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
944 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
945 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
946 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
947 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l5_l6_l7_l16" },
948 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
949 /* L18 seems not to exist. */
950 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8950_pldo, "vdd_l1_l19" },
951 /* L20 & L21 seem not to exist. */
952 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_pldo, "vdd_l8_l11_l12_l17_l22" },
953 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8950_pldo, "vdd_l2_l23" },
954 {}
955 };
956
957 static const struct rpm_regulator_data rpm_pm8953_regulators[] = {
958 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_hfsmps, "vdd_s1" },
959 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_hfsmps, "vdd_s2" },
960 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
961 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
962 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8950_ftsmps2p5, "vdd_s5" },
963 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_ftsmps2p5, "vdd_s6" },
964 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" },
965
966 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8953_ult_nldo, "vdd_l1" },
967 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8953_ult_nldo, "vdd_l2_l3" },
968 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8953_ult_nldo, "vdd_l2_l3" },
969 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
970 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
971 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
972 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
973 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
974 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
975 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
976 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
977 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
978 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
979 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
980 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
981 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
982 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
983 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
984 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8953_ult_nldo, "vdd_l4_l5_l6_l7_l16_l19" },
985 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8953_lnldo, "vdd_l20" },
986 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8953_lnldo, "vdd_l21" },
987 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
988 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8953_ult_nldo, "vdd_l23" },
989 {}
990 };
991
992 static const struct rpm_regulator_data rpm_pm8994_regulators[] = {
993 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" },
994 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" },
995 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
996 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
997 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" },
998 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" },
999 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" },
1000 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" },
1001 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" },
1002 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" },
1003 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" },
1004 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" },
1005 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" },
1006 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" },
1007 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" },
1008 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" },
1009 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" },
1010 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" },
1011 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" },
1012 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" },
1013 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1014 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1015 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" },
1016 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" },
1017 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1018 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" },
1019 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" },
1020 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" },
1021 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" },
1022 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1023 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1024 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" },
1025 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" },
1026 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1027 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1028 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1029 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" },
1030 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" },
1031 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" },
1032 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" },
1033 { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" },
1034 { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" },
1035 { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" },
1036 { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" },
1037 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" },
1038 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" },
1039
1040 {}
1041 };
1042
1043 static const struct rpm_regulator_data rpm_pmi8994_regulators[] = {
1044 { "s1", QCOM_SMD_RPM_SMPB, 1, &pmi8994_ftsmps, "vdd_s1" },
1045 { "s2", QCOM_SMD_RPM_SMPB, 2, &pmi8994_hfsmps, "vdd_s2" },
1046 { "s3", QCOM_SMD_RPM_SMPB, 3, &pmi8994_hfsmps, "vdd_s3" },
1047 { "boost-bypass", QCOM_SMD_RPM_BBYB, 1, &pmi8994_bby, "vdd_bst_byp" },
1048 {}
1049 };
1050
1051 static const struct rpm_regulator_data rpm_pm8998_regulators[] = {
1052 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" },
1053 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" },
1054 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
1055 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
1056 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
1057 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" },
1058 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" },
1059 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" },
1060 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" },
1061 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" },
1062 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" },
1063 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" },
1064 { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" },
1065 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" },
1066 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" },
1067 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" },
1068 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" },
1069 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" },
1070 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" },
1071 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1072 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" },
1073 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" },
1074 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" },
1075 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" },
1076 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1077 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" },
1078 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1079 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1080 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" },
1081 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" },
1082 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" },
1083 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" },
1084 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" },
1085 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" },
1086 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" },
1087 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" },
1088 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" },
1089 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" },
1090 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" },
1091 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" },
1092 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" },
1093 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" },
1094 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" },
1095 {}
1096 };
1097
1098 static const struct rpm_regulator_data rpm_pmi8998_regulators[] = {
1099 { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" },
1100 {}
1101 };
1102
1103 static const struct rpm_regulator_data rpm_pm660_regulators[] = {
1104 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm660_ftsmps, "vdd_s1" },
1105 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm660_ftsmps, "vdd_s2" },
1106 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm660_ftsmps, "vdd_s3" },
1107 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm660_hfsmps, "vdd_s4" },
1108 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" },
1109 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm660_hfsmps, "vdd_s6" },
1110 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l6_l7" },
1111 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_ht_nldo, "vdd_l2_l3" },
1112 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3" },
1113 /* l4 is unaccessible on PM660 */
1114 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" },
1115 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_ht_nldo, "vdd_l1_l6_l7" },
1116 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_ht_nldo, "vdd_l1_l6_l7" },
1117 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1118 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1119 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1120 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1121 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1122 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1123 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1124 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1125 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1126 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1127 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1128 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1129 { }
1130 };
1131
1132 static const struct rpm_regulator_data rpm_pm660l_regulators[] = {
1133 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm660_ftsmps, "vdd_s1" },
1134 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm660_ftsmps, "vdd_s2" },
1135 { "s3", QCOM_SMD_RPM_RWCX, 0, &pm660_ftsmps, "vdd_s3_s4" },
1136 { "s5", QCOM_SMD_RPM_RWMX, 0, &pm660_ftsmps, "vdd_s5" },
1137 { "l1", QCOM_SMD_RPM_LDOB, 1, &pm660_nldo660, "vdd_l1_l9_l10" },
1138 { "l2", QCOM_SMD_RPM_LDOB, 2, &pm660_pldo660, "vdd_l2" },
1139 { "l3", QCOM_SMD_RPM_LDOB, 3, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
1140 { "l4", QCOM_SMD_RPM_LDOB, 4, &pm660_pldo660, "vdd_l4_l6" },
1141 { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
1142 { "l6", QCOM_SMD_RPM_LDOB, 6, &pm660_pldo660, "vdd_l4_l6" },
1143 { "l7", QCOM_SMD_RPM_LDOB, 7, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
1144 { "l8", QCOM_SMD_RPM_LDOB, 8, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
1145 { "l9", QCOM_SMD_RPM_RWLC, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
1146 { "l10", QCOM_SMD_RPM_RWLM, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
1147 { "bob", QCOM_SMD_RPM_BOBB, 1, &pm660l_bob, "vdd_bob", },
1148 { }
1149 };
1150
1151 static const struct rpm_regulator_data rpm_pms405_regulators[] = {
1152 { "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" },
1153 { "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" },
1154 { "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" },
1155 { "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" },
1156 { "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" },
1157 { "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" },
1158 { "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" },
1159 { "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" },
1160 { "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" },
1161 { "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" },
1162 { "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" },
1163 { "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" },
1164 { "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" },
1165 { "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" },
1166 { "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" },
1167 { "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1168 { "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1169 { "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1170 {}
1171 };
1172
1173 static const struct of_device_id rpm_of_match[] = {
1174 { .compatible = "qcom,rpm-mp5496-regulators", .data = &rpm_mp5496_regulators },
1175 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
1176 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
1177 { .compatible = "qcom,rpm-pm8226-regulators", .data = &rpm_pm8226_regulators },
1178 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
1179 { .compatible = "qcom,rpm-pm8950-regulators", .data = &rpm_pm8950_regulators },
1180 { .compatible = "qcom,rpm-pm8953-regulators", .data = &rpm_pm8953_regulators },
1181 { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators },
1182 { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators },
1183 { .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators },
1184 { .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators },
1185 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
1186 { .compatible = "qcom,rpm-pmi8994-regulators", .data = &rpm_pmi8994_regulators },
1187 { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators },
1188 { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators },
1189 {}
1190 };
1191 MODULE_DEVICE_TABLE(of, rpm_of_match);
1192
1193 /**
1194 * rpm_regulator_init_vreg() - initialize all attributes of a qcom_smd-regulator
1195 * @vreg: Pointer to the individual qcom_smd-regulator resource
1196 * @dev: Pointer to the top level qcom_smd-regulator PMIC device
1197 * @node: Pointer to the individual qcom_smd-regulator resource
1198 * device node
1199 * @rpm: Pointer to the rpm bus node
1200 * @pmic_rpm_data: Pointer to a null-terminated array of qcom_smd-regulator
1201 * resources defined for the top level PMIC device
1202 *
1203 * Return: 0 on success, errno on failure
1204 */
rpm_regulator_init_vreg(struct qcom_rpm_reg * vreg,struct device * dev,struct device_node * node,struct qcom_smd_rpm * rpm,const struct rpm_regulator_data * pmic_rpm_data)1205 static int rpm_regulator_init_vreg(struct qcom_rpm_reg *vreg, struct device *dev,
1206 struct device_node *node, struct qcom_smd_rpm *rpm,
1207 const struct rpm_regulator_data *pmic_rpm_data)
1208 {
1209 struct regulator_config config = {};
1210 const struct rpm_regulator_data *rpm_data;
1211 struct regulator_dev *rdev;
1212 int ret;
1213
1214 for (rpm_data = pmic_rpm_data; rpm_data->name; rpm_data++)
1215 if (of_node_name_eq(node, rpm_data->name))
1216 break;
1217
1218 if (!rpm_data->name) {
1219 dev_err(dev, "Unknown regulator %pOFn\n", node);
1220 return -EINVAL;
1221 }
1222
1223 vreg->dev = dev;
1224 vreg->rpm = rpm;
1225 vreg->type = rpm_data->type;
1226 vreg->id = rpm_data->id;
1227
1228 memcpy(&vreg->desc, rpm_data->desc, sizeof(vreg->desc));
1229 vreg->desc.name = rpm_data->name;
1230 vreg->desc.supply_name = rpm_data->supply;
1231 vreg->desc.owner = THIS_MODULE;
1232 vreg->desc.type = REGULATOR_VOLTAGE;
1233 vreg->desc.of_match = rpm_data->name;
1234
1235 config.dev = dev;
1236 config.of_node = node;
1237 config.driver_data = vreg;
1238
1239 rdev = devm_regulator_register(dev, &vreg->desc, &config);
1240 if (IS_ERR(rdev)) {
1241 ret = PTR_ERR(rdev);
1242 dev_err(dev, "%pOFn: devm_regulator_register() failed, ret=%d\n", node, ret);
1243 return ret;
1244 }
1245
1246 return 0;
1247 }
1248
rpm_reg_probe(struct platform_device * pdev)1249 static int rpm_reg_probe(struct platform_device *pdev)
1250 {
1251 struct device *dev = &pdev->dev;
1252 const struct rpm_regulator_data *vreg_data;
1253 struct device_node *node;
1254 struct qcom_rpm_reg *vreg;
1255 struct qcom_smd_rpm *rpm;
1256 int ret;
1257
1258 rpm = dev_get_drvdata(pdev->dev.parent);
1259 if (!rpm) {
1260 dev_err(&pdev->dev, "Unable to retrieve handle to rpm\n");
1261 return -ENODEV;
1262 }
1263
1264 vreg_data = of_device_get_match_data(dev);
1265 if (!vreg_data)
1266 return -ENODEV;
1267
1268 for_each_available_child_of_node(dev->of_node, node) {
1269 vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
1270 if (!vreg) {
1271 of_node_put(node);
1272 return -ENOMEM;
1273 }
1274
1275 ret = rpm_regulator_init_vreg(vreg, dev, node, rpm, vreg_data);
1276
1277 if (ret < 0) {
1278 of_node_put(node);
1279 return ret;
1280 }
1281 }
1282
1283 return 0;
1284 }
1285
1286 static struct platform_driver rpm_reg_driver = {
1287 .probe = rpm_reg_probe,
1288 .driver = {
1289 .name = "qcom_rpm_smd_regulator",
1290 .of_match_table = rpm_of_match,
1291 },
1292 };
1293
rpm_reg_init(void)1294 static int __init rpm_reg_init(void)
1295 {
1296 return platform_driver_register(&rpm_reg_driver);
1297 }
1298 subsys_initcall(rpm_reg_init);
1299
rpm_reg_exit(void)1300 static void __exit rpm_reg_exit(void)
1301 {
1302 platform_driver_unregister(&rpm_reg_driver);
1303 }
1304 module_exit(rpm_reg_exit)
1305
1306 MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
1307 MODULE_LICENSE("GPL v2");
1308