1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 */
4 #include <linux/of.h>
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/rtc.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm.h>
10 #include <linux/regmap.h>
11 #include <linux/slab.h>
12 #include <linux/spinlock.h>
13
14 /* RTC Register offsets from RTC CTRL REG */
15 #define PM8XXX_ALARM_CTRL_OFFSET 0x01
16 #define PM8XXX_RTC_WRITE_OFFSET 0x02
17 #define PM8XXX_RTC_READ_OFFSET 0x06
18 #define PM8XXX_ALARM_RW_OFFSET 0x0A
19
20 /* RTC_CTRL register bit fields */
21 #define PM8xxx_RTC_ENABLE BIT(7)
22 #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
23 #define PM8xxx_RTC_ALARM_ENABLE BIT(7)
24
25 #define NUM_8_BIT_RTC_REGS 0x4
26
27 /**
28 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
29 * @ctrl: base address of control register
30 * @write: base address of write register
31 * @read: base address of read register
32 * @alarm_ctrl: base address of alarm control register
33 * @alarm_ctrl2: base address of alarm control2 register
34 * @alarm_rw: base address of alarm read-write register
35 * @alarm_en: alarm enable mask
36 */
37 struct pm8xxx_rtc_regs {
38 unsigned int ctrl;
39 unsigned int write;
40 unsigned int read;
41 unsigned int alarm_ctrl;
42 unsigned int alarm_ctrl2;
43 unsigned int alarm_rw;
44 unsigned int alarm_en;
45 };
46
47 /**
48 * struct pm8xxx_rtc - rtc driver internal structure
49 * @rtc: rtc device for this driver.
50 * @regmap: regmap used to access RTC registers
51 * @allow_set_time: indicates whether writing to the RTC is allowed
52 * @rtc_alarm_irq: rtc alarm irq number.
53 * @regs: rtc registers description.
54 * @rtc_dev: device structure.
55 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
56 */
57 struct pm8xxx_rtc {
58 struct rtc_device *rtc;
59 struct regmap *regmap;
60 bool allow_set_time;
61 int rtc_alarm_irq;
62 const struct pm8xxx_rtc_regs *regs;
63 struct device *rtc_dev;
64 spinlock_t ctrl_reg_lock;
65 };
66
67 /*
68 * Steps to write the RTC registers.
69 * 1. Disable alarm if enabled.
70 * 2. Disable rtc if enabled.
71 * 3. Write 0x00 to LSB.
72 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
73 * 5. Enable rtc if disabled in step 2.
74 * 6. Enable alarm if disabled in step 1.
75 */
pm8xxx_rtc_set_time(struct device * dev,struct rtc_time * tm)76 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
77 {
78 int rc, i;
79 unsigned long secs, irq_flags;
80 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
81 unsigned int ctrl_reg, rtc_ctrl_reg;
82 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
83 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
84
85 if (!rtc_dd->allow_set_time)
86 return -EACCES;
87
88 secs = rtc_tm_to_time64(tm);
89
90 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
91
92 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
93 value[i] = secs & 0xFF;
94 secs >>= 8;
95 }
96
97 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
98
99 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
100 if (rc)
101 goto rtc_rw_fail;
102
103 if (ctrl_reg & regs->alarm_en) {
104 alarm_enabled = 1;
105 ctrl_reg &= ~regs->alarm_en;
106 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
107 if (rc) {
108 dev_err(dev, "Write to RTC Alarm control register failed\n");
109 goto rtc_rw_fail;
110 }
111 }
112
113 /* Disable RTC H/w before writing on RTC register */
114 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
115 if (rc)
116 goto rtc_rw_fail;
117
118 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
119 rtc_disabled = 1;
120 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
121 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
122 if (rc) {
123 dev_err(dev, "Write to RTC control register failed\n");
124 goto rtc_rw_fail;
125 }
126 }
127
128 /* Write 0 to Byte[0] */
129 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
130 if (rc) {
131 dev_err(dev, "Write to RTC write data register failed\n");
132 goto rtc_rw_fail;
133 }
134
135 /* Write Byte[1], Byte[2], Byte[3] */
136 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
137 &value[1], sizeof(value) - 1);
138 if (rc) {
139 dev_err(dev, "Write to RTC write data register failed\n");
140 goto rtc_rw_fail;
141 }
142
143 /* Write Byte[0] */
144 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
145 if (rc) {
146 dev_err(dev, "Write to RTC write data register failed\n");
147 goto rtc_rw_fail;
148 }
149
150 /* Enable RTC H/w after writing on RTC register */
151 if (rtc_disabled) {
152 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
153 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
154 if (rc) {
155 dev_err(dev, "Write to RTC control register failed\n");
156 goto rtc_rw_fail;
157 }
158 }
159
160 if (alarm_enabled) {
161 ctrl_reg |= regs->alarm_en;
162 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
163 if (rc) {
164 dev_err(dev, "Write to RTC Alarm control register failed\n");
165 goto rtc_rw_fail;
166 }
167 }
168
169 rtc_rw_fail:
170 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
171
172 return rc;
173 }
174
pm8xxx_rtc_read_time(struct device * dev,struct rtc_time * tm)175 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
176 {
177 int rc;
178 u8 value[NUM_8_BIT_RTC_REGS];
179 unsigned long secs;
180 unsigned int reg;
181 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
182 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
183
184 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
185 if (rc) {
186 dev_err(dev, "RTC read data register failed\n");
187 return rc;
188 }
189
190 /*
191 * Read the LSB again and check if there has been a carry over.
192 * If there is, redo the read operation.
193 */
194 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
195 if (rc < 0) {
196 dev_err(dev, "RTC read data register failed\n");
197 return rc;
198 }
199
200 if (unlikely(reg < value[0])) {
201 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
202 value, sizeof(value));
203 if (rc) {
204 dev_err(dev, "RTC read data register failed\n");
205 return rc;
206 }
207 }
208
209 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
210 ((unsigned long)value[3] << 24);
211
212 rtc_time64_to_tm(secs, tm);
213
214 dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
215
216 return 0;
217 }
218
pm8xxx_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alarm)219 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
220 {
221 int rc, i;
222 u8 value[NUM_8_BIT_RTC_REGS];
223 unsigned long secs, irq_flags;
224 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
225 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
226
227 secs = rtc_tm_to_time64(&alarm->time);
228
229 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
230 value[i] = secs & 0xFF;
231 secs >>= 8;
232 }
233
234 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
235 regs->alarm_en, 0);
236 if (rc)
237 return rc;
238
239 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
240
241 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
242 sizeof(value));
243 if (rc) {
244 dev_err(dev, "Write to RTC ALARM register failed\n");
245 goto rtc_rw_fail;
246 }
247
248 if (alarm->enabled) {
249 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
250 regs->alarm_en, regs->alarm_en);
251 if (rc)
252 goto rtc_rw_fail;
253 }
254
255 dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
256 &alarm->time, &alarm->time);
257 rtc_rw_fail:
258 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
259 return rc;
260 }
261
pm8xxx_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alarm)262 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
263 {
264 int rc;
265 unsigned int ctrl_reg;
266 u8 value[NUM_8_BIT_RTC_REGS];
267 unsigned long secs;
268 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
269 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
270
271 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
272 sizeof(value));
273 if (rc) {
274 dev_err(dev, "RTC alarm time read failed\n");
275 return rc;
276 }
277
278 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
279 ((unsigned long)value[3] << 24);
280
281 rtc_time64_to_tm(secs, &alarm->time);
282
283 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
284 if (rc) {
285 dev_err(dev, "Read from RTC alarm control register failed\n");
286 return rc;
287 }
288 alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
289
290 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
291 &alarm->time, &alarm->time);
292
293 return 0;
294 }
295
pm8xxx_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)296 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
297 {
298 int rc;
299 unsigned long irq_flags;
300 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
301 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
302 unsigned int ctrl_reg;
303 u8 value[NUM_8_BIT_RTC_REGS] = {0};
304
305 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
306
307 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
308 if (rc)
309 goto rtc_rw_fail;
310
311 if (enable)
312 ctrl_reg |= regs->alarm_en;
313 else
314 ctrl_reg &= ~regs->alarm_en;
315
316 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
317 if (rc) {
318 dev_err(dev, "Write to RTC control register failed\n");
319 goto rtc_rw_fail;
320 }
321
322 /* Clear Alarm register */
323 if (!enable) {
324 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
325 sizeof(value));
326 if (rc) {
327 dev_err(dev, "Clear RTC ALARM register failed\n");
328 goto rtc_rw_fail;
329 }
330 }
331
332 rtc_rw_fail:
333 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
334 return rc;
335 }
336
337 static const struct rtc_class_ops pm8xxx_rtc_ops = {
338 .read_time = pm8xxx_rtc_read_time,
339 .set_time = pm8xxx_rtc_set_time,
340 .set_alarm = pm8xxx_rtc_set_alarm,
341 .read_alarm = pm8xxx_rtc_read_alarm,
342 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
343 };
344
pm8xxx_alarm_trigger(int irq,void * dev_id)345 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
346 {
347 struct pm8xxx_rtc *rtc_dd = dev_id;
348 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
349 unsigned int ctrl_reg;
350 int rc;
351
352 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
353
354 spin_lock(&rtc_dd->ctrl_reg_lock);
355
356 /* Clear the alarm enable bit */
357 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
358 if (rc) {
359 spin_unlock(&rtc_dd->ctrl_reg_lock);
360 goto rtc_alarm_handled;
361 }
362
363 ctrl_reg &= ~regs->alarm_en;
364
365 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
366 if (rc) {
367 spin_unlock(&rtc_dd->ctrl_reg_lock);
368 dev_err(rtc_dd->rtc_dev,
369 "Write to alarm control register failed\n");
370 goto rtc_alarm_handled;
371 }
372
373 spin_unlock(&rtc_dd->ctrl_reg_lock);
374
375 /* Clear RTC alarm register */
376 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
377 if (rc) {
378 dev_err(rtc_dd->rtc_dev,
379 "RTC Alarm control2 register read failed\n");
380 goto rtc_alarm_handled;
381 }
382
383 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
384 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
385 if (rc)
386 dev_err(rtc_dd->rtc_dev,
387 "Write to RTC Alarm control2 register failed\n");
388
389 rtc_alarm_handled:
390 return IRQ_HANDLED;
391 }
392
pm8xxx_rtc_enable(struct pm8xxx_rtc * rtc_dd)393 static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
394 {
395 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
396 unsigned int ctrl_reg;
397 int rc;
398
399 /* Check if the RTC is on, else turn it on */
400 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
401 if (rc)
402 return rc;
403
404 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
405 ctrl_reg |= PM8xxx_RTC_ENABLE;
406 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
407 if (rc)
408 return rc;
409 }
410
411 return 0;
412 }
413
414 static const struct pm8xxx_rtc_regs pm8921_regs = {
415 .ctrl = 0x11d,
416 .write = 0x11f,
417 .read = 0x123,
418 .alarm_rw = 0x127,
419 .alarm_ctrl = 0x11d,
420 .alarm_ctrl2 = 0x11e,
421 .alarm_en = BIT(1),
422 };
423
424 static const struct pm8xxx_rtc_regs pm8058_regs = {
425 .ctrl = 0x1e8,
426 .write = 0x1ea,
427 .read = 0x1ee,
428 .alarm_rw = 0x1f2,
429 .alarm_ctrl = 0x1e8,
430 .alarm_ctrl2 = 0x1e9,
431 .alarm_en = BIT(1),
432 };
433
434 static const struct pm8xxx_rtc_regs pm8941_regs = {
435 .ctrl = 0x6046,
436 .write = 0x6040,
437 .read = 0x6048,
438 .alarm_rw = 0x6140,
439 .alarm_ctrl = 0x6146,
440 .alarm_ctrl2 = 0x6148,
441 .alarm_en = BIT(7),
442 };
443
444 static const struct pm8xxx_rtc_regs pmk8350_regs = {
445 .ctrl = 0x6146,
446 .write = 0x6140,
447 .read = 0x6148,
448 .alarm_rw = 0x6240,
449 .alarm_ctrl = 0x6246,
450 .alarm_ctrl2 = 0x6248,
451 .alarm_en = BIT(7),
452 };
453
454 /*
455 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
456 */
457 static const struct of_device_id pm8xxx_id_table[] = {
458 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
459 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
460 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
461 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
462 { .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
463 { },
464 };
465 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
466
pm8xxx_rtc_probe(struct platform_device * pdev)467 static int pm8xxx_rtc_probe(struct platform_device *pdev)
468 {
469 int rc;
470 struct pm8xxx_rtc *rtc_dd;
471 const struct of_device_id *match;
472
473 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
474 if (!match)
475 return -ENXIO;
476
477 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
478 if (rtc_dd == NULL)
479 return -ENOMEM;
480
481 /* Initialise spinlock to protect RTC control register */
482 spin_lock_init(&rtc_dd->ctrl_reg_lock);
483
484 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
485 if (!rtc_dd->regmap) {
486 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
487 return -ENXIO;
488 }
489
490 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
491 if (rtc_dd->rtc_alarm_irq < 0)
492 return -ENXIO;
493
494 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
495 "allow-set-time");
496
497 rtc_dd->regs = match->data;
498 rtc_dd->rtc_dev = &pdev->dev;
499
500 rc = pm8xxx_rtc_enable(rtc_dd);
501 if (rc)
502 return rc;
503
504 platform_set_drvdata(pdev, rtc_dd);
505
506 device_init_wakeup(&pdev->dev, 1);
507
508 /* Register the RTC device */
509 rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
510 if (IS_ERR(rtc_dd->rtc))
511 return PTR_ERR(rtc_dd->rtc);
512
513 rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
514 rtc_dd->rtc->range_max = U32_MAX;
515
516 /* Request the alarm IRQ */
517 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
518 pm8xxx_alarm_trigger,
519 IRQF_TRIGGER_RISING,
520 "pm8xxx_rtc_alarm", rtc_dd);
521 if (rc < 0) {
522 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
523 return rc;
524 }
525
526 return devm_rtc_register_device(rtc_dd->rtc);
527 }
528
529 #ifdef CONFIG_PM_SLEEP
pm8xxx_rtc_resume(struct device * dev)530 static int pm8xxx_rtc_resume(struct device *dev)
531 {
532 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
533
534 if (device_may_wakeup(dev))
535 disable_irq_wake(rtc_dd->rtc_alarm_irq);
536
537 return 0;
538 }
539
pm8xxx_rtc_suspend(struct device * dev)540 static int pm8xxx_rtc_suspend(struct device *dev)
541 {
542 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
543
544 if (device_may_wakeup(dev))
545 enable_irq_wake(rtc_dd->rtc_alarm_irq);
546
547 return 0;
548 }
549 #endif
550
551 static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
552 pm8xxx_rtc_suspend,
553 pm8xxx_rtc_resume);
554
555 static struct platform_driver pm8xxx_rtc_driver = {
556 .probe = pm8xxx_rtc_probe,
557 .driver = {
558 .name = "rtc-pm8xxx",
559 .pm = &pm8xxx_rtc_pm_ops,
560 .of_match_table = pm8xxx_id_table,
561 },
562 };
563
564 module_platform_driver(pm8xxx_rtc_driver);
565
566 MODULE_ALIAS("platform:rtc-pm8xxx");
567 MODULE_DESCRIPTION("PMIC8xxx RTC driver");
568 MODULE_LICENSE("GPL v2");
569 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
570