1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 Google LLC
4 */
5
6 #include "ufshcd.h"
7 #include "ufshcd-crypto.h"
8
9 #undef CREATE_TRACE_POINTS
10 #include <trace/hooks/ufshcd.h>
11
12 /* Blk-crypto modes supported by UFS crypto */
13 static const struct ufs_crypto_alg_entry {
14 enum ufs_crypto_alg ufs_alg;
15 enum ufs_crypto_key_size ufs_key_size;
16 } ufs_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
17 [BLK_ENCRYPTION_MODE_AES_256_XTS] = {
18 .ufs_alg = UFS_CRYPTO_ALG_AES_XTS,
19 .ufs_key_size = UFS_CRYPTO_KEY_SIZE_256,
20 },
21 };
22
ufshcd_program_key(struct ufs_hba * hba,const union ufs_crypto_cfg_entry * cfg,int slot)23 static int ufshcd_program_key(struct ufs_hba *hba,
24 const union ufs_crypto_cfg_entry *cfg, int slot)
25 {
26 int i;
27 u32 slot_offset = hba->crypto_cfg_register + slot * sizeof(*cfg);
28 int err = 0;
29
30 ufshcd_hold(hba, false);
31
32 if (hba->vops && hba->vops->program_key) {
33 err = hba->vops->program_key(hba, cfg, slot);
34 goto out;
35 }
36
37 /* Ensure that CFGE is cleared before programming the key */
38 ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
39 for (i = 0; i < 16; i++) {
40 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]),
41 slot_offset + i * sizeof(cfg->reg_val[0]));
42 }
43 /* Write dword 17 */
44 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]),
45 slot_offset + 17 * sizeof(cfg->reg_val[0]));
46 /* Dword 16 must be written last */
47 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]),
48 slot_offset + 16 * sizeof(cfg->reg_val[0]));
49 out:
50 ufshcd_release(hba);
51 return err;
52 }
53
ufshcd_crypto_keyslot_program(struct blk_keyslot_manager * ksm,const struct blk_crypto_key * key,unsigned int slot)54 static int ufshcd_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
55 const struct blk_crypto_key *key,
56 unsigned int slot)
57 {
58 struct ufs_hba *hba = container_of(ksm, struct ufs_hba, ksm);
59 const union ufs_crypto_cap_entry *ccap_array = hba->crypto_cap_array;
60 const struct ufs_crypto_alg_entry *alg =
61 &ufs_crypto_algs[key->crypto_cfg.crypto_mode];
62 u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
63 int i;
64 int cap_idx = -1;
65 union ufs_crypto_cfg_entry cfg = {};
66 int err;
67
68 BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
69 for (i = 0; i < hba->crypto_capabilities.num_crypto_cap; i++) {
70 if (ccap_array[i].algorithm_id == alg->ufs_alg &&
71 ccap_array[i].key_size == alg->ufs_key_size &&
72 (ccap_array[i].sdus_mask & data_unit_mask)) {
73 cap_idx = i;
74 break;
75 }
76 }
77
78 if (WARN_ON(cap_idx < 0))
79 return -EOPNOTSUPP;
80
81 cfg.data_unit_size = data_unit_mask;
82 cfg.crypto_cap_idx = cap_idx;
83 cfg.config_enable = UFS_CRYPTO_CONFIGURATION_ENABLE;
84
85 if (ccap_array[cap_idx].algorithm_id == UFS_CRYPTO_ALG_AES_XTS) {
86 /* In XTS mode, the blk_crypto_key's size is already doubled */
87 memcpy(cfg.crypto_key, key->raw, key->size/2);
88 memcpy(cfg.crypto_key + UFS_CRYPTO_KEY_MAX_SIZE/2,
89 key->raw + key->size/2, key->size/2);
90 } else {
91 memcpy(cfg.crypto_key, key->raw, key->size);
92 }
93
94 err = ufshcd_program_key(hba, &cfg, slot);
95
96 memzero_explicit(&cfg, sizeof(cfg));
97 return err;
98 }
99
ufshcd_clear_keyslot(struct ufs_hba * hba,int slot)100 static int ufshcd_clear_keyslot(struct ufs_hba *hba, int slot)
101 {
102 /*
103 * Clear the crypto cfg on the device. Clearing CFGE
104 * might not be sufficient, so just clear the entire cfg.
105 */
106 union ufs_crypto_cfg_entry cfg = {};
107
108 return ufshcd_program_key(hba, &cfg, slot);
109 }
110
ufshcd_crypto_keyslot_evict(struct blk_keyslot_manager * ksm,const struct blk_crypto_key * key,unsigned int slot)111 static int ufshcd_crypto_keyslot_evict(struct blk_keyslot_manager *ksm,
112 const struct blk_crypto_key *key,
113 unsigned int slot)
114 {
115 struct ufs_hba *hba = container_of(ksm, struct ufs_hba, ksm);
116
117 return ufshcd_clear_keyslot(hba, slot);
118 }
119
ufshcd_crypto_enable(struct ufs_hba * hba)120 bool ufshcd_crypto_enable(struct ufs_hba *hba)
121 {
122 if (!(hba->caps & UFSHCD_CAP_CRYPTO))
123 return false;
124
125 /* Reset might clear all keys, so reprogram all the keys. */
126 if (hba->ksm.num_slots) {
127 int err = -EOPNOTSUPP;
128
129 trace_android_rvh_ufs_reprogram_all_keys(hba, &err);
130 if (err == -EOPNOTSUPP)
131 blk_ksm_reprogram_all_keys(&hba->ksm);
132 }
133
134 if (hba->quirks & UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE)
135 return false;
136
137 return true;
138 }
139
140 static const struct blk_ksm_ll_ops ufshcd_ksm_ops = {
141 .keyslot_program = ufshcd_crypto_keyslot_program,
142 .keyslot_evict = ufshcd_crypto_keyslot_evict,
143 };
144
145 static enum blk_crypto_mode_num
ufshcd_find_blk_crypto_mode(union ufs_crypto_cap_entry cap)146 ufshcd_find_blk_crypto_mode(union ufs_crypto_cap_entry cap)
147 {
148 int i;
149
150 for (i = 0; i < ARRAY_SIZE(ufs_crypto_algs); i++) {
151 BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
152 if (ufs_crypto_algs[i].ufs_alg == cap.algorithm_id &&
153 ufs_crypto_algs[i].ufs_key_size == cap.key_size) {
154 return i;
155 }
156 }
157 return BLK_ENCRYPTION_MODE_INVALID;
158 }
159
160 /**
161 * ufshcd_hba_init_crypto_capabilities - Read crypto capabilities, init crypto
162 * fields in hba
163 * @hba: Per adapter instance
164 *
165 * Return: 0 if crypto was initialized or is not supported, else a -errno value.
166 */
ufshcd_hba_init_crypto_capabilities(struct ufs_hba * hba)167 int ufshcd_hba_init_crypto_capabilities(struct ufs_hba *hba)
168 {
169 int cap_idx;
170 int err = 0;
171 enum blk_crypto_mode_num blk_mode_num;
172
173 if (hba->quirks & UFSHCD_QUIRK_CUSTOM_KEYSLOT_MANAGER)
174 return 0;
175
176 /*
177 * Don't use crypto if either the hardware doesn't advertise the
178 * standard crypto capability bit *or* if the vendor specific driver
179 * hasn't advertised that crypto is supported.
180 */
181 if (!(hba->capabilities & MASK_CRYPTO_SUPPORT) ||
182 !(hba->caps & UFSHCD_CAP_CRYPTO))
183 goto out;
184
185 hba->crypto_capabilities.reg_val =
186 cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
187 hba->crypto_cfg_register =
188 (u32)hba->crypto_capabilities.config_array_ptr * 0x100;
189 hba->crypto_cap_array =
190 devm_kcalloc(hba->dev, hba->crypto_capabilities.num_crypto_cap,
191 sizeof(hba->crypto_cap_array[0]), GFP_KERNEL);
192 if (!hba->crypto_cap_array) {
193 err = -ENOMEM;
194 goto out;
195 }
196
197 /* The actual number of configurations supported is (CFGC+1) */
198 err = devm_blk_ksm_init(hba->dev, &hba->ksm,
199 hba->crypto_capabilities.config_count + 1);
200 if (err)
201 goto out;
202
203 hba->ksm.ksm_ll_ops = ufshcd_ksm_ops;
204 /* UFS only supports 8 bytes for any DUN */
205 hba->ksm.max_dun_bytes_supported = 8;
206 hba->ksm.features = BLK_CRYPTO_FEATURE_STANDARD_KEYS;
207 hba->ksm.dev = hba->dev;
208
209 /*
210 * Cache all the UFS crypto capabilities and advertise the supported
211 * crypto modes and data unit sizes to the block layer.
212 */
213 for (cap_idx = 0; cap_idx < hba->crypto_capabilities.num_crypto_cap;
214 cap_idx++) {
215 hba->crypto_cap_array[cap_idx].reg_val =
216 cpu_to_le32(ufshcd_readl(hba,
217 REG_UFS_CRYPTOCAP +
218 cap_idx * sizeof(__le32)));
219 blk_mode_num = ufshcd_find_blk_crypto_mode(
220 hba->crypto_cap_array[cap_idx]);
221 if (blk_mode_num != BLK_ENCRYPTION_MODE_INVALID)
222 hba->ksm.crypto_modes_supported[blk_mode_num] |=
223 hba->crypto_cap_array[cap_idx].sdus_mask * 512;
224 }
225
226 return 0;
227
228 out:
229 /* Indicate that init failed by clearing UFSHCD_CAP_CRYPTO */
230 hba->caps &= ~UFSHCD_CAP_CRYPTO;
231 return err;
232 }
233
234 /**
235 * ufshcd_init_crypto - Initialize crypto hardware
236 * @hba: Per adapter instance
237 */
ufshcd_init_crypto(struct ufs_hba * hba)238 void ufshcd_init_crypto(struct ufs_hba *hba)
239 {
240 int slot;
241
242 if (!(hba->caps & UFSHCD_CAP_CRYPTO))
243 return;
244
245 /* Clear all keyslots */
246 for (slot = 0; slot < hba->ksm.num_slots; slot++)
247 hba->ksm.ksm_ll_ops.keyslot_evict(&hba->ksm, NULL, slot);
248 }
249
ufshcd_crypto_setup_rq_keyslot_manager(struct ufs_hba * hba,struct request_queue * q)250 void ufshcd_crypto_setup_rq_keyslot_manager(struct ufs_hba *hba,
251 struct request_queue *q)
252 {
253 if (hba->caps & UFSHCD_CAP_CRYPTO)
254 blk_ksm_register(&hba->ksm, q);
255 }
256