1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2017-2019, Linaro Ltd.
5 */
6
7 #include <linux/debugfs.h>
8 #include <linux/err.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/random.h>
12 #include <linux/slab.h>
13 #include <linux/soc/qcom/smem.h>
14 #include <linux/string.h>
15 #include <linux/sys_soc.h>
16 #include <linux/types.h>
17
18 #include <asm/unaligned.h>
19
20 /*
21 * SoC version type with major number in the upper 16 bits and minor
22 * number in the lower 16 bits.
23 */
24 #define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
25 #define SOCINFO_MINOR(ver) ((ver) & 0xffff)
26 #define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
27
28 #define SMEM_SOCINFO_BUILD_ID_LENGTH 32
29 #define SMEM_SOCINFO_CHIP_ID_LENGTH 32
30
31 /*
32 * SMEM item id, used to acquire handles to respective
33 * SMEM region.
34 */
35 #define SMEM_HW_SW_BUILD_ID 137
36
37 #ifdef CONFIG_DEBUG_FS
38 #define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32
39 #define SMEM_IMAGE_VERSION_SIZE 4096
40 #define SMEM_IMAGE_VERSION_NAME_SIZE 75
41 #define SMEM_IMAGE_VERSION_VARIANT_SIZE 20
42 #define SMEM_IMAGE_VERSION_OEM_SIZE 32
43
44 /*
45 * SMEM Image table indices
46 */
47 #define SMEM_IMAGE_TABLE_BOOT_INDEX 0
48 #define SMEM_IMAGE_TABLE_TZ_INDEX 1
49 #define SMEM_IMAGE_TABLE_RPM_INDEX 3
50 #define SMEM_IMAGE_TABLE_APPS_INDEX 10
51 #define SMEM_IMAGE_TABLE_MPSS_INDEX 11
52 #define SMEM_IMAGE_TABLE_ADSP_INDEX 12
53 #define SMEM_IMAGE_TABLE_CNSS_INDEX 13
54 #define SMEM_IMAGE_TABLE_VIDEO_INDEX 14
55 #define SMEM_IMAGE_VERSION_TABLE 469
56
57 /*
58 * SMEM Image table names
59 */
60 static const char *const socinfo_image_names[] = {
61 [SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp",
62 [SMEM_IMAGE_TABLE_APPS_INDEX] = "apps",
63 [SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot",
64 [SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss",
65 [SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss",
66 [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm",
67 [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz",
68 [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video",
69 };
70
71 static const char *const pmic_models[] = {
72 [0] = "Unknown PMIC model",
73 [1] = "PM8941",
74 [2] = "PM8841",
75 [3] = "PM8019",
76 [4] = "PM8226",
77 [5] = "PM8110",
78 [6] = "PMA8084",
79 [7] = "PMI8962",
80 [8] = "PMD9635",
81 [9] = "PM8994",
82 [10] = "PMI8994",
83 [11] = "PM8916",
84 [12] = "PM8004",
85 [13] = "PM8909/PM8058",
86 [14] = "PM8028",
87 [15] = "PM8901",
88 [16] = "PM8950/PM8027",
89 [17] = "PMI8950/ISL9519",
90 [18] = "PMK8001/PM8921",
91 [19] = "PMI8996/PM8018",
92 [20] = "PM8998/PM8015",
93 [21] = "PMI8998/PM8014",
94 [22] = "PM8821",
95 [23] = "PM8038",
96 [24] = "PM8005/PM8922",
97 [25] = "PM8917",
98 [26] = "PM660L",
99 [27] = "PM660",
100 [30] = "PM8150",
101 [31] = "PM8150L",
102 [32] = "PM8150B",
103 [33] = "PMK8002",
104 [36] = "PM8009",
105 };
106 #endif /* CONFIG_DEBUG_FS */
107
108 /* Socinfo SMEM item structure */
109 struct socinfo {
110 __le32 fmt;
111 __le32 id;
112 __le32 ver;
113 char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
114 /* Version 2 */
115 __le32 raw_id;
116 __le32 raw_ver;
117 /* Version 3 */
118 __le32 hw_plat;
119 /* Version 4 */
120 __le32 plat_ver;
121 /* Version 5 */
122 __le32 accessory_chip;
123 /* Version 6 */
124 __le32 hw_plat_subtype;
125 /* Version 7 */
126 __le32 pmic_model;
127 __le32 pmic_die_rev;
128 /* Version 8 */
129 __le32 pmic_model_1;
130 __le32 pmic_die_rev_1;
131 __le32 pmic_model_2;
132 __le32 pmic_die_rev_2;
133 /* Version 9 */
134 __le32 foundry_id;
135 /* Version 10 */
136 __le32 serial_num;
137 /* Version 11 */
138 __le32 num_pmics;
139 __le32 pmic_array_offset;
140 /* Version 12 */
141 __le32 chip_family;
142 __le32 raw_device_family;
143 __le32 raw_device_num;
144 /* Version 13 */
145 __le32 nproduct_id;
146 char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
147 /* Version 14 */
148 __le32 num_clusters;
149 __le32 ncluster_array_offset;
150 __le32 num_defective_parts;
151 __le32 ndefective_parts_array_offset;
152 /* Version 15 */
153 __le32 nmodem_supported;
154 };
155
156 #ifdef CONFIG_DEBUG_FS
157 struct socinfo_params {
158 u32 raw_device_family;
159 u32 hw_plat_subtype;
160 u32 accessory_chip;
161 u32 raw_device_num;
162 u32 chip_family;
163 u32 foundry_id;
164 u32 plat_ver;
165 u32 raw_ver;
166 u32 hw_plat;
167 u32 fmt;
168 u32 nproduct_id;
169 u32 num_clusters;
170 u32 ncluster_array_offset;
171 u32 num_defective_parts;
172 u32 ndefective_parts_array_offset;
173 u32 nmodem_supported;
174 };
175
176 struct smem_image_version {
177 char name[SMEM_IMAGE_VERSION_NAME_SIZE];
178 char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE];
179 char pad;
180 char oem[SMEM_IMAGE_VERSION_OEM_SIZE];
181 };
182 #endif /* CONFIG_DEBUG_FS */
183
184 struct qcom_socinfo {
185 struct soc_device *soc_dev;
186 struct soc_device_attribute attr;
187 #ifdef CONFIG_DEBUG_FS
188 struct dentry *dbg_root;
189 struct socinfo_params info;
190 #endif /* CONFIG_DEBUG_FS */
191 };
192
193 struct soc_id {
194 unsigned int id;
195 const char *name;
196 };
197
198 static const struct soc_id soc_id[] = {
199 { 87, "MSM8960" },
200 { 109, "APQ8064" },
201 { 122, "MSM8660A" },
202 { 123, "MSM8260A" },
203 { 124, "APQ8060A" },
204 { 126, "MSM8974" },
205 { 130, "MPQ8064" },
206 { 138, "MSM8960AB" },
207 { 139, "APQ8060AB" },
208 { 140, "MSM8260AB" },
209 { 141, "MSM8660AB" },
210 { 145, "MSM8626" },
211 { 147, "MSM8610" },
212 { 153, "APQ8064AB" },
213 { 158, "MSM8226" },
214 { 159, "MSM8526" },
215 { 161, "MSM8110" },
216 { 162, "MSM8210" },
217 { 163, "MSM8810" },
218 { 164, "MSM8212" },
219 { 165, "MSM8612" },
220 { 166, "MSM8112" },
221 { 168, "MSM8225Q" },
222 { 169, "MSM8625Q" },
223 { 170, "MSM8125Q" },
224 { 172, "APQ8064AA" },
225 { 178, "APQ8084" },
226 { 184, "APQ8074" },
227 { 185, "MSM8274" },
228 { 186, "MSM8674" },
229 { 194, "MSM8974PRO" },
230 { 198, "MSM8126" },
231 { 199, "APQ8026" },
232 { 200, "MSM8926" },
233 { 205, "MSM8326" },
234 { 206, "MSM8916" },
235 { 207, "MSM8994" },
236 { 208, "APQ8074-AA" },
237 { 209, "APQ8074-AB" },
238 { 210, "APQ8074PRO" },
239 { 211, "MSM8274-AA" },
240 { 212, "MSM8274-AB" },
241 { 213, "MSM8274PRO" },
242 { 214, "MSM8674-AA" },
243 { 215, "MSM8674-AB" },
244 { 216, "MSM8674PRO" },
245 { 217, "MSM8974-AA" },
246 { 218, "MSM8974-AB" },
247 { 219, "APQ8028" },
248 { 220, "MSM8128" },
249 { 221, "MSM8228" },
250 { 222, "MSM8528" },
251 { 223, "MSM8628" },
252 { 224, "MSM8928" },
253 { 225, "MSM8510" },
254 { 226, "MSM8512" },
255 { 233, "MSM8936" },
256 { 239, "MSM8939" },
257 { 240, "APQ8036" },
258 { 241, "APQ8039" },
259 { 246, "MSM8996" },
260 { 247, "APQ8016" },
261 { 248, "MSM8216" },
262 { 249, "MSM8116" },
263 { 250, "MSM8616" },
264 { 251, "MSM8992" },
265 { 253, "APQ8094" },
266 { 290, "MDM9607" },
267 { 291, "APQ8096" },
268 { 292, "MSM8998" },
269 { 293, "MSM8953" },
270 { 296, "MDM8207" },
271 { 297, "MDM9207" },
272 { 298, "MDM9307" },
273 { 299, "MDM9628" },
274 { 304, "APQ8053" },
275 { 305, "MSM8996SG" },
276 { 310, "MSM8996AU" },
277 { 311, "APQ8096AU" },
278 { 312, "APQ8096SG" },
279 { 317, "SDM660" },
280 { 318, "SDM630" },
281 { 319, "APQ8098" },
282 { 321, "SDM845" },
283 { 322, "MDM9206" },
284 { 324, "SDA660" },
285 { 325, "SDM658" },
286 { 326, "SDA658" },
287 { 327, "SDA630" },
288 { 338, "SDM450" },
289 { 341, "SDA845" },
290 { 345, "SDM636" },
291 { 346, "SDA636" },
292 { 349, "SDM632" },
293 { 350, "SDA632" },
294 { 351, "SDA450" },
295 { 356, "SM8250" },
296 { 394, "SM6125" },
297 { 402, "IPQ6018" },
298 { 403, "IPQ6028" },
299 { 421, "IPQ6000" },
300 { 422, "IPQ6010" },
301 { 425, "SC7180" },
302 { 453, "IPQ6005" },
303 { 455, "QRB5165" },
304 };
305
socinfo_machine(struct device * dev,unsigned int id)306 static const char *socinfo_machine(struct device *dev, unsigned int id)
307 {
308 int idx;
309
310 for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) {
311 if (soc_id[idx].id == id)
312 return soc_id[idx].name;
313 }
314
315 return NULL;
316 }
317
318 #ifdef CONFIG_DEBUG_FS
319
320 #define QCOM_OPEN(name, _func) \
321 static int qcom_open_##name(struct inode *inode, struct file *file) \
322 { \
323 return single_open(file, _func, inode->i_private); \
324 } \
325 \
326 static const struct file_operations qcom_ ##name## _ops = { \
327 .open = qcom_open_##name, \
328 .read = seq_read, \
329 .llseek = seq_lseek, \
330 .release = single_release, \
331 }
332
333 #define DEBUGFS_ADD(info, name) \
334 debugfs_create_file(__stringify(name), 0444, \
335 qcom_socinfo->dbg_root, \
336 info, &qcom_ ##name## _ops)
337
338
qcom_show_build_id(struct seq_file * seq,void * p)339 static int qcom_show_build_id(struct seq_file *seq, void *p)
340 {
341 struct socinfo *socinfo = seq->private;
342
343 seq_printf(seq, "%s\n", socinfo->build_id);
344
345 return 0;
346 }
347
qcom_show_pmic_model(struct seq_file * seq,void * p)348 static int qcom_show_pmic_model(struct seq_file *seq, void *p)
349 {
350 struct socinfo *socinfo = seq->private;
351 int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model));
352
353 if (model < 0)
354 return -EINVAL;
355
356 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
357 seq_printf(seq, "%s\n", pmic_models[model]);
358 else
359 seq_printf(seq, "unknown (%d)\n", model);
360
361 return 0;
362 }
363
qcom_show_pmic_model_array(struct seq_file * seq,void * p)364 static int qcom_show_pmic_model_array(struct seq_file *seq, void *p)
365 {
366 struct socinfo *socinfo = seq->private;
367 unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics);
368 unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset);
369 int i;
370 void *ptr = socinfo;
371
372 ptr += pmic_array_offset;
373
374 /* No need for bounds checking, it happened at socinfo_debugfs_init */
375 for (i = 0; i < num_pmics; i++) {
376 unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32)));
377 unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32));
378
379 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
380 seq_printf(seq, "%s %u.%u\n", pmic_models[model],
381 SOCINFO_MAJOR(die_rev),
382 SOCINFO_MINOR(die_rev));
383 else
384 seq_printf(seq, "unknown (%d)\n", model);
385 }
386
387 return 0;
388 }
389
qcom_show_pmic_die_revision(struct seq_file * seq,void * p)390 static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p)
391 {
392 struct socinfo *socinfo = seq->private;
393
394 seq_printf(seq, "%u.%u\n",
395 SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)),
396 SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev)));
397
398 return 0;
399 }
400
qcom_show_chip_id(struct seq_file * seq,void * p)401 static int qcom_show_chip_id(struct seq_file *seq, void *p)
402 {
403 struct socinfo *socinfo = seq->private;
404
405 seq_printf(seq, "%s\n", socinfo->chip_id);
406
407 return 0;
408 }
409
410 QCOM_OPEN(build_id, qcom_show_build_id);
411 QCOM_OPEN(pmic_model, qcom_show_pmic_model);
412 QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array);
413 QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision);
414 QCOM_OPEN(chip_id, qcom_show_chip_id);
415
416 #define DEFINE_IMAGE_OPS(type) \
417 static int show_image_##type(struct seq_file *seq, void *p) \
418 { \
419 struct smem_image_version *image_version = seq->private; \
420 if (image_version->type[0] != '\0') \
421 seq_printf(seq, "%s\n", image_version->type); \
422 return 0; \
423 } \
424 static int open_image_##type(struct inode *inode, struct file *file) \
425 { \
426 return single_open(file, show_image_##type, inode->i_private); \
427 } \
428 \
429 static const struct file_operations qcom_image_##type##_ops = { \
430 .open = open_image_##type, \
431 .read = seq_read, \
432 .llseek = seq_lseek, \
433 .release = single_release, \
434 }
435
436 DEFINE_IMAGE_OPS(name);
437 DEFINE_IMAGE_OPS(variant);
438 DEFINE_IMAGE_OPS(oem);
439
socinfo_debugfs_init(struct qcom_socinfo * qcom_socinfo,struct socinfo * info,size_t info_size)440 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
441 struct socinfo *info, size_t info_size)
442 {
443 struct smem_image_version *versions;
444 struct dentry *dentry;
445 size_t size;
446 int i;
447 unsigned int num_pmics;
448 unsigned int pmic_array_offset;
449
450 qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL);
451
452 qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt);
453
454 debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root,
455 &qcom_socinfo->info.fmt);
456
457 switch (qcom_socinfo->info.fmt) {
458 case SOCINFO_VERSION(0, 15):
459 qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported);
460
461 debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root,
462 &qcom_socinfo->info.nmodem_supported);
463 fallthrough;
464 case SOCINFO_VERSION(0, 14):
465 qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters);
466 qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset);
467 qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts);
468 qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset);
469
470 debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root,
471 &qcom_socinfo->info.num_clusters);
472 debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root,
473 &qcom_socinfo->info.ncluster_array_offset);
474 debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root,
475 &qcom_socinfo->info.num_defective_parts);
476 debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root,
477 &qcom_socinfo->info.ndefective_parts_array_offset);
478 fallthrough;
479 case SOCINFO_VERSION(0, 13):
480 qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id);
481
482 debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root,
483 &qcom_socinfo->info.nproduct_id);
484 DEBUGFS_ADD(info, chip_id);
485 fallthrough;
486 case SOCINFO_VERSION(0, 12):
487 qcom_socinfo->info.chip_family =
488 __le32_to_cpu(info->chip_family);
489 qcom_socinfo->info.raw_device_family =
490 __le32_to_cpu(info->raw_device_family);
491 qcom_socinfo->info.raw_device_num =
492 __le32_to_cpu(info->raw_device_num);
493
494 debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root,
495 &qcom_socinfo->info.chip_family);
496 debugfs_create_x32("raw_device_family", 0444,
497 qcom_socinfo->dbg_root,
498 &qcom_socinfo->info.raw_device_family);
499 debugfs_create_x32("raw_device_number", 0444,
500 qcom_socinfo->dbg_root,
501 &qcom_socinfo->info.raw_device_num);
502 fallthrough;
503 case SOCINFO_VERSION(0, 11):
504 num_pmics = le32_to_cpu(info->num_pmics);
505 pmic_array_offset = le32_to_cpu(info->pmic_array_offset);
506 if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size)
507 DEBUGFS_ADD(info, pmic_model_array);
508 fallthrough;
509 case SOCINFO_VERSION(0, 10):
510 case SOCINFO_VERSION(0, 9):
511 qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id);
512
513 debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root,
514 &qcom_socinfo->info.foundry_id);
515 fallthrough;
516 case SOCINFO_VERSION(0, 8):
517 case SOCINFO_VERSION(0, 7):
518 DEBUGFS_ADD(info, pmic_model);
519 DEBUGFS_ADD(info, pmic_die_rev);
520 fallthrough;
521 case SOCINFO_VERSION(0, 6):
522 qcom_socinfo->info.hw_plat_subtype =
523 __le32_to_cpu(info->hw_plat_subtype);
524
525 debugfs_create_u32("hardware_platform_subtype", 0444,
526 qcom_socinfo->dbg_root,
527 &qcom_socinfo->info.hw_plat_subtype);
528 fallthrough;
529 case SOCINFO_VERSION(0, 5):
530 qcom_socinfo->info.accessory_chip =
531 __le32_to_cpu(info->accessory_chip);
532
533 debugfs_create_u32("accessory_chip", 0444,
534 qcom_socinfo->dbg_root,
535 &qcom_socinfo->info.accessory_chip);
536 fallthrough;
537 case SOCINFO_VERSION(0, 4):
538 qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver);
539
540 debugfs_create_u32("platform_version", 0444,
541 qcom_socinfo->dbg_root,
542 &qcom_socinfo->info.plat_ver);
543 fallthrough;
544 case SOCINFO_VERSION(0, 3):
545 qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat);
546
547 debugfs_create_u32("hardware_platform", 0444,
548 qcom_socinfo->dbg_root,
549 &qcom_socinfo->info.hw_plat);
550 fallthrough;
551 case SOCINFO_VERSION(0, 2):
552 qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver);
553
554 debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root,
555 &qcom_socinfo->info.raw_ver);
556 fallthrough;
557 case SOCINFO_VERSION(0, 1):
558 DEBUGFS_ADD(info, build_id);
559 break;
560 }
561
562 versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE,
563 &size);
564
565 for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) {
566 if (!socinfo_image_names[i])
567 continue;
568
569 dentry = debugfs_create_dir(socinfo_image_names[i],
570 qcom_socinfo->dbg_root);
571 debugfs_create_file("name", 0444, dentry, &versions[i],
572 &qcom_image_name_ops);
573 debugfs_create_file("variant", 0444, dentry, &versions[i],
574 &qcom_image_variant_ops);
575 debugfs_create_file("oem", 0444, dentry, &versions[i],
576 &qcom_image_oem_ops);
577 }
578 }
579
socinfo_debugfs_exit(struct qcom_socinfo * qcom_socinfo)580 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo)
581 {
582 debugfs_remove_recursive(qcom_socinfo->dbg_root);
583 }
584 #else
socinfo_debugfs_init(struct qcom_socinfo * qcom_socinfo,struct socinfo * info,size_t info_size)585 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
586 struct socinfo *info, size_t info_size)
587 {
588 }
socinfo_debugfs_exit(struct qcom_socinfo * qcom_socinfo)589 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { }
590 #endif /* CONFIG_DEBUG_FS */
591
qcom_socinfo_probe(struct platform_device * pdev)592 static int qcom_socinfo_probe(struct platform_device *pdev)
593 {
594 struct qcom_socinfo *qs;
595 struct socinfo *info;
596 size_t item_size;
597
598 info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID,
599 &item_size);
600 if (IS_ERR(info)) {
601 dev_err(&pdev->dev, "Couldn't find socinfo\n");
602 return PTR_ERR(info);
603 }
604
605 qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL);
606 if (!qs)
607 return -ENOMEM;
608
609 qs->attr.family = "Snapdragon";
610 qs->attr.machine = socinfo_machine(&pdev->dev,
611 le32_to_cpu(info->id));
612 qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u",
613 le32_to_cpu(info->id));
614 qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u",
615 SOCINFO_MAJOR(le32_to_cpu(info->ver)),
616 SOCINFO_MINOR(le32_to_cpu(info->ver)));
617 if (offsetof(struct socinfo, serial_num) <= item_size)
618 qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL,
619 "%u",
620 le32_to_cpu(info->serial_num));
621
622 qs->soc_dev = soc_device_register(&qs->attr);
623 if (IS_ERR(qs->soc_dev))
624 return PTR_ERR(qs->soc_dev);
625
626 socinfo_debugfs_init(qs, info, item_size);
627
628 /* Feed the soc specific unique data into entropy pool */
629 add_device_randomness(info, item_size);
630
631 platform_set_drvdata(pdev, qs);
632
633 return 0;
634 }
635
qcom_socinfo_remove(struct platform_device * pdev)636 static int qcom_socinfo_remove(struct platform_device *pdev)
637 {
638 struct qcom_socinfo *qs = platform_get_drvdata(pdev);
639
640 soc_device_unregister(qs->soc_dev);
641
642 socinfo_debugfs_exit(qs);
643
644 return 0;
645 }
646
647 static struct platform_driver qcom_socinfo_driver = {
648 .probe = qcom_socinfo_probe,
649 .remove = qcom_socinfo_remove,
650 .driver = {
651 .name = "qcom-socinfo",
652 },
653 };
654
655 module_platform_driver(qcom_socinfo_driver);
656
657 MODULE_DESCRIPTION("Qualcomm SoCinfo driver");
658 MODULE_LICENSE("GPL v2");
659 MODULE_ALIAS("platform:qcom-socinfo");
660